nouveau_bo.c 30 KB

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  1. /*
  2. * Copyright 2007 Dave Airlied
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. /*
  25. * Authors: Dave Airlied <airlied@linux.ie>
  26. * Ben Skeggs <darktama@iinet.net.au>
  27. * Jeremy Kolb <jkolb@brandeis.edu>
  28. */
  29. #include "drmP.h"
  30. #include "ttm/ttm_page_alloc.h"
  31. #include "nouveau_drm.h"
  32. #include "nouveau_drv.h"
  33. #include "nouveau_dma.h"
  34. #include "nouveau_mm.h"
  35. #include "nouveau_vm.h"
  36. #include <linux/log2.h>
  37. #include <linux/slab.h>
  38. static void
  39. nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
  40. {
  41. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  42. struct drm_device *dev = dev_priv->dev;
  43. struct nouveau_bo *nvbo = nouveau_bo(bo);
  44. if (unlikely(nvbo->gem))
  45. DRM_ERROR("bo %p still attached to GEM object\n", bo);
  46. nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
  47. kfree(nvbo);
  48. }
  49. static void
  50. nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
  51. int *align, int *size)
  52. {
  53. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  54. if (dev_priv->card_type < NV_50) {
  55. if (nvbo->tile_mode) {
  56. if (dev_priv->chipset >= 0x40) {
  57. *align = 65536;
  58. *size = roundup(*size, 64 * nvbo->tile_mode);
  59. } else if (dev_priv->chipset >= 0x30) {
  60. *align = 32768;
  61. *size = roundup(*size, 64 * nvbo->tile_mode);
  62. } else if (dev_priv->chipset >= 0x20) {
  63. *align = 16384;
  64. *size = roundup(*size, 64 * nvbo->tile_mode);
  65. } else if (dev_priv->chipset >= 0x10) {
  66. *align = 16384;
  67. *size = roundup(*size, 32 * nvbo->tile_mode);
  68. }
  69. }
  70. } else {
  71. *size = roundup(*size, (1 << nvbo->page_shift));
  72. *align = max((1 << nvbo->page_shift), *align);
  73. }
  74. *size = roundup(*size, PAGE_SIZE);
  75. }
  76. int
  77. nouveau_bo_new(struct drm_device *dev, int size, int align,
  78. uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
  79. struct nouveau_bo **pnvbo)
  80. {
  81. struct drm_nouveau_private *dev_priv = dev->dev_private;
  82. struct nouveau_bo *nvbo;
  83. size_t acc_size;
  84. int ret;
  85. nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
  86. if (!nvbo)
  87. return -ENOMEM;
  88. INIT_LIST_HEAD(&nvbo->head);
  89. INIT_LIST_HEAD(&nvbo->entry);
  90. INIT_LIST_HEAD(&nvbo->vma_list);
  91. nvbo->tile_mode = tile_mode;
  92. nvbo->tile_flags = tile_flags;
  93. nvbo->bo.bdev = &dev_priv->ttm.bdev;
  94. nvbo->page_shift = 12;
  95. if (dev_priv->bar1_vm) {
  96. if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
  97. nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
  98. }
  99. nouveau_bo_fixup_align(nvbo, flags, &align, &size);
  100. nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
  101. nouveau_bo_placement_set(nvbo, flags, 0);
  102. acc_size = ttm_bo_dma_acc_size(&dev_priv->ttm.bdev, size,
  103. sizeof(struct nouveau_bo));
  104. ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
  105. ttm_bo_type_device, &nvbo->placement,
  106. align >> PAGE_SHIFT, 0, false, NULL, acc_size,
  107. nouveau_bo_del_ttm);
  108. if (ret) {
  109. /* ttm will call nouveau_bo_del_ttm if it fails.. */
  110. return ret;
  111. }
  112. *pnvbo = nvbo;
  113. return 0;
  114. }
  115. static void
  116. set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
  117. {
  118. *n = 0;
  119. if (type & TTM_PL_FLAG_VRAM)
  120. pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
  121. if (type & TTM_PL_FLAG_TT)
  122. pl[(*n)++] = TTM_PL_FLAG_TT | flags;
  123. if (type & TTM_PL_FLAG_SYSTEM)
  124. pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
  125. }
  126. static void
  127. set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
  128. {
  129. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  130. int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
  131. if (dev_priv->card_type == NV_10 &&
  132. nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
  133. nvbo->bo.mem.num_pages < vram_pages / 4) {
  134. /*
  135. * Make sure that the color and depth buffers are handled
  136. * by independent memory controller units. Up to a 9x
  137. * speed up when alpha-blending and depth-test are enabled
  138. * at the same time.
  139. */
  140. if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
  141. nvbo->placement.fpfn = vram_pages / 2;
  142. nvbo->placement.lpfn = ~0;
  143. } else {
  144. nvbo->placement.fpfn = 0;
  145. nvbo->placement.lpfn = vram_pages / 2;
  146. }
  147. }
  148. }
  149. void
  150. nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
  151. {
  152. struct ttm_placement *pl = &nvbo->placement;
  153. uint32_t flags = TTM_PL_MASK_CACHING |
  154. (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
  155. pl->placement = nvbo->placements;
  156. set_placement_list(nvbo->placements, &pl->num_placement,
  157. type, flags);
  158. pl->busy_placement = nvbo->busy_placements;
  159. set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
  160. type | busy, flags);
  161. set_placement_range(nvbo, type);
  162. }
  163. int
  164. nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
  165. {
  166. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  167. struct ttm_buffer_object *bo = &nvbo->bo;
  168. int ret;
  169. if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
  170. NV_ERROR(nouveau_bdev(bo->bdev)->dev,
  171. "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
  172. 1 << bo->mem.mem_type, memtype);
  173. return -EINVAL;
  174. }
  175. if (nvbo->pin_refcnt++)
  176. return 0;
  177. ret = ttm_bo_reserve(bo, false, false, false, 0);
  178. if (ret)
  179. goto out;
  180. nouveau_bo_placement_set(nvbo, memtype, 0);
  181. ret = nouveau_bo_validate(nvbo, false, false, false);
  182. if (ret == 0) {
  183. switch (bo->mem.mem_type) {
  184. case TTM_PL_VRAM:
  185. dev_priv->fb_aper_free -= bo->mem.size;
  186. break;
  187. case TTM_PL_TT:
  188. dev_priv->gart_info.aper_free -= bo->mem.size;
  189. break;
  190. default:
  191. break;
  192. }
  193. }
  194. ttm_bo_unreserve(bo);
  195. out:
  196. if (unlikely(ret))
  197. nvbo->pin_refcnt--;
  198. return ret;
  199. }
  200. int
  201. nouveau_bo_unpin(struct nouveau_bo *nvbo)
  202. {
  203. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  204. struct ttm_buffer_object *bo = &nvbo->bo;
  205. int ret;
  206. if (--nvbo->pin_refcnt)
  207. return 0;
  208. ret = ttm_bo_reserve(bo, false, false, false, 0);
  209. if (ret)
  210. return ret;
  211. nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
  212. ret = nouveau_bo_validate(nvbo, false, false, false);
  213. if (ret == 0) {
  214. switch (bo->mem.mem_type) {
  215. case TTM_PL_VRAM:
  216. dev_priv->fb_aper_free += bo->mem.size;
  217. break;
  218. case TTM_PL_TT:
  219. dev_priv->gart_info.aper_free += bo->mem.size;
  220. break;
  221. default:
  222. break;
  223. }
  224. }
  225. ttm_bo_unreserve(bo);
  226. return ret;
  227. }
  228. int
  229. nouveau_bo_map(struct nouveau_bo *nvbo)
  230. {
  231. int ret;
  232. ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
  233. if (ret)
  234. return ret;
  235. ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
  236. ttm_bo_unreserve(&nvbo->bo);
  237. return ret;
  238. }
  239. void
  240. nouveau_bo_unmap(struct nouveau_bo *nvbo)
  241. {
  242. if (nvbo)
  243. ttm_bo_kunmap(&nvbo->kmap);
  244. }
  245. int
  246. nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
  247. bool no_wait_reserve, bool no_wait_gpu)
  248. {
  249. int ret;
  250. ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
  251. no_wait_reserve, no_wait_gpu);
  252. if (ret)
  253. return ret;
  254. return 0;
  255. }
  256. u16
  257. nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
  258. {
  259. bool is_iomem;
  260. u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  261. mem = &mem[index];
  262. if (is_iomem)
  263. return ioread16_native((void __force __iomem *)mem);
  264. else
  265. return *mem;
  266. }
  267. void
  268. nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
  269. {
  270. bool is_iomem;
  271. u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  272. mem = &mem[index];
  273. if (is_iomem)
  274. iowrite16_native(val, (void __force __iomem *)mem);
  275. else
  276. *mem = val;
  277. }
  278. u32
  279. nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
  280. {
  281. bool is_iomem;
  282. u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  283. mem = &mem[index];
  284. if (is_iomem)
  285. return ioread32_native((void __force __iomem *)mem);
  286. else
  287. return *mem;
  288. }
  289. void
  290. nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
  291. {
  292. bool is_iomem;
  293. u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  294. mem = &mem[index];
  295. if (is_iomem)
  296. iowrite32_native(val, (void __force __iomem *)mem);
  297. else
  298. *mem = val;
  299. }
  300. static struct ttm_tt *
  301. nouveau_ttm_tt_create(struct ttm_bo_device *bdev,
  302. unsigned long size, uint32_t page_flags,
  303. struct page *dummy_read_page)
  304. {
  305. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  306. struct drm_device *dev = dev_priv->dev;
  307. switch (dev_priv->gart_info.type) {
  308. #if __OS_HAS_AGP
  309. case NOUVEAU_GART_AGP:
  310. return ttm_agp_tt_create(bdev, dev->agp->bridge,
  311. size, page_flags, dummy_read_page);
  312. #endif
  313. case NOUVEAU_GART_PDMA:
  314. case NOUVEAU_GART_HW:
  315. return nouveau_sgdma_create_ttm(bdev, size, page_flags,
  316. dummy_read_page);
  317. default:
  318. NV_ERROR(dev, "Unknown GART type %d\n",
  319. dev_priv->gart_info.type);
  320. break;
  321. }
  322. return NULL;
  323. }
  324. static int
  325. nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  326. {
  327. /* We'll do this from user space. */
  328. return 0;
  329. }
  330. static int
  331. nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  332. struct ttm_mem_type_manager *man)
  333. {
  334. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  335. struct drm_device *dev = dev_priv->dev;
  336. switch (type) {
  337. case TTM_PL_SYSTEM:
  338. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  339. man->available_caching = TTM_PL_MASK_CACHING;
  340. man->default_caching = TTM_PL_FLAG_CACHED;
  341. break;
  342. case TTM_PL_VRAM:
  343. if (dev_priv->card_type >= NV_50) {
  344. man->func = &nouveau_vram_manager;
  345. man->io_reserve_fastpath = false;
  346. man->use_io_reserve_lru = true;
  347. } else {
  348. man->func = &ttm_bo_manager_func;
  349. }
  350. man->flags = TTM_MEMTYPE_FLAG_FIXED |
  351. TTM_MEMTYPE_FLAG_MAPPABLE;
  352. man->available_caching = TTM_PL_FLAG_UNCACHED |
  353. TTM_PL_FLAG_WC;
  354. man->default_caching = TTM_PL_FLAG_WC;
  355. break;
  356. case TTM_PL_TT:
  357. if (dev_priv->card_type >= NV_50)
  358. man->func = &nouveau_gart_manager;
  359. else
  360. man->func = &ttm_bo_manager_func;
  361. switch (dev_priv->gart_info.type) {
  362. case NOUVEAU_GART_AGP:
  363. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  364. man->available_caching = TTM_PL_FLAG_UNCACHED |
  365. TTM_PL_FLAG_WC;
  366. man->default_caching = TTM_PL_FLAG_WC;
  367. break;
  368. case NOUVEAU_GART_PDMA:
  369. case NOUVEAU_GART_HW:
  370. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
  371. TTM_MEMTYPE_FLAG_CMA;
  372. man->available_caching = TTM_PL_MASK_CACHING;
  373. man->default_caching = TTM_PL_FLAG_CACHED;
  374. break;
  375. default:
  376. NV_ERROR(dev, "Unknown GART type: %d\n",
  377. dev_priv->gart_info.type);
  378. return -EINVAL;
  379. }
  380. break;
  381. default:
  382. NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
  383. return -EINVAL;
  384. }
  385. return 0;
  386. }
  387. static void
  388. nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
  389. {
  390. struct nouveau_bo *nvbo = nouveau_bo(bo);
  391. switch (bo->mem.mem_type) {
  392. case TTM_PL_VRAM:
  393. nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
  394. TTM_PL_FLAG_SYSTEM);
  395. break;
  396. default:
  397. nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
  398. break;
  399. }
  400. *pl = nvbo->placement;
  401. }
  402. /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
  403. * TTM_PL_{VRAM,TT} directly.
  404. */
  405. static int
  406. nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
  407. struct nouveau_bo *nvbo, bool evict,
  408. bool no_wait_reserve, bool no_wait_gpu,
  409. struct ttm_mem_reg *new_mem)
  410. {
  411. struct nouveau_fence *fence = NULL;
  412. int ret;
  413. ret = nouveau_fence_new(chan, &fence, true);
  414. if (ret)
  415. return ret;
  416. ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
  417. no_wait_reserve, no_wait_gpu, new_mem);
  418. nouveau_fence_unref(&fence);
  419. return ret;
  420. }
  421. static int
  422. nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
  423. struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
  424. {
  425. struct nouveau_mem *node = old_mem->mm_node;
  426. u64 src_offset = node->vma[0].offset;
  427. u64 dst_offset = node->vma[1].offset;
  428. u32 page_count = new_mem->num_pages;
  429. int ret;
  430. page_count = new_mem->num_pages;
  431. while (page_count) {
  432. int line_count = (page_count > 2047) ? 2047 : page_count;
  433. ret = RING_SPACE(chan, 12);
  434. if (ret)
  435. return ret;
  436. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2);
  437. OUT_RING (chan, upper_32_bits(dst_offset));
  438. OUT_RING (chan, lower_32_bits(dst_offset));
  439. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6);
  440. OUT_RING (chan, upper_32_bits(src_offset));
  441. OUT_RING (chan, lower_32_bits(src_offset));
  442. OUT_RING (chan, PAGE_SIZE); /* src_pitch */
  443. OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
  444. OUT_RING (chan, PAGE_SIZE); /* line_length */
  445. OUT_RING (chan, line_count);
  446. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1);
  447. OUT_RING (chan, 0x00100110);
  448. page_count -= line_count;
  449. src_offset += (PAGE_SIZE * line_count);
  450. dst_offset += (PAGE_SIZE * line_count);
  451. }
  452. return 0;
  453. }
  454. static int
  455. nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
  456. struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
  457. {
  458. struct nouveau_mem *node = old_mem->mm_node;
  459. struct nouveau_bo *nvbo = nouveau_bo(bo);
  460. u64 length = (new_mem->num_pages << PAGE_SHIFT);
  461. u64 src_offset = node->vma[0].offset;
  462. u64 dst_offset = node->vma[1].offset;
  463. int ret;
  464. while (length) {
  465. u32 amount, stride, height;
  466. amount = min(length, (u64)(4 * 1024 * 1024));
  467. stride = 16 * 4;
  468. height = amount / stride;
  469. if (new_mem->mem_type == TTM_PL_VRAM &&
  470. nouveau_bo_tile_layout(nvbo)) {
  471. ret = RING_SPACE(chan, 8);
  472. if (ret)
  473. return ret;
  474. BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
  475. OUT_RING (chan, 0);
  476. OUT_RING (chan, 0);
  477. OUT_RING (chan, stride);
  478. OUT_RING (chan, height);
  479. OUT_RING (chan, 1);
  480. OUT_RING (chan, 0);
  481. OUT_RING (chan, 0);
  482. } else {
  483. ret = RING_SPACE(chan, 2);
  484. if (ret)
  485. return ret;
  486. BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
  487. OUT_RING (chan, 1);
  488. }
  489. if (old_mem->mem_type == TTM_PL_VRAM &&
  490. nouveau_bo_tile_layout(nvbo)) {
  491. ret = RING_SPACE(chan, 8);
  492. if (ret)
  493. return ret;
  494. BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
  495. OUT_RING (chan, 0);
  496. OUT_RING (chan, 0);
  497. OUT_RING (chan, stride);
  498. OUT_RING (chan, height);
  499. OUT_RING (chan, 1);
  500. OUT_RING (chan, 0);
  501. OUT_RING (chan, 0);
  502. } else {
  503. ret = RING_SPACE(chan, 2);
  504. if (ret)
  505. return ret;
  506. BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
  507. OUT_RING (chan, 1);
  508. }
  509. ret = RING_SPACE(chan, 14);
  510. if (ret)
  511. return ret;
  512. BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
  513. OUT_RING (chan, upper_32_bits(src_offset));
  514. OUT_RING (chan, upper_32_bits(dst_offset));
  515. BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
  516. OUT_RING (chan, lower_32_bits(src_offset));
  517. OUT_RING (chan, lower_32_bits(dst_offset));
  518. OUT_RING (chan, stride);
  519. OUT_RING (chan, stride);
  520. OUT_RING (chan, stride);
  521. OUT_RING (chan, height);
  522. OUT_RING (chan, 0x00000101);
  523. OUT_RING (chan, 0x00000000);
  524. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
  525. OUT_RING (chan, 0);
  526. length -= amount;
  527. src_offset += amount;
  528. dst_offset += amount;
  529. }
  530. return 0;
  531. }
  532. static inline uint32_t
  533. nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
  534. struct nouveau_channel *chan, struct ttm_mem_reg *mem)
  535. {
  536. if (mem->mem_type == TTM_PL_TT)
  537. return chan->gart_handle;
  538. return chan->vram_handle;
  539. }
  540. static int
  541. nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
  542. struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
  543. {
  544. u32 src_offset = old_mem->start << PAGE_SHIFT;
  545. u32 dst_offset = new_mem->start << PAGE_SHIFT;
  546. u32 page_count = new_mem->num_pages;
  547. int ret;
  548. ret = RING_SPACE(chan, 3);
  549. if (ret)
  550. return ret;
  551. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
  552. OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
  553. OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
  554. page_count = new_mem->num_pages;
  555. while (page_count) {
  556. int line_count = (page_count > 2047) ? 2047 : page_count;
  557. ret = RING_SPACE(chan, 11);
  558. if (ret)
  559. return ret;
  560. BEGIN_RING(chan, NvSubM2MF,
  561. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  562. OUT_RING (chan, src_offset);
  563. OUT_RING (chan, dst_offset);
  564. OUT_RING (chan, PAGE_SIZE); /* src_pitch */
  565. OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
  566. OUT_RING (chan, PAGE_SIZE); /* line_length */
  567. OUT_RING (chan, line_count);
  568. OUT_RING (chan, 0x00000101);
  569. OUT_RING (chan, 0x00000000);
  570. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
  571. OUT_RING (chan, 0);
  572. page_count -= line_count;
  573. src_offset += (PAGE_SIZE * line_count);
  574. dst_offset += (PAGE_SIZE * line_count);
  575. }
  576. return 0;
  577. }
  578. static int
  579. nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
  580. struct ttm_mem_reg *mem, struct nouveau_vma *vma)
  581. {
  582. struct nouveau_mem *node = mem->mm_node;
  583. int ret;
  584. ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
  585. node->page_shift, NV_MEM_ACCESS_RO, vma);
  586. if (ret)
  587. return ret;
  588. if (mem->mem_type == TTM_PL_VRAM)
  589. nouveau_vm_map(vma, node);
  590. else
  591. nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
  592. return 0;
  593. }
  594. static int
  595. nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
  596. bool no_wait_reserve, bool no_wait_gpu,
  597. struct ttm_mem_reg *new_mem)
  598. {
  599. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  600. struct nouveau_channel *chan = chan = dev_priv->channel;
  601. struct nouveau_bo *nvbo = nouveau_bo(bo);
  602. struct ttm_mem_reg *old_mem = &bo->mem;
  603. int ret;
  604. mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
  605. /* create temporary vmas for the transfer and attach them to the
  606. * old nouveau_mem node, these will get cleaned up after ttm has
  607. * destroyed the ttm_mem_reg
  608. */
  609. if (dev_priv->card_type >= NV_50) {
  610. struct nouveau_mem *node = old_mem->mm_node;
  611. ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
  612. if (ret)
  613. goto out;
  614. ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
  615. if (ret)
  616. goto out;
  617. }
  618. if (dev_priv->card_type < NV_50)
  619. ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
  620. else
  621. if (dev_priv->card_type < NV_C0)
  622. ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
  623. else
  624. ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
  625. if (ret == 0) {
  626. ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
  627. no_wait_reserve,
  628. no_wait_gpu, new_mem);
  629. }
  630. out:
  631. mutex_unlock(&chan->mutex);
  632. return ret;
  633. }
  634. static int
  635. nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
  636. bool no_wait_reserve, bool no_wait_gpu,
  637. struct ttm_mem_reg *new_mem)
  638. {
  639. u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  640. struct ttm_placement placement;
  641. struct ttm_mem_reg tmp_mem;
  642. int ret;
  643. placement.fpfn = placement.lpfn = 0;
  644. placement.num_placement = placement.num_busy_placement = 1;
  645. placement.placement = placement.busy_placement = &placement_memtype;
  646. tmp_mem = *new_mem;
  647. tmp_mem.mm_node = NULL;
  648. ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
  649. if (ret)
  650. return ret;
  651. ret = ttm_tt_bind(bo->ttm, &tmp_mem);
  652. if (ret)
  653. goto out;
  654. ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
  655. if (ret)
  656. goto out;
  657. ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
  658. out:
  659. ttm_bo_mem_put(bo, &tmp_mem);
  660. return ret;
  661. }
  662. static int
  663. nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
  664. bool no_wait_reserve, bool no_wait_gpu,
  665. struct ttm_mem_reg *new_mem)
  666. {
  667. u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  668. struct ttm_placement placement;
  669. struct ttm_mem_reg tmp_mem;
  670. int ret;
  671. placement.fpfn = placement.lpfn = 0;
  672. placement.num_placement = placement.num_busy_placement = 1;
  673. placement.placement = placement.busy_placement = &placement_memtype;
  674. tmp_mem = *new_mem;
  675. tmp_mem.mm_node = NULL;
  676. ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
  677. if (ret)
  678. return ret;
  679. ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
  680. if (ret)
  681. goto out;
  682. ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
  683. if (ret)
  684. goto out;
  685. out:
  686. ttm_bo_mem_put(bo, &tmp_mem);
  687. return ret;
  688. }
  689. static void
  690. nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
  691. {
  692. struct nouveau_bo *nvbo = nouveau_bo(bo);
  693. struct nouveau_vma *vma;
  694. /* ttm can now (stupidly) pass the driver bos it didn't create... */
  695. if (bo->destroy != nouveau_bo_del_ttm)
  696. return;
  697. list_for_each_entry(vma, &nvbo->vma_list, head) {
  698. if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
  699. nouveau_vm_map(vma, new_mem->mm_node);
  700. } else
  701. if (new_mem && new_mem->mem_type == TTM_PL_TT &&
  702. nvbo->page_shift == vma->vm->spg_shift) {
  703. nouveau_vm_map_sg(vma, 0, new_mem->
  704. num_pages << PAGE_SHIFT,
  705. new_mem->mm_node);
  706. } else {
  707. nouveau_vm_unmap(vma);
  708. }
  709. }
  710. }
  711. static int
  712. nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
  713. struct nouveau_tile_reg **new_tile)
  714. {
  715. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  716. struct drm_device *dev = dev_priv->dev;
  717. struct nouveau_bo *nvbo = nouveau_bo(bo);
  718. u64 offset = new_mem->start << PAGE_SHIFT;
  719. *new_tile = NULL;
  720. if (new_mem->mem_type != TTM_PL_VRAM)
  721. return 0;
  722. if (dev_priv->card_type >= NV_10) {
  723. *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
  724. nvbo->tile_mode,
  725. nvbo->tile_flags);
  726. }
  727. return 0;
  728. }
  729. static void
  730. nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
  731. struct nouveau_tile_reg *new_tile,
  732. struct nouveau_tile_reg **old_tile)
  733. {
  734. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  735. struct drm_device *dev = dev_priv->dev;
  736. nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
  737. *old_tile = new_tile;
  738. }
  739. static int
  740. nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
  741. bool no_wait_reserve, bool no_wait_gpu,
  742. struct ttm_mem_reg *new_mem)
  743. {
  744. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  745. struct nouveau_bo *nvbo = nouveau_bo(bo);
  746. struct ttm_mem_reg *old_mem = &bo->mem;
  747. struct nouveau_tile_reg *new_tile = NULL;
  748. int ret = 0;
  749. if (dev_priv->card_type < NV_50) {
  750. ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
  751. if (ret)
  752. return ret;
  753. }
  754. /* Fake bo copy. */
  755. if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
  756. BUG_ON(bo->mem.mm_node != NULL);
  757. bo->mem = *new_mem;
  758. new_mem->mm_node = NULL;
  759. goto out;
  760. }
  761. /* Software copy if the card isn't up and running yet. */
  762. if (!dev_priv->channel) {
  763. ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
  764. goto out;
  765. }
  766. /* Hardware assisted copy. */
  767. if (new_mem->mem_type == TTM_PL_SYSTEM)
  768. ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  769. else if (old_mem->mem_type == TTM_PL_SYSTEM)
  770. ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  771. else
  772. ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  773. if (!ret)
  774. goto out;
  775. /* Fallback to software copy. */
  776. ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
  777. out:
  778. if (dev_priv->card_type < NV_50) {
  779. if (ret)
  780. nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
  781. else
  782. nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
  783. }
  784. return ret;
  785. }
  786. static int
  787. nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  788. {
  789. return 0;
  790. }
  791. static int
  792. nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  793. {
  794. struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
  795. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  796. struct drm_device *dev = dev_priv->dev;
  797. int ret;
  798. mem->bus.addr = NULL;
  799. mem->bus.offset = 0;
  800. mem->bus.size = mem->num_pages << PAGE_SHIFT;
  801. mem->bus.base = 0;
  802. mem->bus.is_iomem = false;
  803. if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
  804. return -EINVAL;
  805. switch (mem->mem_type) {
  806. case TTM_PL_SYSTEM:
  807. /* System memory */
  808. return 0;
  809. case TTM_PL_TT:
  810. #if __OS_HAS_AGP
  811. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  812. mem->bus.offset = mem->start << PAGE_SHIFT;
  813. mem->bus.base = dev_priv->gart_info.aper_base;
  814. mem->bus.is_iomem = true;
  815. }
  816. #endif
  817. break;
  818. case TTM_PL_VRAM:
  819. {
  820. struct nouveau_mem *node = mem->mm_node;
  821. u8 page_shift;
  822. if (!dev_priv->bar1_vm) {
  823. mem->bus.offset = mem->start << PAGE_SHIFT;
  824. mem->bus.base = pci_resource_start(dev->pdev, 1);
  825. mem->bus.is_iomem = true;
  826. break;
  827. }
  828. if (dev_priv->card_type >= NV_C0)
  829. page_shift = node->page_shift;
  830. else
  831. page_shift = 12;
  832. ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
  833. page_shift, NV_MEM_ACCESS_RW,
  834. &node->bar_vma);
  835. if (ret)
  836. return ret;
  837. nouveau_vm_map(&node->bar_vma, node);
  838. if (ret) {
  839. nouveau_vm_put(&node->bar_vma);
  840. return ret;
  841. }
  842. mem->bus.offset = node->bar_vma.offset;
  843. if (dev_priv->card_type == NV_50) /*XXX*/
  844. mem->bus.offset -= 0x0020000000ULL;
  845. mem->bus.base = pci_resource_start(dev->pdev, 1);
  846. mem->bus.is_iomem = true;
  847. }
  848. break;
  849. default:
  850. return -EINVAL;
  851. }
  852. return 0;
  853. }
  854. static void
  855. nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  856. {
  857. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  858. struct nouveau_mem *node = mem->mm_node;
  859. if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
  860. return;
  861. if (!node->bar_vma.node)
  862. return;
  863. nouveau_vm_unmap(&node->bar_vma);
  864. nouveau_vm_put(&node->bar_vma);
  865. }
  866. static int
  867. nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
  868. {
  869. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  870. struct nouveau_bo *nvbo = nouveau_bo(bo);
  871. /* as long as the bo isn't in vram, and isn't tiled, we've got
  872. * nothing to do here.
  873. */
  874. if (bo->mem.mem_type != TTM_PL_VRAM) {
  875. if (dev_priv->card_type < NV_50 ||
  876. !nouveau_bo_tile_layout(nvbo))
  877. return 0;
  878. }
  879. /* make sure bo is in mappable vram */
  880. if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
  881. return 0;
  882. nvbo->placement.fpfn = 0;
  883. nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
  884. nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
  885. return nouveau_bo_validate(nvbo, false, true, false);
  886. }
  887. void
  888. nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
  889. {
  890. struct nouveau_fence *old_fence;
  891. if (likely(fence))
  892. nouveau_fence_ref(fence);
  893. spin_lock(&nvbo->bo.bdev->fence_lock);
  894. old_fence = nvbo->bo.sync_obj;
  895. nvbo->bo.sync_obj = fence;
  896. spin_unlock(&nvbo->bo.bdev->fence_lock);
  897. nouveau_fence_unref(&old_fence);
  898. }
  899. static int
  900. nouveau_ttm_tt_populate(struct ttm_tt *ttm)
  901. {
  902. struct ttm_dma_tt *ttm_dma = (void *)ttm;
  903. struct drm_nouveau_private *dev_priv;
  904. struct drm_device *dev;
  905. unsigned i;
  906. int r;
  907. if (ttm->state != tt_unpopulated)
  908. return 0;
  909. dev_priv = nouveau_bdev(ttm->bdev);
  910. dev = dev_priv->dev;
  911. #if __OS_HAS_AGP
  912. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  913. return ttm_agp_tt_populate(ttm);
  914. }
  915. #endif
  916. #ifdef CONFIG_SWIOTLB
  917. if (swiotlb_nr_tbl()) {
  918. return ttm_dma_populate((void *)ttm, dev->dev);
  919. }
  920. #endif
  921. r = ttm_pool_populate(ttm);
  922. if (r) {
  923. return r;
  924. }
  925. for (i = 0; i < ttm->num_pages; i++) {
  926. ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
  927. 0, PAGE_SIZE,
  928. PCI_DMA_BIDIRECTIONAL);
  929. if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
  930. while (--i) {
  931. pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
  932. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  933. ttm_dma->dma_address[i] = 0;
  934. }
  935. ttm_pool_unpopulate(ttm);
  936. return -EFAULT;
  937. }
  938. }
  939. return 0;
  940. }
  941. static void
  942. nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
  943. {
  944. struct ttm_dma_tt *ttm_dma = (void *)ttm;
  945. struct drm_nouveau_private *dev_priv;
  946. struct drm_device *dev;
  947. unsigned i;
  948. dev_priv = nouveau_bdev(ttm->bdev);
  949. dev = dev_priv->dev;
  950. #if __OS_HAS_AGP
  951. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  952. ttm_agp_tt_unpopulate(ttm);
  953. return;
  954. }
  955. #endif
  956. #ifdef CONFIG_SWIOTLB
  957. if (swiotlb_nr_tbl()) {
  958. ttm_dma_unpopulate((void *)ttm, dev->dev);
  959. return;
  960. }
  961. #endif
  962. for (i = 0; i < ttm->num_pages; i++) {
  963. if (ttm_dma->dma_address[i]) {
  964. pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
  965. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  966. }
  967. }
  968. ttm_pool_unpopulate(ttm);
  969. }
  970. struct ttm_bo_driver nouveau_bo_driver = {
  971. .ttm_tt_create = &nouveau_ttm_tt_create,
  972. .ttm_tt_populate = &nouveau_ttm_tt_populate,
  973. .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
  974. .invalidate_caches = nouveau_bo_invalidate_caches,
  975. .init_mem_type = nouveau_bo_init_mem_type,
  976. .evict_flags = nouveau_bo_evict_flags,
  977. .move_notify = nouveau_bo_move_ntfy,
  978. .move = nouveau_bo_move,
  979. .verify_access = nouveau_bo_verify_access,
  980. .sync_obj_signaled = __nouveau_fence_signalled,
  981. .sync_obj_wait = __nouveau_fence_wait,
  982. .sync_obj_flush = __nouveau_fence_flush,
  983. .sync_obj_unref = __nouveau_fence_unref,
  984. .sync_obj_ref = __nouveau_fence_ref,
  985. .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
  986. .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
  987. .io_mem_free = &nouveau_ttm_io_mem_free,
  988. };
  989. struct nouveau_vma *
  990. nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
  991. {
  992. struct nouveau_vma *vma;
  993. list_for_each_entry(vma, &nvbo->vma_list, head) {
  994. if (vma->vm == vm)
  995. return vma;
  996. }
  997. return NULL;
  998. }
  999. int
  1000. nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
  1001. struct nouveau_vma *vma)
  1002. {
  1003. const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
  1004. struct nouveau_mem *node = nvbo->bo.mem.mm_node;
  1005. int ret;
  1006. ret = nouveau_vm_get(vm, size, nvbo->page_shift,
  1007. NV_MEM_ACCESS_RW, vma);
  1008. if (ret)
  1009. return ret;
  1010. if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
  1011. nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
  1012. else
  1013. if (nvbo->bo.mem.mem_type == TTM_PL_TT)
  1014. nouveau_vm_map_sg(vma, 0, size, node);
  1015. list_add_tail(&vma->head, &nvbo->vma_list);
  1016. vma->refcount = 1;
  1017. return 0;
  1018. }
  1019. void
  1020. nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
  1021. {
  1022. if (vma->node) {
  1023. if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
  1024. spin_lock(&nvbo->bo.bdev->fence_lock);
  1025. ttm_bo_wait(&nvbo->bo, false, false, false);
  1026. spin_unlock(&nvbo->bo.bdev->fence_lock);
  1027. nouveau_vm_unmap(vma);
  1028. }
  1029. nouveau_vm_put(vma);
  1030. list_del(&vma->head);
  1031. }
  1032. }