intel_sdvo.c 78 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "drm_crtc.h"
  35. #include "drm_edid.h"
  36. #include "intel_drv.h"
  37. #include "i915_drm.h"
  38. #include "i915_drv.h"
  39. #include "intel_sdvo_regs.h"
  40. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  41. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  42. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  43. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  44. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  45. SDVO_TV_MASK)
  46. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  47. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  48. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  49. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  50. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  51. static const char *tv_format_names[] = {
  52. "NTSC_M" , "NTSC_J" , "NTSC_443",
  53. "PAL_B" , "PAL_D" , "PAL_G" ,
  54. "PAL_H" , "PAL_I" , "PAL_M" ,
  55. "PAL_N" , "PAL_NC" , "PAL_60" ,
  56. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  57. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  58. "SECAM_60"
  59. };
  60. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  61. struct intel_sdvo {
  62. struct intel_encoder base;
  63. struct i2c_adapter *i2c;
  64. u8 slave_addr;
  65. struct i2c_adapter ddc;
  66. /* Register for the SDVO device: SDVOB or SDVOC */
  67. int sdvo_reg;
  68. /* Active outputs controlled by this SDVO output */
  69. uint16_t controlled_output;
  70. /*
  71. * Capabilities of the SDVO device returned by
  72. * i830_sdvo_get_capabilities()
  73. */
  74. struct intel_sdvo_caps caps;
  75. /* Pixel clock limitations reported by the SDVO device, in kHz */
  76. int pixel_clock_min, pixel_clock_max;
  77. /*
  78. * For multiple function SDVO device,
  79. * this is for current attached outputs.
  80. */
  81. uint16_t attached_output;
  82. /*
  83. * Hotplug activation bits for this device
  84. */
  85. uint8_t hotplug_active[2];
  86. /**
  87. * This is used to select the color range of RBG outputs in HDMI mode.
  88. * It is only valid when using TMDS encoding and 8 bit per color mode.
  89. */
  90. uint32_t color_range;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* This is for current tv format name */
  100. int tv_format_index;
  101. /**
  102. * This is set if we treat the device as HDMI, instead of DVI.
  103. */
  104. bool is_hdmi;
  105. bool has_hdmi_monitor;
  106. bool has_hdmi_audio;
  107. /**
  108. * This is set if we detect output of sdvo device as LVDS and
  109. * have a valid fixed mode to use with the panel.
  110. */
  111. bool is_lvds;
  112. /**
  113. * This is sdvo fixed pannel mode pointer
  114. */
  115. struct drm_display_mode *sdvo_lvds_fixed_mode;
  116. /* DDC bus used by this SDVO encoder */
  117. uint8_t ddc_bus;
  118. /* Input timings for adjusted_mode */
  119. struct intel_sdvo_dtd input_dtd;
  120. };
  121. struct intel_sdvo_connector {
  122. struct intel_connector base;
  123. /* Mark the type of connector */
  124. uint16_t output_flag;
  125. enum hdmi_force_audio force_audio;
  126. /* This contains all current supported TV format */
  127. u8 tv_format_supported[TV_FORMAT_NUM];
  128. int format_supported_num;
  129. struct drm_property *tv_format;
  130. /* add the property for the SDVO-TV */
  131. struct drm_property *left;
  132. struct drm_property *right;
  133. struct drm_property *top;
  134. struct drm_property *bottom;
  135. struct drm_property *hpos;
  136. struct drm_property *vpos;
  137. struct drm_property *contrast;
  138. struct drm_property *saturation;
  139. struct drm_property *hue;
  140. struct drm_property *sharpness;
  141. struct drm_property *flicker_filter;
  142. struct drm_property *flicker_filter_adaptive;
  143. struct drm_property *flicker_filter_2d;
  144. struct drm_property *tv_chroma_filter;
  145. struct drm_property *tv_luma_filter;
  146. struct drm_property *dot_crawl;
  147. /* add the property for the SDVO-TV/LVDS */
  148. struct drm_property *brightness;
  149. /* Add variable to record current setting for the above property */
  150. u32 left_margin, right_margin, top_margin, bottom_margin;
  151. /* this is to get the range of margin.*/
  152. u32 max_hscan, max_vscan;
  153. u32 max_hpos, cur_hpos;
  154. u32 max_vpos, cur_vpos;
  155. u32 cur_brightness, max_brightness;
  156. u32 cur_contrast, max_contrast;
  157. u32 cur_saturation, max_saturation;
  158. u32 cur_hue, max_hue;
  159. u32 cur_sharpness, max_sharpness;
  160. u32 cur_flicker_filter, max_flicker_filter;
  161. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  162. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  163. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  164. u32 cur_tv_luma_filter, max_tv_luma_filter;
  165. u32 cur_dot_crawl, max_dot_crawl;
  166. };
  167. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  168. {
  169. return container_of(encoder, struct intel_sdvo, base.base);
  170. }
  171. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  172. {
  173. return container_of(intel_attached_encoder(connector),
  174. struct intel_sdvo, base);
  175. }
  176. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  177. {
  178. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  179. }
  180. static bool
  181. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  182. static bool
  183. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  184. struct intel_sdvo_connector *intel_sdvo_connector,
  185. int type);
  186. static bool
  187. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  188. struct intel_sdvo_connector *intel_sdvo_connector);
  189. /**
  190. * Writes the SDVOB or SDVOC with the given value, but always writes both
  191. * SDVOB and SDVOC to work around apparent hardware issues (according to
  192. * comments in the BIOS).
  193. */
  194. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  195. {
  196. struct drm_device *dev = intel_sdvo->base.base.dev;
  197. struct drm_i915_private *dev_priv = dev->dev_private;
  198. u32 bval = val, cval = val;
  199. int i;
  200. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  201. I915_WRITE(intel_sdvo->sdvo_reg, val);
  202. I915_READ(intel_sdvo->sdvo_reg);
  203. return;
  204. }
  205. if (intel_sdvo->sdvo_reg == SDVOB) {
  206. cval = I915_READ(SDVOC);
  207. } else {
  208. bval = I915_READ(SDVOB);
  209. }
  210. /*
  211. * Write the registers twice for luck. Sometimes,
  212. * writing them only once doesn't appear to 'stick'.
  213. * The BIOS does this too. Yay, magic
  214. */
  215. for (i = 0; i < 2; i++)
  216. {
  217. I915_WRITE(SDVOB, bval);
  218. I915_READ(SDVOB);
  219. I915_WRITE(SDVOC, cval);
  220. I915_READ(SDVOC);
  221. }
  222. }
  223. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  224. {
  225. struct i2c_msg msgs[] = {
  226. {
  227. .addr = intel_sdvo->slave_addr,
  228. .flags = 0,
  229. .len = 1,
  230. .buf = &addr,
  231. },
  232. {
  233. .addr = intel_sdvo->slave_addr,
  234. .flags = I2C_M_RD,
  235. .len = 1,
  236. .buf = ch,
  237. }
  238. };
  239. int ret;
  240. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  241. return true;
  242. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  243. return false;
  244. }
  245. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  246. /** Mapping of command numbers to names, for debug output */
  247. static const struct _sdvo_cmd_name {
  248. u8 cmd;
  249. const char *name;
  250. } sdvo_cmd_names[] = {
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  294. /* Add the op code for SDVO enhancements */
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  339. /* HDMI op code */
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  360. };
  361. #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
  362. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  363. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  364. const void *args, int args_len)
  365. {
  366. int i;
  367. DRM_DEBUG_KMS("%s: W: %02X ",
  368. SDVO_NAME(intel_sdvo), cmd);
  369. for (i = 0; i < args_len; i++)
  370. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  371. for (; i < 8; i++)
  372. DRM_LOG_KMS(" ");
  373. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  374. if (cmd == sdvo_cmd_names[i].cmd) {
  375. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  376. break;
  377. }
  378. }
  379. if (i == ARRAY_SIZE(sdvo_cmd_names))
  380. DRM_LOG_KMS("(%02X)", cmd);
  381. DRM_LOG_KMS("\n");
  382. }
  383. static const char *cmd_status_names[] = {
  384. "Power on",
  385. "Success",
  386. "Not supported",
  387. "Invalid arg",
  388. "Pending",
  389. "Target not specified",
  390. "Scaling not supported"
  391. };
  392. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  393. const void *args, int args_len)
  394. {
  395. u8 buf[args_len*2 + 2], status;
  396. struct i2c_msg msgs[args_len + 3];
  397. int i, ret;
  398. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  399. for (i = 0; i < args_len; i++) {
  400. msgs[i].addr = intel_sdvo->slave_addr;
  401. msgs[i].flags = 0;
  402. msgs[i].len = 2;
  403. msgs[i].buf = buf + 2 *i;
  404. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  405. buf[2*i + 1] = ((u8*)args)[i];
  406. }
  407. msgs[i].addr = intel_sdvo->slave_addr;
  408. msgs[i].flags = 0;
  409. msgs[i].len = 2;
  410. msgs[i].buf = buf + 2*i;
  411. buf[2*i + 0] = SDVO_I2C_OPCODE;
  412. buf[2*i + 1] = cmd;
  413. /* the following two are to read the response */
  414. status = SDVO_I2C_CMD_STATUS;
  415. msgs[i+1].addr = intel_sdvo->slave_addr;
  416. msgs[i+1].flags = 0;
  417. msgs[i+1].len = 1;
  418. msgs[i+1].buf = &status;
  419. msgs[i+2].addr = intel_sdvo->slave_addr;
  420. msgs[i+2].flags = I2C_M_RD;
  421. msgs[i+2].len = 1;
  422. msgs[i+2].buf = &status;
  423. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  424. if (ret < 0) {
  425. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  426. return false;
  427. }
  428. if (ret != i+3) {
  429. /* failure in I2C transfer */
  430. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  431. return false;
  432. }
  433. return true;
  434. }
  435. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  436. void *response, int response_len)
  437. {
  438. u8 retry = 5;
  439. u8 status;
  440. int i;
  441. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  442. /*
  443. * The documentation states that all commands will be
  444. * processed within 15µs, and that we need only poll
  445. * the status byte a maximum of 3 times in order for the
  446. * command to be complete.
  447. *
  448. * Check 5 times in case the hardware failed to read the docs.
  449. */
  450. if (!intel_sdvo_read_byte(intel_sdvo,
  451. SDVO_I2C_CMD_STATUS,
  452. &status))
  453. goto log_fail;
  454. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  455. udelay(15);
  456. if (!intel_sdvo_read_byte(intel_sdvo,
  457. SDVO_I2C_CMD_STATUS,
  458. &status))
  459. goto log_fail;
  460. }
  461. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  462. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  463. else
  464. DRM_LOG_KMS("(??? %d)", status);
  465. if (status != SDVO_CMD_STATUS_SUCCESS)
  466. goto log_fail;
  467. /* Read the command response */
  468. for (i = 0; i < response_len; i++) {
  469. if (!intel_sdvo_read_byte(intel_sdvo,
  470. SDVO_I2C_RETURN_0 + i,
  471. &((u8 *)response)[i]))
  472. goto log_fail;
  473. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  474. }
  475. DRM_LOG_KMS("\n");
  476. return true;
  477. log_fail:
  478. DRM_LOG_KMS("... failed\n");
  479. return false;
  480. }
  481. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  482. {
  483. if (mode->clock >= 100000)
  484. return 1;
  485. else if (mode->clock >= 50000)
  486. return 2;
  487. else
  488. return 4;
  489. }
  490. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  491. u8 ddc_bus)
  492. {
  493. /* This must be the immediately preceding write before the i2c xfer */
  494. return intel_sdvo_write_cmd(intel_sdvo,
  495. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  496. &ddc_bus, 1);
  497. }
  498. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  499. {
  500. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  501. return false;
  502. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  503. }
  504. static bool
  505. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  506. {
  507. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  508. return false;
  509. return intel_sdvo_read_response(intel_sdvo, value, len);
  510. }
  511. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  512. {
  513. struct intel_sdvo_set_target_input_args targets = {0};
  514. return intel_sdvo_set_value(intel_sdvo,
  515. SDVO_CMD_SET_TARGET_INPUT,
  516. &targets, sizeof(targets));
  517. }
  518. /**
  519. * Return whether each input is trained.
  520. *
  521. * This function is making an assumption about the layout of the response,
  522. * which should be checked against the docs.
  523. */
  524. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  525. {
  526. struct intel_sdvo_get_trained_inputs_response response;
  527. BUILD_BUG_ON(sizeof(response) != 1);
  528. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  529. &response, sizeof(response)))
  530. return false;
  531. *input_1 = response.input0_trained;
  532. *input_2 = response.input1_trained;
  533. return true;
  534. }
  535. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  536. u16 outputs)
  537. {
  538. return intel_sdvo_set_value(intel_sdvo,
  539. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  540. &outputs, sizeof(outputs));
  541. }
  542. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  543. int mode)
  544. {
  545. u8 state = SDVO_ENCODER_STATE_ON;
  546. switch (mode) {
  547. case DRM_MODE_DPMS_ON:
  548. state = SDVO_ENCODER_STATE_ON;
  549. break;
  550. case DRM_MODE_DPMS_STANDBY:
  551. state = SDVO_ENCODER_STATE_STANDBY;
  552. break;
  553. case DRM_MODE_DPMS_SUSPEND:
  554. state = SDVO_ENCODER_STATE_SUSPEND;
  555. break;
  556. case DRM_MODE_DPMS_OFF:
  557. state = SDVO_ENCODER_STATE_OFF;
  558. break;
  559. }
  560. return intel_sdvo_set_value(intel_sdvo,
  561. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  562. }
  563. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  564. int *clock_min,
  565. int *clock_max)
  566. {
  567. struct intel_sdvo_pixel_clock_range clocks;
  568. BUILD_BUG_ON(sizeof(clocks) != 4);
  569. if (!intel_sdvo_get_value(intel_sdvo,
  570. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  571. &clocks, sizeof(clocks)))
  572. return false;
  573. /* Convert the values from units of 10 kHz to kHz. */
  574. *clock_min = clocks.min * 10;
  575. *clock_max = clocks.max * 10;
  576. return true;
  577. }
  578. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  579. u16 outputs)
  580. {
  581. return intel_sdvo_set_value(intel_sdvo,
  582. SDVO_CMD_SET_TARGET_OUTPUT,
  583. &outputs, sizeof(outputs));
  584. }
  585. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  586. struct intel_sdvo_dtd *dtd)
  587. {
  588. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  589. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  590. }
  591. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  592. struct intel_sdvo_dtd *dtd)
  593. {
  594. return intel_sdvo_set_timing(intel_sdvo,
  595. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  596. }
  597. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  598. struct intel_sdvo_dtd *dtd)
  599. {
  600. return intel_sdvo_set_timing(intel_sdvo,
  601. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  602. }
  603. static bool
  604. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  605. uint16_t clock,
  606. uint16_t width,
  607. uint16_t height)
  608. {
  609. struct intel_sdvo_preferred_input_timing_args args;
  610. memset(&args, 0, sizeof(args));
  611. args.clock = clock;
  612. args.width = width;
  613. args.height = height;
  614. args.interlace = 0;
  615. if (intel_sdvo->is_lvds &&
  616. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  617. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  618. args.scaled = 1;
  619. return intel_sdvo_set_value(intel_sdvo,
  620. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  621. &args, sizeof(args));
  622. }
  623. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  624. struct intel_sdvo_dtd *dtd)
  625. {
  626. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  627. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  628. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  629. &dtd->part1, sizeof(dtd->part1)) &&
  630. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  631. &dtd->part2, sizeof(dtd->part2));
  632. }
  633. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  634. {
  635. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  636. }
  637. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  638. const struct drm_display_mode *mode)
  639. {
  640. uint16_t width, height;
  641. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  642. uint16_t h_sync_offset, v_sync_offset;
  643. width = mode->crtc_hdisplay;
  644. height = mode->crtc_vdisplay;
  645. /* do some mode translations */
  646. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  647. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  648. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  649. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  650. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  651. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  652. dtd->part1.clock = mode->clock / 10;
  653. dtd->part1.h_active = width & 0xff;
  654. dtd->part1.h_blank = h_blank_len & 0xff;
  655. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  656. ((h_blank_len >> 8) & 0xf);
  657. dtd->part1.v_active = height & 0xff;
  658. dtd->part1.v_blank = v_blank_len & 0xff;
  659. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  660. ((v_blank_len >> 8) & 0xf);
  661. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  662. dtd->part2.h_sync_width = h_sync_len & 0xff;
  663. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  664. (v_sync_len & 0xf);
  665. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  666. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  667. ((v_sync_len & 0x30) >> 4);
  668. dtd->part2.dtd_flags = 0x18;
  669. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  670. dtd->part2.dtd_flags |= 0x2;
  671. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  672. dtd->part2.dtd_flags |= 0x4;
  673. dtd->part2.sdvo_flags = 0;
  674. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  675. dtd->part2.reserved = 0;
  676. }
  677. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  678. const struct intel_sdvo_dtd *dtd)
  679. {
  680. mode->hdisplay = dtd->part1.h_active;
  681. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  682. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  683. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  684. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  685. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  686. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  687. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  688. mode->vdisplay = dtd->part1.v_active;
  689. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  690. mode->vsync_start = mode->vdisplay;
  691. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  692. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  693. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  694. mode->vsync_end = mode->vsync_start +
  695. (dtd->part2.v_sync_off_width & 0xf);
  696. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  697. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  698. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  699. mode->clock = dtd->part1.clock * 10;
  700. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  701. if (dtd->part2.dtd_flags & 0x2)
  702. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  703. if (dtd->part2.dtd_flags & 0x4)
  704. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  705. }
  706. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  707. {
  708. struct intel_sdvo_encode encode;
  709. BUILD_BUG_ON(sizeof(encode) != 2);
  710. return intel_sdvo_get_value(intel_sdvo,
  711. SDVO_CMD_GET_SUPP_ENCODE,
  712. &encode, sizeof(encode));
  713. }
  714. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  715. uint8_t mode)
  716. {
  717. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  718. }
  719. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  720. uint8_t mode)
  721. {
  722. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  723. }
  724. #if 0
  725. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  726. {
  727. int i, j;
  728. uint8_t set_buf_index[2];
  729. uint8_t av_split;
  730. uint8_t buf_size;
  731. uint8_t buf[48];
  732. uint8_t *pos;
  733. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  734. for (i = 0; i <= av_split; i++) {
  735. set_buf_index[0] = i; set_buf_index[1] = 0;
  736. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  737. set_buf_index, 2);
  738. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  739. intel_sdvo_read_response(encoder, &buf_size, 1);
  740. pos = buf;
  741. for (j = 0; j <= buf_size; j += 8) {
  742. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  743. NULL, 0);
  744. intel_sdvo_read_response(encoder, pos, 8);
  745. pos += 8;
  746. }
  747. }
  748. }
  749. #endif
  750. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
  751. {
  752. struct dip_infoframe avi_if = {
  753. .type = DIP_TYPE_AVI,
  754. .ver = DIP_VERSION_AVI,
  755. .len = DIP_LEN_AVI,
  756. };
  757. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  758. uint8_t set_buf_index[2] = { 1, 0 };
  759. uint64_t *data = (uint64_t *)&avi_if;
  760. unsigned i;
  761. intel_dip_infoframe_csum(&avi_if);
  762. if (!intel_sdvo_set_value(intel_sdvo,
  763. SDVO_CMD_SET_HBUF_INDEX,
  764. set_buf_index, 2))
  765. return false;
  766. for (i = 0; i < sizeof(avi_if); i += 8) {
  767. if (!intel_sdvo_set_value(intel_sdvo,
  768. SDVO_CMD_SET_HBUF_DATA,
  769. data, 8))
  770. return false;
  771. data++;
  772. }
  773. return intel_sdvo_set_value(intel_sdvo,
  774. SDVO_CMD_SET_HBUF_TXRATE,
  775. &tx_rate, 1);
  776. }
  777. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  778. {
  779. struct intel_sdvo_tv_format format;
  780. uint32_t format_map;
  781. format_map = 1 << intel_sdvo->tv_format_index;
  782. memset(&format, 0, sizeof(format));
  783. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  784. BUILD_BUG_ON(sizeof(format) != 6);
  785. return intel_sdvo_set_value(intel_sdvo,
  786. SDVO_CMD_SET_TV_FORMAT,
  787. &format, sizeof(format));
  788. }
  789. static bool
  790. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  791. struct drm_display_mode *mode)
  792. {
  793. struct intel_sdvo_dtd output_dtd;
  794. if (!intel_sdvo_set_target_output(intel_sdvo,
  795. intel_sdvo->attached_output))
  796. return false;
  797. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  798. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  799. return false;
  800. return true;
  801. }
  802. static bool
  803. intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
  804. struct drm_display_mode *mode,
  805. struct drm_display_mode *adjusted_mode)
  806. {
  807. /* Reset the input timing to the screen. Assume always input 0. */
  808. if (!intel_sdvo_set_target_input(intel_sdvo))
  809. return false;
  810. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  811. mode->clock / 10,
  812. mode->hdisplay,
  813. mode->vdisplay))
  814. return false;
  815. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  816. &intel_sdvo->input_dtd))
  817. return false;
  818. intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
  819. return true;
  820. }
  821. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  822. struct drm_display_mode *mode,
  823. struct drm_display_mode *adjusted_mode)
  824. {
  825. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  826. int multiplier;
  827. /* We need to construct preferred input timings based on our
  828. * output timings. To do that, we have to set the output
  829. * timings, even though this isn't really the right place in
  830. * the sequence to do it. Oh well.
  831. */
  832. if (intel_sdvo->is_tv) {
  833. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  834. return false;
  835. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  836. mode,
  837. adjusted_mode);
  838. } else if (intel_sdvo->is_lvds) {
  839. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  840. intel_sdvo->sdvo_lvds_fixed_mode))
  841. return false;
  842. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  843. mode,
  844. adjusted_mode);
  845. }
  846. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  847. * SDVO device will factor out the multiplier during mode_set.
  848. */
  849. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  850. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  851. return true;
  852. }
  853. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  854. struct drm_display_mode *mode,
  855. struct drm_display_mode *adjusted_mode)
  856. {
  857. struct drm_device *dev = encoder->dev;
  858. struct drm_i915_private *dev_priv = dev->dev_private;
  859. struct drm_crtc *crtc = encoder->crtc;
  860. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  861. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  862. u32 sdvox;
  863. struct intel_sdvo_in_out_map in_out;
  864. struct intel_sdvo_dtd input_dtd;
  865. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  866. int rate;
  867. if (!mode)
  868. return;
  869. /* First, set the input mapping for the first input to our controlled
  870. * output. This is only correct if we're a single-input device, in
  871. * which case the first input is the output from the appropriate SDVO
  872. * channel on the motherboard. In a two-input device, the first input
  873. * will be SDVOB and the second SDVOC.
  874. */
  875. in_out.in0 = intel_sdvo->attached_output;
  876. in_out.in1 = 0;
  877. intel_sdvo_set_value(intel_sdvo,
  878. SDVO_CMD_SET_IN_OUT_MAP,
  879. &in_out, sizeof(in_out));
  880. /* Set the output timings to the screen */
  881. if (!intel_sdvo_set_target_output(intel_sdvo,
  882. intel_sdvo->attached_output))
  883. return;
  884. /* We have tried to get input timing in mode_fixup, and filled into
  885. * adjusted_mode.
  886. */
  887. if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
  888. input_dtd = intel_sdvo->input_dtd;
  889. } else {
  890. /* Set the output timing to the screen */
  891. if (!intel_sdvo_set_target_output(intel_sdvo,
  892. intel_sdvo->attached_output))
  893. return;
  894. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  895. (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
  896. }
  897. /* Set the input timing to the screen. Assume always input 0. */
  898. if (!intel_sdvo_set_target_input(intel_sdvo))
  899. return;
  900. if (intel_sdvo->has_hdmi_monitor) {
  901. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  902. intel_sdvo_set_colorimetry(intel_sdvo,
  903. SDVO_COLORIMETRY_RGB256);
  904. intel_sdvo_set_avi_infoframe(intel_sdvo);
  905. } else
  906. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  907. if (intel_sdvo->is_tv &&
  908. !intel_sdvo_set_tv_format(intel_sdvo))
  909. return;
  910. (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
  911. switch (pixel_multiplier) {
  912. default:
  913. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  914. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  915. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  916. }
  917. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  918. return;
  919. /* Set the SDVO control regs. */
  920. if (INTEL_INFO(dev)->gen >= 4) {
  921. /* The real mode polarity is set by the SDVO commands, using
  922. * struct intel_sdvo_dtd. */
  923. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  924. if (intel_sdvo->is_hdmi)
  925. sdvox |= intel_sdvo->color_range;
  926. if (INTEL_INFO(dev)->gen < 5)
  927. sdvox |= SDVO_BORDER_ENABLE;
  928. } else {
  929. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  930. switch (intel_sdvo->sdvo_reg) {
  931. case SDVOB:
  932. sdvox &= SDVOB_PRESERVE_MASK;
  933. break;
  934. case SDVOC:
  935. sdvox &= SDVOC_PRESERVE_MASK;
  936. break;
  937. }
  938. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  939. }
  940. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  941. sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
  942. else
  943. sdvox |= TRANSCODER(intel_crtc->pipe);
  944. if (intel_sdvo->has_hdmi_audio)
  945. sdvox |= SDVO_AUDIO_ENABLE;
  946. if (INTEL_INFO(dev)->gen >= 4) {
  947. /* done in crtc_mode_set as the dpll_md reg must be written early */
  948. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  949. /* done in crtc_mode_set as it lives inside the dpll register */
  950. } else {
  951. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  952. }
  953. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  954. INTEL_INFO(dev)->gen < 5)
  955. sdvox |= SDVO_STALL_SELECT;
  956. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  957. }
  958. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  959. {
  960. struct drm_device *dev = encoder->dev;
  961. struct drm_i915_private *dev_priv = dev->dev_private;
  962. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  963. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  964. u32 temp;
  965. if (mode != DRM_MODE_DPMS_ON) {
  966. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  967. if (0)
  968. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  969. if (mode == DRM_MODE_DPMS_OFF) {
  970. temp = I915_READ(intel_sdvo->sdvo_reg);
  971. if ((temp & SDVO_ENABLE) != 0) {
  972. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  973. }
  974. }
  975. } else {
  976. bool input1, input2;
  977. int i;
  978. u8 status;
  979. temp = I915_READ(intel_sdvo->sdvo_reg);
  980. if ((temp & SDVO_ENABLE) == 0)
  981. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  982. for (i = 0; i < 2; i++)
  983. intel_wait_for_vblank(dev, intel_crtc->pipe);
  984. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  985. /* Warn if the device reported failure to sync.
  986. * A lot of SDVO devices fail to notify of sync, but it's
  987. * a given it the status is a success, we succeeded.
  988. */
  989. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  990. DRM_DEBUG_KMS("First %s output reported failure to "
  991. "sync\n", SDVO_NAME(intel_sdvo));
  992. }
  993. if (0)
  994. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  995. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  996. }
  997. return;
  998. }
  999. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1000. struct drm_display_mode *mode)
  1001. {
  1002. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1003. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1004. return MODE_NO_DBLESCAN;
  1005. if (intel_sdvo->pixel_clock_min > mode->clock)
  1006. return MODE_CLOCK_LOW;
  1007. if (intel_sdvo->pixel_clock_max < mode->clock)
  1008. return MODE_CLOCK_HIGH;
  1009. if (intel_sdvo->is_lvds) {
  1010. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1011. return MODE_PANEL;
  1012. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1013. return MODE_PANEL;
  1014. }
  1015. return MODE_OK;
  1016. }
  1017. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1018. {
  1019. BUILD_BUG_ON(sizeof(*caps) != 8);
  1020. if (!intel_sdvo_get_value(intel_sdvo,
  1021. SDVO_CMD_GET_DEVICE_CAPS,
  1022. caps, sizeof(*caps)))
  1023. return false;
  1024. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1025. " vendor_id: %d\n"
  1026. " device_id: %d\n"
  1027. " device_rev_id: %d\n"
  1028. " sdvo_version_major: %d\n"
  1029. " sdvo_version_minor: %d\n"
  1030. " sdvo_inputs_mask: %d\n"
  1031. " smooth_scaling: %d\n"
  1032. " sharp_scaling: %d\n"
  1033. " up_scaling: %d\n"
  1034. " down_scaling: %d\n"
  1035. " stall_support: %d\n"
  1036. " output_flags: %d\n",
  1037. caps->vendor_id,
  1038. caps->device_id,
  1039. caps->device_rev_id,
  1040. caps->sdvo_version_major,
  1041. caps->sdvo_version_minor,
  1042. caps->sdvo_inputs_mask,
  1043. caps->smooth_scaling,
  1044. caps->sharp_scaling,
  1045. caps->up_scaling,
  1046. caps->down_scaling,
  1047. caps->stall_support,
  1048. caps->output_flags);
  1049. return true;
  1050. }
  1051. static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
  1052. {
  1053. u8 response[2];
  1054. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1055. &response, 2) && response[0];
  1056. }
  1057. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1058. {
  1059. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1060. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
  1061. }
  1062. static bool
  1063. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1064. {
  1065. /* Is there more than one type of output? */
  1066. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1067. }
  1068. static struct edid *
  1069. intel_sdvo_get_edid(struct drm_connector *connector)
  1070. {
  1071. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1072. return drm_get_edid(connector, &sdvo->ddc);
  1073. }
  1074. /* Mac mini hack -- use the same DDC as the analog connector */
  1075. static struct edid *
  1076. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1077. {
  1078. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1079. return drm_get_edid(connector,
  1080. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  1081. }
  1082. enum drm_connector_status
  1083. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1084. {
  1085. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1086. enum drm_connector_status status;
  1087. struct edid *edid;
  1088. edid = intel_sdvo_get_edid(connector);
  1089. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1090. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1091. /*
  1092. * Don't use the 1 as the argument of DDC bus switch to get
  1093. * the EDID. It is used for SDVO SPD ROM.
  1094. */
  1095. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1096. intel_sdvo->ddc_bus = ddc;
  1097. edid = intel_sdvo_get_edid(connector);
  1098. if (edid)
  1099. break;
  1100. }
  1101. /*
  1102. * If we found the EDID on the other bus,
  1103. * assume that is the correct DDC bus.
  1104. */
  1105. if (edid == NULL)
  1106. intel_sdvo->ddc_bus = saved_ddc;
  1107. }
  1108. /*
  1109. * When there is no edid and no monitor is connected with VGA
  1110. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1111. */
  1112. if (edid == NULL)
  1113. edid = intel_sdvo_get_analog_edid(connector);
  1114. status = connector_status_unknown;
  1115. if (edid != NULL) {
  1116. /* DDC bus is shared, match EDID to connector type */
  1117. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1118. status = connector_status_connected;
  1119. if (intel_sdvo->is_hdmi) {
  1120. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1121. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1122. }
  1123. } else
  1124. status = connector_status_disconnected;
  1125. connector->display_info.raw_edid = NULL;
  1126. kfree(edid);
  1127. }
  1128. if (status == connector_status_connected) {
  1129. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1130. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1131. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1132. }
  1133. return status;
  1134. }
  1135. static bool
  1136. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1137. struct edid *edid)
  1138. {
  1139. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1140. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1141. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1142. connector_is_digital, monitor_is_digital);
  1143. return connector_is_digital == monitor_is_digital;
  1144. }
  1145. static enum drm_connector_status
  1146. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1147. {
  1148. uint16_t response;
  1149. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1150. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1151. enum drm_connector_status ret;
  1152. if (!intel_sdvo_write_cmd(intel_sdvo,
  1153. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1154. return connector_status_unknown;
  1155. /* add 30ms delay when the output type might be TV */
  1156. if (intel_sdvo->caps.output_flags &
  1157. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
  1158. mdelay(30);
  1159. if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
  1160. return connector_status_unknown;
  1161. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1162. response & 0xff, response >> 8,
  1163. intel_sdvo_connector->output_flag);
  1164. if (response == 0)
  1165. return connector_status_disconnected;
  1166. intel_sdvo->attached_output = response;
  1167. intel_sdvo->has_hdmi_monitor = false;
  1168. intel_sdvo->has_hdmi_audio = false;
  1169. if ((intel_sdvo_connector->output_flag & response) == 0)
  1170. ret = connector_status_disconnected;
  1171. else if (IS_TMDS(intel_sdvo_connector))
  1172. ret = intel_sdvo_tmds_sink_detect(connector);
  1173. else {
  1174. struct edid *edid;
  1175. /* if we have an edid check it matches the connection */
  1176. edid = intel_sdvo_get_edid(connector);
  1177. if (edid == NULL)
  1178. edid = intel_sdvo_get_analog_edid(connector);
  1179. if (edid != NULL) {
  1180. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1181. edid))
  1182. ret = connector_status_connected;
  1183. else
  1184. ret = connector_status_disconnected;
  1185. connector->display_info.raw_edid = NULL;
  1186. kfree(edid);
  1187. } else
  1188. ret = connector_status_connected;
  1189. }
  1190. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1191. if (ret == connector_status_connected) {
  1192. intel_sdvo->is_tv = false;
  1193. intel_sdvo->is_lvds = false;
  1194. intel_sdvo->base.needs_tv_clock = false;
  1195. if (response & SDVO_TV_MASK) {
  1196. intel_sdvo->is_tv = true;
  1197. intel_sdvo->base.needs_tv_clock = true;
  1198. }
  1199. if (response & SDVO_LVDS_MASK)
  1200. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1201. }
  1202. return ret;
  1203. }
  1204. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1205. {
  1206. struct edid *edid;
  1207. /* set the bus switch and get the modes */
  1208. edid = intel_sdvo_get_edid(connector);
  1209. /*
  1210. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1211. * link between analog and digital outputs. So, if the regular SDVO
  1212. * DDC fails, check to see if the analog output is disconnected, in
  1213. * which case we'll look there for the digital DDC data.
  1214. */
  1215. if (edid == NULL)
  1216. edid = intel_sdvo_get_analog_edid(connector);
  1217. if (edid != NULL) {
  1218. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1219. edid)) {
  1220. drm_mode_connector_update_edid_property(connector, edid);
  1221. drm_add_edid_modes(connector, edid);
  1222. }
  1223. connector->display_info.raw_edid = NULL;
  1224. kfree(edid);
  1225. }
  1226. }
  1227. /*
  1228. * Set of SDVO TV modes.
  1229. * Note! This is in reply order (see loop in get_tv_modes).
  1230. * XXX: all 60Hz refresh?
  1231. */
  1232. static const struct drm_display_mode sdvo_tv_modes[] = {
  1233. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1234. 416, 0, 200, 201, 232, 233, 0,
  1235. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1236. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1237. 416, 0, 240, 241, 272, 273, 0,
  1238. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1239. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1240. 496, 0, 300, 301, 332, 333, 0,
  1241. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1242. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1243. 736, 0, 350, 351, 382, 383, 0,
  1244. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1245. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1246. 736, 0, 400, 401, 432, 433, 0,
  1247. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1248. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1249. 736, 0, 480, 481, 512, 513, 0,
  1250. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1251. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1252. 800, 0, 480, 481, 512, 513, 0,
  1253. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1254. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1255. 800, 0, 576, 577, 608, 609, 0,
  1256. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1257. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1258. 816, 0, 350, 351, 382, 383, 0,
  1259. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1260. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1261. 816, 0, 400, 401, 432, 433, 0,
  1262. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1263. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1264. 816, 0, 480, 481, 512, 513, 0,
  1265. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1266. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1267. 816, 0, 540, 541, 572, 573, 0,
  1268. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1269. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1270. 816, 0, 576, 577, 608, 609, 0,
  1271. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1272. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1273. 864, 0, 576, 577, 608, 609, 0,
  1274. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1275. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1276. 896, 0, 600, 601, 632, 633, 0,
  1277. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1278. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1279. 928, 0, 624, 625, 656, 657, 0,
  1280. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1281. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1282. 1016, 0, 766, 767, 798, 799, 0,
  1283. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1284. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1285. 1120, 0, 768, 769, 800, 801, 0,
  1286. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1287. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1288. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1289. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1290. };
  1291. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1292. {
  1293. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1294. struct intel_sdvo_sdtv_resolution_request tv_res;
  1295. uint32_t reply = 0, format_map = 0;
  1296. int i;
  1297. /* Read the list of supported input resolutions for the selected TV
  1298. * format.
  1299. */
  1300. format_map = 1 << intel_sdvo->tv_format_index;
  1301. memcpy(&tv_res, &format_map,
  1302. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1303. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1304. return;
  1305. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1306. if (!intel_sdvo_write_cmd(intel_sdvo,
  1307. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1308. &tv_res, sizeof(tv_res)))
  1309. return;
  1310. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1311. return;
  1312. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1313. if (reply & (1 << i)) {
  1314. struct drm_display_mode *nmode;
  1315. nmode = drm_mode_duplicate(connector->dev,
  1316. &sdvo_tv_modes[i]);
  1317. if (nmode)
  1318. drm_mode_probed_add(connector, nmode);
  1319. }
  1320. }
  1321. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1322. {
  1323. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1324. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1325. struct drm_display_mode *newmode;
  1326. /*
  1327. * Attempt to get the mode list from DDC.
  1328. * Assume that the preferred modes are
  1329. * arranged in priority order.
  1330. */
  1331. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1332. if (list_empty(&connector->probed_modes) == false)
  1333. goto end;
  1334. /* Fetch modes from VBT */
  1335. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1336. newmode = drm_mode_duplicate(connector->dev,
  1337. dev_priv->sdvo_lvds_vbt_mode);
  1338. if (newmode != NULL) {
  1339. /* Guarantee the mode is preferred */
  1340. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1341. DRM_MODE_TYPE_DRIVER);
  1342. drm_mode_probed_add(connector, newmode);
  1343. }
  1344. }
  1345. end:
  1346. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1347. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1348. intel_sdvo->sdvo_lvds_fixed_mode =
  1349. drm_mode_duplicate(connector->dev, newmode);
  1350. drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
  1351. 0);
  1352. intel_sdvo->is_lvds = true;
  1353. break;
  1354. }
  1355. }
  1356. }
  1357. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1358. {
  1359. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1360. if (IS_TV(intel_sdvo_connector))
  1361. intel_sdvo_get_tv_modes(connector);
  1362. else if (IS_LVDS(intel_sdvo_connector))
  1363. intel_sdvo_get_lvds_modes(connector);
  1364. else
  1365. intel_sdvo_get_ddc_modes(connector);
  1366. return !list_empty(&connector->probed_modes);
  1367. }
  1368. static void
  1369. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1370. {
  1371. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1372. struct drm_device *dev = connector->dev;
  1373. if (intel_sdvo_connector->left)
  1374. drm_property_destroy(dev, intel_sdvo_connector->left);
  1375. if (intel_sdvo_connector->right)
  1376. drm_property_destroy(dev, intel_sdvo_connector->right);
  1377. if (intel_sdvo_connector->top)
  1378. drm_property_destroy(dev, intel_sdvo_connector->top);
  1379. if (intel_sdvo_connector->bottom)
  1380. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1381. if (intel_sdvo_connector->hpos)
  1382. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1383. if (intel_sdvo_connector->vpos)
  1384. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1385. if (intel_sdvo_connector->saturation)
  1386. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1387. if (intel_sdvo_connector->contrast)
  1388. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1389. if (intel_sdvo_connector->hue)
  1390. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1391. if (intel_sdvo_connector->sharpness)
  1392. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1393. if (intel_sdvo_connector->flicker_filter)
  1394. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1395. if (intel_sdvo_connector->flicker_filter_2d)
  1396. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1397. if (intel_sdvo_connector->flicker_filter_adaptive)
  1398. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1399. if (intel_sdvo_connector->tv_luma_filter)
  1400. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1401. if (intel_sdvo_connector->tv_chroma_filter)
  1402. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1403. if (intel_sdvo_connector->dot_crawl)
  1404. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1405. if (intel_sdvo_connector->brightness)
  1406. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1407. }
  1408. static void intel_sdvo_destroy(struct drm_connector *connector)
  1409. {
  1410. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1411. if (intel_sdvo_connector->tv_format)
  1412. drm_property_destroy(connector->dev,
  1413. intel_sdvo_connector->tv_format);
  1414. intel_sdvo_destroy_enhance_property(connector);
  1415. drm_sysfs_connector_remove(connector);
  1416. drm_connector_cleanup(connector);
  1417. kfree(connector);
  1418. }
  1419. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1420. {
  1421. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1422. struct edid *edid;
  1423. bool has_audio = false;
  1424. if (!intel_sdvo->is_hdmi)
  1425. return false;
  1426. edid = intel_sdvo_get_edid(connector);
  1427. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1428. has_audio = drm_detect_monitor_audio(edid);
  1429. return has_audio;
  1430. }
  1431. static int
  1432. intel_sdvo_set_property(struct drm_connector *connector,
  1433. struct drm_property *property,
  1434. uint64_t val)
  1435. {
  1436. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1437. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1438. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1439. uint16_t temp_value;
  1440. uint8_t cmd;
  1441. int ret;
  1442. ret = drm_connector_property_set_value(connector, property, val);
  1443. if (ret)
  1444. return ret;
  1445. if (property == dev_priv->force_audio_property) {
  1446. int i = val;
  1447. bool has_audio;
  1448. if (i == intel_sdvo_connector->force_audio)
  1449. return 0;
  1450. intel_sdvo_connector->force_audio = i;
  1451. if (i == HDMI_AUDIO_AUTO)
  1452. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1453. else
  1454. has_audio = (i == HDMI_AUDIO_ON);
  1455. if (has_audio == intel_sdvo->has_hdmi_audio)
  1456. return 0;
  1457. intel_sdvo->has_hdmi_audio = has_audio;
  1458. goto done;
  1459. }
  1460. if (property == dev_priv->broadcast_rgb_property) {
  1461. if (val == !!intel_sdvo->color_range)
  1462. return 0;
  1463. intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1464. goto done;
  1465. }
  1466. #define CHECK_PROPERTY(name, NAME) \
  1467. if (intel_sdvo_connector->name == property) { \
  1468. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1469. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1470. cmd = SDVO_CMD_SET_##NAME; \
  1471. intel_sdvo_connector->cur_##name = temp_value; \
  1472. goto set_value; \
  1473. }
  1474. if (property == intel_sdvo_connector->tv_format) {
  1475. if (val >= TV_FORMAT_NUM)
  1476. return -EINVAL;
  1477. if (intel_sdvo->tv_format_index ==
  1478. intel_sdvo_connector->tv_format_supported[val])
  1479. return 0;
  1480. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1481. goto done;
  1482. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1483. temp_value = val;
  1484. if (intel_sdvo_connector->left == property) {
  1485. drm_connector_property_set_value(connector,
  1486. intel_sdvo_connector->right, val);
  1487. if (intel_sdvo_connector->left_margin == temp_value)
  1488. return 0;
  1489. intel_sdvo_connector->left_margin = temp_value;
  1490. intel_sdvo_connector->right_margin = temp_value;
  1491. temp_value = intel_sdvo_connector->max_hscan -
  1492. intel_sdvo_connector->left_margin;
  1493. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1494. goto set_value;
  1495. } else if (intel_sdvo_connector->right == property) {
  1496. drm_connector_property_set_value(connector,
  1497. intel_sdvo_connector->left, val);
  1498. if (intel_sdvo_connector->right_margin == temp_value)
  1499. return 0;
  1500. intel_sdvo_connector->left_margin = temp_value;
  1501. intel_sdvo_connector->right_margin = temp_value;
  1502. temp_value = intel_sdvo_connector->max_hscan -
  1503. intel_sdvo_connector->left_margin;
  1504. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1505. goto set_value;
  1506. } else if (intel_sdvo_connector->top == property) {
  1507. drm_connector_property_set_value(connector,
  1508. intel_sdvo_connector->bottom, val);
  1509. if (intel_sdvo_connector->top_margin == temp_value)
  1510. return 0;
  1511. intel_sdvo_connector->top_margin = temp_value;
  1512. intel_sdvo_connector->bottom_margin = temp_value;
  1513. temp_value = intel_sdvo_connector->max_vscan -
  1514. intel_sdvo_connector->top_margin;
  1515. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1516. goto set_value;
  1517. } else if (intel_sdvo_connector->bottom == property) {
  1518. drm_connector_property_set_value(connector,
  1519. intel_sdvo_connector->top, val);
  1520. if (intel_sdvo_connector->bottom_margin == temp_value)
  1521. return 0;
  1522. intel_sdvo_connector->top_margin = temp_value;
  1523. intel_sdvo_connector->bottom_margin = temp_value;
  1524. temp_value = intel_sdvo_connector->max_vscan -
  1525. intel_sdvo_connector->top_margin;
  1526. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1527. goto set_value;
  1528. }
  1529. CHECK_PROPERTY(hpos, HPOS)
  1530. CHECK_PROPERTY(vpos, VPOS)
  1531. CHECK_PROPERTY(saturation, SATURATION)
  1532. CHECK_PROPERTY(contrast, CONTRAST)
  1533. CHECK_PROPERTY(hue, HUE)
  1534. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1535. CHECK_PROPERTY(sharpness, SHARPNESS)
  1536. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1537. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1538. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1539. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1540. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1541. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1542. }
  1543. return -EINVAL; /* unknown property */
  1544. set_value:
  1545. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1546. return -EIO;
  1547. done:
  1548. if (intel_sdvo->base.base.crtc) {
  1549. struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
  1550. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1551. crtc->y, crtc->fb);
  1552. }
  1553. return 0;
  1554. #undef CHECK_PROPERTY
  1555. }
  1556. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1557. .dpms = intel_sdvo_dpms,
  1558. .mode_fixup = intel_sdvo_mode_fixup,
  1559. .prepare = intel_encoder_prepare,
  1560. .mode_set = intel_sdvo_mode_set,
  1561. .commit = intel_encoder_commit,
  1562. };
  1563. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1564. .dpms = drm_helper_connector_dpms,
  1565. .detect = intel_sdvo_detect,
  1566. .fill_modes = drm_helper_probe_single_connector_modes,
  1567. .set_property = intel_sdvo_set_property,
  1568. .destroy = intel_sdvo_destroy,
  1569. };
  1570. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1571. .get_modes = intel_sdvo_get_modes,
  1572. .mode_valid = intel_sdvo_mode_valid,
  1573. .best_encoder = intel_best_encoder,
  1574. };
  1575. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1576. {
  1577. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1578. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1579. drm_mode_destroy(encoder->dev,
  1580. intel_sdvo->sdvo_lvds_fixed_mode);
  1581. i2c_del_adapter(&intel_sdvo->ddc);
  1582. intel_encoder_destroy(encoder);
  1583. }
  1584. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1585. .destroy = intel_sdvo_enc_destroy,
  1586. };
  1587. static void
  1588. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1589. {
  1590. uint16_t mask = 0;
  1591. unsigned int num_bits;
  1592. /* Make a mask of outputs less than or equal to our own priority in the
  1593. * list.
  1594. */
  1595. switch (sdvo->controlled_output) {
  1596. case SDVO_OUTPUT_LVDS1:
  1597. mask |= SDVO_OUTPUT_LVDS1;
  1598. case SDVO_OUTPUT_LVDS0:
  1599. mask |= SDVO_OUTPUT_LVDS0;
  1600. case SDVO_OUTPUT_TMDS1:
  1601. mask |= SDVO_OUTPUT_TMDS1;
  1602. case SDVO_OUTPUT_TMDS0:
  1603. mask |= SDVO_OUTPUT_TMDS0;
  1604. case SDVO_OUTPUT_RGB1:
  1605. mask |= SDVO_OUTPUT_RGB1;
  1606. case SDVO_OUTPUT_RGB0:
  1607. mask |= SDVO_OUTPUT_RGB0;
  1608. break;
  1609. }
  1610. /* Count bits to find what number we are in the priority list. */
  1611. mask &= sdvo->caps.output_flags;
  1612. num_bits = hweight16(mask);
  1613. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1614. if (num_bits > 3)
  1615. num_bits = 3;
  1616. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1617. sdvo->ddc_bus = 1 << num_bits;
  1618. }
  1619. /**
  1620. * Choose the appropriate DDC bus for control bus switch command for this
  1621. * SDVO output based on the controlled output.
  1622. *
  1623. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1624. * outputs, then LVDS outputs.
  1625. */
  1626. static void
  1627. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1628. struct intel_sdvo *sdvo, u32 reg)
  1629. {
  1630. struct sdvo_device_mapping *mapping;
  1631. if (IS_SDVOB(reg))
  1632. mapping = &(dev_priv->sdvo_mappings[0]);
  1633. else
  1634. mapping = &(dev_priv->sdvo_mappings[1]);
  1635. if (mapping->initialized)
  1636. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1637. else
  1638. intel_sdvo_guess_ddc_bus(sdvo);
  1639. }
  1640. static void
  1641. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1642. struct intel_sdvo *sdvo, u32 reg)
  1643. {
  1644. struct sdvo_device_mapping *mapping;
  1645. u8 pin;
  1646. if (IS_SDVOB(reg))
  1647. mapping = &dev_priv->sdvo_mappings[0];
  1648. else
  1649. mapping = &dev_priv->sdvo_mappings[1];
  1650. pin = GMBUS_PORT_DPB;
  1651. if (mapping->initialized)
  1652. pin = mapping->i2c_pin;
  1653. if (pin < GMBUS_NUM_PORTS) {
  1654. sdvo->i2c = &dev_priv->gmbus[pin].adapter;
  1655. intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
  1656. intel_gmbus_force_bit(sdvo->i2c, true);
  1657. } else {
  1658. sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
  1659. }
  1660. }
  1661. static bool
  1662. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1663. {
  1664. return intel_sdvo_check_supp_encode(intel_sdvo);
  1665. }
  1666. static u8
  1667. intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1668. {
  1669. struct drm_i915_private *dev_priv = dev->dev_private;
  1670. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1671. if (IS_SDVOB(sdvo_reg)) {
  1672. my_mapping = &dev_priv->sdvo_mappings[0];
  1673. other_mapping = &dev_priv->sdvo_mappings[1];
  1674. } else {
  1675. my_mapping = &dev_priv->sdvo_mappings[1];
  1676. other_mapping = &dev_priv->sdvo_mappings[0];
  1677. }
  1678. /* If the BIOS described our SDVO device, take advantage of it. */
  1679. if (my_mapping->slave_addr)
  1680. return my_mapping->slave_addr;
  1681. /* If the BIOS only described a different SDVO device, use the
  1682. * address that it isn't using.
  1683. */
  1684. if (other_mapping->slave_addr) {
  1685. if (other_mapping->slave_addr == 0x70)
  1686. return 0x72;
  1687. else
  1688. return 0x70;
  1689. }
  1690. /* No SDVO device info is found for another DVO port,
  1691. * so use mapping assumption we had before BIOS parsing.
  1692. */
  1693. if (IS_SDVOB(sdvo_reg))
  1694. return 0x70;
  1695. else
  1696. return 0x72;
  1697. }
  1698. static void
  1699. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1700. struct intel_sdvo *encoder)
  1701. {
  1702. drm_connector_init(encoder->base.base.dev,
  1703. &connector->base.base,
  1704. &intel_sdvo_connector_funcs,
  1705. connector->base.base.connector_type);
  1706. drm_connector_helper_add(&connector->base.base,
  1707. &intel_sdvo_connector_helper_funcs);
  1708. connector->base.base.interlace_allowed = 1;
  1709. connector->base.base.doublescan_allowed = 0;
  1710. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1711. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1712. drm_sysfs_connector_add(&connector->base.base);
  1713. }
  1714. static void
  1715. intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
  1716. {
  1717. struct drm_device *dev = connector->base.base.dev;
  1718. intel_attach_force_audio_property(&connector->base.base);
  1719. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
  1720. intel_attach_broadcast_rgb_property(&connector->base.base);
  1721. }
  1722. static bool
  1723. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1724. {
  1725. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1726. struct drm_connector *connector;
  1727. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1728. struct intel_connector *intel_connector;
  1729. struct intel_sdvo_connector *intel_sdvo_connector;
  1730. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1731. if (!intel_sdvo_connector)
  1732. return false;
  1733. if (device == 0) {
  1734. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1735. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1736. } else if (device == 1) {
  1737. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1738. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1739. }
  1740. intel_connector = &intel_sdvo_connector->base;
  1741. connector = &intel_connector->base;
  1742. if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
  1743. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1744. intel_sdvo->hotplug_active[0] |= 1 << device;
  1745. /* Some SDVO devices have one-shot hotplug interrupts.
  1746. * Ensure that they get re-enabled when an interrupt happens.
  1747. */
  1748. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1749. intel_sdvo_enable_hotplug(intel_encoder);
  1750. }
  1751. else
  1752. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1753. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1754. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1755. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1756. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1757. intel_sdvo->is_hdmi = true;
  1758. }
  1759. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1760. (1 << INTEL_ANALOG_CLONE_BIT));
  1761. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1762. if (intel_sdvo->is_hdmi)
  1763. intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
  1764. return true;
  1765. }
  1766. static bool
  1767. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1768. {
  1769. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1770. struct drm_connector *connector;
  1771. struct intel_connector *intel_connector;
  1772. struct intel_sdvo_connector *intel_sdvo_connector;
  1773. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1774. if (!intel_sdvo_connector)
  1775. return false;
  1776. intel_connector = &intel_sdvo_connector->base;
  1777. connector = &intel_connector->base;
  1778. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1779. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1780. intel_sdvo->controlled_output |= type;
  1781. intel_sdvo_connector->output_flag = type;
  1782. intel_sdvo->is_tv = true;
  1783. intel_sdvo->base.needs_tv_clock = true;
  1784. intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1785. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1786. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1787. goto err;
  1788. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1789. goto err;
  1790. return true;
  1791. err:
  1792. intel_sdvo_destroy(connector);
  1793. return false;
  1794. }
  1795. static bool
  1796. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1797. {
  1798. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1799. struct drm_connector *connector;
  1800. struct intel_connector *intel_connector;
  1801. struct intel_sdvo_connector *intel_sdvo_connector;
  1802. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1803. if (!intel_sdvo_connector)
  1804. return false;
  1805. intel_connector = &intel_sdvo_connector->base;
  1806. connector = &intel_connector->base;
  1807. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1808. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1809. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1810. if (device == 0) {
  1811. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1812. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1813. } else if (device == 1) {
  1814. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1815. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1816. }
  1817. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1818. (1 << INTEL_ANALOG_CLONE_BIT));
  1819. intel_sdvo_connector_init(intel_sdvo_connector,
  1820. intel_sdvo);
  1821. return true;
  1822. }
  1823. static bool
  1824. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  1825. {
  1826. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1827. struct drm_connector *connector;
  1828. struct intel_connector *intel_connector;
  1829. struct intel_sdvo_connector *intel_sdvo_connector;
  1830. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1831. if (!intel_sdvo_connector)
  1832. return false;
  1833. intel_connector = &intel_sdvo_connector->base;
  1834. connector = &intel_connector->base;
  1835. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1836. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1837. if (device == 0) {
  1838. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1839. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1840. } else if (device == 1) {
  1841. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1842. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1843. }
  1844. intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1845. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1846. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1847. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1848. goto err;
  1849. return true;
  1850. err:
  1851. intel_sdvo_destroy(connector);
  1852. return false;
  1853. }
  1854. static bool
  1855. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  1856. {
  1857. intel_sdvo->is_tv = false;
  1858. intel_sdvo->base.needs_tv_clock = false;
  1859. intel_sdvo->is_lvds = false;
  1860. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1861. if (flags & SDVO_OUTPUT_TMDS0)
  1862. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  1863. return false;
  1864. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1865. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  1866. return false;
  1867. /* TV has no XXX1 function block */
  1868. if (flags & SDVO_OUTPUT_SVID0)
  1869. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  1870. return false;
  1871. if (flags & SDVO_OUTPUT_CVBS0)
  1872. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  1873. return false;
  1874. if (flags & SDVO_OUTPUT_RGB0)
  1875. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  1876. return false;
  1877. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1878. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  1879. return false;
  1880. if (flags & SDVO_OUTPUT_LVDS0)
  1881. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  1882. return false;
  1883. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1884. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  1885. return false;
  1886. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1887. unsigned char bytes[2];
  1888. intel_sdvo->controlled_output = 0;
  1889. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  1890. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1891. SDVO_NAME(intel_sdvo),
  1892. bytes[0], bytes[1]);
  1893. return false;
  1894. }
  1895. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  1896. return true;
  1897. }
  1898. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  1899. struct intel_sdvo_connector *intel_sdvo_connector,
  1900. int type)
  1901. {
  1902. struct drm_device *dev = intel_sdvo->base.base.dev;
  1903. struct intel_sdvo_tv_format format;
  1904. uint32_t format_map, i;
  1905. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  1906. return false;
  1907. BUILD_BUG_ON(sizeof(format) != 6);
  1908. if (!intel_sdvo_get_value(intel_sdvo,
  1909. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1910. &format, sizeof(format)))
  1911. return false;
  1912. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1913. if (format_map == 0)
  1914. return false;
  1915. intel_sdvo_connector->format_supported_num = 0;
  1916. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1917. if (format_map & (1 << i))
  1918. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  1919. intel_sdvo_connector->tv_format =
  1920. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1921. "mode", intel_sdvo_connector->format_supported_num);
  1922. if (!intel_sdvo_connector->tv_format)
  1923. return false;
  1924. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  1925. drm_property_add_enum(
  1926. intel_sdvo_connector->tv_format, i,
  1927. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  1928. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  1929. drm_connector_attach_property(&intel_sdvo_connector->base.base,
  1930. intel_sdvo_connector->tv_format, 0);
  1931. return true;
  1932. }
  1933. #define ENHANCEMENT(name, NAME) do { \
  1934. if (enhancements.name) { \
  1935. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1936. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1937. return false; \
  1938. intel_sdvo_connector->max_##name = data_value[0]; \
  1939. intel_sdvo_connector->cur_##name = response; \
  1940. intel_sdvo_connector->name = \
  1941. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  1942. if (!intel_sdvo_connector->name) return false; \
  1943. drm_connector_attach_property(connector, \
  1944. intel_sdvo_connector->name, \
  1945. intel_sdvo_connector->cur_##name); \
  1946. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1947. data_value[0], data_value[1], response); \
  1948. } \
  1949. } while (0)
  1950. static bool
  1951. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  1952. struct intel_sdvo_connector *intel_sdvo_connector,
  1953. struct intel_sdvo_enhancements_reply enhancements)
  1954. {
  1955. struct drm_device *dev = intel_sdvo->base.base.dev;
  1956. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  1957. uint16_t response, data_value[2];
  1958. /* when horizontal overscan is supported, Add the left/right property */
  1959. if (enhancements.overscan_h) {
  1960. if (!intel_sdvo_get_value(intel_sdvo,
  1961. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1962. &data_value, 4))
  1963. return false;
  1964. if (!intel_sdvo_get_value(intel_sdvo,
  1965. SDVO_CMD_GET_OVERSCAN_H,
  1966. &response, 2))
  1967. return false;
  1968. intel_sdvo_connector->max_hscan = data_value[0];
  1969. intel_sdvo_connector->left_margin = data_value[0] - response;
  1970. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  1971. intel_sdvo_connector->left =
  1972. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  1973. if (!intel_sdvo_connector->left)
  1974. return false;
  1975. drm_connector_attach_property(connector,
  1976. intel_sdvo_connector->left,
  1977. intel_sdvo_connector->left_margin);
  1978. intel_sdvo_connector->right =
  1979. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  1980. if (!intel_sdvo_connector->right)
  1981. return false;
  1982. drm_connector_attach_property(connector,
  1983. intel_sdvo_connector->right,
  1984. intel_sdvo_connector->right_margin);
  1985. DRM_DEBUG_KMS("h_overscan: max %d, "
  1986. "default %d, current %d\n",
  1987. data_value[0], data_value[1], response);
  1988. }
  1989. if (enhancements.overscan_v) {
  1990. if (!intel_sdvo_get_value(intel_sdvo,
  1991. SDVO_CMD_GET_MAX_OVERSCAN_V,
  1992. &data_value, 4))
  1993. return false;
  1994. if (!intel_sdvo_get_value(intel_sdvo,
  1995. SDVO_CMD_GET_OVERSCAN_V,
  1996. &response, 2))
  1997. return false;
  1998. intel_sdvo_connector->max_vscan = data_value[0];
  1999. intel_sdvo_connector->top_margin = data_value[0] - response;
  2000. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2001. intel_sdvo_connector->top =
  2002. drm_property_create_range(dev, 0,
  2003. "top_margin", 0, data_value[0]);
  2004. if (!intel_sdvo_connector->top)
  2005. return false;
  2006. drm_connector_attach_property(connector,
  2007. intel_sdvo_connector->top,
  2008. intel_sdvo_connector->top_margin);
  2009. intel_sdvo_connector->bottom =
  2010. drm_property_create_range(dev, 0,
  2011. "bottom_margin", 0, data_value[0]);
  2012. if (!intel_sdvo_connector->bottom)
  2013. return false;
  2014. drm_connector_attach_property(connector,
  2015. intel_sdvo_connector->bottom,
  2016. intel_sdvo_connector->bottom_margin);
  2017. DRM_DEBUG_KMS("v_overscan: max %d, "
  2018. "default %d, current %d\n",
  2019. data_value[0], data_value[1], response);
  2020. }
  2021. ENHANCEMENT(hpos, HPOS);
  2022. ENHANCEMENT(vpos, VPOS);
  2023. ENHANCEMENT(saturation, SATURATION);
  2024. ENHANCEMENT(contrast, CONTRAST);
  2025. ENHANCEMENT(hue, HUE);
  2026. ENHANCEMENT(sharpness, SHARPNESS);
  2027. ENHANCEMENT(brightness, BRIGHTNESS);
  2028. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2029. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2030. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2031. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2032. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2033. if (enhancements.dot_crawl) {
  2034. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2035. return false;
  2036. intel_sdvo_connector->max_dot_crawl = 1;
  2037. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2038. intel_sdvo_connector->dot_crawl =
  2039. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2040. if (!intel_sdvo_connector->dot_crawl)
  2041. return false;
  2042. drm_connector_attach_property(connector,
  2043. intel_sdvo_connector->dot_crawl,
  2044. intel_sdvo_connector->cur_dot_crawl);
  2045. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2046. }
  2047. return true;
  2048. }
  2049. static bool
  2050. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2051. struct intel_sdvo_connector *intel_sdvo_connector,
  2052. struct intel_sdvo_enhancements_reply enhancements)
  2053. {
  2054. struct drm_device *dev = intel_sdvo->base.base.dev;
  2055. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2056. uint16_t response, data_value[2];
  2057. ENHANCEMENT(brightness, BRIGHTNESS);
  2058. return true;
  2059. }
  2060. #undef ENHANCEMENT
  2061. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2062. struct intel_sdvo_connector *intel_sdvo_connector)
  2063. {
  2064. union {
  2065. struct intel_sdvo_enhancements_reply reply;
  2066. uint16_t response;
  2067. } enhancements;
  2068. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2069. enhancements.response = 0;
  2070. intel_sdvo_get_value(intel_sdvo,
  2071. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2072. &enhancements, sizeof(enhancements));
  2073. if (enhancements.response == 0) {
  2074. DRM_DEBUG_KMS("No enhancement is supported\n");
  2075. return true;
  2076. }
  2077. if (IS_TV(intel_sdvo_connector))
  2078. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2079. else if (IS_LVDS(intel_sdvo_connector))
  2080. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2081. else
  2082. return true;
  2083. }
  2084. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2085. struct i2c_msg *msgs,
  2086. int num)
  2087. {
  2088. struct intel_sdvo *sdvo = adapter->algo_data;
  2089. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2090. return -EIO;
  2091. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2092. }
  2093. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2094. {
  2095. struct intel_sdvo *sdvo = adapter->algo_data;
  2096. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2097. }
  2098. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2099. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2100. .functionality = intel_sdvo_ddc_proxy_func
  2101. };
  2102. static bool
  2103. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2104. struct drm_device *dev)
  2105. {
  2106. sdvo->ddc.owner = THIS_MODULE;
  2107. sdvo->ddc.class = I2C_CLASS_DDC;
  2108. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2109. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2110. sdvo->ddc.algo_data = sdvo;
  2111. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2112. return i2c_add_adapter(&sdvo->ddc) == 0;
  2113. }
  2114. bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2115. {
  2116. struct drm_i915_private *dev_priv = dev->dev_private;
  2117. struct intel_encoder *intel_encoder;
  2118. struct intel_sdvo *intel_sdvo;
  2119. int i;
  2120. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2121. if (!intel_sdvo)
  2122. return false;
  2123. intel_sdvo->sdvo_reg = sdvo_reg;
  2124. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
  2125. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2126. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
  2127. kfree(intel_sdvo);
  2128. return false;
  2129. }
  2130. /* encoder type will be decided later */
  2131. intel_encoder = &intel_sdvo->base;
  2132. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2133. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2134. /* Read the regs to test if we can talk to the device */
  2135. for (i = 0; i < 0x40; i++) {
  2136. u8 byte;
  2137. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2138. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2139. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2140. goto err;
  2141. }
  2142. }
  2143. if (IS_SDVOB(sdvo_reg))
  2144. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2145. else
  2146. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2147. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2148. /* In default case sdvo lvds is false */
  2149. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2150. goto err;
  2151. /* Set up hotplug command - note paranoia about contents of reply.
  2152. * We assume that the hardware is in a sane state, and only touch
  2153. * the bits we think we understand.
  2154. */
  2155. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
  2156. &intel_sdvo->hotplug_active, 2);
  2157. intel_sdvo->hotplug_active[0] &= ~0x3;
  2158. if (intel_sdvo_output_setup(intel_sdvo,
  2159. intel_sdvo->caps.output_flags) != true) {
  2160. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2161. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2162. goto err;
  2163. }
  2164. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2165. /* Set the input timing to the screen. Assume always input 0. */
  2166. if (!intel_sdvo_set_target_input(intel_sdvo))
  2167. goto err;
  2168. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2169. &intel_sdvo->pixel_clock_min,
  2170. &intel_sdvo->pixel_clock_max))
  2171. goto err;
  2172. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2173. "clock range %dMHz - %dMHz, "
  2174. "input 1: %c, input 2: %c, "
  2175. "output 1: %c, output 2: %c\n",
  2176. SDVO_NAME(intel_sdvo),
  2177. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2178. intel_sdvo->caps.device_rev_id,
  2179. intel_sdvo->pixel_clock_min / 1000,
  2180. intel_sdvo->pixel_clock_max / 1000,
  2181. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2182. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2183. /* check currently supported outputs */
  2184. intel_sdvo->caps.output_flags &
  2185. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2186. intel_sdvo->caps.output_flags &
  2187. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2188. return true;
  2189. err:
  2190. drm_encoder_cleanup(&intel_encoder->base);
  2191. i2c_del_adapter(&intel_sdvo->ddc);
  2192. kfree(intel_sdvo);
  2193. return false;
  2194. }