intel_crt.c 17 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "drm_crtc.h"
  32. #include "drm_crtc_helper.h"
  33. #include "drm_edid.h"
  34. #include "intel_drv.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  39. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  40. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  41. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  42. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  43. ADPA_CRT_HOTPLUG_ENABLE)
  44. struct intel_crt {
  45. struct intel_encoder base;
  46. bool force_hotplug_required;
  47. };
  48. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  49. {
  50. return container_of(intel_attached_encoder(connector),
  51. struct intel_crt, base);
  52. }
  53. static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
  54. {
  55. struct drm_device *dev = encoder->dev;
  56. struct drm_i915_private *dev_priv = dev->dev_private;
  57. u32 temp, reg;
  58. if (HAS_PCH_SPLIT(dev))
  59. reg = PCH_ADPA;
  60. else
  61. reg = ADPA;
  62. temp = I915_READ(reg);
  63. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  64. temp &= ~ADPA_DAC_ENABLE;
  65. switch (mode) {
  66. case DRM_MODE_DPMS_ON:
  67. temp |= ADPA_DAC_ENABLE;
  68. break;
  69. case DRM_MODE_DPMS_STANDBY:
  70. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  71. break;
  72. case DRM_MODE_DPMS_SUSPEND:
  73. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  74. break;
  75. case DRM_MODE_DPMS_OFF:
  76. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  77. break;
  78. }
  79. I915_WRITE(reg, temp);
  80. }
  81. static int intel_crt_mode_valid(struct drm_connector *connector,
  82. struct drm_display_mode *mode)
  83. {
  84. struct drm_device *dev = connector->dev;
  85. int max_clock = 0;
  86. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  87. return MODE_NO_DBLESCAN;
  88. if (mode->clock < 25000)
  89. return MODE_CLOCK_LOW;
  90. if (IS_GEN2(dev))
  91. max_clock = 350000;
  92. else
  93. max_clock = 400000;
  94. if (mode->clock > max_clock)
  95. return MODE_CLOCK_HIGH;
  96. return MODE_OK;
  97. }
  98. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  99. struct drm_display_mode *mode,
  100. struct drm_display_mode *adjusted_mode)
  101. {
  102. return true;
  103. }
  104. static void intel_crt_mode_set(struct drm_encoder *encoder,
  105. struct drm_display_mode *mode,
  106. struct drm_display_mode *adjusted_mode)
  107. {
  108. struct drm_device *dev = encoder->dev;
  109. struct drm_crtc *crtc = encoder->crtc;
  110. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  111. struct drm_i915_private *dev_priv = dev->dev_private;
  112. int dpll_md_reg;
  113. u32 adpa, dpll_md;
  114. u32 adpa_reg;
  115. dpll_md_reg = DPLL_MD(intel_crtc->pipe);
  116. if (HAS_PCH_SPLIT(dev))
  117. adpa_reg = PCH_ADPA;
  118. else
  119. adpa_reg = ADPA;
  120. /*
  121. * Disable separate mode multiplier used when cloning SDVO to CRT
  122. * XXX this needs to be adjusted when we really are cloning
  123. */
  124. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  125. dpll_md = I915_READ(dpll_md_reg);
  126. I915_WRITE(dpll_md_reg,
  127. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  128. }
  129. adpa = ADPA_HOTPLUG_BITS;
  130. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  131. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  132. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  133. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  134. /* For CPT allow 3 pipe config, for others just use A or B */
  135. if (HAS_PCH_CPT(dev))
  136. adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  137. else if (intel_crtc->pipe == 0)
  138. adpa |= ADPA_PIPE_A_SELECT;
  139. else
  140. adpa |= ADPA_PIPE_B_SELECT;
  141. if (!HAS_PCH_SPLIT(dev))
  142. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  143. I915_WRITE(adpa_reg, adpa);
  144. }
  145. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  146. {
  147. struct drm_device *dev = connector->dev;
  148. struct intel_crt *crt = intel_attached_crt(connector);
  149. struct drm_i915_private *dev_priv = dev->dev_private;
  150. u32 adpa;
  151. bool ret;
  152. /* The first time through, trigger an explicit detection cycle */
  153. if (crt->force_hotplug_required) {
  154. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  155. u32 save_adpa;
  156. crt->force_hotplug_required = 0;
  157. save_adpa = adpa = I915_READ(PCH_ADPA);
  158. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  159. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  160. if (turn_off_dac)
  161. adpa &= ~ADPA_DAC_ENABLE;
  162. I915_WRITE(PCH_ADPA, adpa);
  163. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  164. 1000))
  165. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  166. if (turn_off_dac) {
  167. I915_WRITE(PCH_ADPA, save_adpa);
  168. POSTING_READ(PCH_ADPA);
  169. }
  170. }
  171. /* Check the status to see if both blue and green are on now */
  172. adpa = I915_READ(PCH_ADPA);
  173. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  174. ret = true;
  175. else
  176. ret = false;
  177. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  178. return ret;
  179. }
  180. /**
  181. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  182. *
  183. * Not for i915G/i915GM
  184. *
  185. * \return true if CRT is connected.
  186. * \return false if CRT is disconnected.
  187. */
  188. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  189. {
  190. struct drm_device *dev = connector->dev;
  191. struct drm_i915_private *dev_priv = dev->dev_private;
  192. u32 hotplug_en, orig, stat;
  193. bool ret = false;
  194. int i, tries = 0;
  195. if (HAS_PCH_SPLIT(dev))
  196. return intel_ironlake_crt_detect_hotplug(connector);
  197. /*
  198. * On 4 series desktop, CRT detect sequence need to be done twice
  199. * to get a reliable result.
  200. */
  201. if (IS_G4X(dev) && !IS_GM45(dev))
  202. tries = 2;
  203. else
  204. tries = 1;
  205. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  206. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  207. for (i = 0; i < tries ; i++) {
  208. /* turn on the FORCE_DETECT */
  209. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  210. /* wait for FORCE_DETECT to go off */
  211. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  212. CRT_HOTPLUG_FORCE_DETECT) == 0,
  213. 1000))
  214. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  215. }
  216. stat = I915_READ(PORT_HOTPLUG_STAT);
  217. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  218. ret = true;
  219. /* clear the interrupt we just generated, if any */
  220. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  221. /* and put the bits back */
  222. I915_WRITE(PORT_HOTPLUG_EN, orig);
  223. return ret;
  224. }
  225. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  226. {
  227. struct intel_crt *crt = intel_attached_crt(connector);
  228. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  229. /* CRT should always be at 0, but check anyway */
  230. if (crt->base.type != INTEL_OUTPUT_ANALOG)
  231. return false;
  232. if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
  233. struct edid *edid;
  234. bool is_digital = false;
  235. edid = drm_get_edid(connector,
  236. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  237. /*
  238. * This may be a DVI-I connector with a shared DDC
  239. * link between analog and digital outputs, so we
  240. * have to check the EDID input spec of the attached device.
  241. *
  242. * On the other hand, what should we do if it is a broken EDID?
  243. */
  244. if (edid != NULL) {
  245. is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  246. connector->display_info.raw_edid = NULL;
  247. kfree(edid);
  248. }
  249. if (!is_digital) {
  250. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  251. return true;
  252. } else {
  253. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  254. }
  255. }
  256. return false;
  257. }
  258. static enum drm_connector_status
  259. intel_crt_load_detect(struct intel_crt *crt)
  260. {
  261. struct drm_device *dev = crt->base.base.dev;
  262. struct drm_i915_private *dev_priv = dev->dev_private;
  263. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  264. uint32_t save_bclrpat;
  265. uint32_t save_vtotal;
  266. uint32_t vtotal, vactive;
  267. uint32_t vsample;
  268. uint32_t vblank, vblank_start, vblank_end;
  269. uint32_t dsl;
  270. uint32_t bclrpat_reg;
  271. uint32_t vtotal_reg;
  272. uint32_t vblank_reg;
  273. uint32_t vsync_reg;
  274. uint32_t pipeconf_reg;
  275. uint32_t pipe_dsl_reg;
  276. uint8_t st00;
  277. enum drm_connector_status status;
  278. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  279. bclrpat_reg = BCLRPAT(pipe);
  280. vtotal_reg = VTOTAL(pipe);
  281. vblank_reg = VBLANK(pipe);
  282. vsync_reg = VSYNC(pipe);
  283. pipeconf_reg = PIPECONF(pipe);
  284. pipe_dsl_reg = PIPEDSL(pipe);
  285. save_bclrpat = I915_READ(bclrpat_reg);
  286. save_vtotal = I915_READ(vtotal_reg);
  287. vblank = I915_READ(vblank_reg);
  288. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  289. vactive = (save_vtotal & 0x7ff) + 1;
  290. vblank_start = (vblank & 0xfff) + 1;
  291. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  292. /* Set the border color to purple. */
  293. I915_WRITE(bclrpat_reg, 0x500050);
  294. if (!IS_GEN2(dev)) {
  295. uint32_t pipeconf = I915_READ(pipeconf_reg);
  296. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  297. POSTING_READ(pipeconf_reg);
  298. /* Wait for next Vblank to substitue
  299. * border color for Color info */
  300. intel_wait_for_vblank(dev, pipe);
  301. st00 = I915_READ8(VGA_MSR_WRITE);
  302. status = ((st00 & (1 << 4)) != 0) ?
  303. connector_status_connected :
  304. connector_status_disconnected;
  305. I915_WRITE(pipeconf_reg, pipeconf);
  306. } else {
  307. bool restore_vblank = false;
  308. int count, detect;
  309. /*
  310. * If there isn't any border, add some.
  311. * Yes, this will flicker
  312. */
  313. if (vblank_start <= vactive && vblank_end >= vtotal) {
  314. uint32_t vsync = I915_READ(vsync_reg);
  315. uint32_t vsync_start = (vsync & 0xffff) + 1;
  316. vblank_start = vsync_start;
  317. I915_WRITE(vblank_reg,
  318. (vblank_start - 1) |
  319. ((vblank_end - 1) << 16));
  320. restore_vblank = true;
  321. }
  322. /* sample in the vertical border, selecting the larger one */
  323. if (vblank_start - vactive >= vtotal - vblank_end)
  324. vsample = (vblank_start + vactive) >> 1;
  325. else
  326. vsample = (vtotal + vblank_end) >> 1;
  327. /*
  328. * Wait for the border to be displayed
  329. */
  330. while (I915_READ(pipe_dsl_reg) >= vactive)
  331. ;
  332. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  333. ;
  334. /*
  335. * Watch ST00 for an entire scanline
  336. */
  337. detect = 0;
  338. count = 0;
  339. do {
  340. count++;
  341. /* Read the ST00 VGA status register */
  342. st00 = I915_READ8(VGA_MSR_WRITE);
  343. if (st00 & (1 << 4))
  344. detect++;
  345. } while ((I915_READ(pipe_dsl_reg) == dsl));
  346. /* restore vblank if necessary */
  347. if (restore_vblank)
  348. I915_WRITE(vblank_reg, vblank);
  349. /*
  350. * If more than 3/4 of the scanline detected a monitor,
  351. * then it is assumed to be present. This works even on i830,
  352. * where there isn't any way to force the border color across
  353. * the screen
  354. */
  355. status = detect * 4 > count * 3 ?
  356. connector_status_connected :
  357. connector_status_disconnected;
  358. }
  359. /* Restore previous settings */
  360. I915_WRITE(bclrpat_reg, save_bclrpat);
  361. return status;
  362. }
  363. static enum drm_connector_status
  364. intel_crt_detect(struct drm_connector *connector, bool force)
  365. {
  366. struct drm_device *dev = connector->dev;
  367. struct intel_crt *crt = intel_attached_crt(connector);
  368. struct drm_crtc *crtc;
  369. enum drm_connector_status status;
  370. if (I915_HAS_HOTPLUG(dev)) {
  371. if (intel_crt_detect_hotplug(connector)) {
  372. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  373. return connector_status_connected;
  374. } else {
  375. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  376. return connector_status_disconnected;
  377. }
  378. }
  379. if (intel_crt_detect_ddc(connector))
  380. return connector_status_connected;
  381. if (!force)
  382. return connector->status;
  383. /* for pre-945g platforms use load detect */
  384. crtc = crt->base.base.crtc;
  385. if (crtc && crtc->enabled) {
  386. status = intel_crt_load_detect(crt);
  387. } else {
  388. struct intel_load_detect_pipe tmp;
  389. if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
  390. &tmp)) {
  391. if (intel_crt_detect_ddc(connector))
  392. status = connector_status_connected;
  393. else
  394. status = intel_crt_load_detect(crt);
  395. intel_release_load_detect_pipe(&crt->base, connector,
  396. &tmp);
  397. } else
  398. status = connector_status_unknown;
  399. }
  400. return status;
  401. }
  402. static void intel_crt_destroy(struct drm_connector *connector)
  403. {
  404. drm_sysfs_connector_remove(connector);
  405. drm_connector_cleanup(connector);
  406. kfree(connector);
  407. }
  408. static int intel_crt_get_modes(struct drm_connector *connector)
  409. {
  410. struct drm_device *dev = connector->dev;
  411. struct drm_i915_private *dev_priv = dev->dev_private;
  412. int ret;
  413. ret = intel_ddc_get_modes(connector,
  414. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  415. if (ret || !IS_G4X(dev))
  416. return ret;
  417. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  418. return intel_ddc_get_modes(connector,
  419. &dev_priv->gmbus[GMBUS_PORT_DPB].adapter);
  420. }
  421. static int intel_crt_set_property(struct drm_connector *connector,
  422. struct drm_property *property,
  423. uint64_t value)
  424. {
  425. return 0;
  426. }
  427. static void intel_crt_reset(struct drm_connector *connector)
  428. {
  429. struct drm_device *dev = connector->dev;
  430. struct intel_crt *crt = intel_attached_crt(connector);
  431. if (HAS_PCH_SPLIT(dev))
  432. crt->force_hotplug_required = 1;
  433. }
  434. /*
  435. * Routines for controlling stuff on the analog port
  436. */
  437. static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
  438. .dpms = intel_crt_dpms,
  439. .mode_fixup = intel_crt_mode_fixup,
  440. .prepare = intel_encoder_prepare,
  441. .commit = intel_encoder_commit,
  442. .mode_set = intel_crt_mode_set,
  443. };
  444. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  445. .reset = intel_crt_reset,
  446. .dpms = drm_helper_connector_dpms,
  447. .detect = intel_crt_detect,
  448. .fill_modes = drm_helper_probe_single_connector_modes,
  449. .destroy = intel_crt_destroy,
  450. .set_property = intel_crt_set_property,
  451. };
  452. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  453. .mode_valid = intel_crt_mode_valid,
  454. .get_modes = intel_crt_get_modes,
  455. .best_encoder = intel_best_encoder,
  456. };
  457. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  458. .destroy = intel_encoder_destroy,
  459. };
  460. static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  461. {
  462. DRM_DEBUG_KMS("Skipping CRT initialization for %s\n", id->ident);
  463. return 1;
  464. }
  465. static const struct dmi_system_id intel_no_crt[] = {
  466. {
  467. .callback = intel_no_crt_dmi_callback,
  468. .ident = "ACER ZGB",
  469. .matches = {
  470. DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  471. DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  472. },
  473. },
  474. { }
  475. };
  476. void intel_crt_init(struct drm_device *dev)
  477. {
  478. struct drm_connector *connector;
  479. struct intel_crt *crt;
  480. struct intel_connector *intel_connector;
  481. struct drm_i915_private *dev_priv = dev->dev_private;
  482. /* Skip machines without VGA that falsely report hotplug events */
  483. if (dmi_check_system(intel_no_crt))
  484. return;
  485. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  486. if (!crt)
  487. return;
  488. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  489. if (!intel_connector) {
  490. kfree(crt);
  491. return;
  492. }
  493. connector = &intel_connector->base;
  494. drm_connector_init(dev, &intel_connector->base,
  495. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  496. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  497. DRM_MODE_ENCODER_DAC);
  498. intel_connector_attach_encoder(intel_connector, &crt->base);
  499. crt->base.type = INTEL_OUTPUT_ANALOG;
  500. crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT |
  501. 1 << INTEL_ANALOG_CLONE_BIT |
  502. 1 << INTEL_SDVO_LVDS_CLONE_BIT);
  503. crt->base.crtc_mask = (1 << 0) | (1 << 1);
  504. if (IS_GEN2(dev))
  505. connector->interlace_allowed = 0;
  506. else
  507. connector->interlace_allowed = 1;
  508. connector->doublescan_allowed = 0;
  509. drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
  510. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  511. drm_sysfs_connector_add(connector);
  512. if (I915_HAS_HOTPLUG(dev))
  513. connector->polled = DRM_CONNECTOR_POLL_HPD;
  514. else
  515. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  516. /*
  517. * Configure the automatic hotplug detection stuff
  518. */
  519. crt->force_hotplug_required = 0;
  520. if (HAS_PCH_SPLIT(dev)) {
  521. u32 adpa;
  522. adpa = I915_READ(PCH_ADPA);
  523. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  524. adpa |= ADPA_HOTPLUG_BITS;
  525. I915_WRITE(PCH_ADPA, adpa);
  526. POSTING_READ(PCH_ADPA);
  527. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  528. crt->force_hotplug_required = 1;
  529. }
  530. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  531. }