i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/slab.h>
  39. #include <linux/pagemap.h>
  40. #define I810_BUF_FREE 2
  41. #define I810_BUF_CLIENT 1
  42. #define I810_BUF_HARDWARE 0
  43. #define I810_BUF_UNMAPPED 0
  44. #define I810_BUF_MAPPED 1
  45. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  46. {
  47. struct drm_device_dma *dma = dev->dma;
  48. int i;
  49. int used;
  50. /* Linear search might not be the best solution */
  51. for (i = 0; i < dma->buf_count; i++) {
  52. struct drm_buf *buf = dma->buflist[i];
  53. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  54. /* In use is already a pointer */
  55. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  56. I810_BUF_CLIENT);
  57. if (used == I810_BUF_FREE)
  58. return buf;
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(struct drm_device *dev, struct drm_buf *buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. struct drm_file *priv = filp->private_data;
  80. struct drm_device *dev;
  81. drm_i810_private_t *dev_priv;
  82. struct drm_buf *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. dev = priv->minor->dev;
  85. dev_priv = dev->dev_private;
  86. buf = dev_priv->mmap_buffer;
  87. buf_priv = buf->dev_private;
  88. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  89. buf_priv->currently_mapped = I810_BUF_MAPPED;
  90. if (io_remap_pfn_range(vma, vma->vm_start,
  91. vma->vm_pgoff,
  92. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  93. return -EAGAIN;
  94. return 0;
  95. }
  96. static const struct file_operations i810_buffer_fops = {
  97. .open = drm_open,
  98. .release = drm_release,
  99. .unlocked_ioctl = drm_ioctl,
  100. .mmap = i810_mmap_buffers,
  101. .fasync = drm_fasync,
  102. .llseek = noop_llseek,
  103. };
  104. static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv)
  105. {
  106. struct drm_device *dev = file_priv->minor->dev;
  107. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  108. drm_i810_private_t *dev_priv = dev->dev_private;
  109. const struct file_operations *old_fops;
  110. int retcode = 0;
  111. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  112. return -EINVAL;
  113. down_write(&current->mm->mmap_sem);
  114. old_fops = file_priv->filp->f_op;
  115. file_priv->filp->f_op = &i810_buffer_fops;
  116. dev_priv->mmap_buffer = buf;
  117. buf_priv->virtual = (void *)do_mmap(file_priv->filp, 0, buf->total,
  118. PROT_READ | PROT_WRITE,
  119. MAP_SHARED, buf->bus_address);
  120. dev_priv->mmap_buffer = NULL;
  121. file_priv->filp->f_op = old_fops;
  122. if (IS_ERR(buf_priv->virtual)) {
  123. /* Real error */
  124. DRM_ERROR("mmap error\n");
  125. retcode = PTR_ERR(buf_priv->virtual);
  126. buf_priv->virtual = NULL;
  127. }
  128. up_write(&current->mm->mmap_sem);
  129. return retcode;
  130. }
  131. static int i810_unmap_buffer(struct drm_buf *buf)
  132. {
  133. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  134. int retcode = 0;
  135. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  136. return -EINVAL;
  137. down_write(&current->mm->mmap_sem);
  138. retcode = do_munmap(current->mm,
  139. (unsigned long)buf_priv->virtual,
  140. (size_t) buf->total);
  141. up_write(&current->mm->mmap_sem);
  142. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  143. buf_priv->virtual = NULL;
  144. return retcode;
  145. }
  146. static int i810_dma_get_buffer(struct drm_device *dev, drm_i810_dma_t *d,
  147. struct drm_file *file_priv)
  148. {
  149. struct drm_buf *buf;
  150. drm_i810_buf_priv_t *buf_priv;
  151. int retcode = 0;
  152. buf = i810_freelist_get(dev);
  153. if (!buf) {
  154. retcode = -ENOMEM;
  155. DRM_DEBUG("retcode=%d\n", retcode);
  156. return retcode;
  157. }
  158. retcode = i810_map_buffer(buf, file_priv);
  159. if (retcode) {
  160. i810_freelist_put(dev, buf);
  161. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  162. return retcode;
  163. }
  164. buf->file_priv = file_priv;
  165. buf_priv = buf->dev_private;
  166. d->granted = 1;
  167. d->request_idx = buf->idx;
  168. d->request_size = buf->total;
  169. d->virtual = buf_priv->virtual;
  170. return retcode;
  171. }
  172. static int i810_dma_cleanup(struct drm_device *dev)
  173. {
  174. struct drm_device_dma *dma = dev->dma;
  175. /* Make sure interrupts are disabled here because the uninstall ioctl
  176. * may not have been called from userspace and after dev_private
  177. * is freed, it's too late.
  178. */
  179. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  180. drm_irq_uninstall(dev);
  181. if (dev->dev_private) {
  182. int i;
  183. drm_i810_private_t *dev_priv =
  184. (drm_i810_private_t *) dev->dev_private;
  185. if (dev_priv->ring.virtual_start)
  186. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  187. if (dev_priv->hw_status_page) {
  188. pci_free_consistent(dev->pdev, PAGE_SIZE,
  189. dev_priv->hw_status_page,
  190. dev_priv->dma_status_page);
  191. }
  192. kfree(dev->dev_private);
  193. dev->dev_private = NULL;
  194. for (i = 0; i < dma->buf_count; i++) {
  195. struct drm_buf *buf = dma->buflist[i];
  196. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  197. if (buf_priv->kernel_virtual && buf->total)
  198. drm_core_ioremapfree(&buf_priv->map, dev);
  199. }
  200. }
  201. return 0;
  202. }
  203. static int i810_wait_ring(struct drm_device *dev, int n)
  204. {
  205. drm_i810_private_t *dev_priv = dev->dev_private;
  206. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  207. int iters = 0;
  208. unsigned long end;
  209. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  210. end = jiffies + (HZ * 3);
  211. while (ring->space < n) {
  212. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  213. ring->space = ring->head - (ring->tail + 8);
  214. if (ring->space < 0)
  215. ring->space += ring->Size;
  216. if (ring->head != last_head) {
  217. end = jiffies + (HZ * 3);
  218. last_head = ring->head;
  219. }
  220. iters++;
  221. if (time_before(end, jiffies)) {
  222. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  223. DRM_ERROR("lockup\n");
  224. goto out_wait_ring;
  225. }
  226. udelay(1);
  227. }
  228. out_wait_ring:
  229. return iters;
  230. }
  231. static void i810_kernel_lost_context(struct drm_device *dev)
  232. {
  233. drm_i810_private_t *dev_priv = dev->dev_private;
  234. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  235. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  236. ring->tail = I810_READ(LP_RING + RING_TAIL);
  237. ring->space = ring->head - (ring->tail + 8);
  238. if (ring->space < 0)
  239. ring->space += ring->Size;
  240. }
  241. static int i810_freelist_init(struct drm_device *dev, drm_i810_private_t *dev_priv)
  242. {
  243. struct drm_device_dma *dma = dev->dma;
  244. int my_idx = 24;
  245. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  246. int i;
  247. if (dma->buf_count > 1019) {
  248. /* Not enough space in the status page for the freelist */
  249. return -EINVAL;
  250. }
  251. for (i = 0; i < dma->buf_count; i++) {
  252. struct drm_buf *buf = dma->buflist[i];
  253. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  254. buf_priv->in_use = hw_status++;
  255. buf_priv->my_use_idx = my_idx;
  256. my_idx += 4;
  257. *buf_priv->in_use = I810_BUF_FREE;
  258. buf_priv->map.offset = buf->bus_address;
  259. buf_priv->map.size = buf->total;
  260. buf_priv->map.type = _DRM_AGP;
  261. buf_priv->map.flags = 0;
  262. buf_priv->map.mtrr = 0;
  263. drm_core_ioremap(&buf_priv->map, dev);
  264. buf_priv->kernel_virtual = buf_priv->map.handle;
  265. }
  266. return 0;
  267. }
  268. static int i810_dma_initialize(struct drm_device *dev,
  269. drm_i810_private_t *dev_priv,
  270. drm_i810_init_t *init)
  271. {
  272. struct drm_map_list *r_list;
  273. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  274. list_for_each_entry(r_list, &dev->maplist, head) {
  275. if (r_list->map &&
  276. r_list->map->type == _DRM_SHM &&
  277. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  278. dev_priv->sarea_map = r_list->map;
  279. break;
  280. }
  281. }
  282. if (!dev_priv->sarea_map) {
  283. dev->dev_private = (void *)dev_priv;
  284. i810_dma_cleanup(dev);
  285. DRM_ERROR("can not find sarea!\n");
  286. return -EINVAL;
  287. }
  288. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  289. if (!dev_priv->mmio_map) {
  290. dev->dev_private = (void *)dev_priv;
  291. i810_dma_cleanup(dev);
  292. DRM_ERROR("can not find mmio map!\n");
  293. return -EINVAL;
  294. }
  295. dev->agp_buffer_token = init->buffers_offset;
  296. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  297. if (!dev->agp_buffer_map) {
  298. dev->dev_private = (void *)dev_priv;
  299. i810_dma_cleanup(dev);
  300. DRM_ERROR("can not find dma buffer map!\n");
  301. return -EINVAL;
  302. }
  303. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  304. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  305. dev_priv->ring.Start = init->ring_start;
  306. dev_priv->ring.End = init->ring_end;
  307. dev_priv->ring.Size = init->ring_size;
  308. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  309. dev_priv->ring.map.size = init->ring_size;
  310. dev_priv->ring.map.type = _DRM_AGP;
  311. dev_priv->ring.map.flags = 0;
  312. dev_priv->ring.map.mtrr = 0;
  313. drm_core_ioremap(&dev_priv->ring.map, dev);
  314. if (dev_priv->ring.map.handle == NULL) {
  315. dev->dev_private = (void *)dev_priv;
  316. i810_dma_cleanup(dev);
  317. DRM_ERROR("can not ioremap virtual address for"
  318. " ring buffer\n");
  319. return -ENOMEM;
  320. }
  321. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  322. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  323. dev_priv->w = init->w;
  324. dev_priv->h = init->h;
  325. dev_priv->pitch = init->pitch;
  326. dev_priv->back_offset = init->back_offset;
  327. dev_priv->depth_offset = init->depth_offset;
  328. dev_priv->front_offset = init->front_offset;
  329. dev_priv->overlay_offset = init->overlay_offset;
  330. dev_priv->overlay_physical = init->overlay_physical;
  331. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  332. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  333. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  334. /* Program Hardware Status Page */
  335. dev_priv->hw_status_page =
  336. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  337. &dev_priv->dma_status_page);
  338. if (!dev_priv->hw_status_page) {
  339. dev->dev_private = (void *)dev_priv;
  340. i810_dma_cleanup(dev);
  341. DRM_ERROR("Can not allocate hardware status page\n");
  342. return -ENOMEM;
  343. }
  344. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  345. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  346. I810_WRITE(0x02080, dev_priv->dma_status_page);
  347. DRM_DEBUG("Enabled hardware status page\n");
  348. /* Now we need to init our freelist */
  349. if (i810_freelist_init(dev, dev_priv) != 0) {
  350. dev->dev_private = (void *)dev_priv;
  351. i810_dma_cleanup(dev);
  352. DRM_ERROR("Not enough space in the status page for"
  353. " the freelist\n");
  354. return -ENOMEM;
  355. }
  356. dev->dev_private = (void *)dev_priv;
  357. return 0;
  358. }
  359. static int i810_dma_init(struct drm_device *dev, void *data,
  360. struct drm_file *file_priv)
  361. {
  362. drm_i810_private_t *dev_priv;
  363. drm_i810_init_t *init = data;
  364. int retcode = 0;
  365. switch (init->func) {
  366. case I810_INIT_DMA_1_4:
  367. DRM_INFO("Using v1.4 init.\n");
  368. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  369. if (dev_priv == NULL)
  370. return -ENOMEM;
  371. retcode = i810_dma_initialize(dev, dev_priv, init);
  372. break;
  373. case I810_CLEANUP_DMA:
  374. DRM_INFO("DMA Cleanup\n");
  375. retcode = i810_dma_cleanup(dev);
  376. break;
  377. default:
  378. return -EINVAL;
  379. }
  380. return retcode;
  381. }
  382. /* Most efficient way to verify state for the i810 is as it is
  383. * emitted. Non-conformant state is silently dropped.
  384. *
  385. * Use 'volatile' & local var tmp to force the emitted values to be
  386. * identical to the verified ones.
  387. */
  388. static void i810EmitContextVerified(struct drm_device *dev,
  389. volatile unsigned int *code)
  390. {
  391. drm_i810_private_t *dev_priv = dev->dev_private;
  392. int i, j = 0;
  393. unsigned int tmp;
  394. RING_LOCALS;
  395. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  396. OUT_RING(GFX_OP_COLOR_FACTOR);
  397. OUT_RING(code[I810_CTXREG_CF1]);
  398. OUT_RING(GFX_OP_STIPPLE);
  399. OUT_RING(code[I810_CTXREG_ST1]);
  400. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  401. tmp = code[i];
  402. if ((tmp & (7 << 29)) == (3 << 29) &&
  403. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  404. OUT_RING(tmp);
  405. j++;
  406. } else
  407. printk("constext state dropped!!!\n");
  408. }
  409. if (j & 1)
  410. OUT_RING(0);
  411. ADVANCE_LP_RING();
  412. }
  413. static void i810EmitTexVerified(struct drm_device *dev, volatile unsigned int *code)
  414. {
  415. drm_i810_private_t *dev_priv = dev->dev_private;
  416. int i, j = 0;
  417. unsigned int tmp;
  418. RING_LOCALS;
  419. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  420. OUT_RING(GFX_OP_MAP_INFO);
  421. OUT_RING(code[I810_TEXREG_MI1]);
  422. OUT_RING(code[I810_TEXREG_MI2]);
  423. OUT_RING(code[I810_TEXREG_MI3]);
  424. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  425. tmp = code[i];
  426. if ((tmp & (7 << 29)) == (3 << 29) &&
  427. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  428. OUT_RING(tmp);
  429. j++;
  430. } else
  431. printk("texture state dropped!!!\n");
  432. }
  433. if (j & 1)
  434. OUT_RING(0);
  435. ADVANCE_LP_RING();
  436. }
  437. /* Need to do some additional checking when setting the dest buffer.
  438. */
  439. static void i810EmitDestVerified(struct drm_device *dev,
  440. volatile unsigned int *code)
  441. {
  442. drm_i810_private_t *dev_priv = dev->dev_private;
  443. unsigned int tmp;
  444. RING_LOCALS;
  445. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  446. tmp = code[I810_DESTREG_DI1];
  447. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  448. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  449. OUT_RING(tmp);
  450. } else
  451. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  452. tmp, dev_priv->front_di1, dev_priv->back_di1);
  453. /* invarient:
  454. */
  455. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  456. OUT_RING(dev_priv->zi1);
  457. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  458. OUT_RING(code[I810_DESTREG_DV1]);
  459. OUT_RING(GFX_OP_DRAWRECT_INFO);
  460. OUT_RING(code[I810_DESTREG_DR1]);
  461. OUT_RING(code[I810_DESTREG_DR2]);
  462. OUT_RING(code[I810_DESTREG_DR3]);
  463. OUT_RING(code[I810_DESTREG_DR4]);
  464. OUT_RING(0);
  465. ADVANCE_LP_RING();
  466. }
  467. static void i810EmitState(struct drm_device *dev)
  468. {
  469. drm_i810_private_t *dev_priv = dev->dev_private;
  470. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  471. unsigned int dirty = sarea_priv->dirty;
  472. DRM_DEBUG("%x\n", dirty);
  473. if (dirty & I810_UPLOAD_BUFFERS) {
  474. i810EmitDestVerified(dev, sarea_priv->BufferState);
  475. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  476. }
  477. if (dirty & I810_UPLOAD_CTX) {
  478. i810EmitContextVerified(dev, sarea_priv->ContextState);
  479. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  480. }
  481. if (dirty & I810_UPLOAD_TEX0) {
  482. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  483. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  484. }
  485. if (dirty & I810_UPLOAD_TEX1) {
  486. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  487. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  488. }
  489. }
  490. /* need to verify
  491. */
  492. static void i810_dma_dispatch_clear(struct drm_device *dev, int flags,
  493. unsigned int clear_color,
  494. unsigned int clear_zval)
  495. {
  496. drm_i810_private_t *dev_priv = dev->dev_private;
  497. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  498. int nbox = sarea_priv->nbox;
  499. struct drm_clip_rect *pbox = sarea_priv->boxes;
  500. int pitch = dev_priv->pitch;
  501. int cpp = 2;
  502. int i;
  503. RING_LOCALS;
  504. if (dev_priv->current_page == 1) {
  505. unsigned int tmp = flags;
  506. flags &= ~(I810_FRONT | I810_BACK);
  507. if (tmp & I810_FRONT)
  508. flags |= I810_BACK;
  509. if (tmp & I810_BACK)
  510. flags |= I810_FRONT;
  511. }
  512. i810_kernel_lost_context(dev);
  513. if (nbox > I810_NR_SAREA_CLIPRECTS)
  514. nbox = I810_NR_SAREA_CLIPRECTS;
  515. for (i = 0; i < nbox; i++, pbox++) {
  516. unsigned int x = pbox->x1;
  517. unsigned int y = pbox->y1;
  518. unsigned int width = (pbox->x2 - x) * cpp;
  519. unsigned int height = pbox->y2 - y;
  520. unsigned int start = y * pitch + x * cpp;
  521. if (pbox->x1 > pbox->x2 ||
  522. pbox->y1 > pbox->y2 ||
  523. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  524. continue;
  525. if (flags & I810_FRONT) {
  526. BEGIN_LP_RING(6);
  527. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  528. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  529. OUT_RING((height << 16) | width);
  530. OUT_RING(start);
  531. OUT_RING(clear_color);
  532. OUT_RING(0);
  533. ADVANCE_LP_RING();
  534. }
  535. if (flags & I810_BACK) {
  536. BEGIN_LP_RING(6);
  537. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  538. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  539. OUT_RING((height << 16) | width);
  540. OUT_RING(dev_priv->back_offset + start);
  541. OUT_RING(clear_color);
  542. OUT_RING(0);
  543. ADVANCE_LP_RING();
  544. }
  545. if (flags & I810_DEPTH) {
  546. BEGIN_LP_RING(6);
  547. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  548. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  549. OUT_RING((height << 16) | width);
  550. OUT_RING(dev_priv->depth_offset + start);
  551. OUT_RING(clear_zval);
  552. OUT_RING(0);
  553. ADVANCE_LP_RING();
  554. }
  555. }
  556. }
  557. static void i810_dma_dispatch_swap(struct drm_device *dev)
  558. {
  559. drm_i810_private_t *dev_priv = dev->dev_private;
  560. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  561. int nbox = sarea_priv->nbox;
  562. struct drm_clip_rect *pbox = sarea_priv->boxes;
  563. int pitch = dev_priv->pitch;
  564. int cpp = 2;
  565. int i;
  566. RING_LOCALS;
  567. DRM_DEBUG("swapbuffers\n");
  568. i810_kernel_lost_context(dev);
  569. if (nbox > I810_NR_SAREA_CLIPRECTS)
  570. nbox = I810_NR_SAREA_CLIPRECTS;
  571. for (i = 0; i < nbox; i++, pbox++) {
  572. unsigned int w = pbox->x2 - pbox->x1;
  573. unsigned int h = pbox->y2 - pbox->y1;
  574. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  575. unsigned int start = dst;
  576. if (pbox->x1 > pbox->x2 ||
  577. pbox->y1 > pbox->y2 ||
  578. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  579. continue;
  580. BEGIN_LP_RING(6);
  581. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  582. OUT_RING(pitch | (0xCC << 16));
  583. OUT_RING((h << 16) | (w * cpp));
  584. if (dev_priv->current_page == 0)
  585. OUT_RING(dev_priv->front_offset + start);
  586. else
  587. OUT_RING(dev_priv->back_offset + start);
  588. OUT_RING(pitch);
  589. if (dev_priv->current_page == 0)
  590. OUT_RING(dev_priv->back_offset + start);
  591. else
  592. OUT_RING(dev_priv->front_offset + start);
  593. ADVANCE_LP_RING();
  594. }
  595. }
  596. static void i810_dma_dispatch_vertex(struct drm_device *dev,
  597. struct drm_buf *buf, int discard, int used)
  598. {
  599. drm_i810_private_t *dev_priv = dev->dev_private;
  600. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  601. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  602. struct drm_clip_rect *box = sarea_priv->boxes;
  603. int nbox = sarea_priv->nbox;
  604. unsigned long address = (unsigned long)buf->bus_address;
  605. unsigned long start = address - dev->agp->base;
  606. int i = 0;
  607. RING_LOCALS;
  608. i810_kernel_lost_context(dev);
  609. if (nbox > I810_NR_SAREA_CLIPRECTS)
  610. nbox = I810_NR_SAREA_CLIPRECTS;
  611. if (used > 4 * 1024)
  612. used = 0;
  613. if (sarea_priv->dirty)
  614. i810EmitState(dev);
  615. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  616. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  617. *(u32 *) buf_priv->kernel_virtual =
  618. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  619. if (used & 4) {
  620. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  621. used += 4;
  622. }
  623. i810_unmap_buffer(buf);
  624. }
  625. if (used) {
  626. do {
  627. if (i < nbox) {
  628. BEGIN_LP_RING(4);
  629. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  630. SC_ENABLE);
  631. OUT_RING(GFX_OP_SCISSOR_INFO);
  632. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  633. OUT_RING((box[i].x2 -
  634. 1) | ((box[i].y2 - 1) << 16));
  635. ADVANCE_LP_RING();
  636. }
  637. BEGIN_LP_RING(4);
  638. OUT_RING(CMD_OP_BATCH_BUFFER);
  639. OUT_RING(start | BB1_PROTECTED);
  640. OUT_RING(start + used - 4);
  641. OUT_RING(0);
  642. ADVANCE_LP_RING();
  643. } while (++i < nbox);
  644. }
  645. if (discard) {
  646. dev_priv->counter++;
  647. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  648. I810_BUF_HARDWARE);
  649. BEGIN_LP_RING(8);
  650. OUT_RING(CMD_STORE_DWORD_IDX);
  651. OUT_RING(20);
  652. OUT_RING(dev_priv->counter);
  653. OUT_RING(CMD_STORE_DWORD_IDX);
  654. OUT_RING(buf_priv->my_use_idx);
  655. OUT_RING(I810_BUF_FREE);
  656. OUT_RING(CMD_REPORT_HEAD);
  657. OUT_RING(0);
  658. ADVANCE_LP_RING();
  659. }
  660. }
  661. static void i810_dma_dispatch_flip(struct drm_device *dev)
  662. {
  663. drm_i810_private_t *dev_priv = dev->dev_private;
  664. int pitch = dev_priv->pitch;
  665. RING_LOCALS;
  666. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  667. dev_priv->current_page,
  668. dev_priv->sarea_priv->pf_current_page);
  669. i810_kernel_lost_context(dev);
  670. BEGIN_LP_RING(2);
  671. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  672. OUT_RING(0);
  673. ADVANCE_LP_RING();
  674. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  675. /* On i815 at least ASYNC is buggy */
  676. /* pitch<<5 is from 11.2.8 p158,
  677. its the pitch / 8 then left shifted 8,
  678. so (pitch >> 3) << 8 */
  679. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  680. if (dev_priv->current_page == 0) {
  681. OUT_RING(dev_priv->back_offset);
  682. dev_priv->current_page = 1;
  683. } else {
  684. OUT_RING(dev_priv->front_offset);
  685. dev_priv->current_page = 0;
  686. }
  687. OUT_RING(0);
  688. ADVANCE_LP_RING();
  689. BEGIN_LP_RING(2);
  690. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  691. OUT_RING(0);
  692. ADVANCE_LP_RING();
  693. /* Increment the frame counter. The client-side 3D driver must
  694. * throttle the framerate by waiting for this value before
  695. * performing the swapbuffer ioctl.
  696. */
  697. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  698. }
  699. static void i810_dma_quiescent(struct drm_device *dev)
  700. {
  701. drm_i810_private_t *dev_priv = dev->dev_private;
  702. RING_LOCALS;
  703. i810_kernel_lost_context(dev);
  704. BEGIN_LP_RING(4);
  705. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  706. OUT_RING(CMD_REPORT_HEAD);
  707. OUT_RING(0);
  708. OUT_RING(0);
  709. ADVANCE_LP_RING();
  710. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  711. }
  712. static int i810_flush_queue(struct drm_device *dev)
  713. {
  714. drm_i810_private_t *dev_priv = dev->dev_private;
  715. struct drm_device_dma *dma = dev->dma;
  716. int i, ret = 0;
  717. RING_LOCALS;
  718. i810_kernel_lost_context(dev);
  719. BEGIN_LP_RING(2);
  720. OUT_RING(CMD_REPORT_HEAD);
  721. OUT_RING(0);
  722. ADVANCE_LP_RING();
  723. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  724. for (i = 0; i < dma->buf_count; i++) {
  725. struct drm_buf *buf = dma->buflist[i];
  726. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  727. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  728. I810_BUF_FREE);
  729. if (used == I810_BUF_HARDWARE)
  730. DRM_DEBUG("reclaimed from HARDWARE\n");
  731. if (used == I810_BUF_CLIENT)
  732. DRM_DEBUG("still on client\n");
  733. }
  734. return ret;
  735. }
  736. /* Must be called with the lock held */
  737. static void i810_reclaim_buffers(struct drm_device *dev,
  738. struct drm_file *file_priv)
  739. {
  740. struct drm_device_dma *dma = dev->dma;
  741. int i;
  742. if (!dma)
  743. return;
  744. if (!dev->dev_private)
  745. return;
  746. if (!dma->buflist)
  747. return;
  748. i810_flush_queue(dev);
  749. for (i = 0; i < dma->buf_count; i++) {
  750. struct drm_buf *buf = dma->buflist[i];
  751. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  752. if (buf->file_priv == file_priv && buf_priv) {
  753. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  754. I810_BUF_FREE);
  755. if (used == I810_BUF_CLIENT)
  756. DRM_DEBUG("reclaimed from client\n");
  757. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  758. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  759. }
  760. }
  761. }
  762. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  763. struct drm_file *file_priv)
  764. {
  765. LOCK_TEST_WITH_RETURN(dev, file_priv);
  766. i810_flush_queue(dev);
  767. return 0;
  768. }
  769. static int i810_dma_vertex(struct drm_device *dev, void *data,
  770. struct drm_file *file_priv)
  771. {
  772. struct drm_device_dma *dma = dev->dma;
  773. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  774. u32 *hw_status = dev_priv->hw_status_page;
  775. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  776. dev_priv->sarea_priv;
  777. drm_i810_vertex_t *vertex = data;
  778. LOCK_TEST_WITH_RETURN(dev, file_priv);
  779. DRM_DEBUG("idx %d used %d discard %d\n",
  780. vertex->idx, vertex->used, vertex->discard);
  781. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  782. return -EINVAL;
  783. i810_dma_dispatch_vertex(dev,
  784. dma->buflist[vertex->idx],
  785. vertex->discard, vertex->used);
  786. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  787. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  788. sarea_priv->last_enqueue = dev_priv->counter - 1;
  789. sarea_priv->last_dispatch = (int)hw_status[5];
  790. return 0;
  791. }
  792. static int i810_clear_bufs(struct drm_device *dev, void *data,
  793. struct drm_file *file_priv)
  794. {
  795. drm_i810_clear_t *clear = data;
  796. LOCK_TEST_WITH_RETURN(dev, file_priv);
  797. /* GH: Someone's doing nasty things... */
  798. if (!dev->dev_private)
  799. return -EINVAL;
  800. i810_dma_dispatch_clear(dev, clear->flags,
  801. clear->clear_color, clear->clear_depth);
  802. return 0;
  803. }
  804. static int i810_swap_bufs(struct drm_device *dev, void *data,
  805. struct drm_file *file_priv)
  806. {
  807. DRM_DEBUG("\n");
  808. LOCK_TEST_WITH_RETURN(dev, file_priv);
  809. i810_dma_dispatch_swap(dev);
  810. return 0;
  811. }
  812. static int i810_getage(struct drm_device *dev, void *data,
  813. struct drm_file *file_priv)
  814. {
  815. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  816. u32 *hw_status = dev_priv->hw_status_page;
  817. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  818. dev_priv->sarea_priv;
  819. sarea_priv->last_dispatch = (int)hw_status[5];
  820. return 0;
  821. }
  822. static int i810_getbuf(struct drm_device *dev, void *data,
  823. struct drm_file *file_priv)
  824. {
  825. int retcode = 0;
  826. drm_i810_dma_t *d = data;
  827. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  828. u32 *hw_status = dev_priv->hw_status_page;
  829. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  830. dev_priv->sarea_priv;
  831. LOCK_TEST_WITH_RETURN(dev, file_priv);
  832. d->granted = 0;
  833. retcode = i810_dma_get_buffer(dev, d, file_priv);
  834. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  835. task_pid_nr(current), retcode, d->granted);
  836. sarea_priv->last_dispatch = (int)hw_status[5];
  837. return retcode;
  838. }
  839. static int i810_copybuf(struct drm_device *dev, void *data,
  840. struct drm_file *file_priv)
  841. {
  842. /* Never copy - 2.4.x doesn't need it */
  843. return 0;
  844. }
  845. static int i810_docopy(struct drm_device *dev, void *data,
  846. struct drm_file *file_priv)
  847. {
  848. /* Never copy - 2.4.x doesn't need it */
  849. return 0;
  850. }
  851. static void i810_dma_dispatch_mc(struct drm_device *dev, struct drm_buf *buf, int used,
  852. unsigned int last_render)
  853. {
  854. drm_i810_private_t *dev_priv = dev->dev_private;
  855. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  856. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  857. unsigned long address = (unsigned long)buf->bus_address;
  858. unsigned long start = address - dev->agp->base;
  859. int u;
  860. RING_LOCALS;
  861. i810_kernel_lost_context(dev);
  862. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  863. if (u != I810_BUF_CLIENT)
  864. DRM_DEBUG("MC found buffer that isn't mine!\n");
  865. if (used > 4 * 1024)
  866. used = 0;
  867. sarea_priv->dirty = 0x7f;
  868. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  869. dev_priv->counter++;
  870. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  871. DRM_DEBUG("start : %lx\n", start);
  872. DRM_DEBUG("used : %d\n", used);
  873. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  874. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  875. if (used & 4) {
  876. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  877. used += 4;
  878. }
  879. i810_unmap_buffer(buf);
  880. }
  881. BEGIN_LP_RING(4);
  882. OUT_RING(CMD_OP_BATCH_BUFFER);
  883. OUT_RING(start | BB1_PROTECTED);
  884. OUT_RING(start + used - 4);
  885. OUT_RING(0);
  886. ADVANCE_LP_RING();
  887. BEGIN_LP_RING(8);
  888. OUT_RING(CMD_STORE_DWORD_IDX);
  889. OUT_RING(buf_priv->my_use_idx);
  890. OUT_RING(I810_BUF_FREE);
  891. OUT_RING(0);
  892. OUT_RING(CMD_STORE_DWORD_IDX);
  893. OUT_RING(16);
  894. OUT_RING(last_render);
  895. OUT_RING(0);
  896. ADVANCE_LP_RING();
  897. }
  898. static int i810_dma_mc(struct drm_device *dev, void *data,
  899. struct drm_file *file_priv)
  900. {
  901. struct drm_device_dma *dma = dev->dma;
  902. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  903. u32 *hw_status = dev_priv->hw_status_page;
  904. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  905. dev_priv->sarea_priv;
  906. drm_i810_mc_t *mc = data;
  907. LOCK_TEST_WITH_RETURN(dev, file_priv);
  908. if (mc->idx >= dma->buf_count || mc->idx < 0)
  909. return -EINVAL;
  910. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  911. mc->last_render);
  912. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  913. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  914. sarea_priv->last_enqueue = dev_priv->counter - 1;
  915. sarea_priv->last_dispatch = (int)hw_status[5];
  916. return 0;
  917. }
  918. static int i810_rstatus(struct drm_device *dev, void *data,
  919. struct drm_file *file_priv)
  920. {
  921. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  922. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  923. }
  924. static int i810_ov0_info(struct drm_device *dev, void *data,
  925. struct drm_file *file_priv)
  926. {
  927. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  928. drm_i810_overlay_t *ov = data;
  929. ov->offset = dev_priv->overlay_offset;
  930. ov->physical = dev_priv->overlay_physical;
  931. return 0;
  932. }
  933. static int i810_fstatus(struct drm_device *dev, void *data,
  934. struct drm_file *file_priv)
  935. {
  936. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  937. LOCK_TEST_WITH_RETURN(dev, file_priv);
  938. return I810_READ(0x30008);
  939. }
  940. static int i810_ov0_flip(struct drm_device *dev, void *data,
  941. struct drm_file *file_priv)
  942. {
  943. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  944. LOCK_TEST_WITH_RETURN(dev, file_priv);
  945. /* Tell the overlay to update */
  946. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  947. return 0;
  948. }
  949. /* Not sure why this isn't set all the time:
  950. */
  951. static void i810_do_init_pageflip(struct drm_device *dev)
  952. {
  953. drm_i810_private_t *dev_priv = dev->dev_private;
  954. DRM_DEBUG("\n");
  955. dev_priv->page_flipping = 1;
  956. dev_priv->current_page = 0;
  957. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  958. }
  959. static int i810_do_cleanup_pageflip(struct drm_device *dev)
  960. {
  961. drm_i810_private_t *dev_priv = dev->dev_private;
  962. DRM_DEBUG("\n");
  963. if (dev_priv->current_page != 0)
  964. i810_dma_dispatch_flip(dev);
  965. dev_priv->page_flipping = 0;
  966. return 0;
  967. }
  968. static int i810_flip_bufs(struct drm_device *dev, void *data,
  969. struct drm_file *file_priv)
  970. {
  971. drm_i810_private_t *dev_priv = dev->dev_private;
  972. DRM_DEBUG("\n");
  973. LOCK_TEST_WITH_RETURN(dev, file_priv);
  974. if (!dev_priv->page_flipping)
  975. i810_do_init_pageflip(dev);
  976. i810_dma_dispatch_flip(dev);
  977. return 0;
  978. }
  979. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  980. {
  981. /* i810 has 4 more counters */
  982. dev->counters += 4;
  983. dev->types[6] = _DRM_STAT_IRQ;
  984. dev->types[7] = _DRM_STAT_PRIMARY;
  985. dev->types[8] = _DRM_STAT_SECONDARY;
  986. dev->types[9] = _DRM_STAT_DMA;
  987. pci_set_master(dev->pdev);
  988. return 0;
  989. }
  990. void i810_driver_lastclose(struct drm_device *dev)
  991. {
  992. i810_dma_cleanup(dev);
  993. }
  994. void i810_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
  995. {
  996. if (dev->dev_private) {
  997. drm_i810_private_t *dev_priv = dev->dev_private;
  998. if (dev_priv->page_flipping)
  999. i810_do_cleanup_pageflip(dev);
  1000. }
  1001. }
  1002. void i810_driver_reclaim_buffers_locked(struct drm_device *dev,
  1003. struct drm_file *file_priv)
  1004. {
  1005. i810_reclaim_buffers(dev, file_priv);
  1006. }
  1007. int i810_driver_dma_quiescent(struct drm_device *dev)
  1008. {
  1009. i810_dma_quiescent(dev);
  1010. return 0;
  1011. }
  1012. struct drm_ioctl_desc i810_ioctls[] = {
  1013. DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1014. DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
  1015. DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
  1016. DRM_IOCTL_DEF_DRV(I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1017. DRM_IOCTL_DEF_DRV(I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED),
  1018. DRM_IOCTL_DEF_DRV(I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED),
  1019. DRM_IOCTL_DEF_DRV(I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
  1020. DRM_IOCTL_DEF_DRV(I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED),
  1021. DRM_IOCTL_DEF_DRV(I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED),
  1022. DRM_IOCTL_DEF_DRV(I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED),
  1023. DRM_IOCTL_DEF_DRV(I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED),
  1024. DRM_IOCTL_DEF_DRV(I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED),
  1025. DRM_IOCTL_DEF_DRV(I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1026. DRM_IOCTL_DEF_DRV(I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED),
  1027. DRM_IOCTL_DEF_DRV(I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
  1028. };
  1029. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1030. /**
  1031. * Determine if the device really is AGP or not.
  1032. *
  1033. * All Intel graphics chipsets are treated as AGP, even if they are really
  1034. * PCI-e.
  1035. *
  1036. * \param dev The device to be tested.
  1037. *
  1038. * \returns
  1039. * A value of 1 is always retured to indictate every i810 is AGP.
  1040. */
  1041. int i810_driver_device_is_agp(struct drm_device *dev)
  1042. {
  1043. return 1;
  1044. }