Kconfig 8.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298
  1. #
  2. # DMA engine configuration
  3. #
  4. menuconfig DMADEVICES
  5. bool "DMA Engine support"
  6. depends on HAS_DMA
  7. help
  8. DMA engines can do asynchronous data transfers without
  9. involving the host CPU. Currently, this framework can be
  10. used to offload memory copies in the network stack and
  11. RAID operations in the MD driver. This menu only presents
  12. DMA Device drivers supported by the configured arch, it may
  13. be empty in some cases.
  14. config DMADEVICES_DEBUG
  15. bool "DMA Engine debugging"
  16. depends on DMADEVICES != n
  17. help
  18. This is an option for use by developers; most people should
  19. say N here. This enables DMA engine core and driver debugging.
  20. config DMADEVICES_VDEBUG
  21. bool "DMA Engine verbose debugging"
  22. depends on DMADEVICES_DEBUG != n
  23. help
  24. This is an option for use by developers; most people should
  25. say N here. This enables deeper (more verbose) debugging of
  26. the DMA engine core and drivers.
  27. if DMADEVICES
  28. comment "DMA Devices"
  29. config INTEL_MID_DMAC
  30. tristate "Intel MID DMA support for Peripheral DMA controllers"
  31. depends on PCI && X86
  32. select DMA_ENGINE
  33. default n
  34. help
  35. Enable support for the Intel(R) MID DMA engine present
  36. in Intel MID chipsets.
  37. Say Y here if you have such a chipset.
  38. If unsure, say N.
  39. config ASYNC_TX_ENABLE_CHANNEL_SWITCH
  40. bool
  41. config AMBA_PL08X
  42. bool "ARM PrimeCell PL080 or PL081 support"
  43. depends on ARM_AMBA && EXPERIMENTAL
  44. select DMA_ENGINE
  45. help
  46. Platform has a PL08x DMAC device
  47. which can provide DMA engine support
  48. config INTEL_IOATDMA
  49. tristate "Intel I/OAT DMA support"
  50. depends on PCI && X86
  51. select DMA_ENGINE
  52. select DCA
  53. select ASYNC_TX_DISABLE_PQ_VAL_DMA
  54. select ASYNC_TX_DISABLE_XOR_VAL_DMA
  55. help
  56. Enable support for the Intel(R) I/OAT DMA engine present
  57. in recent Intel Xeon chipsets.
  58. Say Y here if you have such a chipset.
  59. If unsure, say N.
  60. config INTEL_IOP_ADMA
  61. tristate "Intel IOP ADMA support"
  62. depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
  63. select DMA_ENGINE
  64. select ASYNC_TX_ENABLE_CHANNEL_SWITCH
  65. help
  66. Enable support for the Intel(R) IOP Series RAID engines.
  67. config DW_DMAC
  68. tristate "Synopsys DesignWare AHB DMA support"
  69. depends on HAVE_CLK
  70. select DMA_ENGINE
  71. default y if CPU_AT32AP7000
  72. help
  73. Support the Synopsys DesignWare AHB DMA controller. This
  74. can be integrated in chips such as the Atmel AT32ap7000.
  75. config AT_HDMAC
  76. tristate "Atmel AHB DMA support"
  77. depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
  78. select DMA_ENGINE
  79. help
  80. Support the Atmel AHB DMA controller. This can be integrated in
  81. chips such as the Atmel AT91SAM9RL.
  82. config FSL_DMA
  83. tristate "Freescale Elo and Elo Plus DMA support"
  84. depends on FSL_SOC
  85. select DMA_ENGINE
  86. select ASYNC_TX_ENABLE_CHANNEL_SWITCH
  87. ---help---
  88. Enable support for the Freescale Elo and Elo Plus DMA controllers.
  89. The Elo is the DMA controller on some 82xx and 83xx parts, and the
  90. Elo Plus is the DMA controller on 85xx and 86xx parts.
  91. config MPC512X_DMA
  92. tristate "Freescale MPC512x built-in DMA engine support"
  93. depends on PPC_MPC512x || PPC_MPC831x
  94. select DMA_ENGINE
  95. ---help---
  96. Enable support for the Freescale MPC512x built-in DMA engine.
  97. config MV_XOR
  98. bool "Marvell XOR engine support"
  99. depends on PLAT_ORION
  100. select DMA_ENGINE
  101. select ASYNC_TX_ENABLE_CHANNEL_SWITCH
  102. ---help---
  103. Enable support for the Marvell XOR engine.
  104. config MX3_IPU
  105. bool "MX3x Image Processing Unit support"
  106. depends on ARCH_MXC
  107. select DMA_ENGINE
  108. default y
  109. help
  110. If you plan to use the Image Processing unit in the i.MX3x, say
  111. Y here. If unsure, select Y.
  112. config MX3_IPU_IRQS
  113. int "Number of dynamically mapped interrupts for IPU"
  114. depends on MX3_IPU
  115. range 2 137
  116. default 4
  117. help
  118. Out of 137 interrupt sources on i.MX31 IPU only very few are used.
  119. To avoid bloating the irq_desc[] array we allocate a sufficient
  120. number of IRQ slots and map them dynamically to specific sources.
  121. config TXX9_DMAC
  122. tristate "Toshiba TXx9 SoC DMA support"
  123. depends on MACH_TX49XX || MACH_TX39XX
  124. select DMA_ENGINE
  125. help
  126. Support the TXx9 SoC internal DMA controller. This can be
  127. integrated in chips such as the Toshiba TX4927/38/39.
  128. config SH_DMAE
  129. tristate "Renesas SuperH DMAC support"
  130. depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
  131. depends on !SH_DMA_API
  132. select DMA_ENGINE
  133. help
  134. Enable support for the Renesas SuperH DMA controllers.
  135. config COH901318
  136. bool "ST-Ericsson COH901318 DMA support"
  137. select DMA_ENGINE
  138. depends on ARCH_U300
  139. help
  140. Enable support for ST-Ericsson COH 901 318 DMA.
  141. config STE_DMA40
  142. bool "ST-Ericsson DMA40 support"
  143. depends on ARCH_U8500
  144. select DMA_ENGINE
  145. help
  146. Support for ST-Ericsson DMA40 controller
  147. config AMCC_PPC440SPE_ADMA
  148. tristate "AMCC PPC440SPe ADMA support"
  149. depends on 440SPe || 440SP
  150. select DMA_ENGINE
  151. select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  152. select ASYNC_TX_ENABLE_CHANNEL_SWITCH
  153. help
  154. Enable support for the AMCC PPC440SPe RAID engines.
  155. config TIMB_DMA
  156. tristate "Timberdale FPGA DMA support"
  157. depends on MFD_TIMBERDALE || HAS_IOMEM
  158. select DMA_ENGINE
  159. help
  160. Enable support for the Timberdale FPGA DMA engine.
  161. config SIRF_DMA
  162. tristate "CSR SiRFprimaII DMA support"
  163. depends on ARCH_PRIMA2
  164. select DMA_ENGINE
  165. help
  166. Enable support for the CSR SiRFprimaII DMA engine.
  167. config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  168. bool
  169. config PL330_DMA
  170. tristate "DMA API Driver for PL330"
  171. select DMA_ENGINE
  172. depends on ARM_AMBA
  173. help
  174. Select if your platform has one or more PL330 DMACs.
  175. You need to provide platform specific settings via
  176. platform_data for a dma-pl330 device.
  177. config PCH_DMA
  178. tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
  179. depends on PCI && X86
  180. select DMA_ENGINE
  181. help
  182. Enable support for Intel EG20T PCH DMA engine.
  183. This driver also can be used for LAPIS Semiconductor IOH(Input/
  184. Output Hub), ML7213, ML7223 and ML7831.
  185. ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
  186. for MP(Media Phone) use and ML7831 IOH is for general purpose use.
  187. ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
  188. ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
  189. config IMX_SDMA
  190. tristate "i.MX SDMA support"
  191. depends on ARCH_MXC
  192. select DMA_ENGINE
  193. help
  194. Support the i.MX SDMA engine. This engine is integrated into
  195. Freescale i.MX25/31/35/51/53 chips.
  196. config IMX_DMA
  197. tristate "i.MX DMA support"
  198. depends on ARCH_MXC
  199. select DMA_ENGINE
  200. help
  201. Support the i.MX DMA engine. This engine is integrated into
  202. Freescale i.MX1/21/27 chips.
  203. config MXS_DMA
  204. bool "MXS DMA support"
  205. depends on SOC_IMX23 || SOC_IMX28
  206. select DMA_ENGINE
  207. help
  208. Support the MXS DMA engine. This engine including APBH-DMA
  209. and APBX-DMA is integrated into Freescale i.MX23/28 chips.
  210. config EP93XX_DMA
  211. bool "Cirrus Logic EP93xx DMA support"
  212. depends on ARCH_EP93XX
  213. select DMA_ENGINE
  214. help
  215. Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
  216. config DMA_SA11X0
  217. tristate "SA-11x0 DMA support"
  218. depends on ARCH_SA1100
  219. select DMA_ENGINE
  220. help
  221. Support the DMA engine found on Intel StrongARM SA-1100 and
  222. SA-1110 SoCs. This DMA engine can only be used with on-chip
  223. devices.
  224. config DMA_ENGINE
  225. bool
  226. comment "DMA Clients"
  227. depends on DMA_ENGINE
  228. config NET_DMA
  229. bool "Network: TCP receive copy offload"
  230. depends on DMA_ENGINE && NET
  231. default (INTEL_IOATDMA || FSL_DMA)
  232. help
  233. This enables the use of DMA engines in the network stack to
  234. offload receive copy-to-user operations, freeing CPU cycles.
  235. Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
  236. say N.
  237. config ASYNC_TX_DMA
  238. bool "Async_tx: Offload support for the async_tx api"
  239. depends on DMA_ENGINE
  240. help
  241. This allows the async_tx api to take advantage of offload engines for
  242. memcpy, memset, xor, and raid6 p+q operations. If your platform has
  243. a dma engine that can perform raid operations and you have enabled
  244. MD_RAID456 say Y.
  245. If unsure, say N.
  246. config DMATEST
  247. tristate "DMA Test client"
  248. depends on DMA_ENGINE
  249. help
  250. Simple DMA test client. Say N unless you're debugging a
  251. DMA Device driver.
  252. endif