setup.c 16 KB

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  1. /*
  2. * Renesas System Solutions Asia Pte. Ltd - Migo-R
  3. *
  4. * Copyright (C) 2008 Magnus Damm
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/init.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/input.h>
  14. #include <linux/input/sh_keysc.h>
  15. #include <linux/mmc/host.h>
  16. #include <linux/mmc/sh_mobile_sdhi.h>
  17. #include <linux/mtd/physmap.h>
  18. #include <linux/mtd/nand.h>
  19. #include <linux/i2c.h>
  20. #include <linux/smc91x.h>
  21. #include <linux/delay.h>
  22. #include <linux/clk.h>
  23. #include <linux/gpio.h>
  24. #include <linux/videodev2.h>
  25. #include <video/sh_mobile_lcdc.h>
  26. #include <media/sh_mobile_ceu.h>
  27. #include <media/ov772x.h>
  28. #include <media/soc_camera.h>
  29. #include <media/tw9910.h>
  30. #include <asm/clock.h>
  31. #include <asm/machvec.h>
  32. #include <asm/io.h>
  33. #include <asm/suspend.h>
  34. #include <mach/migor.h>
  35. #include <cpu/sh7722.h>
  36. /* Address IRQ Size Bus Description
  37. * 0x00000000 64MB 16 NOR Flash (SP29PL256N)
  38. * 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
  39. * 0x10000000 IRQ0 16 Ethernet (SMC91C111)
  40. * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
  41. * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
  42. */
  43. static struct smc91x_platdata smc91x_info = {
  44. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  45. };
  46. static struct resource smc91x_eth_resources[] = {
  47. [0] = {
  48. .name = "SMC91C111" ,
  49. .start = 0x10000300,
  50. .end = 0x1000030f,
  51. .flags = IORESOURCE_MEM,
  52. },
  53. [1] = {
  54. .start = 32, /* IRQ0 */
  55. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  56. },
  57. };
  58. static struct platform_device smc91x_eth_device = {
  59. .name = "smc91x",
  60. .num_resources = ARRAY_SIZE(smc91x_eth_resources),
  61. .resource = smc91x_eth_resources,
  62. .dev = {
  63. .platform_data = &smc91x_info,
  64. },
  65. };
  66. static struct sh_keysc_info sh_keysc_info = {
  67. .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
  68. .scan_timing = 3,
  69. .delay = 5,
  70. .keycodes = {
  71. 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
  72. 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
  73. 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
  74. 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
  75. 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
  76. },
  77. };
  78. static struct resource sh_keysc_resources[] = {
  79. [0] = {
  80. .start = 0x044b0000,
  81. .end = 0x044b000f,
  82. .flags = IORESOURCE_MEM,
  83. },
  84. [1] = {
  85. .start = 79,
  86. .flags = IORESOURCE_IRQ,
  87. },
  88. };
  89. static struct platform_device sh_keysc_device = {
  90. .name = "sh_keysc",
  91. .id = 0, /* "keysc0" clock */
  92. .num_resources = ARRAY_SIZE(sh_keysc_resources),
  93. .resource = sh_keysc_resources,
  94. .dev = {
  95. .platform_data = &sh_keysc_info,
  96. },
  97. };
  98. static struct mtd_partition migor_nor_flash_partitions[] =
  99. {
  100. {
  101. .name = "uboot",
  102. .offset = 0,
  103. .size = (1 * 1024 * 1024),
  104. .mask_flags = MTD_WRITEABLE, /* Read-only */
  105. },
  106. {
  107. .name = "rootfs",
  108. .offset = MTDPART_OFS_APPEND,
  109. .size = (15 * 1024 * 1024),
  110. },
  111. {
  112. .name = "other",
  113. .offset = MTDPART_OFS_APPEND,
  114. .size = MTDPART_SIZ_FULL,
  115. },
  116. };
  117. static struct physmap_flash_data migor_nor_flash_data = {
  118. .width = 2,
  119. .parts = migor_nor_flash_partitions,
  120. .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
  121. };
  122. static struct resource migor_nor_flash_resources[] = {
  123. [0] = {
  124. .name = "NOR Flash",
  125. .start = 0x00000000,
  126. .end = 0x03ffffff,
  127. .flags = IORESOURCE_MEM,
  128. }
  129. };
  130. static struct platform_device migor_nor_flash_device = {
  131. .name = "physmap-flash",
  132. .resource = migor_nor_flash_resources,
  133. .num_resources = ARRAY_SIZE(migor_nor_flash_resources),
  134. .dev = {
  135. .platform_data = &migor_nor_flash_data,
  136. },
  137. };
  138. static struct mtd_partition migor_nand_flash_partitions[] = {
  139. {
  140. .name = "nanddata1",
  141. .offset = 0x0,
  142. .size = 512 * 1024 * 1024,
  143. },
  144. {
  145. .name = "nanddata2",
  146. .offset = MTDPART_OFS_APPEND,
  147. .size = 512 * 1024 * 1024,
  148. },
  149. };
  150. static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
  151. unsigned int ctrl)
  152. {
  153. struct nand_chip *chip = mtd->priv;
  154. if (cmd == NAND_CMD_NONE)
  155. return;
  156. if (ctrl & NAND_CLE)
  157. writeb(cmd, chip->IO_ADDR_W + 0x00400000);
  158. else if (ctrl & NAND_ALE)
  159. writeb(cmd, chip->IO_ADDR_W + 0x00800000);
  160. else
  161. writeb(cmd, chip->IO_ADDR_W);
  162. }
  163. static int migor_nand_flash_ready(struct mtd_info *mtd)
  164. {
  165. return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
  166. }
  167. static struct platform_nand_data migor_nand_flash_data = {
  168. .chip = {
  169. .nr_chips = 1,
  170. .partitions = migor_nand_flash_partitions,
  171. .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
  172. .chip_delay = 20,
  173. .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
  174. },
  175. .ctrl = {
  176. .dev_ready = migor_nand_flash_ready,
  177. .cmd_ctrl = migor_nand_flash_cmd_ctl,
  178. },
  179. };
  180. static struct resource migor_nand_flash_resources[] = {
  181. [0] = {
  182. .name = "NAND Flash",
  183. .start = 0x18000000,
  184. .end = 0x18ffffff,
  185. .flags = IORESOURCE_MEM,
  186. },
  187. };
  188. static struct platform_device migor_nand_flash_device = {
  189. .name = "gen_nand",
  190. .resource = migor_nand_flash_resources,
  191. .num_resources = ARRAY_SIZE(migor_nand_flash_resources),
  192. .dev = {
  193. .platform_data = &migor_nand_flash_data,
  194. }
  195. };
  196. static const struct fb_videomode migor_lcd_modes[] = {
  197. {
  198. #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
  199. .name = "LB070WV1",
  200. .xres = 800,
  201. .yres = 480,
  202. .left_margin = 64,
  203. .right_margin = 16,
  204. .hsync_len = 120,
  205. .sync = 0,
  206. #elif defined(CONFIG_SH_MIGOR_QVGA)
  207. .name = "PH240320T",
  208. .xres = 320,
  209. .yres = 240,
  210. .left_margin = 0,
  211. .right_margin = 16,
  212. .hsync_len = 8,
  213. .sync = FB_SYNC_HOR_HIGH_ACT,
  214. #endif
  215. .upper_margin = 1,
  216. .lower_margin = 17,
  217. .vsync_len = 2,
  218. },
  219. };
  220. static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
  221. #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
  222. .clock_source = LCDC_CLK_BUS,
  223. .ch[0] = {
  224. .chan = LCDC_CHAN_MAINLCD,
  225. .fourcc = V4L2_PIX_FMT_RGB565,
  226. .interface_type = RGB16,
  227. .clock_divider = 2,
  228. .lcd_modes = migor_lcd_modes,
  229. .num_modes = ARRAY_SIZE(migor_lcd_modes),
  230. .panel_cfg = { /* 7.0 inch */
  231. .width = 152,
  232. .height = 91,
  233. },
  234. }
  235. #elif defined(CONFIG_SH_MIGOR_QVGA)
  236. .clock_source = LCDC_CLK_PERIPHERAL,
  237. .ch[0] = {
  238. .chan = LCDC_CHAN_MAINLCD,
  239. .fourcc = V4L2_PIX_FMT_RGB565,
  240. .interface_type = SYS16A,
  241. .clock_divider = 10,
  242. .lcd_modes = migor_lcd_modes,
  243. .num_modes = ARRAY_SIZE(migor_lcd_modes),
  244. .panel_cfg = {
  245. .width = 49, /* 2.4 inch */
  246. .height = 37,
  247. .setup_sys = migor_lcd_qvga_setup,
  248. },
  249. .sys_bus_cfg = {
  250. .ldmt2r = 0x06000a09,
  251. .ldmt3r = 0x180e3418,
  252. /* set 1s delay to encourage fsync() */
  253. .deferred_io_msec = 1000,
  254. },
  255. }
  256. #endif
  257. };
  258. static struct resource migor_lcdc_resources[] = {
  259. [0] = {
  260. .name = "LCDC",
  261. .start = 0xfe940000, /* P4-only space */
  262. .end = 0xfe942fff,
  263. .flags = IORESOURCE_MEM,
  264. },
  265. [1] = {
  266. .start = 28,
  267. .flags = IORESOURCE_IRQ,
  268. },
  269. };
  270. static struct platform_device migor_lcdc_device = {
  271. .name = "sh_mobile_lcdc_fb",
  272. .num_resources = ARRAY_SIZE(migor_lcdc_resources),
  273. .resource = migor_lcdc_resources,
  274. .dev = {
  275. .platform_data = &sh_mobile_lcdc_info,
  276. },
  277. };
  278. static struct clk *camera_clk;
  279. static DEFINE_MUTEX(camera_lock);
  280. static void camera_power_on(int is_tw)
  281. {
  282. mutex_lock(&camera_lock);
  283. /* Use 10 MHz VIO_CKO instead of 24 MHz to work
  284. * around signal quality issues on Panel Board V2.1.
  285. */
  286. camera_clk = clk_get(NULL, "video_clk");
  287. clk_set_rate(camera_clk, 10000000);
  288. clk_enable(camera_clk); /* start VIO_CKO */
  289. /* use VIO_RST to take camera out of reset */
  290. mdelay(10);
  291. if (is_tw) {
  292. gpio_set_value(GPIO_PTT2, 0);
  293. gpio_set_value(GPIO_PTT0, 0);
  294. } else {
  295. gpio_set_value(GPIO_PTT0, 1);
  296. }
  297. gpio_set_value(GPIO_PTT3, 0);
  298. mdelay(10);
  299. gpio_set_value(GPIO_PTT3, 1);
  300. mdelay(10); /* wait to let chip come out of reset */
  301. }
  302. static void camera_power_off(void)
  303. {
  304. clk_disable(camera_clk); /* stop VIO_CKO */
  305. clk_put(camera_clk);
  306. gpio_set_value(GPIO_PTT3, 0);
  307. mutex_unlock(&camera_lock);
  308. }
  309. static int ov7725_power(struct device *dev, int mode)
  310. {
  311. if (mode)
  312. camera_power_on(0);
  313. else
  314. camera_power_off();
  315. return 0;
  316. }
  317. static int tw9910_power(struct device *dev, int mode)
  318. {
  319. if (mode)
  320. camera_power_on(1);
  321. else
  322. camera_power_off();
  323. return 0;
  324. }
  325. static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
  326. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  327. };
  328. static struct resource migor_ceu_resources[] = {
  329. [0] = {
  330. .name = "CEU",
  331. .start = 0xfe910000,
  332. .end = 0xfe91009f,
  333. .flags = IORESOURCE_MEM,
  334. },
  335. [1] = {
  336. .start = 52,
  337. .flags = IORESOURCE_IRQ,
  338. },
  339. [2] = {
  340. /* place holder for contiguous memory */
  341. },
  342. };
  343. static struct platform_device migor_ceu_device = {
  344. .name = "sh_mobile_ceu",
  345. .id = 0, /* "ceu0" clock */
  346. .num_resources = ARRAY_SIZE(migor_ceu_resources),
  347. .resource = migor_ceu_resources,
  348. .dev = {
  349. .platform_data = &sh_mobile_ceu_info,
  350. },
  351. };
  352. static struct resource sdhi_cn9_resources[] = {
  353. [0] = {
  354. .name = "SDHI",
  355. .start = 0x04ce0000,
  356. .end = 0x04ce00ff,
  357. .flags = IORESOURCE_MEM,
  358. },
  359. [1] = {
  360. .start = 100,
  361. .flags = IORESOURCE_IRQ,
  362. },
  363. };
  364. static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
  365. .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
  366. .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
  367. .tmio_caps = MMC_CAP_SDIO_IRQ,
  368. };
  369. static struct platform_device sdhi_cn9_device = {
  370. .name = "sh_mobile_sdhi",
  371. .num_resources = ARRAY_SIZE(sdhi_cn9_resources),
  372. .resource = sdhi_cn9_resources,
  373. .dev = {
  374. .platform_data = &sh7724_sdhi_data,
  375. },
  376. };
  377. static struct i2c_board_info migor_i2c_devices[] = {
  378. {
  379. I2C_BOARD_INFO("rs5c372b", 0x32),
  380. },
  381. {
  382. I2C_BOARD_INFO("migor_ts", 0x51),
  383. .irq = 38, /* IRQ6 */
  384. },
  385. {
  386. I2C_BOARD_INFO("wm8978", 0x1a),
  387. },
  388. };
  389. static struct i2c_board_info migor_i2c_camera[] = {
  390. {
  391. I2C_BOARD_INFO("ov772x", 0x21),
  392. },
  393. {
  394. I2C_BOARD_INFO("tw9910", 0x45),
  395. },
  396. };
  397. static struct ov772x_camera_info ov7725_info;
  398. static struct soc_camera_link ov7725_link = {
  399. .power = ov7725_power,
  400. .board_info = &migor_i2c_camera[0],
  401. .i2c_adapter_id = 0,
  402. .priv = &ov7725_info,
  403. };
  404. static struct tw9910_video_info tw9910_info = {
  405. .buswidth = SOCAM_DATAWIDTH_8,
  406. .mpout = TW9910_MPO_FIELD,
  407. };
  408. static struct soc_camera_link tw9910_link = {
  409. .power = tw9910_power,
  410. .board_info = &migor_i2c_camera[1],
  411. .i2c_adapter_id = 0,
  412. .priv = &tw9910_info,
  413. };
  414. static struct platform_device migor_camera[] = {
  415. {
  416. .name = "soc-camera-pdrv",
  417. .id = 0,
  418. .dev = {
  419. .platform_data = &ov7725_link,
  420. },
  421. }, {
  422. .name = "soc-camera-pdrv",
  423. .id = 1,
  424. .dev = {
  425. .platform_data = &tw9910_link,
  426. },
  427. },
  428. };
  429. static struct platform_device *migor_devices[] __initdata = {
  430. &smc91x_eth_device,
  431. &sh_keysc_device,
  432. &migor_lcdc_device,
  433. &migor_ceu_device,
  434. &migor_nor_flash_device,
  435. &migor_nand_flash_device,
  436. &sdhi_cn9_device,
  437. &migor_camera[0],
  438. &migor_camera[1],
  439. };
  440. extern char migor_sdram_enter_start;
  441. extern char migor_sdram_enter_end;
  442. extern char migor_sdram_leave_start;
  443. extern char migor_sdram_leave_end;
  444. static int __init migor_devices_setup(void)
  445. {
  446. /* register board specific self-refresh code */
  447. sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
  448. &migor_sdram_enter_start,
  449. &migor_sdram_enter_end,
  450. &migor_sdram_leave_start,
  451. &migor_sdram_leave_end);
  452. /* Let D11 LED show STATUS0 */
  453. gpio_request(GPIO_FN_STATUS0, NULL);
  454. /* Lit D12 LED show PDSTATUS */
  455. gpio_request(GPIO_FN_PDSTATUS, NULL);
  456. /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
  457. gpio_request(GPIO_FN_IRQ0, NULL);
  458. __raw_writel(0x00003400, BSC_CS4BCR);
  459. __raw_writel(0x00110080, BSC_CS4WCR);
  460. /* KEYSC */
  461. gpio_request(GPIO_FN_KEYOUT0, NULL);
  462. gpio_request(GPIO_FN_KEYOUT1, NULL);
  463. gpio_request(GPIO_FN_KEYOUT2, NULL);
  464. gpio_request(GPIO_FN_KEYOUT3, NULL);
  465. gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
  466. gpio_request(GPIO_FN_KEYIN1, NULL);
  467. gpio_request(GPIO_FN_KEYIN2, NULL);
  468. gpio_request(GPIO_FN_KEYIN3, NULL);
  469. gpio_request(GPIO_FN_KEYIN4, NULL);
  470. gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
  471. /* NAND Flash */
  472. gpio_request(GPIO_FN_CS6A_CE2B, NULL);
  473. __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
  474. gpio_request(GPIO_PTA1, NULL);
  475. gpio_direction_input(GPIO_PTA1);
  476. /* SDHI */
  477. gpio_request(GPIO_FN_SDHICD, NULL);
  478. gpio_request(GPIO_FN_SDHIWP, NULL);
  479. gpio_request(GPIO_FN_SDHID3, NULL);
  480. gpio_request(GPIO_FN_SDHID2, NULL);
  481. gpio_request(GPIO_FN_SDHID1, NULL);
  482. gpio_request(GPIO_FN_SDHID0, NULL);
  483. gpio_request(GPIO_FN_SDHICMD, NULL);
  484. gpio_request(GPIO_FN_SDHICLK, NULL);
  485. /* Touch Panel */
  486. gpio_request(GPIO_FN_IRQ6, NULL);
  487. /* LCD Panel */
  488. #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
  489. gpio_request(GPIO_FN_LCDD17, NULL);
  490. gpio_request(GPIO_FN_LCDD16, NULL);
  491. gpio_request(GPIO_FN_LCDD15, NULL);
  492. gpio_request(GPIO_FN_LCDD14, NULL);
  493. gpio_request(GPIO_FN_LCDD13, NULL);
  494. gpio_request(GPIO_FN_LCDD12, NULL);
  495. gpio_request(GPIO_FN_LCDD11, NULL);
  496. gpio_request(GPIO_FN_LCDD10, NULL);
  497. gpio_request(GPIO_FN_LCDD8, NULL);
  498. gpio_request(GPIO_FN_LCDD7, NULL);
  499. gpio_request(GPIO_FN_LCDD6, NULL);
  500. gpio_request(GPIO_FN_LCDD5, NULL);
  501. gpio_request(GPIO_FN_LCDD4, NULL);
  502. gpio_request(GPIO_FN_LCDD3, NULL);
  503. gpio_request(GPIO_FN_LCDD2, NULL);
  504. gpio_request(GPIO_FN_LCDD1, NULL);
  505. gpio_request(GPIO_FN_LCDRS, NULL);
  506. gpio_request(GPIO_FN_LCDCS, NULL);
  507. gpio_request(GPIO_FN_LCDRD, NULL);
  508. gpio_request(GPIO_FN_LCDWR, NULL);
  509. gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
  510. gpio_direction_output(GPIO_PTH2, 1);
  511. #endif
  512. #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
  513. gpio_request(GPIO_FN_LCDD15, NULL);
  514. gpio_request(GPIO_FN_LCDD14, NULL);
  515. gpio_request(GPIO_FN_LCDD13, NULL);
  516. gpio_request(GPIO_FN_LCDD12, NULL);
  517. gpio_request(GPIO_FN_LCDD11, NULL);
  518. gpio_request(GPIO_FN_LCDD10, NULL);
  519. gpio_request(GPIO_FN_LCDD9, NULL);
  520. gpio_request(GPIO_FN_LCDD8, NULL);
  521. gpio_request(GPIO_FN_LCDD7, NULL);
  522. gpio_request(GPIO_FN_LCDD6, NULL);
  523. gpio_request(GPIO_FN_LCDD5, NULL);
  524. gpio_request(GPIO_FN_LCDD4, NULL);
  525. gpio_request(GPIO_FN_LCDD3, NULL);
  526. gpio_request(GPIO_FN_LCDD2, NULL);
  527. gpio_request(GPIO_FN_LCDD1, NULL);
  528. gpio_request(GPIO_FN_LCDD0, NULL);
  529. gpio_request(GPIO_FN_LCDLCLK, NULL);
  530. gpio_request(GPIO_FN_LCDDCK, NULL);
  531. gpio_request(GPIO_FN_LCDVEPWC, NULL);
  532. gpio_request(GPIO_FN_LCDVCPWC, NULL);
  533. gpio_request(GPIO_FN_LCDVSYN, NULL);
  534. gpio_request(GPIO_FN_LCDHSYN, NULL);
  535. gpio_request(GPIO_FN_LCDDISP, NULL);
  536. gpio_request(GPIO_FN_LCDDON, NULL);
  537. #endif
  538. /* CEU */
  539. gpio_request(GPIO_FN_VIO_CLK2, NULL);
  540. gpio_request(GPIO_FN_VIO_VD2, NULL);
  541. gpio_request(GPIO_FN_VIO_HD2, NULL);
  542. gpio_request(GPIO_FN_VIO_FLD, NULL);
  543. gpio_request(GPIO_FN_VIO_CKO, NULL);
  544. gpio_request(GPIO_FN_VIO_D15, NULL);
  545. gpio_request(GPIO_FN_VIO_D14, NULL);
  546. gpio_request(GPIO_FN_VIO_D13, NULL);
  547. gpio_request(GPIO_FN_VIO_D12, NULL);
  548. gpio_request(GPIO_FN_VIO_D11, NULL);
  549. gpio_request(GPIO_FN_VIO_D10, NULL);
  550. gpio_request(GPIO_FN_VIO_D9, NULL);
  551. gpio_request(GPIO_FN_VIO_D8, NULL);
  552. gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
  553. gpio_direction_output(GPIO_PTT3, 0);
  554. gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
  555. gpio_direction_output(GPIO_PTT2, 1);
  556. gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
  557. #ifdef CONFIG_SH_MIGOR_RTA_WVGA
  558. gpio_direction_output(GPIO_PTT0, 0);
  559. #else
  560. gpio_direction_output(GPIO_PTT0, 1);
  561. #endif
  562. __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
  563. platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
  564. /* SIU: Port B */
  565. gpio_request(GPIO_FN_SIUBOLR, NULL);
  566. gpio_request(GPIO_FN_SIUBOBT, NULL);
  567. gpio_request(GPIO_FN_SIUBISLD, NULL);
  568. gpio_request(GPIO_FN_SIUBOSLD, NULL);
  569. gpio_request(GPIO_FN_SIUMCKB, NULL);
  570. /*
  571. * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
  572. * output. Need only SIUB, set to output for master mode (table 34.2)
  573. */
  574. __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
  575. i2c_register_board_info(0, migor_i2c_devices,
  576. ARRAY_SIZE(migor_i2c_devices));
  577. return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
  578. }
  579. arch_initcall(migor_devices_setup);
  580. /* Return the board specific boot mode pin configuration */
  581. static int migor_mode_pins(void)
  582. {
  583. /* MD0=1, MD1=1, MD2=0: Clock Mode 3
  584. * MD3=0: 16-bit Area0 Bus Width
  585. * MD5=1: Little Endian
  586. * TSTMD=1, MD8=0: Test Mode Disabled
  587. */
  588. return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
  589. }
  590. /*
  591. * The Machine Vector
  592. */
  593. static struct sh_machine_vector mv_migor __initmv = {
  594. .mv_name = "Migo-R",
  595. .mv_mode_pins = migor_mode_pins,
  596. };