mpc8xx_pic.c 4.1 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/stddef.h>
  3. #include <linux/init.h>
  4. #include <linux/sched.h>
  5. #include <linux/signal.h>
  6. #include <linux/irq.h>
  7. #include <linux/dma-mapping.h>
  8. #include <asm/prom.h>
  9. #include <asm/irq.h>
  10. #include <asm/io.h>
  11. #include <asm/8xx_immap.h>
  12. #include "mpc8xx_pic.h"
  13. #define PIC_VEC_SPURRIOUS 15
  14. extern int cpm_get_irq(struct pt_regs *regs);
  15. static struct irq_domain *mpc8xx_pic_host;
  16. #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
  17. static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  18. static sysconf8xx_t __iomem *siu_reg;
  19. int cpm_get_irq(struct pt_regs *regs);
  20. static void mpc8xx_unmask_irq(struct irq_data *d)
  21. {
  22. int bit, word;
  23. unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  24. bit = irq_nr & 0x1f;
  25. word = irq_nr >> 5;
  26. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  27. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  28. }
  29. static void mpc8xx_mask_irq(struct irq_data *d)
  30. {
  31. int bit, word;
  32. unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  33. bit = irq_nr & 0x1f;
  34. word = irq_nr >> 5;
  35. ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
  36. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  37. }
  38. static void mpc8xx_ack(struct irq_data *d)
  39. {
  40. int bit;
  41. unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  42. bit = irq_nr & 0x1f;
  43. out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
  44. }
  45. static void mpc8xx_end_irq(struct irq_data *d)
  46. {
  47. int bit, word;
  48. unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  49. bit = irq_nr & 0x1f;
  50. word = irq_nr >> 5;
  51. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  52. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  53. }
  54. static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
  55. {
  56. if (flow_type & IRQ_TYPE_EDGE_FALLING) {
  57. irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
  58. unsigned int siel = in_be32(&siu_reg->sc_siel);
  59. /* only external IRQ senses are programmable */
  60. if ((hw & 1) == 0) {
  61. siel |= (0x80000000 >> hw);
  62. out_be32(&siu_reg->sc_siel, siel);
  63. __irq_set_handler_locked(d->irq, handle_edge_irq);
  64. }
  65. }
  66. return 0;
  67. }
  68. static struct irq_chip mpc8xx_pic = {
  69. .name = "MPC8XX SIU",
  70. .irq_unmask = mpc8xx_unmask_irq,
  71. .irq_mask = mpc8xx_mask_irq,
  72. .irq_ack = mpc8xx_ack,
  73. .irq_eoi = mpc8xx_end_irq,
  74. .irq_set_type = mpc8xx_set_irq_type,
  75. };
  76. unsigned int mpc8xx_get_irq(void)
  77. {
  78. int irq;
  79. /* For MPC8xx, read the SIVEC register and shift the bits down
  80. * to get the irq number.
  81. */
  82. irq = in_be32(&siu_reg->sc_sivec) >> 26;
  83. if (irq == PIC_VEC_SPURRIOUS)
  84. irq = NO_IRQ;
  85. return irq_linear_revmap(mpc8xx_pic_host, irq);
  86. }
  87. static int mpc8xx_pic_host_map(struct irq_domain *h, unsigned int virq,
  88. irq_hw_number_t hw)
  89. {
  90. pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
  91. /* Set default irq handle */
  92. irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
  93. return 0;
  94. }
  95. static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
  96. const u32 *intspec, unsigned int intsize,
  97. irq_hw_number_t *out_hwirq, unsigned int *out_flags)
  98. {
  99. static unsigned char map_pic_senses[4] = {
  100. IRQ_TYPE_EDGE_RISING,
  101. IRQ_TYPE_LEVEL_LOW,
  102. IRQ_TYPE_LEVEL_HIGH,
  103. IRQ_TYPE_EDGE_FALLING,
  104. };
  105. *out_hwirq = intspec[0];
  106. if (intsize > 1 && intspec[1] < 4)
  107. *out_flags = map_pic_senses[intspec[1]];
  108. else
  109. *out_flags = IRQ_TYPE_NONE;
  110. return 0;
  111. }
  112. static struct irq_domain_ops mpc8xx_pic_host_ops = {
  113. .map = mpc8xx_pic_host_map,
  114. .xlate = mpc8xx_pic_host_xlate,
  115. };
  116. int mpc8xx_pic_init(void)
  117. {
  118. struct resource res;
  119. struct device_node *np;
  120. int ret;
  121. np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
  122. if (np == NULL)
  123. np = of_find_node_by_type(NULL, "mpc8xx-pic");
  124. if (np == NULL) {
  125. printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
  126. return -ENOMEM;
  127. }
  128. ret = of_address_to_resource(np, 0, &res);
  129. if (ret)
  130. goto out;
  131. siu_reg = ioremap(res.start, resource_size(&res));
  132. if (siu_reg == NULL) {
  133. ret = -EINVAL;
  134. goto out;
  135. }
  136. mpc8xx_pic_host = irq_domain_add_linear(np, 64, &mpc8xx_pic_host_ops, NULL);
  137. if (mpc8xx_pic_host == NULL) {
  138. printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
  139. ret = -ENOMEM;
  140. goto out;
  141. }
  142. return 0;
  143. out:
  144. of_node_put(np);
  145. return ret;
  146. }