suspend.c 9.0 KB

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  1. /*
  2. * MPC83xx suspend support
  3. *
  4. * Author: Scott Wood <scottwood@freescale.com>
  5. *
  6. * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License version 2 as published
  10. * by the Free Software Foundation.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/pm.h>
  14. #include <linux/types.h>
  15. #include <linux/ioport.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/wait.h>
  18. #include <linux/kthread.h>
  19. #include <linux/freezer.h>
  20. #include <linux/suspend.h>
  21. #include <linux/fsl_devices.h>
  22. #include <linux/of_platform.h>
  23. #include <linux/export.h>
  24. #include <asm/reg.h>
  25. #include <asm/io.h>
  26. #include <asm/time.h>
  27. #include <asm/mpc6xx.h>
  28. #include <asm/switch_to.h>
  29. #include <sysdev/fsl_soc.h>
  30. #define PMCCR1_NEXT_STATE 0x0C /* Next state for power management */
  31. #define PMCCR1_NEXT_STATE_SHIFT 2
  32. #define PMCCR1_CURR_STATE 0x03 /* Current state for power management*/
  33. #define IMMR_SYSCR_OFFSET 0x100
  34. #define IMMR_RCW_OFFSET 0x900
  35. #define RCW_PCI_HOST 0x80000000
  36. void mpc83xx_enter_deep_sleep(phys_addr_t immrbase);
  37. struct mpc83xx_pmc {
  38. u32 config;
  39. #define PMCCR_DLPEN 2 /* DDR SDRAM low power enable */
  40. #define PMCCR_SLPEN 1 /* System low power enable */
  41. u32 event;
  42. u32 mask;
  43. /* All but PMCI are deep-sleep only */
  44. #define PMCER_GPIO 0x100
  45. #define PMCER_PCI 0x080
  46. #define PMCER_USB 0x040
  47. #define PMCER_ETSEC1 0x020
  48. #define PMCER_ETSEC2 0x010
  49. #define PMCER_TIMER 0x008
  50. #define PMCER_INT1 0x004
  51. #define PMCER_INT2 0x002
  52. #define PMCER_PMCI 0x001
  53. #define PMCER_ALL 0x1FF
  54. /* deep-sleep only */
  55. u32 config1;
  56. #define PMCCR1_USE_STATE 0x80000000
  57. #define PMCCR1_PME_EN 0x00000080
  58. #define PMCCR1_ASSERT_PME 0x00000040
  59. #define PMCCR1_POWER_OFF 0x00000020
  60. /* deep-sleep only */
  61. u32 config2;
  62. };
  63. struct mpc83xx_rcw {
  64. u32 rcwlr;
  65. u32 rcwhr;
  66. };
  67. struct mpc83xx_clock {
  68. u32 spmr;
  69. u32 occr;
  70. u32 sccr;
  71. };
  72. struct mpc83xx_syscr {
  73. __be32 sgprl;
  74. __be32 sgprh;
  75. __be32 spridr;
  76. __be32 :32;
  77. __be32 spcr;
  78. __be32 sicrl;
  79. __be32 sicrh;
  80. };
  81. struct mpc83xx_saved {
  82. u32 sicrl;
  83. u32 sicrh;
  84. u32 sccr;
  85. };
  86. struct pmc_type {
  87. int has_deep_sleep;
  88. };
  89. static struct platform_device *pmc_dev;
  90. static int has_deep_sleep, deep_sleeping;
  91. static int pmc_irq;
  92. static struct mpc83xx_pmc __iomem *pmc_regs;
  93. static struct mpc83xx_clock __iomem *clock_regs;
  94. static struct mpc83xx_syscr __iomem *syscr_regs;
  95. static struct mpc83xx_saved saved_regs;
  96. static int is_pci_agent, wake_from_pci;
  97. static phys_addr_t immrbase;
  98. static int pci_pm_state;
  99. static DECLARE_WAIT_QUEUE_HEAD(agent_wq);
  100. int fsl_deep_sleep(void)
  101. {
  102. return deep_sleeping;
  103. }
  104. EXPORT_SYMBOL(fsl_deep_sleep);
  105. static int mpc83xx_change_state(void)
  106. {
  107. u32 curr_state;
  108. u32 reg_cfg1 = in_be32(&pmc_regs->config1);
  109. if (is_pci_agent) {
  110. pci_pm_state = (reg_cfg1 & PMCCR1_NEXT_STATE) >>
  111. PMCCR1_NEXT_STATE_SHIFT;
  112. curr_state = reg_cfg1 & PMCCR1_CURR_STATE;
  113. if (curr_state != pci_pm_state) {
  114. reg_cfg1 &= ~PMCCR1_CURR_STATE;
  115. reg_cfg1 |= pci_pm_state;
  116. out_be32(&pmc_regs->config1, reg_cfg1);
  117. wake_up(&agent_wq);
  118. return 1;
  119. }
  120. }
  121. return 0;
  122. }
  123. static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
  124. {
  125. u32 event = in_be32(&pmc_regs->event);
  126. int ret = IRQ_NONE;
  127. if (mpc83xx_change_state())
  128. ret = IRQ_HANDLED;
  129. if (event) {
  130. out_be32(&pmc_regs->event, event);
  131. ret = IRQ_HANDLED;
  132. }
  133. return ret;
  134. }
  135. static void mpc83xx_suspend_restore_regs(void)
  136. {
  137. out_be32(&syscr_regs->sicrl, saved_regs.sicrl);
  138. out_be32(&syscr_regs->sicrh, saved_regs.sicrh);
  139. out_be32(&clock_regs->sccr, saved_regs.sccr);
  140. }
  141. static void mpc83xx_suspend_save_regs(void)
  142. {
  143. saved_regs.sicrl = in_be32(&syscr_regs->sicrl);
  144. saved_regs.sicrh = in_be32(&syscr_regs->sicrh);
  145. saved_regs.sccr = in_be32(&clock_regs->sccr);
  146. }
  147. static int mpc83xx_suspend_enter(suspend_state_t state)
  148. {
  149. int ret = -EAGAIN;
  150. /* Don't go to sleep if there's a race where pci_pm_state changes
  151. * between the agent thread checking it and the PM code disabling
  152. * interrupts.
  153. */
  154. if (wake_from_pci) {
  155. if (pci_pm_state != (deep_sleeping ? 3 : 2))
  156. goto out;
  157. out_be32(&pmc_regs->config1,
  158. in_be32(&pmc_regs->config1) | PMCCR1_PME_EN);
  159. }
  160. /* Put the system into low-power mode and the RAM
  161. * into self-refresh mode once the core goes to
  162. * sleep.
  163. */
  164. out_be32(&pmc_regs->config, PMCCR_SLPEN | PMCCR_DLPEN);
  165. /* If it has deep sleep (i.e. it's an 831x or compatible),
  166. * disable power to the core upon entering sleep mode. This will
  167. * require going through the boot firmware upon a wakeup event.
  168. */
  169. if (deep_sleeping) {
  170. mpc83xx_suspend_save_regs();
  171. out_be32(&pmc_regs->mask, PMCER_ALL);
  172. out_be32(&pmc_regs->config1,
  173. in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF);
  174. enable_kernel_fp();
  175. mpc83xx_enter_deep_sleep(immrbase);
  176. out_be32(&pmc_regs->config1,
  177. in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
  178. out_be32(&pmc_regs->mask, PMCER_PMCI);
  179. mpc83xx_suspend_restore_regs();
  180. } else {
  181. out_be32(&pmc_regs->mask, PMCER_PMCI);
  182. mpc6xx_enter_standby();
  183. }
  184. ret = 0;
  185. out:
  186. out_be32(&pmc_regs->config1,
  187. in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN);
  188. return ret;
  189. }
  190. static void mpc83xx_suspend_end(void)
  191. {
  192. deep_sleeping = 0;
  193. }
  194. static int mpc83xx_suspend_valid(suspend_state_t state)
  195. {
  196. return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM;
  197. }
  198. static int mpc83xx_suspend_begin(suspend_state_t state)
  199. {
  200. switch (state) {
  201. case PM_SUSPEND_STANDBY:
  202. deep_sleeping = 0;
  203. return 0;
  204. case PM_SUSPEND_MEM:
  205. if (has_deep_sleep)
  206. deep_sleeping = 1;
  207. return 0;
  208. default:
  209. return -EINVAL;
  210. }
  211. }
  212. static int agent_thread_fn(void *data)
  213. {
  214. while (1) {
  215. wait_event_interruptible(agent_wq, pci_pm_state >= 2);
  216. try_to_freeze();
  217. if (signal_pending(current) || pci_pm_state < 2)
  218. continue;
  219. /* With a preemptible kernel (or SMP), this could race with
  220. * a userspace-driven suspend request. It's probably best
  221. * to avoid mixing the two with such a configuration (or
  222. * else fix it by adding a mutex to state_store that we can
  223. * synchronize with).
  224. */
  225. wake_from_pci = 1;
  226. pm_suspend(pci_pm_state == 3 ? PM_SUSPEND_MEM :
  227. PM_SUSPEND_STANDBY);
  228. wake_from_pci = 0;
  229. }
  230. return 0;
  231. }
  232. static void mpc83xx_set_agent(void)
  233. {
  234. out_be32(&pmc_regs->config1, PMCCR1_USE_STATE);
  235. out_be32(&pmc_regs->mask, PMCER_PMCI);
  236. kthread_run(agent_thread_fn, NULL, "PCI power mgt");
  237. }
  238. static int mpc83xx_is_pci_agent(void)
  239. {
  240. struct mpc83xx_rcw __iomem *rcw_regs;
  241. int ret;
  242. rcw_regs = ioremap(get_immrbase() + IMMR_RCW_OFFSET,
  243. sizeof(struct mpc83xx_rcw));
  244. if (!rcw_regs)
  245. return -ENOMEM;
  246. ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST);
  247. iounmap(rcw_regs);
  248. return ret;
  249. }
  250. static const struct platform_suspend_ops mpc83xx_suspend_ops = {
  251. .valid = mpc83xx_suspend_valid,
  252. .begin = mpc83xx_suspend_begin,
  253. .enter = mpc83xx_suspend_enter,
  254. .end = mpc83xx_suspend_end,
  255. };
  256. static struct of_device_id pmc_match[];
  257. static int pmc_probe(struct platform_device *ofdev)
  258. {
  259. const struct of_device_id *match;
  260. struct device_node *np = ofdev->dev.of_node;
  261. struct resource res;
  262. struct pmc_type *type;
  263. int ret = 0;
  264. match = of_match_device(pmc_match, &ofdev->dev);
  265. if (!match)
  266. return -EINVAL;
  267. type = match->data;
  268. if (!of_device_is_available(np))
  269. return -ENODEV;
  270. has_deep_sleep = type->has_deep_sleep;
  271. immrbase = get_immrbase();
  272. pmc_dev = ofdev;
  273. is_pci_agent = mpc83xx_is_pci_agent();
  274. if (is_pci_agent < 0)
  275. return is_pci_agent;
  276. ret = of_address_to_resource(np, 0, &res);
  277. if (ret)
  278. return -ENODEV;
  279. pmc_irq = irq_of_parse_and_map(np, 0);
  280. if (pmc_irq != NO_IRQ) {
  281. ret = request_irq(pmc_irq, pmc_irq_handler, IRQF_SHARED,
  282. "pmc", ofdev);
  283. if (ret)
  284. return -EBUSY;
  285. }
  286. pmc_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
  287. if (!pmc_regs) {
  288. ret = -ENOMEM;
  289. goto out;
  290. }
  291. ret = of_address_to_resource(np, 1, &res);
  292. if (ret) {
  293. ret = -ENODEV;
  294. goto out_pmc;
  295. }
  296. clock_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
  297. if (!clock_regs) {
  298. ret = -ENOMEM;
  299. goto out_pmc;
  300. }
  301. if (has_deep_sleep) {
  302. syscr_regs = ioremap(immrbase + IMMR_SYSCR_OFFSET,
  303. sizeof(*syscr_regs));
  304. if (!syscr_regs) {
  305. ret = -ENOMEM;
  306. goto out_syscr;
  307. }
  308. }
  309. if (is_pci_agent)
  310. mpc83xx_set_agent();
  311. suspend_set_ops(&mpc83xx_suspend_ops);
  312. return 0;
  313. out_syscr:
  314. iounmap(clock_regs);
  315. out_pmc:
  316. iounmap(pmc_regs);
  317. out:
  318. if (pmc_irq != NO_IRQ)
  319. free_irq(pmc_irq, ofdev);
  320. return ret;
  321. }
  322. static int pmc_remove(struct platform_device *ofdev)
  323. {
  324. return -EPERM;
  325. };
  326. static struct pmc_type pmc_types[] = {
  327. {
  328. .has_deep_sleep = 1,
  329. },
  330. {
  331. .has_deep_sleep = 0,
  332. }
  333. };
  334. static struct of_device_id pmc_match[] = {
  335. {
  336. .compatible = "fsl,mpc8313-pmc",
  337. .data = &pmc_types[0],
  338. },
  339. {
  340. .compatible = "fsl,mpc8349-pmc",
  341. .data = &pmc_types[1],
  342. },
  343. {}
  344. };
  345. static struct platform_driver pmc_driver = {
  346. .driver = {
  347. .name = "mpc83xx-pmc",
  348. .owner = THIS_MODULE,
  349. .of_match_table = pmc_match,
  350. },
  351. .probe = pmc_probe,
  352. .remove = pmc_remove
  353. };
  354. static int pmc_init(void)
  355. {
  356. return platform_driver_register(&pmc_driver);
  357. }
  358. module_init(pmc_init);