book3s_paired_singles.c 31 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License, version 2, as
  4. * published by the Free Software Foundation.
  5. *
  6. * This program is distributed in the hope that it will be useful,
  7. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. *
  11. * You should have received a copy of the GNU General Public License
  12. * along with this program; if not, write to the Free Software
  13. * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  14. *
  15. * Copyright Novell Inc 2010
  16. *
  17. * Authors: Alexander Graf <agraf@suse.de>
  18. */
  19. #include <asm/kvm.h>
  20. #include <asm/kvm_ppc.h>
  21. #include <asm/disassemble.h>
  22. #include <asm/kvm_book3s.h>
  23. #include <asm/kvm_fpu.h>
  24. #include <asm/reg.h>
  25. #include <asm/cacheflush.h>
  26. #include <linux/vmalloc.h>
  27. /* #define DEBUG */
  28. #ifdef DEBUG
  29. #define dprintk printk
  30. #else
  31. #define dprintk(...) do { } while(0);
  32. #endif
  33. #define OP_LFS 48
  34. #define OP_LFSU 49
  35. #define OP_LFD 50
  36. #define OP_LFDU 51
  37. #define OP_STFS 52
  38. #define OP_STFSU 53
  39. #define OP_STFD 54
  40. #define OP_STFDU 55
  41. #define OP_PSQ_L 56
  42. #define OP_PSQ_LU 57
  43. #define OP_PSQ_ST 60
  44. #define OP_PSQ_STU 61
  45. #define OP_31_LFSX 535
  46. #define OP_31_LFSUX 567
  47. #define OP_31_LFDX 599
  48. #define OP_31_LFDUX 631
  49. #define OP_31_STFSX 663
  50. #define OP_31_STFSUX 695
  51. #define OP_31_STFX 727
  52. #define OP_31_STFUX 759
  53. #define OP_31_LWIZX 887
  54. #define OP_31_STFIWX 983
  55. #define OP_59_FADDS 21
  56. #define OP_59_FSUBS 20
  57. #define OP_59_FSQRTS 22
  58. #define OP_59_FDIVS 18
  59. #define OP_59_FRES 24
  60. #define OP_59_FMULS 25
  61. #define OP_59_FRSQRTES 26
  62. #define OP_59_FMSUBS 28
  63. #define OP_59_FMADDS 29
  64. #define OP_59_FNMSUBS 30
  65. #define OP_59_FNMADDS 31
  66. #define OP_63_FCMPU 0
  67. #define OP_63_FCPSGN 8
  68. #define OP_63_FRSP 12
  69. #define OP_63_FCTIW 14
  70. #define OP_63_FCTIWZ 15
  71. #define OP_63_FDIV 18
  72. #define OP_63_FADD 21
  73. #define OP_63_FSQRT 22
  74. #define OP_63_FSEL 23
  75. #define OP_63_FRE 24
  76. #define OP_63_FMUL 25
  77. #define OP_63_FRSQRTE 26
  78. #define OP_63_FMSUB 28
  79. #define OP_63_FMADD 29
  80. #define OP_63_FNMSUB 30
  81. #define OP_63_FNMADD 31
  82. #define OP_63_FCMPO 32
  83. #define OP_63_MTFSB1 38 // XXX
  84. #define OP_63_FSUB 20
  85. #define OP_63_FNEG 40
  86. #define OP_63_MCRFS 64
  87. #define OP_63_MTFSB0 70
  88. #define OP_63_FMR 72
  89. #define OP_63_MTFSFI 134
  90. #define OP_63_FABS 264
  91. #define OP_63_MFFS 583
  92. #define OP_63_MTFSF 711
  93. #define OP_4X_PS_CMPU0 0
  94. #define OP_4X_PSQ_LX 6
  95. #define OP_4XW_PSQ_STX 7
  96. #define OP_4A_PS_SUM0 10
  97. #define OP_4A_PS_SUM1 11
  98. #define OP_4A_PS_MULS0 12
  99. #define OP_4A_PS_MULS1 13
  100. #define OP_4A_PS_MADDS0 14
  101. #define OP_4A_PS_MADDS1 15
  102. #define OP_4A_PS_DIV 18
  103. #define OP_4A_PS_SUB 20
  104. #define OP_4A_PS_ADD 21
  105. #define OP_4A_PS_SEL 23
  106. #define OP_4A_PS_RES 24
  107. #define OP_4A_PS_MUL 25
  108. #define OP_4A_PS_RSQRTE 26
  109. #define OP_4A_PS_MSUB 28
  110. #define OP_4A_PS_MADD 29
  111. #define OP_4A_PS_NMSUB 30
  112. #define OP_4A_PS_NMADD 31
  113. #define OP_4X_PS_CMPO0 32
  114. #define OP_4X_PSQ_LUX 38
  115. #define OP_4XW_PSQ_STUX 39
  116. #define OP_4X_PS_NEG 40
  117. #define OP_4X_PS_CMPU1 64
  118. #define OP_4X_PS_MR 72
  119. #define OP_4X_PS_CMPO1 96
  120. #define OP_4X_PS_NABS 136
  121. #define OP_4X_PS_ABS 264
  122. #define OP_4X_PS_MERGE00 528
  123. #define OP_4X_PS_MERGE01 560
  124. #define OP_4X_PS_MERGE10 592
  125. #define OP_4X_PS_MERGE11 624
  126. #define SCALAR_NONE 0
  127. #define SCALAR_HIGH (1 << 0)
  128. #define SCALAR_LOW (1 << 1)
  129. #define SCALAR_NO_PS0 (1 << 2)
  130. #define SCALAR_NO_PS1 (1 << 3)
  131. #define GQR_ST_TYPE_MASK 0x00000007
  132. #define GQR_ST_TYPE_SHIFT 0
  133. #define GQR_ST_SCALE_MASK 0x00003f00
  134. #define GQR_ST_SCALE_SHIFT 8
  135. #define GQR_LD_TYPE_MASK 0x00070000
  136. #define GQR_LD_TYPE_SHIFT 16
  137. #define GQR_LD_SCALE_MASK 0x3f000000
  138. #define GQR_LD_SCALE_SHIFT 24
  139. #define GQR_QUANTIZE_FLOAT 0
  140. #define GQR_QUANTIZE_U8 4
  141. #define GQR_QUANTIZE_U16 5
  142. #define GQR_QUANTIZE_S8 6
  143. #define GQR_QUANTIZE_S16 7
  144. #define FPU_LS_SINGLE 0
  145. #define FPU_LS_DOUBLE 1
  146. #define FPU_LS_SINGLE_LOW 2
  147. static inline void kvmppc_sync_qpr(struct kvm_vcpu *vcpu, int rt)
  148. {
  149. kvm_cvt_df(&vcpu->arch.fpr[rt], &vcpu->arch.qpr[rt]);
  150. }
  151. static void kvmppc_inject_pf(struct kvm_vcpu *vcpu, ulong eaddr, bool is_store)
  152. {
  153. u64 dsisr;
  154. struct kvm_vcpu_arch_shared *shared = vcpu->arch.shared;
  155. shared->msr = kvmppc_set_field(shared->msr, 33, 36, 0);
  156. shared->msr = kvmppc_set_field(shared->msr, 42, 47, 0);
  157. shared->dar = eaddr;
  158. /* Page Fault */
  159. dsisr = kvmppc_set_field(0, 33, 33, 1);
  160. if (is_store)
  161. shared->dsisr = kvmppc_set_field(dsisr, 38, 38, 1);
  162. kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE);
  163. }
  164. static int kvmppc_emulate_fpr_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
  165. int rs, ulong addr, int ls_type)
  166. {
  167. int emulated = EMULATE_FAIL;
  168. int r;
  169. char tmp[8];
  170. int len = sizeof(u32);
  171. if (ls_type == FPU_LS_DOUBLE)
  172. len = sizeof(u64);
  173. /* read from memory */
  174. r = kvmppc_ld(vcpu, &addr, len, tmp, true);
  175. vcpu->arch.paddr_accessed = addr;
  176. if (r < 0) {
  177. kvmppc_inject_pf(vcpu, addr, false);
  178. goto done_load;
  179. } else if (r == EMULATE_DO_MMIO) {
  180. emulated = kvmppc_handle_load(run, vcpu, KVM_MMIO_REG_FPR | rs,
  181. len, 1);
  182. goto done_load;
  183. }
  184. emulated = EMULATE_DONE;
  185. /* put in registers */
  186. switch (ls_type) {
  187. case FPU_LS_SINGLE:
  188. kvm_cvt_fd((u32*)tmp, &vcpu->arch.fpr[rs]);
  189. vcpu->arch.qpr[rs] = *((u32*)tmp);
  190. break;
  191. case FPU_LS_DOUBLE:
  192. vcpu->arch.fpr[rs] = *((u64*)tmp);
  193. break;
  194. }
  195. dprintk(KERN_INFO "KVM: FPR_LD [0x%llx] at 0x%lx (%d)\n", *(u64*)tmp,
  196. addr, len);
  197. done_load:
  198. return emulated;
  199. }
  200. static int kvmppc_emulate_fpr_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
  201. int rs, ulong addr, int ls_type)
  202. {
  203. int emulated = EMULATE_FAIL;
  204. int r;
  205. char tmp[8];
  206. u64 val;
  207. int len;
  208. switch (ls_type) {
  209. case FPU_LS_SINGLE:
  210. kvm_cvt_df(&vcpu->arch.fpr[rs], (u32*)tmp);
  211. val = *((u32*)tmp);
  212. len = sizeof(u32);
  213. break;
  214. case FPU_LS_SINGLE_LOW:
  215. *((u32*)tmp) = vcpu->arch.fpr[rs];
  216. val = vcpu->arch.fpr[rs] & 0xffffffff;
  217. len = sizeof(u32);
  218. break;
  219. case FPU_LS_DOUBLE:
  220. *((u64*)tmp) = vcpu->arch.fpr[rs];
  221. val = vcpu->arch.fpr[rs];
  222. len = sizeof(u64);
  223. break;
  224. default:
  225. val = 0;
  226. len = 0;
  227. }
  228. r = kvmppc_st(vcpu, &addr, len, tmp, true);
  229. vcpu->arch.paddr_accessed = addr;
  230. if (r < 0) {
  231. kvmppc_inject_pf(vcpu, addr, true);
  232. } else if (r == EMULATE_DO_MMIO) {
  233. emulated = kvmppc_handle_store(run, vcpu, val, len, 1);
  234. } else {
  235. emulated = EMULATE_DONE;
  236. }
  237. dprintk(KERN_INFO "KVM: FPR_ST [0x%llx] at 0x%lx (%d)\n",
  238. val, addr, len);
  239. return emulated;
  240. }
  241. static int kvmppc_emulate_psq_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
  242. int rs, ulong addr, bool w, int i)
  243. {
  244. int emulated = EMULATE_FAIL;
  245. int r;
  246. float one = 1.0;
  247. u32 tmp[2];
  248. /* read from memory */
  249. if (w) {
  250. r = kvmppc_ld(vcpu, &addr, sizeof(u32), tmp, true);
  251. memcpy(&tmp[1], &one, sizeof(u32));
  252. } else {
  253. r = kvmppc_ld(vcpu, &addr, sizeof(u32) * 2, tmp, true);
  254. }
  255. vcpu->arch.paddr_accessed = addr;
  256. if (r < 0) {
  257. kvmppc_inject_pf(vcpu, addr, false);
  258. goto done_load;
  259. } else if ((r == EMULATE_DO_MMIO) && w) {
  260. emulated = kvmppc_handle_load(run, vcpu, KVM_MMIO_REG_FPR | rs,
  261. 4, 1);
  262. vcpu->arch.qpr[rs] = tmp[1];
  263. goto done_load;
  264. } else if (r == EMULATE_DO_MMIO) {
  265. emulated = kvmppc_handle_load(run, vcpu, KVM_MMIO_REG_FQPR | rs,
  266. 8, 1);
  267. goto done_load;
  268. }
  269. emulated = EMULATE_DONE;
  270. /* put in registers */
  271. kvm_cvt_fd(&tmp[0], &vcpu->arch.fpr[rs]);
  272. vcpu->arch.qpr[rs] = tmp[1];
  273. dprintk(KERN_INFO "KVM: PSQ_LD [0x%x, 0x%x] at 0x%lx (%d)\n", tmp[0],
  274. tmp[1], addr, w ? 4 : 8);
  275. done_load:
  276. return emulated;
  277. }
  278. static int kvmppc_emulate_psq_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
  279. int rs, ulong addr, bool w, int i)
  280. {
  281. int emulated = EMULATE_FAIL;
  282. int r;
  283. u32 tmp[2];
  284. int len = w ? sizeof(u32) : sizeof(u64);
  285. kvm_cvt_df(&vcpu->arch.fpr[rs], &tmp[0]);
  286. tmp[1] = vcpu->arch.qpr[rs];
  287. r = kvmppc_st(vcpu, &addr, len, tmp, true);
  288. vcpu->arch.paddr_accessed = addr;
  289. if (r < 0) {
  290. kvmppc_inject_pf(vcpu, addr, true);
  291. } else if ((r == EMULATE_DO_MMIO) && w) {
  292. emulated = kvmppc_handle_store(run, vcpu, tmp[0], 4, 1);
  293. } else if (r == EMULATE_DO_MMIO) {
  294. u64 val = ((u64)tmp[0] << 32) | tmp[1];
  295. emulated = kvmppc_handle_store(run, vcpu, val, 8, 1);
  296. } else {
  297. emulated = EMULATE_DONE;
  298. }
  299. dprintk(KERN_INFO "KVM: PSQ_ST [0x%x, 0x%x] at 0x%lx (%d)\n",
  300. tmp[0], tmp[1], addr, len);
  301. return emulated;
  302. }
  303. /*
  304. * Cuts out inst bits with ordering according to spec.
  305. * That means the leftmost bit is zero. All given bits are included.
  306. */
  307. static inline u32 inst_get_field(u32 inst, int msb, int lsb)
  308. {
  309. return kvmppc_get_field(inst, msb + 32, lsb + 32);
  310. }
  311. /*
  312. * Replaces inst bits with ordering according to spec.
  313. */
  314. static inline u32 inst_set_field(u32 inst, int msb, int lsb, int value)
  315. {
  316. return kvmppc_set_field(inst, msb + 32, lsb + 32, value);
  317. }
  318. bool kvmppc_inst_is_paired_single(struct kvm_vcpu *vcpu, u32 inst)
  319. {
  320. if (!(vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE))
  321. return false;
  322. switch (get_op(inst)) {
  323. case OP_PSQ_L:
  324. case OP_PSQ_LU:
  325. case OP_PSQ_ST:
  326. case OP_PSQ_STU:
  327. case OP_LFS:
  328. case OP_LFSU:
  329. case OP_LFD:
  330. case OP_LFDU:
  331. case OP_STFS:
  332. case OP_STFSU:
  333. case OP_STFD:
  334. case OP_STFDU:
  335. return true;
  336. case 4:
  337. /* X form */
  338. switch (inst_get_field(inst, 21, 30)) {
  339. case OP_4X_PS_CMPU0:
  340. case OP_4X_PSQ_LX:
  341. case OP_4X_PS_CMPO0:
  342. case OP_4X_PSQ_LUX:
  343. case OP_4X_PS_NEG:
  344. case OP_4X_PS_CMPU1:
  345. case OP_4X_PS_MR:
  346. case OP_4X_PS_CMPO1:
  347. case OP_4X_PS_NABS:
  348. case OP_4X_PS_ABS:
  349. case OP_4X_PS_MERGE00:
  350. case OP_4X_PS_MERGE01:
  351. case OP_4X_PS_MERGE10:
  352. case OP_4X_PS_MERGE11:
  353. return true;
  354. }
  355. /* XW form */
  356. switch (inst_get_field(inst, 25, 30)) {
  357. case OP_4XW_PSQ_STX:
  358. case OP_4XW_PSQ_STUX:
  359. return true;
  360. }
  361. /* A form */
  362. switch (inst_get_field(inst, 26, 30)) {
  363. case OP_4A_PS_SUM1:
  364. case OP_4A_PS_SUM0:
  365. case OP_4A_PS_MULS0:
  366. case OP_4A_PS_MULS1:
  367. case OP_4A_PS_MADDS0:
  368. case OP_4A_PS_MADDS1:
  369. case OP_4A_PS_DIV:
  370. case OP_4A_PS_SUB:
  371. case OP_4A_PS_ADD:
  372. case OP_4A_PS_SEL:
  373. case OP_4A_PS_RES:
  374. case OP_4A_PS_MUL:
  375. case OP_4A_PS_RSQRTE:
  376. case OP_4A_PS_MSUB:
  377. case OP_4A_PS_MADD:
  378. case OP_4A_PS_NMSUB:
  379. case OP_4A_PS_NMADD:
  380. return true;
  381. }
  382. break;
  383. case 59:
  384. switch (inst_get_field(inst, 21, 30)) {
  385. case OP_59_FADDS:
  386. case OP_59_FSUBS:
  387. case OP_59_FDIVS:
  388. case OP_59_FRES:
  389. case OP_59_FRSQRTES:
  390. return true;
  391. }
  392. switch (inst_get_field(inst, 26, 30)) {
  393. case OP_59_FMULS:
  394. case OP_59_FMSUBS:
  395. case OP_59_FMADDS:
  396. case OP_59_FNMSUBS:
  397. case OP_59_FNMADDS:
  398. return true;
  399. }
  400. break;
  401. case 63:
  402. switch (inst_get_field(inst, 21, 30)) {
  403. case OP_63_MTFSB0:
  404. case OP_63_MTFSB1:
  405. case OP_63_MTFSF:
  406. case OP_63_MTFSFI:
  407. case OP_63_MCRFS:
  408. case OP_63_MFFS:
  409. case OP_63_FCMPU:
  410. case OP_63_FCMPO:
  411. case OP_63_FNEG:
  412. case OP_63_FMR:
  413. case OP_63_FABS:
  414. case OP_63_FRSP:
  415. case OP_63_FDIV:
  416. case OP_63_FADD:
  417. case OP_63_FSUB:
  418. case OP_63_FCTIW:
  419. case OP_63_FCTIWZ:
  420. case OP_63_FRSQRTE:
  421. case OP_63_FCPSGN:
  422. return true;
  423. }
  424. switch (inst_get_field(inst, 26, 30)) {
  425. case OP_63_FMUL:
  426. case OP_63_FSEL:
  427. case OP_63_FMSUB:
  428. case OP_63_FMADD:
  429. case OP_63_FNMSUB:
  430. case OP_63_FNMADD:
  431. return true;
  432. }
  433. break;
  434. case 31:
  435. switch (inst_get_field(inst, 21, 30)) {
  436. case OP_31_LFSX:
  437. case OP_31_LFSUX:
  438. case OP_31_LFDX:
  439. case OP_31_LFDUX:
  440. case OP_31_STFSX:
  441. case OP_31_STFSUX:
  442. case OP_31_STFX:
  443. case OP_31_STFUX:
  444. case OP_31_STFIWX:
  445. return true;
  446. }
  447. break;
  448. }
  449. return false;
  450. }
  451. static int get_d_signext(u32 inst)
  452. {
  453. int d = inst & 0x8ff;
  454. if (d & 0x800)
  455. return -(d & 0x7ff);
  456. return (d & 0x7ff);
  457. }
  458. static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
  459. int reg_out, int reg_in1, int reg_in2,
  460. int reg_in3, int scalar,
  461. void (*func)(u64 *fpscr,
  462. u32 *dst, u32 *src1,
  463. u32 *src2, u32 *src3))
  464. {
  465. u32 *qpr = vcpu->arch.qpr;
  466. u64 *fpr = vcpu->arch.fpr;
  467. u32 ps0_out;
  468. u32 ps0_in1, ps0_in2, ps0_in3;
  469. u32 ps1_in1, ps1_in2, ps1_in3;
  470. /* RC */
  471. WARN_ON(rc);
  472. /* PS0 */
  473. kvm_cvt_df(&fpr[reg_in1], &ps0_in1);
  474. kvm_cvt_df(&fpr[reg_in2], &ps0_in2);
  475. kvm_cvt_df(&fpr[reg_in3], &ps0_in3);
  476. if (scalar & SCALAR_LOW)
  477. ps0_in2 = qpr[reg_in2];
  478. func(&vcpu->arch.fpscr, &ps0_out, &ps0_in1, &ps0_in2, &ps0_in3);
  479. dprintk(KERN_INFO "PS3 ps0 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
  480. ps0_in1, ps0_in2, ps0_in3, ps0_out);
  481. if (!(scalar & SCALAR_NO_PS0))
  482. kvm_cvt_fd(&ps0_out, &fpr[reg_out]);
  483. /* PS1 */
  484. ps1_in1 = qpr[reg_in1];
  485. ps1_in2 = qpr[reg_in2];
  486. ps1_in3 = qpr[reg_in3];
  487. if (scalar & SCALAR_HIGH)
  488. ps1_in2 = ps0_in2;
  489. if (!(scalar & SCALAR_NO_PS1))
  490. func(&vcpu->arch.fpscr, &qpr[reg_out], &ps1_in1, &ps1_in2, &ps1_in3);
  491. dprintk(KERN_INFO "PS3 ps1 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
  492. ps1_in1, ps1_in2, ps1_in3, qpr[reg_out]);
  493. return EMULATE_DONE;
  494. }
  495. static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
  496. int reg_out, int reg_in1, int reg_in2,
  497. int scalar,
  498. void (*func)(u64 *fpscr,
  499. u32 *dst, u32 *src1,
  500. u32 *src2))
  501. {
  502. u32 *qpr = vcpu->arch.qpr;
  503. u64 *fpr = vcpu->arch.fpr;
  504. u32 ps0_out;
  505. u32 ps0_in1, ps0_in2;
  506. u32 ps1_out;
  507. u32 ps1_in1, ps1_in2;
  508. /* RC */
  509. WARN_ON(rc);
  510. /* PS0 */
  511. kvm_cvt_df(&fpr[reg_in1], &ps0_in1);
  512. if (scalar & SCALAR_LOW)
  513. ps0_in2 = qpr[reg_in2];
  514. else
  515. kvm_cvt_df(&fpr[reg_in2], &ps0_in2);
  516. func(&vcpu->arch.fpscr, &ps0_out, &ps0_in1, &ps0_in2);
  517. if (!(scalar & SCALAR_NO_PS0)) {
  518. dprintk(KERN_INFO "PS2 ps0 -> f(0x%x, 0x%x) = 0x%x\n",
  519. ps0_in1, ps0_in2, ps0_out);
  520. kvm_cvt_fd(&ps0_out, &fpr[reg_out]);
  521. }
  522. /* PS1 */
  523. ps1_in1 = qpr[reg_in1];
  524. ps1_in2 = qpr[reg_in2];
  525. if (scalar & SCALAR_HIGH)
  526. ps1_in2 = ps0_in2;
  527. func(&vcpu->arch.fpscr, &ps1_out, &ps1_in1, &ps1_in2);
  528. if (!(scalar & SCALAR_NO_PS1)) {
  529. qpr[reg_out] = ps1_out;
  530. dprintk(KERN_INFO "PS2 ps1 -> f(0x%x, 0x%x) = 0x%x\n",
  531. ps1_in1, ps1_in2, qpr[reg_out]);
  532. }
  533. return EMULATE_DONE;
  534. }
  535. static int kvmppc_ps_one_in(struct kvm_vcpu *vcpu, bool rc,
  536. int reg_out, int reg_in,
  537. void (*func)(u64 *t,
  538. u32 *dst, u32 *src1))
  539. {
  540. u32 *qpr = vcpu->arch.qpr;
  541. u64 *fpr = vcpu->arch.fpr;
  542. u32 ps0_out, ps0_in;
  543. u32 ps1_in;
  544. /* RC */
  545. WARN_ON(rc);
  546. /* PS0 */
  547. kvm_cvt_df(&fpr[reg_in], &ps0_in);
  548. func(&vcpu->arch.fpscr, &ps0_out, &ps0_in);
  549. dprintk(KERN_INFO "PS1 ps0 -> f(0x%x) = 0x%x\n",
  550. ps0_in, ps0_out);
  551. kvm_cvt_fd(&ps0_out, &fpr[reg_out]);
  552. /* PS1 */
  553. ps1_in = qpr[reg_in];
  554. func(&vcpu->arch.fpscr, &qpr[reg_out], &ps1_in);
  555. dprintk(KERN_INFO "PS1 ps1 -> f(0x%x) = 0x%x\n",
  556. ps1_in, qpr[reg_out]);
  557. return EMULATE_DONE;
  558. }
  559. int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
  560. {
  561. u32 inst = kvmppc_get_last_inst(vcpu);
  562. enum emulation_result emulated = EMULATE_DONE;
  563. int ax_rd = inst_get_field(inst, 6, 10);
  564. int ax_ra = inst_get_field(inst, 11, 15);
  565. int ax_rb = inst_get_field(inst, 16, 20);
  566. int ax_rc = inst_get_field(inst, 21, 25);
  567. short full_d = inst_get_field(inst, 16, 31);
  568. u64 *fpr_d = &vcpu->arch.fpr[ax_rd];
  569. u64 *fpr_a = &vcpu->arch.fpr[ax_ra];
  570. u64 *fpr_b = &vcpu->arch.fpr[ax_rb];
  571. u64 *fpr_c = &vcpu->arch.fpr[ax_rc];
  572. bool rcomp = (inst & 1) ? true : false;
  573. u32 cr = kvmppc_get_cr(vcpu);
  574. #ifdef DEBUG
  575. int i;
  576. #endif
  577. if (!kvmppc_inst_is_paired_single(vcpu, inst))
  578. return EMULATE_FAIL;
  579. if (!(vcpu->arch.shared->msr & MSR_FP)) {
  580. kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL);
  581. return EMULATE_AGAIN;
  582. }
  583. kvmppc_giveup_ext(vcpu, MSR_FP);
  584. preempt_disable();
  585. enable_kernel_fp();
  586. /* Do we need to clear FE0 / FE1 here? Don't think so. */
  587. #ifdef DEBUG
  588. for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) {
  589. u32 f;
  590. kvm_cvt_df(&vcpu->arch.fpr[i], &f);
  591. dprintk(KERN_INFO "FPR[%d] = 0x%x / 0x%llx QPR[%d] = 0x%x\n",
  592. i, f, vcpu->arch.fpr[i], i, vcpu->arch.qpr[i]);
  593. }
  594. #endif
  595. switch (get_op(inst)) {
  596. case OP_PSQ_L:
  597. {
  598. ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
  599. bool w = inst_get_field(inst, 16, 16) ? true : false;
  600. int i = inst_get_field(inst, 17, 19);
  601. addr += get_d_signext(inst);
  602. emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
  603. break;
  604. }
  605. case OP_PSQ_LU:
  606. {
  607. ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
  608. bool w = inst_get_field(inst, 16, 16) ? true : false;
  609. int i = inst_get_field(inst, 17, 19);
  610. addr += get_d_signext(inst);
  611. emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
  612. if (emulated == EMULATE_DONE)
  613. kvmppc_set_gpr(vcpu, ax_ra, addr);
  614. break;
  615. }
  616. case OP_PSQ_ST:
  617. {
  618. ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
  619. bool w = inst_get_field(inst, 16, 16) ? true : false;
  620. int i = inst_get_field(inst, 17, 19);
  621. addr += get_d_signext(inst);
  622. emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
  623. break;
  624. }
  625. case OP_PSQ_STU:
  626. {
  627. ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
  628. bool w = inst_get_field(inst, 16, 16) ? true : false;
  629. int i = inst_get_field(inst, 17, 19);
  630. addr += get_d_signext(inst);
  631. emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
  632. if (emulated == EMULATE_DONE)
  633. kvmppc_set_gpr(vcpu, ax_ra, addr);
  634. break;
  635. }
  636. case 4:
  637. /* X form */
  638. switch (inst_get_field(inst, 21, 30)) {
  639. case OP_4X_PS_CMPU0:
  640. /* XXX */
  641. emulated = EMULATE_FAIL;
  642. break;
  643. case OP_4X_PSQ_LX:
  644. {
  645. ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
  646. bool w = inst_get_field(inst, 21, 21) ? true : false;
  647. int i = inst_get_field(inst, 22, 24);
  648. addr += kvmppc_get_gpr(vcpu, ax_rb);
  649. emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
  650. break;
  651. }
  652. case OP_4X_PS_CMPO0:
  653. /* XXX */
  654. emulated = EMULATE_FAIL;
  655. break;
  656. case OP_4X_PSQ_LUX:
  657. {
  658. ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
  659. bool w = inst_get_field(inst, 21, 21) ? true : false;
  660. int i = inst_get_field(inst, 22, 24);
  661. addr += kvmppc_get_gpr(vcpu, ax_rb);
  662. emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
  663. if (emulated == EMULATE_DONE)
  664. kvmppc_set_gpr(vcpu, ax_ra, addr);
  665. break;
  666. }
  667. case OP_4X_PS_NEG:
  668. vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
  669. vcpu->arch.fpr[ax_rd] ^= 0x8000000000000000ULL;
  670. vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
  671. vcpu->arch.qpr[ax_rd] ^= 0x80000000;
  672. break;
  673. case OP_4X_PS_CMPU1:
  674. /* XXX */
  675. emulated = EMULATE_FAIL;
  676. break;
  677. case OP_4X_PS_MR:
  678. WARN_ON(rcomp);
  679. vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
  680. vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
  681. break;
  682. case OP_4X_PS_CMPO1:
  683. /* XXX */
  684. emulated = EMULATE_FAIL;
  685. break;
  686. case OP_4X_PS_NABS:
  687. WARN_ON(rcomp);
  688. vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
  689. vcpu->arch.fpr[ax_rd] |= 0x8000000000000000ULL;
  690. vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
  691. vcpu->arch.qpr[ax_rd] |= 0x80000000;
  692. break;
  693. case OP_4X_PS_ABS:
  694. WARN_ON(rcomp);
  695. vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
  696. vcpu->arch.fpr[ax_rd] &= ~0x8000000000000000ULL;
  697. vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
  698. vcpu->arch.qpr[ax_rd] &= ~0x80000000;
  699. break;
  700. case OP_4X_PS_MERGE00:
  701. WARN_ON(rcomp);
  702. vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_ra];
  703. /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */
  704. kvm_cvt_df(&vcpu->arch.fpr[ax_rb],
  705. &vcpu->arch.qpr[ax_rd]);
  706. break;
  707. case OP_4X_PS_MERGE01:
  708. WARN_ON(rcomp);
  709. vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_ra];
  710. vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
  711. break;
  712. case OP_4X_PS_MERGE10:
  713. WARN_ON(rcomp);
  714. /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */
  715. kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
  716. &vcpu->arch.fpr[ax_rd]);
  717. /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */
  718. kvm_cvt_df(&vcpu->arch.fpr[ax_rb],
  719. &vcpu->arch.qpr[ax_rd]);
  720. break;
  721. case OP_4X_PS_MERGE11:
  722. WARN_ON(rcomp);
  723. /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */
  724. kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
  725. &vcpu->arch.fpr[ax_rd]);
  726. vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
  727. break;
  728. }
  729. /* XW form */
  730. switch (inst_get_field(inst, 25, 30)) {
  731. case OP_4XW_PSQ_STX:
  732. {
  733. ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
  734. bool w = inst_get_field(inst, 21, 21) ? true : false;
  735. int i = inst_get_field(inst, 22, 24);
  736. addr += kvmppc_get_gpr(vcpu, ax_rb);
  737. emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
  738. break;
  739. }
  740. case OP_4XW_PSQ_STUX:
  741. {
  742. ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
  743. bool w = inst_get_field(inst, 21, 21) ? true : false;
  744. int i = inst_get_field(inst, 22, 24);
  745. addr += kvmppc_get_gpr(vcpu, ax_rb);
  746. emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
  747. if (emulated == EMULATE_DONE)
  748. kvmppc_set_gpr(vcpu, ax_ra, addr);
  749. break;
  750. }
  751. }
  752. /* A form */
  753. switch (inst_get_field(inst, 26, 30)) {
  754. case OP_4A_PS_SUM1:
  755. emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
  756. ax_rb, ax_ra, SCALAR_NO_PS0 | SCALAR_HIGH, fps_fadds);
  757. vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rc];
  758. break;
  759. case OP_4A_PS_SUM0:
  760. emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
  761. ax_ra, ax_rb, SCALAR_NO_PS1 | SCALAR_LOW, fps_fadds);
  762. vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rc];
  763. break;
  764. case OP_4A_PS_MULS0:
  765. emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
  766. ax_ra, ax_rc, SCALAR_HIGH, fps_fmuls);
  767. break;
  768. case OP_4A_PS_MULS1:
  769. emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
  770. ax_ra, ax_rc, SCALAR_LOW, fps_fmuls);
  771. break;
  772. case OP_4A_PS_MADDS0:
  773. emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
  774. ax_ra, ax_rc, ax_rb, SCALAR_HIGH, fps_fmadds);
  775. break;
  776. case OP_4A_PS_MADDS1:
  777. emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
  778. ax_ra, ax_rc, ax_rb, SCALAR_LOW, fps_fmadds);
  779. break;
  780. case OP_4A_PS_DIV:
  781. emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
  782. ax_ra, ax_rb, SCALAR_NONE, fps_fdivs);
  783. break;
  784. case OP_4A_PS_SUB:
  785. emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
  786. ax_ra, ax_rb, SCALAR_NONE, fps_fsubs);
  787. break;
  788. case OP_4A_PS_ADD:
  789. emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
  790. ax_ra, ax_rb, SCALAR_NONE, fps_fadds);
  791. break;
  792. case OP_4A_PS_SEL:
  793. emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
  794. ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fsel);
  795. break;
  796. case OP_4A_PS_RES:
  797. emulated = kvmppc_ps_one_in(vcpu, rcomp, ax_rd,
  798. ax_rb, fps_fres);
  799. break;
  800. case OP_4A_PS_MUL:
  801. emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
  802. ax_ra, ax_rc, SCALAR_NONE, fps_fmuls);
  803. break;
  804. case OP_4A_PS_RSQRTE:
  805. emulated = kvmppc_ps_one_in(vcpu, rcomp, ax_rd,
  806. ax_rb, fps_frsqrte);
  807. break;
  808. case OP_4A_PS_MSUB:
  809. emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
  810. ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fmsubs);
  811. break;
  812. case OP_4A_PS_MADD:
  813. emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
  814. ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fmadds);
  815. break;
  816. case OP_4A_PS_NMSUB:
  817. emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
  818. ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fnmsubs);
  819. break;
  820. case OP_4A_PS_NMADD:
  821. emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
  822. ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fnmadds);
  823. break;
  824. }
  825. break;
  826. /* Real FPU operations */
  827. case OP_LFS:
  828. {
  829. ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
  830. emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
  831. FPU_LS_SINGLE);
  832. break;
  833. }
  834. case OP_LFSU:
  835. {
  836. ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
  837. emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
  838. FPU_LS_SINGLE);
  839. if (emulated == EMULATE_DONE)
  840. kvmppc_set_gpr(vcpu, ax_ra, addr);
  841. break;
  842. }
  843. case OP_LFD:
  844. {
  845. ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
  846. emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
  847. FPU_LS_DOUBLE);
  848. break;
  849. }
  850. case OP_LFDU:
  851. {
  852. ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
  853. emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
  854. FPU_LS_DOUBLE);
  855. if (emulated == EMULATE_DONE)
  856. kvmppc_set_gpr(vcpu, ax_ra, addr);
  857. break;
  858. }
  859. case OP_STFS:
  860. {
  861. ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
  862. emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
  863. FPU_LS_SINGLE);
  864. break;
  865. }
  866. case OP_STFSU:
  867. {
  868. ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
  869. emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
  870. FPU_LS_SINGLE);
  871. if (emulated == EMULATE_DONE)
  872. kvmppc_set_gpr(vcpu, ax_ra, addr);
  873. break;
  874. }
  875. case OP_STFD:
  876. {
  877. ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
  878. emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
  879. FPU_LS_DOUBLE);
  880. break;
  881. }
  882. case OP_STFDU:
  883. {
  884. ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
  885. emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
  886. FPU_LS_DOUBLE);
  887. if (emulated == EMULATE_DONE)
  888. kvmppc_set_gpr(vcpu, ax_ra, addr);
  889. break;
  890. }
  891. case 31:
  892. switch (inst_get_field(inst, 21, 30)) {
  893. case OP_31_LFSX:
  894. {
  895. ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
  896. addr += kvmppc_get_gpr(vcpu, ax_rb);
  897. emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
  898. addr, FPU_LS_SINGLE);
  899. break;
  900. }
  901. case OP_31_LFSUX:
  902. {
  903. ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
  904. kvmppc_get_gpr(vcpu, ax_rb);
  905. emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
  906. addr, FPU_LS_SINGLE);
  907. if (emulated == EMULATE_DONE)
  908. kvmppc_set_gpr(vcpu, ax_ra, addr);
  909. break;
  910. }
  911. case OP_31_LFDX:
  912. {
  913. ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
  914. kvmppc_get_gpr(vcpu, ax_rb);
  915. emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
  916. addr, FPU_LS_DOUBLE);
  917. break;
  918. }
  919. case OP_31_LFDUX:
  920. {
  921. ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
  922. kvmppc_get_gpr(vcpu, ax_rb);
  923. emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
  924. addr, FPU_LS_DOUBLE);
  925. if (emulated == EMULATE_DONE)
  926. kvmppc_set_gpr(vcpu, ax_ra, addr);
  927. break;
  928. }
  929. case OP_31_STFSX:
  930. {
  931. ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
  932. kvmppc_get_gpr(vcpu, ax_rb);
  933. emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
  934. addr, FPU_LS_SINGLE);
  935. break;
  936. }
  937. case OP_31_STFSUX:
  938. {
  939. ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
  940. kvmppc_get_gpr(vcpu, ax_rb);
  941. emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
  942. addr, FPU_LS_SINGLE);
  943. if (emulated == EMULATE_DONE)
  944. kvmppc_set_gpr(vcpu, ax_ra, addr);
  945. break;
  946. }
  947. case OP_31_STFX:
  948. {
  949. ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
  950. kvmppc_get_gpr(vcpu, ax_rb);
  951. emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
  952. addr, FPU_LS_DOUBLE);
  953. break;
  954. }
  955. case OP_31_STFUX:
  956. {
  957. ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
  958. kvmppc_get_gpr(vcpu, ax_rb);
  959. emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
  960. addr, FPU_LS_DOUBLE);
  961. if (emulated == EMULATE_DONE)
  962. kvmppc_set_gpr(vcpu, ax_ra, addr);
  963. break;
  964. }
  965. case OP_31_STFIWX:
  966. {
  967. ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
  968. kvmppc_get_gpr(vcpu, ax_rb);
  969. emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
  970. addr,
  971. FPU_LS_SINGLE_LOW);
  972. break;
  973. }
  974. break;
  975. }
  976. break;
  977. case 59:
  978. switch (inst_get_field(inst, 21, 30)) {
  979. case OP_59_FADDS:
  980. fpd_fadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
  981. kvmppc_sync_qpr(vcpu, ax_rd);
  982. break;
  983. case OP_59_FSUBS:
  984. fpd_fsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
  985. kvmppc_sync_qpr(vcpu, ax_rd);
  986. break;
  987. case OP_59_FDIVS:
  988. fpd_fdivs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
  989. kvmppc_sync_qpr(vcpu, ax_rd);
  990. break;
  991. case OP_59_FRES:
  992. fpd_fres(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
  993. kvmppc_sync_qpr(vcpu, ax_rd);
  994. break;
  995. case OP_59_FRSQRTES:
  996. fpd_frsqrtes(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
  997. kvmppc_sync_qpr(vcpu, ax_rd);
  998. break;
  999. }
  1000. switch (inst_get_field(inst, 26, 30)) {
  1001. case OP_59_FMULS:
  1002. fpd_fmuls(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c);
  1003. kvmppc_sync_qpr(vcpu, ax_rd);
  1004. break;
  1005. case OP_59_FMSUBS:
  1006. fpd_fmsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
  1007. kvmppc_sync_qpr(vcpu, ax_rd);
  1008. break;
  1009. case OP_59_FMADDS:
  1010. fpd_fmadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
  1011. kvmppc_sync_qpr(vcpu, ax_rd);
  1012. break;
  1013. case OP_59_FNMSUBS:
  1014. fpd_fnmsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
  1015. kvmppc_sync_qpr(vcpu, ax_rd);
  1016. break;
  1017. case OP_59_FNMADDS:
  1018. fpd_fnmadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
  1019. kvmppc_sync_qpr(vcpu, ax_rd);
  1020. break;
  1021. }
  1022. break;
  1023. case 63:
  1024. switch (inst_get_field(inst, 21, 30)) {
  1025. case OP_63_MTFSB0:
  1026. case OP_63_MTFSB1:
  1027. case OP_63_MCRFS:
  1028. case OP_63_MTFSFI:
  1029. /* XXX need to implement */
  1030. break;
  1031. case OP_63_MFFS:
  1032. /* XXX missing CR */
  1033. *fpr_d = vcpu->arch.fpscr;
  1034. break;
  1035. case OP_63_MTFSF:
  1036. /* XXX missing fm bits */
  1037. /* XXX missing CR */
  1038. vcpu->arch.fpscr = *fpr_b;
  1039. break;
  1040. case OP_63_FCMPU:
  1041. {
  1042. u32 tmp_cr;
  1043. u32 cr0_mask = 0xf0000000;
  1044. u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
  1045. fpd_fcmpu(&vcpu->arch.fpscr, &tmp_cr, fpr_a, fpr_b);
  1046. cr &= ~(cr0_mask >> cr_shift);
  1047. cr |= (cr & cr0_mask) >> cr_shift;
  1048. break;
  1049. }
  1050. case OP_63_FCMPO:
  1051. {
  1052. u32 tmp_cr;
  1053. u32 cr0_mask = 0xf0000000;
  1054. u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
  1055. fpd_fcmpo(&vcpu->arch.fpscr, &tmp_cr, fpr_a, fpr_b);
  1056. cr &= ~(cr0_mask >> cr_shift);
  1057. cr |= (cr & cr0_mask) >> cr_shift;
  1058. break;
  1059. }
  1060. case OP_63_FNEG:
  1061. fpd_fneg(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
  1062. break;
  1063. case OP_63_FMR:
  1064. *fpr_d = *fpr_b;
  1065. break;
  1066. case OP_63_FABS:
  1067. fpd_fabs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
  1068. break;
  1069. case OP_63_FCPSGN:
  1070. fpd_fcpsgn(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
  1071. break;
  1072. case OP_63_FDIV:
  1073. fpd_fdiv(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
  1074. break;
  1075. case OP_63_FADD:
  1076. fpd_fadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
  1077. break;
  1078. case OP_63_FSUB:
  1079. fpd_fsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
  1080. break;
  1081. case OP_63_FCTIW:
  1082. fpd_fctiw(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
  1083. break;
  1084. case OP_63_FCTIWZ:
  1085. fpd_fctiwz(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
  1086. break;
  1087. case OP_63_FRSP:
  1088. fpd_frsp(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
  1089. kvmppc_sync_qpr(vcpu, ax_rd);
  1090. break;
  1091. case OP_63_FRSQRTE:
  1092. {
  1093. double one = 1.0f;
  1094. /* fD = sqrt(fB) */
  1095. fpd_fsqrt(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
  1096. /* fD = 1.0f / fD */
  1097. fpd_fdiv(&vcpu->arch.fpscr, &cr, fpr_d, (u64*)&one, fpr_d);
  1098. break;
  1099. }
  1100. }
  1101. switch (inst_get_field(inst, 26, 30)) {
  1102. case OP_63_FMUL:
  1103. fpd_fmul(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c);
  1104. break;
  1105. case OP_63_FSEL:
  1106. fpd_fsel(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
  1107. break;
  1108. case OP_63_FMSUB:
  1109. fpd_fmsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
  1110. break;
  1111. case OP_63_FMADD:
  1112. fpd_fmadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
  1113. break;
  1114. case OP_63_FNMSUB:
  1115. fpd_fnmsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
  1116. break;
  1117. case OP_63_FNMADD:
  1118. fpd_fnmadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
  1119. break;
  1120. }
  1121. break;
  1122. }
  1123. #ifdef DEBUG
  1124. for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) {
  1125. u32 f;
  1126. kvm_cvt_df(&vcpu->arch.fpr[i], &f);
  1127. dprintk(KERN_INFO "FPR[%d] = 0x%x\n", i, f);
  1128. }
  1129. #endif
  1130. if (rcomp)
  1131. kvmppc_set_cr(vcpu, cr);
  1132. preempt_enable();
  1133. return emulated;
  1134. }