currituck.dts 7.2 KB

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  1. /*
  2. * Device Tree Source for IBM Embedded PPC 476 Platform
  3. *
  4. * Copyright © 2011 Tony Breeds IBM Corporation
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without
  8. * any warranty of any kind, whether express or implied.
  9. */
  10. /dts-v1/;
  11. /memreserve/ 0x01f00000 0x00100000; // spin table
  12. / {
  13. #address-cells = <2>;
  14. #size-cells = <2>;
  15. model = "ibm,currituck";
  16. compatible = "ibm,currituck";
  17. dcr-parent = <&{/cpus/cpu@0}>;
  18. aliases {
  19. serial0 = &UART0;
  20. };
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu@0 {
  25. device_type = "cpu";
  26. model = "PowerPC,476";
  27. reg = <0>;
  28. clock-frequency = <1600000000>; // 1.6 GHz
  29. timebase-frequency = <100000000>; // 100Mhz
  30. i-cache-line-size = <32>;
  31. d-cache-line-size = <32>;
  32. i-cache-size = <32768>;
  33. d-cache-size = <32768>;
  34. dcr-controller;
  35. dcr-access-method = "native";
  36. status = "ok";
  37. };
  38. cpu@1 {
  39. device_type = "cpu";
  40. model = "PowerPC,476";
  41. reg = <1>;
  42. clock-frequency = <1600000000>; // 1.6 GHz
  43. timebase-frequency = <100000000>; // 100Mhz
  44. i-cache-line-size = <32>;
  45. d-cache-line-size = <32>;
  46. i-cache-size = <32768>;
  47. d-cache-size = <32768>;
  48. dcr-controller;
  49. dcr-access-method = "native";
  50. status = "disabled";
  51. enable-method = "spin-table";
  52. cpu-release-addr = <0x0 0x01f00000>;
  53. };
  54. };
  55. memory {
  56. device_type = "memory";
  57. reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
  58. };
  59. MPIC: interrupt-controller {
  60. compatible = "chrp,open-pic";
  61. interrupt-controller;
  62. dcr-reg = <0xffc00000 0x00040000>;
  63. #address-cells = <0>;
  64. #size-cells = <0>;
  65. #interrupt-cells = <2>;
  66. };
  67. plb {
  68. compatible = "ibm,plb6";
  69. #address-cells = <2>;
  70. #size-cells = <2>;
  71. ranges;
  72. clock-frequency = <200000000>; // 200Mhz
  73. POB0: opb {
  74. compatible = "ibm,opb-4xx", "ibm,opb";
  75. #address-cells = <1>;
  76. #size-cells = <1>;
  77. /* Wish there was a nicer way of specifying a full
  78. * 32-bit range
  79. */
  80. ranges = <0x00000000 0x00000200 0x00000000 0x80000000
  81. 0x80000000 0x00000200 0x80000000 0x80000000>;
  82. clock-frequency = <100000000>;
  83. UART0: serial@10000000 {
  84. device_type = "serial";
  85. compatible = "ns16750", "ns16550";
  86. reg = <0x10000000 0x00000008>;
  87. virtual-reg = <0xe1000000>;
  88. clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
  89. current-speed = <115200>;
  90. interrupt-parent = <&MPIC>;
  91. interrupts = <34 2>;
  92. };
  93. IIC0: i2c@00000000 {
  94. compatible = "ibm,iic-currituck", "ibm,iic";
  95. reg = <0x0 0x00000014>;
  96. interrupt-parent = <&MPIC>;
  97. interrupts = <79 2>;
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. rtc@68 {
  101. compatible = "stm,m41t80", "m41st85";
  102. reg = <0x68>;
  103. };
  104. };
  105. };
  106. PCIE0: pciex@10100000000 { // 4xGBIF1
  107. device_type = "pci";
  108. #interrupt-cells = <1>;
  109. #size-cells = <2>;
  110. #address-cells = <3>;
  111. compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
  112. primary;
  113. port = <0x0>; /* port number */
  114. reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
  115. 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
  116. dcr-reg = <0x80 0x20>;
  117. // pci_space < pci_addr > < cpu_addr > < size >
  118. ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
  119. 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
  120. /* Inbound starting at 0 to memsize filled in by zImage */
  121. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
  122. /* This drives busses 0 to 0xf */
  123. bus-range = <0x0 0xf>;
  124. /* Legacy interrupts (note the weird polarity, the bridge seems
  125. * to invert PCIe legacy interrupts).
  126. * We are de-swizzling here because the numbers are actually for
  127. * port of the root complex virtual P2P bridge. But I want
  128. * to avoid putting a node for it in the tree, so the numbers
  129. * below are basically de-swizzled numbers.
  130. * The real slot is on idsel 0, so the swizzling is 1:1
  131. */
  132. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  133. interrupt-map = <
  134. 0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
  135. 0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
  136. 0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
  137. 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
  138. };
  139. PCIE1: pciex@30100000000 { // 4xGBIF0
  140. device_type = "pci";
  141. #interrupt-cells = <1>;
  142. #size-cells = <2>;
  143. #address-cells = <3>;
  144. compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
  145. primary;
  146. port = <0x1>; /* port number */
  147. reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */
  148. 0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
  149. dcr-reg = <0x60 0x20>;
  150. ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
  151. 0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>;
  152. /* Inbound starting at 0 to memsize filled in by zImage */
  153. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
  154. /* This drives busses 0 to 0xf */
  155. bus-range = <0x0 0xf>;
  156. /* Legacy interrupts (note the weird polarity, the bridge seems
  157. * to invert PCIe legacy interrupts).
  158. * We are de-swizzling here because the numbers are actually for
  159. * port of the root complex virtual P2P bridge. But I want
  160. * to avoid putting a node for it in the tree, so the numbers
  161. * below are basically de-swizzled numbers.
  162. * The real slot is on idsel 0, so the swizzling is 1:1
  163. */
  164. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  165. interrupt-map = <
  166. 0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
  167. 0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
  168. 0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
  169. 0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
  170. };
  171. PCIE2: pciex@38100000000 { // 2xGBIF0
  172. device_type = "pci";
  173. #interrupt-cells = <1>;
  174. #size-cells = <2>;
  175. #address-cells = <3>;
  176. compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
  177. primary;
  178. port = <0x2>; /* port number */
  179. reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */
  180. 0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
  181. dcr-reg = <0xA0 0x20>;
  182. ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
  183. 0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>;
  184. /* Inbound starting at 0 to memsize filled in by zImage */
  185. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
  186. /* This drives busses 0 to 0xf */
  187. bus-range = <0x0 0xf>;
  188. /* Legacy interrupts (note the weird polarity, the bridge seems
  189. * to invert PCIe legacy interrupts).
  190. * We are de-swizzling here because the numbers are actually for
  191. * port of the root complex virtual P2P bridge. But I want
  192. * to avoid putting a node for it in the tree, so the numbers
  193. * below are basically de-swizzled numbers.
  194. * The real slot is on idsel 0, so the swizzling is 1:1
  195. */
  196. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  197. interrupt-map = <
  198. 0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
  199. 0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
  200. 0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
  201. 0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
  202. };
  203. };
  204. chosen {
  205. linux,stdout-path = &UART0;
  206. };
  207. };