clock.c 5.0 KB

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  1. /* linux/arch/arm/plat-s5p/clock.c
  2. *
  3. * Copyright 2009 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * S5P - Common clock support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/list.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/clk.h>
  19. #include <linux/device.h>
  20. #include <linux/io.h>
  21. #include <asm/div64.h>
  22. #include <mach/regs-clock.h>
  23. #include <plat/clock.h>
  24. #include <plat/clock-clksrc.h>
  25. #include <plat/s5p-clock.h>
  26. /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
  27. * clk_ext_xtal_mux.
  28. */
  29. struct clk clk_ext_xtal_mux = {
  30. .name = "ext_xtal",
  31. .id = -1,
  32. };
  33. struct clk clk_xusbxti = {
  34. .name = "xusbxti",
  35. .id = -1,
  36. };
  37. struct clk s5p_clk_27m = {
  38. .name = "clk_27m",
  39. .id = -1,
  40. .rate = 27000000,
  41. };
  42. /* 48MHz USB Phy clock output */
  43. struct clk clk_48m = {
  44. .name = "clk_48m",
  45. .id = -1,
  46. .rate = 48000000,
  47. };
  48. /* APLL clock output
  49. * No need .ctrlbit, this is always on
  50. */
  51. struct clk clk_fout_apll = {
  52. .name = "fout_apll",
  53. .id = -1,
  54. };
  55. /* BPLL clock output */
  56. struct clk clk_fout_bpll = {
  57. .name = "fout_bpll",
  58. .id = -1,
  59. };
  60. /* CPLL clock output */
  61. struct clk clk_fout_cpll = {
  62. .name = "fout_cpll",
  63. .id = -1,
  64. };
  65. /* MPLL clock output
  66. * No need .ctrlbit, this is always on
  67. */
  68. struct clk clk_fout_mpll = {
  69. .name = "fout_mpll",
  70. .id = -1,
  71. };
  72. /* EPLL clock output */
  73. struct clk clk_fout_epll = {
  74. .name = "fout_epll",
  75. .id = -1,
  76. .ctrlbit = (1 << 31),
  77. };
  78. /* DPLL clock output */
  79. struct clk clk_fout_dpll = {
  80. .name = "fout_dpll",
  81. .id = -1,
  82. .ctrlbit = (1 << 31),
  83. };
  84. /* VPLL clock output */
  85. struct clk clk_fout_vpll = {
  86. .name = "fout_vpll",
  87. .id = -1,
  88. .ctrlbit = (1 << 31),
  89. };
  90. /* Possible clock sources for APLL Mux */
  91. static struct clk *clk_src_apll_list[] = {
  92. [0] = &clk_fin_apll,
  93. [1] = &clk_fout_apll,
  94. };
  95. struct clksrc_sources clk_src_apll = {
  96. .sources = clk_src_apll_list,
  97. .nr_sources = ARRAY_SIZE(clk_src_apll_list),
  98. };
  99. /* Possible clock sources for BPLL Mux */
  100. static struct clk *clk_src_bpll_list[] = {
  101. [0] = &clk_fin_bpll,
  102. [1] = &clk_fout_bpll,
  103. };
  104. struct clksrc_sources clk_src_bpll = {
  105. .sources = clk_src_bpll_list,
  106. .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
  107. };
  108. /* Possible clock sources for CPLL Mux */
  109. static struct clk *clk_src_cpll_list[] = {
  110. [0] = &clk_fin_cpll,
  111. [1] = &clk_fout_cpll,
  112. };
  113. struct clksrc_sources clk_src_cpll = {
  114. .sources = clk_src_cpll_list,
  115. .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
  116. };
  117. /* Possible clock sources for MPLL Mux */
  118. static struct clk *clk_src_mpll_list[] = {
  119. [0] = &clk_fin_mpll,
  120. [1] = &clk_fout_mpll,
  121. };
  122. struct clksrc_sources clk_src_mpll = {
  123. .sources = clk_src_mpll_list,
  124. .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
  125. };
  126. /* Possible clock sources for EPLL Mux */
  127. static struct clk *clk_src_epll_list[] = {
  128. [0] = &clk_fin_epll,
  129. [1] = &clk_fout_epll,
  130. };
  131. struct clksrc_sources clk_src_epll = {
  132. .sources = clk_src_epll_list,
  133. .nr_sources = ARRAY_SIZE(clk_src_epll_list),
  134. };
  135. /* Possible clock sources for DPLL Mux */
  136. static struct clk *clk_src_dpll_list[] = {
  137. [0] = &clk_fin_dpll,
  138. [1] = &clk_fout_dpll,
  139. };
  140. struct clksrc_sources clk_src_dpll = {
  141. .sources = clk_src_dpll_list,
  142. .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
  143. };
  144. struct clk clk_vpll = {
  145. .name = "vpll",
  146. .id = -1,
  147. };
  148. int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
  149. {
  150. unsigned int ctrlbit = clk->ctrlbit;
  151. u32 con;
  152. con = __raw_readl(reg);
  153. con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
  154. __raw_writel(con, reg);
  155. return 0;
  156. }
  157. int s5p_epll_enable(struct clk *clk, int enable)
  158. {
  159. unsigned int ctrlbit = clk->ctrlbit;
  160. unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
  161. if (enable)
  162. __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
  163. else
  164. __raw_writel(epll_con, S5P_EPLL_CON);
  165. return 0;
  166. }
  167. unsigned long s5p_epll_get_rate(struct clk *clk)
  168. {
  169. return clk->rate;
  170. }
  171. int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
  172. {
  173. struct clk *pclk;
  174. int ret;
  175. pclk = clk_get_parent(clk);
  176. if (IS_ERR(pclk))
  177. return -EINVAL;
  178. ret = pclk->ops->set_rate(pclk, rate);
  179. clk_put(pclk);
  180. return ret;
  181. }
  182. unsigned long s5p_spdif_get_rate(struct clk *clk)
  183. {
  184. struct clk *pclk;
  185. int rate;
  186. pclk = clk_get_parent(clk);
  187. if (IS_ERR(pclk))
  188. return -EINVAL;
  189. rate = pclk->ops->get_rate(pclk);
  190. clk_put(pclk);
  191. return rate;
  192. }
  193. struct clk_ops s5p_sclk_spdif_ops = {
  194. .set_rate = s5p_spdif_set_rate,
  195. .get_rate = s5p_spdif_get_rate,
  196. };
  197. static struct clk *s5p_clks[] __initdata = {
  198. &clk_ext_xtal_mux,
  199. &clk_48m,
  200. &s5p_clk_27m,
  201. &clk_fout_apll,
  202. &clk_fout_mpll,
  203. &clk_fout_epll,
  204. &clk_fout_dpll,
  205. &clk_fout_vpll,
  206. &clk_vpll,
  207. &clk_xusbxti,
  208. };
  209. void __init s5p_register_clocks(unsigned long xtal_freq)
  210. {
  211. int ret;
  212. clk_ext_xtal_mux.rate = xtal_freq;
  213. ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
  214. if (ret > 0)
  215. printk(KERN_ERR "Failed to register s5p clocks\n");
  216. }