pxa3xx_nand.h 2.3 KB

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  1. #ifndef __ASM_ARCH_PXA3XX_NAND_H
  2. #define __ASM_ARCH_PXA3XX_NAND_H
  3. #include <linux/mtd/mtd.h>
  4. #include <linux/mtd/partitions.h>
  5. struct pxa3xx_nand_timing {
  6. unsigned int tCH; /* Enable signal hold time */
  7. unsigned int tCS; /* Enable signal setup time */
  8. unsigned int tWH; /* ND_nWE high duration */
  9. unsigned int tWP; /* ND_nWE pulse time */
  10. unsigned int tRH; /* ND_nRE high duration */
  11. unsigned int tRP; /* ND_nRE pulse width */
  12. unsigned int tR; /* ND_nWE high to ND_nRE low for read */
  13. unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
  14. unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
  15. };
  16. struct pxa3xx_nand_cmdset {
  17. uint16_t read1;
  18. uint16_t read2;
  19. uint16_t program;
  20. uint16_t read_status;
  21. uint16_t read_id;
  22. uint16_t erase;
  23. uint16_t reset;
  24. uint16_t lock;
  25. uint16_t unlock;
  26. uint16_t lock_status;
  27. };
  28. struct pxa3xx_nand_flash {
  29. char *name;
  30. uint32_t chip_id;
  31. unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
  32. unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
  33. unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
  34. unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
  35. unsigned int num_blocks; /* Number of physical blocks in Flash */
  36. struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
  37. };
  38. /*
  39. * Current pxa3xx_nand controller has two chip select which
  40. * both be workable.
  41. *
  42. * Notice should be taken that:
  43. * When you want to use this feature, you should not enable the
  44. * keep configuration feature, for two chip select could be
  45. * attached with different nand chip. The different page size
  46. * and timing requirement make the keep configuration impossible.
  47. */
  48. /* The max num of chip select current support */
  49. #define NUM_CHIP_SELECT (2)
  50. struct pxa3xx_nand_platform_data {
  51. /* the data flash bus is shared between the Static Memory
  52. * Controller and the Data Flash Controller, the arbiter
  53. * controls the ownership of the bus
  54. */
  55. int enable_arbiter;
  56. /* allow platform code to keep OBM/bootloader defined NFC config */
  57. int keep_config;
  58. /* indicate how many chip selects will be used */
  59. int num_cs;
  60. const struct mtd_partition *parts[NUM_CHIP_SELECT];
  61. unsigned int nr_parts[NUM_CHIP_SELECT];
  62. const struct pxa3xx_nand_flash * flash;
  63. size_t num_flash;
  64. };
  65. extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
  66. #endif /* __ASM_ARCH_PXA3XX_NAND_H */