cpuidle44xx.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229
  1. /*
  2. * OMAP4 CPU idle Routines
  3. *
  4. * Copyright (C) 2011 Texas Instruments, Inc.
  5. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  6. * Rajendra Nayak <rnayak@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/sched.h>
  13. #include <linux/cpuidle.h>
  14. #include <linux/cpu_pm.h>
  15. #include <linux/export.h>
  16. #include <linux/clockchips.h>
  17. #include <asm/proc-fns.h>
  18. #include "common.h"
  19. #include "pm.h"
  20. #include "prm.h"
  21. #ifdef CONFIG_CPU_IDLE
  22. /* Machine specific information to be recorded in the C-state driver_data */
  23. struct omap4_idle_statedata {
  24. u32 cpu_state;
  25. u32 mpu_logic_state;
  26. u32 mpu_state;
  27. u8 valid;
  28. };
  29. static struct cpuidle_params cpuidle_params_table[] = {
  30. /* C1 - CPU0 ON + CPU1 ON + MPU ON */
  31. {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
  32. /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
  33. {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
  34. /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
  35. {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
  36. };
  37. #define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
  38. struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
  39. static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
  40. /**
  41. * omap4_enter_idle - Programs OMAP4 to enter the specified state
  42. * @dev: cpuidle device
  43. * @drv: cpuidle driver
  44. * @index: the index of state to be entered
  45. *
  46. * Called from the CPUidle framework to program the device to the
  47. * specified low power state selected by the governor.
  48. * Returns the amount of time spent in the low power state.
  49. */
  50. static int omap4_enter_idle(struct cpuidle_device *dev,
  51. struct cpuidle_driver *drv,
  52. int index)
  53. {
  54. struct omap4_idle_statedata *cx =
  55. cpuidle_get_statedata(&dev->states_usage[index]);
  56. u32 cpu1_state;
  57. int cpu_id = smp_processor_id();
  58. local_fiq_disable();
  59. /*
  60. * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
  61. * This is necessary to honour hardware recommondation
  62. * of triggeing all the possible low power modes once CPU1 is
  63. * out of coherency and in OFF mode.
  64. * Update dev->last_state so that governor stats reflects right
  65. * data.
  66. */
  67. cpu1_state = pwrdm_read_pwrst(cpu1_pd);
  68. if (cpu1_state != PWRDM_POWER_OFF) {
  69. index = drv->safe_state_index;
  70. cx = cpuidle_get_statedata(&dev->states_usage[index]);
  71. }
  72. if (index > 0)
  73. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
  74. /*
  75. * Call idle CPU PM enter notifier chain so that
  76. * VFP and per CPU interrupt context is saved.
  77. */
  78. if (cx->cpu_state == PWRDM_POWER_OFF)
  79. cpu_pm_enter();
  80. pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
  81. omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
  82. /*
  83. * Call idle CPU cluster PM enter notifier chain
  84. * to save GIC and wakeupgen context.
  85. */
  86. if ((cx->mpu_state == PWRDM_POWER_RET) &&
  87. (cx->mpu_logic_state == PWRDM_POWER_OFF))
  88. cpu_cluster_pm_enter();
  89. omap4_enter_lowpower(dev->cpu, cx->cpu_state);
  90. /*
  91. * Call idle CPU PM exit notifier chain to restore
  92. * VFP and per CPU IRQ context. Only CPU0 state is
  93. * considered since CPU1 is managed by CPU hotplug.
  94. */
  95. if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
  96. cpu_pm_exit();
  97. /*
  98. * Call idle CPU cluster PM exit notifier chain
  99. * to restore GIC and wakeupgen context.
  100. */
  101. if (omap4_mpuss_read_prev_context_state())
  102. cpu_cluster_pm_exit();
  103. if (index > 0)
  104. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
  105. local_fiq_enable();
  106. return index;
  107. }
  108. DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
  109. struct cpuidle_driver omap4_idle_driver = {
  110. .name = "omap4_idle",
  111. .owner = THIS_MODULE,
  112. .en_core_tk_irqen = 1,
  113. };
  114. static inline void _fill_cstate(struct cpuidle_driver *drv,
  115. int idx, const char *descr)
  116. {
  117. struct cpuidle_state *state = &drv->states[idx];
  118. state->exit_latency = cpuidle_params_table[idx].exit_latency;
  119. state->target_residency = cpuidle_params_table[idx].target_residency;
  120. state->flags = CPUIDLE_FLAG_TIME_VALID;
  121. state->enter = omap4_enter_idle;
  122. sprintf(state->name, "C%d", idx + 1);
  123. strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
  124. }
  125. static inline struct omap4_idle_statedata *_fill_cstate_usage(
  126. struct cpuidle_device *dev,
  127. int idx)
  128. {
  129. struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
  130. struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
  131. cx->valid = cpuidle_params_table[idx].valid;
  132. cpuidle_set_statedata(state_usage, cx);
  133. return cx;
  134. }
  135. /**
  136. * omap4_idle_init - Init routine for OMAP4 idle
  137. *
  138. * Registers the OMAP4 specific cpuidle driver to the cpuidle
  139. * framework with the valid set of states.
  140. */
  141. int __init omap4_idle_init(void)
  142. {
  143. struct omap4_idle_statedata *cx;
  144. struct cpuidle_device *dev;
  145. struct cpuidle_driver *drv = &omap4_idle_driver;
  146. unsigned int cpu_id = 0;
  147. mpu_pd = pwrdm_lookup("mpu_pwrdm");
  148. cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
  149. cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
  150. if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
  151. return -ENODEV;
  152. drv->safe_state_index = -1;
  153. dev = &per_cpu(omap4_idle_dev, cpu_id);
  154. dev->cpu = cpu_id;
  155. /* C1 - CPU0 ON + CPU1 ON + MPU ON */
  156. _fill_cstate(drv, 0, "MPUSS ON");
  157. drv->safe_state_index = 0;
  158. cx = _fill_cstate_usage(dev, 0);
  159. cx->valid = 1; /* C1 is always valid */
  160. cx->cpu_state = PWRDM_POWER_ON;
  161. cx->mpu_state = PWRDM_POWER_ON;
  162. cx->mpu_logic_state = PWRDM_POWER_RET;
  163. /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
  164. _fill_cstate(drv, 1, "MPUSS CSWR");
  165. cx = _fill_cstate_usage(dev, 1);
  166. cx->cpu_state = PWRDM_POWER_OFF;
  167. cx->mpu_state = PWRDM_POWER_RET;
  168. cx->mpu_logic_state = PWRDM_POWER_RET;
  169. /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
  170. _fill_cstate(drv, 2, "MPUSS OSWR");
  171. cx = _fill_cstate_usage(dev, 2);
  172. cx->cpu_state = PWRDM_POWER_OFF;
  173. cx->mpu_state = PWRDM_POWER_RET;
  174. cx->mpu_logic_state = PWRDM_POWER_OFF;
  175. drv->state_count = OMAP4_NUM_STATES;
  176. cpuidle_register_driver(&omap4_idle_driver);
  177. dev->state_count = OMAP4_NUM_STATES;
  178. if (cpuidle_register_device(dev)) {
  179. pr_err("%s: CPUidle register device failed\n", __func__);
  180. return -EIO;
  181. }
  182. return 0;
  183. }
  184. #else
  185. int __init omap4_idle_init(void)
  186. {
  187. return 0;
  188. }
  189. #endif /* CONFIG_CPU_IDLE */