am35xx-emac.c 3.6 KB

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  1. /*
  2. * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
  3. *
  4. * Based on mach-omap2/board-am3517evm.c
  5. * Copyright (C) 2009 Texas Instruments Incorporated
  6. * Author: Ranjith Lohithakshan <ranjithl@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
  13. * whether express or implied; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. */
  17. #include <linux/clk.h>
  18. #include <linux/davinci_emac.h>
  19. #include <linux/platform_device.h>
  20. #include <plat/irqs.h>
  21. #include <mach/am35xx.h>
  22. #include "control.h"
  23. static struct mdio_platform_data am35xx_emac_mdio_pdata;
  24. static struct resource am35xx_emac_mdio_resources[] = {
  25. DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K),
  26. };
  27. static struct platform_device am35xx_emac_mdio_device = {
  28. .name = "davinci_mdio",
  29. .id = 0,
  30. .num_resources = ARRAY_SIZE(am35xx_emac_mdio_resources),
  31. .resource = am35xx_emac_mdio_resources,
  32. .dev.platform_data = &am35xx_emac_mdio_pdata,
  33. };
  34. static void am35xx_enable_emac_int(void)
  35. {
  36. u32 regval;
  37. regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
  38. regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
  39. AM35XX_CPGMAC_C0_TX_PULSE_CLR |
  40. AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
  41. AM35XX_CPGMAC_C0_RX_THRESH_CLR);
  42. omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
  43. regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
  44. }
  45. static void am35xx_disable_emac_int(void)
  46. {
  47. u32 regval;
  48. regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
  49. regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
  50. AM35XX_CPGMAC_C0_TX_PULSE_CLR);
  51. omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
  52. regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
  53. }
  54. static struct emac_platform_data am35xx_emac_pdata = {
  55. .ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET,
  56. .ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET,
  57. .ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET,
  58. .ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE,
  59. .hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR,
  60. .version = EMAC_VERSION_2,
  61. .interrupt_enable = am35xx_enable_emac_int,
  62. .interrupt_disable = am35xx_disable_emac_int,
  63. };
  64. static struct resource am35xx_emac_resources[] = {
  65. DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000),
  66. DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ),
  67. DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ),
  68. DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ),
  69. DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ),
  70. };
  71. static struct platform_device am35xx_emac_device = {
  72. .name = "davinci_emac",
  73. .id = -1,
  74. .num_resources = ARRAY_SIZE(am35xx_emac_resources),
  75. .resource = am35xx_emac_resources,
  76. .dev = {
  77. .platform_data = &am35xx_emac_pdata,
  78. },
  79. };
  80. void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
  81. {
  82. unsigned int regval;
  83. int err;
  84. am35xx_emac_pdata.rmii_en = rmii_en;
  85. am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq;
  86. err = platform_device_register(&am35xx_emac_device);
  87. if (err) {
  88. pr_err("AM35x: failed registering EMAC device: %d\n", err);
  89. return;
  90. }
  91. err = platform_device_register(&am35xx_emac_mdio_device);
  92. if (err) {
  93. pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err);
  94. platform_device_unregister(&am35xx_emac_device);
  95. return;
  96. }
  97. regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
  98. regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
  99. omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
  100. regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
  101. }