devices-qsd8x50.c 8.3 KB

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  1. /*
  2. * Copyright (C) 2008 Google, Inc.
  3. * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  4. *
  5. * This software is licensed under the terms of the GNU General Public
  6. * License version 2, as published by the Free Software Foundation, and
  7. * may be copied, distributed, and modified under those terms.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/clkdev.h>
  18. #include <linux/dma-mapping.h>
  19. #include <mach/irqs.h>
  20. #include <mach/msm_iomap.h>
  21. #include <mach/dma.h>
  22. #include <mach/board.h>
  23. #include "devices.h"
  24. #include <asm/mach/flash.h>
  25. #include <mach/mmc.h>
  26. #include "clock-pcom.h"
  27. static struct resource resources_uart3[] = {
  28. {
  29. .start = INT_UART3,
  30. .end = INT_UART3,
  31. .flags = IORESOURCE_IRQ,
  32. },
  33. {
  34. .start = MSM_UART3_PHYS,
  35. .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
  36. .flags = IORESOURCE_MEM,
  37. .name = "uart_resource"
  38. },
  39. };
  40. struct platform_device msm_device_uart3 = {
  41. .name = "msm_serial",
  42. .id = 2,
  43. .num_resources = ARRAY_SIZE(resources_uart3),
  44. .resource = resources_uart3,
  45. };
  46. struct platform_device msm_device_smd = {
  47. .name = "msm_smd",
  48. .id = -1,
  49. };
  50. static struct resource resources_otg[] = {
  51. {
  52. .start = MSM_HSUSB_PHYS,
  53. .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
  54. .flags = IORESOURCE_MEM,
  55. },
  56. {
  57. .start = INT_USB_HS,
  58. .end = INT_USB_HS,
  59. .flags = IORESOURCE_IRQ,
  60. },
  61. };
  62. struct platform_device msm_device_otg = {
  63. .name = "msm_otg",
  64. .id = -1,
  65. .num_resources = ARRAY_SIZE(resources_otg),
  66. .resource = resources_otg,
  67. .dev = {
  68. .coherent_dma_mask = 0xffffffff,
  69. },
  70. };
  71. static struct resource resources_hsusb[] = {
  72. {
  73. .start = MSM_HSUSB_PHYS,
  74. .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
  75. .flags = IORESOURCE_MEM,
  76. },
  77. {
  78. .start = INT_USB_HS,
  79. .end = INT_USB_HS,
  80. .flags = IORESOURCE_IRQ,
  81. },
  82. };
  83. struct platform_device msm_device_hsusb = {
  84. .name = "msm_hsusb",
  85. .id = -1,
  86. .num_resources = ARRAY_SIZE(resources_hsusb),
  87. .resource = resources_hsusb,
  88. .dev = {
  89. .coherent_dma_mask = 0xffffffff,
  90. },
  91. };
  92. static u64 dma_mask = 0xffffffffULL;
  93. static struct resource resources_hsusb_host[] = {
  94. {
  95. .start = MSM_HSUSB_PHYS,
  96. .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
  97. .flags = IORESOURCE_MEM,
  98. },
  99. {
  100. .start = INT_USB_HS,
  101. .end = INT_USB_HS,
  102. .flags = IORESOURCE_IRQ,
  103. },
  104. };
  105. struct platform_device msm_device_hsusb_host = {
  106. .name = "msm_hsusb_host",
  107. .id = -1,
  108. .num_resources = ARRAY_SIZE(resources_hsusb_host),
  109. .resource = resources_hsusb_host,
  110. .dev = {
  111. .dma_mask = &dma_mask,
  112. .coherent_dma_mask = 0xffffffffULL,
  113. },
  114. };
  115. static struct resource resources_sdc1[] = {
  116. {
  117. .start = MSM_SDC1_PHYS,
  118. .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
  119. .flags = IORESOURCE_MEM,
  120. },
  121. {
  122. .start = INT_SDC1_0,
  123. .end = INT_SDC1_0,
  124. .flags = IORESOURCE_IRQ,
  125. .name = "cmd_irq",
  126. },
  127. {
  128. .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
  129. .name = "status_irq"
  130. },
  131. {
  132. .start = 8,
  133. .end = 8,
  134. .flags = IORESOURCE_DMA,
  135. },
  136. };
  137. static struct resource resources_sdc2[] = {
  138. {
  139. .start = MSM_SDC2_PHYS,
  140. .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
  141. .flags = IORESOURCE_MEM,
  142. },
  143. {
  144. .start = INT_SDC2_0,
  145. .end = INT_SDC2_0,
  146. .flags = IORESOURCE_IRQ,
  147. .name = "cmd_irq",
  148. },
  149. {
  150. .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
  151. .name = "status_irq"
  152. },
  153. {
  154. .start = 8,
  155. .end = 8,
  156. .flags = IORESOURCE_DMA,
  157. },
  158. };
  159. static struct resource resources_sdc3[] = {
  160. {
  161. .start = MSM_SDC3_PHYS,
  162. .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
  163. .flags = IORESOURCE_MEM,
  164. },
  165. {
  166. .start = INT_SDC3_0,
  167. .end = INT_SDC3_0,
  168. .flags = IORESOURCE_IRQ,
  169. .name = "cmd_irq",
  170. },
  171. {
  172. .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
  173. .name = "status_irq"
  174. },
  175. {
  176. .start = 8,
  177. .end = 8,
  178. .flags = IORESOURCE_DMA,
  179. },
  180. };
  181. static struct resource resources_sdc4[] = {
  182. {
  183. .start = MSM_SDC4_PHYS,
  184. .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
  185. .flags = IORESOURCE_MEM,
  186. },
  187. {
  188. .start = INT_SDC4_0,
  189. .end = INT_SDC4_0,
  190. .flags = IORESOURCE_IRQ,
  191. .name = "cmd_irq",
  192. },
  193. {
  194. .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
  195. .name = "status_irq"
  196. },
  197. {
  198. .start = 8,
  199. .end = 8,
  200. .flags = IORESOURCE_DMA,
  201. },
  202. };
  203. struct platform_device msm_device_sdc1 = {
  204. .name = "msm_sdcc",
  205. .id = 1,
  206. .num_resources = ARRAY_SIZE(resources_sdc1),
  207. .resource = resources_sdc1,
  208. .dev = {
  209. .coherent_dma_mask = 0xffffffff,
  210. },
  211. };
  212. struct platform_device msm_device_sdc2 = {
  213. .name = "msm_sdcc",
  214. .id = 2,
  215. .num_resources = ARRAY_SIZE(resources_sdc2),
  216. .resource = resources_sdc2,
  217. .dev = {
  218. .coherent_dma_mask = 0xffffffff,
  219. },
  220. };
  221. struct platform_device msm_device_sdc3 = {
  222. .name = "msm_sdcc",
  223. .id = 3,
  224. .num_resources = ARRAY_SIZE(resources_sdc3),
  225. .resource = resources_sdc3,
  226. .dev = {
  227. .coherent_dma_mask = 0xffffffff,
  228. },
  229. };
  230. struct platform_device msm_device_sdc4 = {
  231. .name = "msm_sdcc",
  232. .id = 4,
  233. .num_resources = ARRAY_SIZE(resources_sdc4),
  234. .resource = resources_sdc4,
  235. .dev = {
  236. .coherent_dma_mask = 0xffffffff,
  237. },
  238. };
  239. static struct platform_device *msm_sdcc_devices[] __initdata = {
  240. &msm_device_sdc1,
  241. &msm_device_sdc2,
  242. &msm_device_sdc3,
  243. &msm_device_sdc4,
  244. };
  245. int __init msm_add_sdcc(unsigned int controller,
  246. struct msm_mmc_platform_data *plat,
  247. unsigned int stat_irq, unsigned long stat_irq_flags)
  248. {
  249. struct platform_device *pdev;
  250. struct resource *res;
  251. if (controller < 1 || controller > 4)
  252. return -EINVAL;
  253. pdev = msm_sdcc_devices[controller-1];
  254. pdev->dev.platform_data = plat;
  255. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
  256. if (!res)
  257. return -EINVAL;
  258. else if (stat_irq) {
  259. res->start = res->end = stat_irq;
  260. res->flags &= ~IORESOURCE_DISABLED;
  261. res->flags |= stat_irq_flags;
  262. }
  263. return platform_device_register(pdev);
  264. }
  265. struct clk_lookup msm_clocks_8x50[] = {
  266. CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
  267. CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
  268. CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
  269. CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
  270. CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
  271. CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
  272. CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
  273. CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
  274. CLK_PCOM("i2c_clk", I2C_CLK, NULL, 0),
  275. CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
  276. CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
  277. CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
  278. CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
  279. CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
  280. CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
  281. CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
  282. CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
  283. CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0),
  284. CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
  285. CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
  286. CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
  287. CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
  288. CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
  289. CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
  290. CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
  291. CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF),
  292. CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF),
  293. CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF),
  294. CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF),
  295. CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
  296. CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
  297. CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
  298. CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
  299. CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
  300. CLK_PCOM("uart_clk", UART1_CLK, NULL, OFF),
  301. CLK_PCOM("uart_clk", UART2_CLK, NULL, 0),
  302. CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF),
  303. CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF),
  304. CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0),
  305. CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
  306. CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
  307. CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
  308. CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN),
  309. CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
  310. CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
  311. CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
  312. CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF),
  313. CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF),
  314. CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF),
  315. CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF),
  316. CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
  317. };
  318. unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);