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phyus
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linux-vybrid_public
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linux-vybrid_pu...
/
arch
/
arm
/
mach-exynos
/
include
/
mach
/
regs-pmu.h

regs-pmu.h 9.3 KB
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  1. /* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
    2. 

  2.  *
    3. 

  3.  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
    4. 

  4.  *		http://www.samsung.com
    5. 

  5.  *
    6. 

  6.  * EXYNOS4 - Power management unit definition
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11. */
    12. 

  12. 

  13. #ifndef __ASM_ARCH_REGS_PMU_H
    14. 

  14. #define __ASM_ARCH_REGS_PMU_H __FILE__
    15. 

  15. 

  16. #include <mach/map.h>
    17. 

  17. 

  18. #define S5P_PMUREG(x)				(S5P_VA_PMU + (x))
    19. 

  19. 

  20. #define S5P_CENTRAL_SEQ_CONFIGURATION		S5P_PMUREG(0x0200)
    21. 

  21. 

  22. #define S5P_CENTRAL_LOWPWR_CFG			(1 << 16)
    23. 

  23. 

  24. #define S5P_CENTRAL_SEQ_OPTION			S5P_PMUREG(0x0208)
    25. 

  25. 

  26. #define S5P_USE_STANDBY_WFI0			(1 << 16)
    27. 

  27. #define S5P_USE_STANDBY_WFI1			(1 << 17)
    28. 

  28. #define S5P_USE_STANDBYWFI_ISP_ARM		(1 << 18)
    29. 

  29. #define S5P_USE_STANDBY_WFE0			(1 << 24)
    30. 

  30. #define S5P_USE_STANDBY_WFE1			(1 << 25)
    31. 

  31. #define S5P_USE_STANDBYWFE_ISP_ARM		(1 << 26)
    32. 

  32. 

  33. #define S5P_SWRESET				S5P_PMUREG(0x0400)
    34. 

  34. #define EXYNOS_SWRESET				S5P_PMUREG(0x0400)
    35. 

  35. 

  36. #define S5P_WAKEUP_STAT				S5P_PMUREG(0x0600)
    37. 

  37. #define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)
    38. 

  38. #define S5P_WAKEUP_MASK				S5P_PMUREG(0x0608)
    39. 

  39. 

  40. #define S5P_HDMI_PHY_CONTROL			S5P_PMUREG(0x0700)
    41. 

  41. #define S5P_HDMI_PHY_ENABLE			(1 << 0)
    42. 

  42. 

  43. #define S5P_DAC_PHY_CONTROL			S5P_PMUREG(0x070C)
    44. 

  44. #define S5P_DAC_PHY_ENABLE			(1 << 0)
    45. 

  45. 

  46. #define S5P_MIPI_DPHY_CONTROL(n)		S5P_PMUREG(0x0710 + (n) * 4)
    47. 

  47. #define S5P_MIPI_DPHY_ENABLE			(1 << 0)
    48. 

  48. #define S5P_MIPI_DPHY_SRESETN			(1 << 1)
    49. 

  49. #define S5P_MIPI_DPHY_MRESETN			(1 << 2)
    50. 

  50. 

  51. #define S5P_INFORM0				S5P_PMUREG(0x0800)
    52. 

  52. #define S5P_INFORM1				S5P_PMUREG(0x0804)
    53. 

  53. #define S5P_INFORM2				S5P_PMUREG(0x0808)
    54. 

  54. #define S5P_INFORM3				S5P_PMUREG(0x080C)
    55. 

  55. #define S5P_INFORM4				S5P_PMUREG(0x0810)
    56. 

  56. #define S5P_INFORM5				S5P_PMUREG(0x0814)
    57. 

  57. #define S5P_INFORM6				S5P_PMUREG(0x0818)
    58. 

  58. #define S5P_INFORM7				S5P_PMUREG(0x081C)
    59. 

  59. 

  60. #define S5P_ARM_CORE0_LOWPWR			S5P_PMUREG(0x1000)
    61. 

  61. #define S5P_DIS_IRQ_CORE0			S5P_PMUREG(0x1004)
    62. 

  62. #define S5P_DIS_IRQ_CENTRAL0			S5P_PMUREG(0x1008)
    63. 

  63. #define S5P_ARM_CORE1_LOWPWR			S5P_PMUREG(0x1010)
    64. 

  64. #define S5P_DIS_IRQ_CORE1			S5P_PMUREG(0x1014)
    65. 

  65. #define S5P_DIS_IRQ_CENTRAL1			S5P_PMUREG(0x1018)
    66. 

  66. #define S5P_ARM_COMMON_LOWPWR			S5P_PMUREG(0x1080)
    67. 

  67. #define S5P_L2_0_LOWPWR				S5P_PMUREG(0x10C0)
    68. 

  68. #define S5P_L2_1_LOWPWR				S5P_PMUREG(0x10C4)
    69. 

  69. #define S5P_CMU_ACLKSTOP_LOWPWR			S5P_PMUREG(0x1100)
    70. 

  70. #define S5P_CMU_SCLKSTOP_LOWPWR			S5P_PMUREG(0x1104)
    71. 

  71. #define S5P_CMU_RESET_LOWPWR			S5P_PMUREG(0x110C)
    72. 

  72. #define S5P_APLL_SYSCLK_LOWPWR			S5P_PMUREG(0x1120)
    73. 

  73. #define S5P_MPLL_SYSCLK_LOWPWR			S5P_PMUREG(0x1124)
    74. 

  74. #define S5P_VPLL_SYSCLK_LOWPWR			S5P_PMUREG(0x1128)
    75. 

  75. #define S5P_EPLL_SYSCLK_LOWPWR			S5P_PMUREG(0x112C)
    76. 

  76. #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR	S5P_PMUREG(0x1138)
    77. 

  77. #define S5P_CMU_RESET_GPSALIVE_LOWPWR		S5P_PMUREG(0x113C)
    78. 

  78. #define S5P_CMU_CLKSTOP_CAM_LOWPWR		S5P_PMUREG(0x1140)
    79. 

  79. #define S5P_CMU_CLKSTOP_TV_LOWPWR		S5P_PMUREG(0x1144)
    80. 

  80. #define S5P_CMU_CLKSTOP_MFC_LOWPWR		S5P_PMUREG(0x1148)
    81. 

  81. #define S5P_CMU_CLKSTOP_G3D_LOWPWR		S5P_PMUREG(0x114C)
    82. 

  82. #define S5P_CMU_CLKSTOP_LCD0_LOWPWR		S5P_PMUREG(0x1150)
    83. 

  83. #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR		S5P_PMUREG(0x1158)
    84. 

  84. #define S5P_CMU_CLKSTOP_GPS_LOWPWR		S5P_PMUREG(0x115C)
    85. 

  85. #define S5P_CMU_RESET_CAM_LOWPWR		S5P_PMUREG(0x1160)
    86. 

  86. #define S5P_CMU_RESET_TV_LOWPWR			S5P_PMUREG(0x1164)
    87. 

  87. #define S5P_CMU_RESET_MFC_LOWPWR		S5P_PMUREG(0x1168)
    88. 

  88. #define S5P_CMU_RESET_G3D_LOWPWR		S5P_PMUREG(0x116C)
    89. 

  89. #define S5P_CMU_RESET_LCD0_LOWPWR		S5P_PMUREG(0x1170)
    90. 

  90. #define S5P_CMU_RESET_MAUDIO_LOWPWR		S5P_PMUREG(0x1178)
    91. 

  91. #define S5P_CMU_RESET_GPS_LOWPWR		S5P_PMUREG(0x117C)
    92. 

  92. #define S5P_TOP_BUS_LOWPWR			S5P_PMUREG(0x1180)
    93. 

  93. #define S5P_TOP_RETENTION_LOWPWR		S5P_PMUREG(0x1184)
    94. 

  94. #define S5P_TOP_PWR_LOWPWR			S5P_PMUREG(0x1188)
    95. 

  95. #define S5P_LOGIC_RESET_LOWPWR			S5P_PMUREG(0x11A0)
    96. 

  96. #define S5P_ONENAND_MEM_LOWPWR			S5P_PMUREG(0x11C0)
    97. 

  97. #define S5P_G2D_ACP_MEM_LOWPWR			S5P_PMUREG(0x11C8)
    98. 

  98. #define S5P_USBOTG_MEM_LOWPWR			S5P_PMUREG(0x11CC)
    99. 

  99. #define S5P_HSMMC_MEM_LOWPWR			S5P_PMUREG(0x11D0)
    100. 

  100. #define S5P_CSSYS_MEM_LOWPWR			S5P_PMUREG(0x11D4)
    101. 

  101. #define S5P_SECSS_MEM_LOWPWR			S5P_PMUREG(0x11D8)
    102. 

  102. #define S5P_PAD_RETENTION_DRAM_LOWPWR		S5P_PMUREG(0x1200)
    103. 

  103. #define S5P_PAD_RETENTION_MAUDIO_LOWPWR		S5P_PMUREG(0x1204)
    104. 

  104. #define S5P_PAD_RETENTION_GPIO_LOWPWR		S5P_PMUREG(0x1220)
    105. 

  105. #define S5P_PAD_RETENTION_UART_LOWPWR		S5P_PMUREG(0x1224)
    106. 

  106. #define S5P_PAD_RETENTION_MMCA_LOWPWR		S5P_PMUREG(0x1228)
    107. 

  107. #define S5P_PAD_RETENTION_MMCB_LOWPWR		S5P_PMUREG(0x122C)
    108. 

  108. #define S5P_PAD_RETENTION_EBIA_LOWPWR		S5P_PMUREG(0x1230)
    109. 

  109. #define S5P_PAD_RETENTION_EBIB_LOWPWR		S5P_PMUREG(0x1234)
    110. 

  110. #define S5P_PAD_RETENTION_ISOLATION_LOWPWR	S5P_PMUREG(0x1240)
    111. 

  111. #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR	S5P_PMUREG(0x1260)
    112. 

  112. #define S5P_XUSBXTI_LOWPWR			S5P_PMUREG(0x1280)
    113. 

  113. #define S5P_XXTI_LOWPWR				S5P_PMUREG(0x1284)
    114. 

  114. #define S5P_EXT_REGULATOR_LOWPWR		S5P_PMUREG(0x12C0)
    115. 

  115. #define S5P_GPIO_MODE_LOWPWR			S5P_PMUREG(0x1300)
    116. 

  116. #define S5P_GPIO_MODE_MAUDIO_LOWPWR		S5P_PMUREG(0x1340)
    117. 

  117. #define S5P_CAM_LOWPWR				S5P_PMUREG(0x1380)
    118. 

  118. #define S5P_TV_LOWPWR				S5P_PMUREG(0x1384)
    119. 

  119. #define S5P_MFC_LOWPWR				S5P_PMUREG(0x1388)
    120. 

  120. #define S5P_G3D_LOWPWR				S5P_PMUREG(0x138C)
    121. 

  121. #define S5P_LCD0_LOWPWR				S5P_PMUREG(0x1390)
    122. 

  122. #define S5P_MAUDIO_LOWPWR			S5P_PMUREG(0x1398)
    123. 

  123. #define S5P_GPS_LOWPWR				S5P_PMUREG(0x139C)
    124. 

  124. #define S5P_GPS_ALIVE_LOWPWR			S5P_PMUREG(0x13A0)
    125. 

  125. 

  126. #define S5P_ARM_CORE0_CONFIGURATION		S5P_PMUREG(0x2000)
    127. 

  127. #define S5P_ARM_CORE0_OPTION			S5P_PMUREG(0x2008)
    128. 

  128. #define S5P_ARM_CORE1_CONFIGURATION		S5P_PMUREG(0x2080)
    129. 

  129. #define S5P_ARM_CORE1_STATUS			S5P_PMUREG(0x2084)
    130. 

  130. #define S5P_ARM_CORE1_OPTION			S5P_PMUREG(0x2088)
    131. 

  131. 

  132. #define S5P_ARM_COMMON_OPTION			S5P_PMUREG(0x2408)
    133. 

  133. #define S5P_TOP_PWR_OPTION			S5P_PMUREG(0x2C48)
    134. 

  134. #define S5P_CAM_OPTION				S5P_PMUREG(0x3C08)
    135. 

  135. #define S5P_TV_OPTION				S5P_PMUREG(0x3C28)
    136. 

  136. #define S5P_MFC_OPTION				S5P_PMUREG(0x3C48)
    137. 

  137. #define S5P_G3D_OPTION				S5P_PMUREG(0x3C68)
    138. 

  138. #define S5P_LCD0_OPTION				S5P_PMUREG(0x3C88)
    139. 

  139. #define S5P_LCD1_OPTION				S5P_PMUREG(0x3CA8)
    140. 

  140. #define S5P_MAUDIO_OPTION			S5P_PMUREG(0x3CC8)
    141. 

  141. #define S5P_GPS_OPTION				S5P_PMUREG(0x3CE8)
    142. 

  142. #define S5P_GPS_ALIVE_OPTION			S5P_PMUREG(0x3D08)
    143. 

  143. 

  144. #define S5P_PAD_RET_MAUDIO_OPTION		S5P_PMUREG(0x3028)
    145. 

  145. #define S5P_PAD_RET_GPIO_OPTION			S5P_PMUREG(0x3108)
    146. 

  146. #define S5P_PAD_RET_UART_OPTION			S5P_PMUREG(0x3128)
    147. 

  147. #define S5P_PAD_RET_MMCA_OPTION			S5P_PMUREG(0x3148)
    148. 

  148. #define S5P_PAD_RET_MMCB_OPTION			S5P_PMUREG(0x3168)
    149. 

  149. #define S5P_PAD_RET_EBIA_OPTION			S5P_PMUREG(0x3188)
    150. 

  150. #define S5P_PAD_RET_EBIB_OPTION			S5P_PMUREG(0x31A8)
    151. 

  151. 

  152. #define S5P_PMU_CAM_CONF			S5P_PMUREG(0x3C00)
    153. 

  153. #define S5P_PMU_TV_CONF				S5P_PMUREG(0x3C20)
    154. 

  154. #define S5P_PMU_MFC_CONF			S5P_PMUREG(0x3C40)
    155. 

  155. #define S5P_PMU_G3D_CONF			S5P_PMUREG(0x3C60)
    156. 

  156. #define S5P_PMU_LCD0_CONF			S5P_PMUREG(0x3C80)
    157. 

  157. #define S5P_PMU_GPS_CONF			S5P_PMUREG(0x3CE0)
    158. 

  158. 

  159. #define S5P_PMU_SATA_PHY_CONTROL_EN		0x1
    160. 

  160. #define S5P_CORE_LOCAL_PWR_EN			0x3
    161. 

  161. #define S5P_INT_LOCAL_PWR_EN			0x7
    162. 

  162. 

  163. #define S5P_CHECK_SLEEP				0x00000BAD
    164. 

  164. 

  165. /* Only for EXYNOS4210 */
    166. 

  166. #define S5P_USBHOST_PHY_CONTROL		S5P_PMUREG(0x0708)
    167. 

  167. #define S5P_USBHOST_PHY_ENABLE		(1 << 0)
    168. 

  168. 

  169. #define S5P_PMU_SATA_PHY_CONTROL	S5P_PMUREG(0x0720)
    170. 

  170. 

  171. #define S5P_CMU_CLKSTOP_LCD1_LOWPWR	S5P_PMUREG(0x1154)
    172. 

  172. #define S5P_CMU_RESET_LCD1_LOWPWR	S5P_PMUREG(0x1174)
    173. 

  173. #define S5P_MODIMIF_MEM_LOWPWR		S5P_PMUREG(0x11C4)
    174. 

  174. #define S5P_PCIE_MEM_LOWPWR		S5P_PMUREG(0x11E0)
    175. 

  175. #define S5P_SATA_MEM_LOWPWR		S5P_PMUREG(0x11E4)
    176. 

  176. #define S5P_LCD1_LOWPWR			S5P_PMUREG(0x1394)
    177. 

  177. 

  178. #define S5P_PMU_LCD1_CONF		S5P_PMUREG(0x3CA0)
    179. 

  179. 

  180. /* Only for EXYNOS4212 */
    181. 

  181. #define S5P_ISP_ARM_LOWPWR			S5P_PMUREG(0x1050)
    182. 

  182. #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR	S5P_PMUREG(0x1054)
    183. 

  183. #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR	S5P_PMUREG(0x1058)
    184. 

  184. #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR		S5P_PMUREG(0x1110)
    185. 

  185. #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR		S5P_PMUREG(0x1114)
    186. 

  186. #define S5P_CMU_RESET_COREBLK_LOWPWR		S5P_PMUREG(0x111C)
    187. 

  187. #define S5P_MPLLUSER_SYSCLK_LOWPWR		S5P_PMUREG(0x1130)
    188. 

  188. #define S5P_CMU_CLKSTOP_ISP_LOWPWR		S5P_PMUREG(0x1154)
    189. 

  189. #define S5P_CMU_RESET_ISP_LOWPWR		S5P_PMUREG(0x1174)
    190. 

  190. #define S5P_TOP_BUS_COREBLK_LOWPWR		S5P_PMUREG(0x1190)
    191. 

  191. #define S5P_TOP_RETENTION_COREBLK_LOWPWR	S5P_PMUREG(0x1194)
    192. 

  192. #define S5P_TOP_PWR_COREBLK_LOWPWR		S5P_PMUREG(0x1198)
    193. 

  193. #define S5P_OSCCLK_GATE_LOWPWR			S5P_PMUREG(0x11A4)
    194. 

  194. #define S5P_LOGIC_RESET_COREBLK_LOWPWR		S5P_PMUREG(0x11B0)
    195. 

  195. #define S5P_OSCCLK_GATE_COREBLK_LOWPWR		S5P_PMUREG(0x11B4)
    196. 

  196. #define S5P_HSI_MEM_LOWPWR			S5P_PMUREG(0x11C4)
    197. 

  197. #define S5P_ROTATOR_MEM_LOWPWR			S5P_PMUREG(0x11DC)
    198. 

  198. #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR	S5P_PMUREG(0x123C)
    199. 

  199. #define S5P_PAD_ISOLATION_COREBLK_LOWPWR	S5P_PMUREG(0x1250)
    200. 

  200. #define S5P_GPIO_MODE_COREBLK_LOWPWR		S5P_PMUREG(0x1320)
    201. 

  201. #define S5P_TOP_ASB_RESET_LOWPWR		S5P_PMUREG(0x1344)
    202. 

  202. #define S5P_TOP_ASB_ISOLATION_LOWPWR		S5P_PMUREG(0x1348)
    203. 

  203. #define S5P_ISP_LOWPWR				S5P_PMUREG(0x1394)
    204. 

  204. #define S5P_DRAM_FREQ_DOWN_LOWPWR		S5P_PMUREG(0x13B0)
    205. 

  205. #define S5P_DDRPHY_DLLOFF_LOWPWR		S5P_PMUREG(0x13B4)
    206. 

  206. #define S5P_CMU_SYSCLK_ISP_LOWPWR		S5P_PMUREG(0x13B8)
    207. 

  207. #define S5P_CMU_SYSCLK_GPS_LOWPWR		S5P_PMUREG(0x13BC)
    208. 

  208. #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR		S5P_PMUREG(0x13C0)
    209. 

  209. 

  210. #define S5P_ARM_L2_0_OPTION			S5P_PMUREG(0x2608)
    211. 

  211. #define S5P_ARM_L2_1_OPTION			S5P_PMUREG(0x2628)
    212. 

  212. #define S5P_ONENAND_MEM_OPTION			S5P_PMUREG(0x2E08)
    213. 

  213. #define S5P_HSI_MEM_OPTION			S5P_PMUREG(0x2E28)
    214. 

  214. #define S5P_G2D_ACP_MEM_OPTION			S5P_PMUREG(0x2E48)
    215. 

  215. #define S5P_USBOTG_MEM_OPTION			S5P_PMUREG(0x2E68)
    216. 

  216. #define S5P_HSMMC_MEM_OPTION			S5P_PMUREG(0x2E88)
    217. 

  217. #define S5P_CSSYS_MEM_OPTION			S5P_PMUREG(0x2EA8)
    218. 

  218. #define S5P_SECSS_MEM_OPTION			S5P_PMUREG(0x2EC8)
    219. 

  219. #define S5P_ROTATOR_MEM_OPTION			S5P_PMUREG(0x2F48)
    220. 

  220. 

  221. #endif /* __ASM_ARCH_REGS_PMU_H */
    222.