dma.c 3.5 KB

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  1. /*
  2. * arch/arm/mach-ep93xx/dma.c
  3. *
  4. * Platform support code for the EP93xx dmaengine driver.
  5. *
  6. * Copyright (C) 2011 Mika Westerberg
  7. *
  8. * This work is based on the original dma-m2p implementation with
  9. * following copyrights:
  10. *
  11. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  12. * Copyright (C) 2006 Applied Data Systems
  13. * Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or (at
  18. * your option) any later version.
  19. */
  20. #include <linux/dmaengine.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/kernel.h>
  25. #include <linux/platform_device.h>
  26. #include <mach/dma.h>
  27. #include <mach/hardware.h>
  28. #include "soc.h"
  29. #define DMA_CHANNEL(_name, _base, _irq) \
  30. { .name = (_name), .base = (_base), .irq = (_irq) }
  31. /*
  32. * DMA M2P channels.
  33. *
  34. * On the EP93xx chip the following peripherals my be allocated to the 10
  35. * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
  36. *
  37. * I2S contains 3 Tx and 3 Rx DMA Channels
  38. * AAC contains 3 Tx and 3 Rx DMA Channels
  39. * UART1 contains 1 Tx and 1 Rx DMA Channels
  40. * UART2 contains 1 Tx and 1 Rx DMA Channels
  41. * UART3 contains 1 Tx and 1 Rx DMA Channels
  42. * IrDA contains 1 Tx and 1 Rx DMA Channels
  43. *
  44. * Registers are mapped statically in ep93xx_map_io().
  45. */
  46. static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
  47. DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
  48. DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
  49. DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
  50. DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
  51. DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
  52. DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
  53. DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
  54. DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
  55. DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
  56. DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
  57. };
  58. static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
  59. .channels = ep93xx_dma_m2p_channels,
  60. .num_channels = ARRAY_SIZE(ep93xx_dma_m2p_channels),
  61. };
  62. static struct platform_device ep93xx_dma_m2p_device = {
  63. .name = "ep93xx-dma-m2p",
  64. .id = -1,
  65. .dev = {
  66. .platform_data = &ep93xx_dma_m2p_data,
  67. },
  68. };
  69. /*
  70. * DMA M2M channels.
  71. *
  72. * There are 2 M2M channels which support memcpy/memset and in addition simple
  73. * hardware requests from/to SSP and IDE. We do not implement an external
  74. * hardware requests.
  75. *
  76. * Registers are mapped statically in ep93xx_map_io().
  77. */
  78. static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
  79. DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
  80. DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
  81. };
  82. static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
  83. .channels = ep93xx_dma_m2m_channels,
  84. .num_channels = ARRAY_SIZE(ep93xx_dma_m2m_channels),
  85. };
  86. static struct platform_device ep93xx_dma_m2m_device = {
  87. .name = "ep93xx-dma-m2m",
  88. .id = -1,
  89. .dev = {
  90. .platform_data = &ep93xx_dma_m2m_data,
  91. },
  92. };
  93. static int __init ep93xx_dma_init(void)
  94. {
  95. platform_device_register(&ep93xx_dma_m2p_device);
  96. platform_device_register(&ep93xx_dma_m2m_device);
  97. return 0;
  98. }
  99. arch_initcall(ep93xx_dma_init);