smp_scu.c 2.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687
  1. /*
  2. * linux/arch/arm/kernel/smp_scu.c
  3. *
  4. * Copyright (C) 2002 ARM Ltd.
  5. * All Rights Reserved
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <asm/smp_scu.h>
  14. #include <asm/cacheflush.h>
  15. #include <asm/cputype.h>
  16. #define SCU_CTRL 0x00
  17. #define SCU_CONFIG 0x04
  18. #define SCU_CPU_STATUS 0x08
  19. #define SCU_INVALIDATE 0x0c
  20. #define SCU_FPGA_REVISION 0x10
  21. #ifdef CONFIG_SMP
  22. /*
  23. * Get the number of CPU cores from the SCU configuration
  24. */
  25. unsigned int __init scu_get_core_count(void __iomem *scu_base)
  26. {
  27. unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG);
  28. return (ncores & 0x03) + 1;
  29. }
  30. /*
  31. * Enable the SCU
  32. */
  33. void scu_enable(void __iomem *scu_base)
  34. {
  35. u32 scu_ctrl;
  36. #ifdef CONFIG_ARM_ERRATA_764369
  37. /* Cortex-A9 only */
  38. if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
  39. scu_ctrl = __raw_readl(scu_base + 0x30);
  40. if (!(scu_ctrl & 1))
  41. __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
  42. }
  43. #endif
  44. scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
  45. /* already enabled? */
  46. if (scu_ctrl & 1)
  47. return;
  48. scu_ctrl |= 1;
  49. __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
  50. /*
  51. * Ensure that the data accessed by CPU0 before the SCU was
  52. * initialised is visible to the other CPUs.
  53. */
  54. flush_cache_all();
  55. }
  56. #endif
  57. /*
  58. * Set the executing CPUs power mode as defined. This will be in
  59. * preparation for it executing a WFI instruction.
  60. *
  61. * This function must be called with preemption disabled, and as it
  62. * has the side effect of disabling coherency, caches must have been
  63. * flushed. Interrupts must also have been disabled.
  64. */
  65. int scu_power_mode(void __iomem *scu_base, unsigned int mode)
  66. {
  67. unsigned int val;
  68. int cpu = smp_processor_id();
  69. if (mode > 3 || mode == 1 || cpu > 3)
  70. return -EINVAL;
  71. val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
  72. val |= mode;
  73. __raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
  74. return 0;
  75. }