timer-sp.c 4.6 KB

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  1. /*
  2. * linux/arch/arm/common/timer-sp.c
  3. *
  4. * Copyright (C) 1999 - 2003 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/clk.h>
  22. #include <linux/clocksource.h>
  23. #include <linux/clockchips.h>
  24. #include <linux/err.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/irq.h>
  27. #include <linux/io.h>
  28. #include <asm/sched_clock.h>
  29. #include <asm/hardware/arm_timer.h>
  30. static long __init sp804_get_clock_rate(const char *name)
  31. {
  32. struct clk *clk;
  33. long rate;
  34. int err;
  35. clk = clk_get_sys("sp804", name);
  36. if (IS_ERR(clk)) {
  37. pr_err("sp804: %s clock not found: %d\n", name,
  38. (int)PTR_ERR(clk));
  39. return PTR_ERR(clk);
  40. }
  41. err = clk_prepare(clk);
  42. if (err) {
  43. pr_err("sp804: %s clock failed to prepare: %d\n", name, err);
  44. clk_put(clk);
  45. return err;
  46. }
  47. err = clk_enable(clk);
  48. if (err) {
  49. pr_err("sp804: %s clock failed to enable: %d\n", name, err);
  50. clk_unprepare(clk);
  51. clk_put(clk);
  52. return err;
  53. }
  54. rate = clk_get_rate(clk);
  55. if (rate < 0) {
  56. pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate);
  57. clk_disable(clk);
  58. clk_unprepare(clk);
  59. clk_put(clk);
  60. }
  61. return rate;
  62. }
  63. static void __iomem *sched_clock_base;
  64. static u32 sp804_read(void)
  65. {
  66. return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
  67. }
  68. void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
  69. const char *name,
  70. int use_sched_clock)
  71. {
  72. long rate = sp804_get_clock_rate(name);
  73. if (rate < 0)
  74. return;
  75. /* setup timer 0 as free-running clocksource */
  76. writel(0, base + TIMER_CTRL);
  77. writel(0xffffffff, base + TIMER_LOAD);
  78. writel(0xffffffff, base + TIMER_VALUE);
  79. writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
  80. base + TIMER_CTRL);
  81. clocksource_mmio_init(base + TIMER_VALUE, name,
  82. rate, 200, 32, clocksource_mmio_readl_down);
  83. if (use_sched_clock) {
  84. sched_clock_base = base;
  85. setup_sched_clock(sp804_read, 32, rate);
  86. }
  87. }
  88. static void __iomem *clkevt_base;
  89. static unsigned long clkevt_reload;
  90. /*
  91. * IRQ handler for the timer
  92. */
  93. static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
  94. {
  95. struct clock_event_device *evt = dev_id;
  96. /* clear the interrupt */
  97. writel(1, clkevt_base + TIMER_INTCLR);
  98. evt->event_handler(evt);
  99. return IRQ_HANDLED;
  100. }
  101. static void sp804_set_mode(enum clock_event_mode mode,
  102. struct clock_event_device *evt)
  103. {
  104. unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
  105. writel(ctrl, clkevt_base + TIMER_CTRL);
  106. switch (mode) {
  107. case CLOCK_EVT_MODE_PERIODIC:
  108. writel(clkevt_reload, clkevt_base + TIMER_LOAD);
  109. ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
  110. break;
  111. case CLOCK_EVT_MODE_ONESHOT:
  112. /* period set, and timer enabled in 'next_event' hook */
  113. ctrl |= TIMER_CTRL_ONESHOT;
  114. break;
  115. case CLOCK_EVT_MODE_UNUSED:
  116. case CLOCK_EVT_MODE_SHUTDOWN:
  117. default:
  118. break;
  119. }
  120. writel(ctrl, clkevt_base + TIMER_CTRL);
  121. }
  122. static int sp804_set_next_event(unsigned long next,
  123. struct clock_event_device *evt)
  124. {
  125. unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
  126. writel(next, clkevt_base + TIMER_LOAD);
  127. writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
  128. return 0;
  129. }
  130. static struct clock_event_device sp804_clockevent = {
  131. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  132. .set_mode = sp804_set_mode,
  133. .set_next_event = sp804_set_next_event,
  134. .rating = 300,
  135. .cpumask = cpu_all_mask,
  136. };
  137. static struct irqaction sp804_timer_irq = {
  138. .name = "timer",
  139. .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  140. .handler = sp804_timer_interrupt,
  141. .dev_id = &sp804_clockevent,
  142. };
  143. void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
  144. const char *name)
  145. {
  146. struct clock_event_device *evt = &sp804_clockevent;
  147. long rate = sp804_get_clock_rate(name);
  148. if (rate < 0)
  149. return;
  150. clkevt_base = base;
  151. clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
  152. evt->name = name;
  153. evt->irq = irq;
  154. setup_irq(irq, &sp804_timer_irq);
  155. clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
  156. }