be_main.c 136 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796
  1. /**
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. static unsigned int gcrashmode = 0;
  48. static unsigned int num_hba = 0;
  49. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  50. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  51. MODULE_VERSION(BUILD_STR);
  52. MODULE_AUTHOR("Emulex Corporation");
  53. MODULE_LICENSE("GPL");
  54. module_param(be_iopoll_budget, int, 0);
  55. module_param(enable_msix, int, 0);
  56. module_param(be_max_phys_size, uint, S_IRUGO);
  57. MODULE_PARM_DESC(be_max_phys_size,
  58. "Maximum Size (In Kilobytes) of physically contiguous "
  59. "memory that can be allocated. Range is 16 - 128");
  60. #define beiscsi_disp_param(_name)\
  61. ssize_t \
  62. beiscsi_##_name##_disp(struct device *dev,\
  63. struct device_attribute *attrib, char *buf) \
  64. { \
  65. struct Scsi_Host *shost = class_to_shost(dev);\
  66. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  67. uint32_t param_val = 0; \
  68. param_val = phba->attr_##_name;\
  69. return snprintf(buf, PAGE_SIZE, "%d\n",\
  70. phba->attr_##_name);\
  71. }
  72. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  73. int \
  74. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  75. {\
  76. if (val >= _minval && val <= _maxval) {\
  77. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  78. "BA_%d : beiscsi_"#_name" updated "\
  79. "from 0x%x ==> 0x%x\n",\
  80. phba->attr_##_name, val); \
  81. phba->attr_##_name = val;\
  82. return 0;\
  83. } \
  84. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  85. "BA_%d beiscsi_"#_name" attribute "\
  86. "cannot be updated to 0x%x, "\
  87. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  88. return -EINVAL;\
  89. }
  90. #define beiscsi_store_param(_name) \
  91. ssize_t \
  92. beiscsi_##_name##_store(struct device *dev,\
  93. struct device_attribute *attr, const char *buf,\
  94. size_t count) \
  95. { \
  96. struct Scsi_Host *shost = class_to_shost(dev);\
  97. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  98. uint32_t param_val = 0;\
  99. if (!isdigit(buf[0]))\
  100. return -EINVAL;\
  101. if (sscanf(buf, "%i", &param_val) != 1)\
  102. return -EINVAL;\
  103. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  104. return strlen(buf);\
  105. else \
  106. return -EINVAL;\
  107. }
  108. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  109. int \
  110. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  111. { \
  112. if (val >= _minval && val <= _maxval) {\
  113. phba->attr_##_name = val;\
  114. return 0;\
  115. } \
  116. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  117. "BA_%d beiscsi_"#_name" attribute " \
  118. "cannot be updated to 0x%x, "\
  119. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  120. phba->attr_##_name = _defval;\
  121. return -EINVAL;\
  122. }
  123. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  124. static uint beiscsi_##_name = _defval;\
  125. module_param(beiscsi_##_name, uint, S_IRUGO);\
  126. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  127. beiscsi_disp_param(_name)\
  128. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  129. beiscsi_store_param(_name)\
  130. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  131. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  132. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  133. /*
  134. * When new log level added update the
  135. * the MAX allowed value for log_enable
  136. */
  137. BEISCSI_RW_ATTR(log_enable, 0x00,
  138. 0xFF, 0x00, "Enable logging Bit Mask\n"
  139. "\t\t\t\tInitialization Events : 0x01\n"
  140. "\t\t\t\tMailbox Events : 0x02\n"
  141. "\t\t\t\tMiscellaneous Events : 0x04\n"
  142. "\t\t\t\tError Handling : 0x08\n"
  143. "\t\t\t\tIO Path Events : 0x10\n"
  144. "\t\t\t\tConfiguration Path : 0x20\n");
  145. struct device_attribute *beiscsi_attrs[] = {
  146. &dev_attr_beiscsi_log_enable,
  147. NULL,
  148. };
  149. static char const *cqe_desc[] = {
  150. "RESERVED_DESC",
  151. "SOL_CMD_COMPLETE",
  152. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  153. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  154. "CXN_KILLED_BURST_LEN_MISMATCH",
  155. "CXN_KILLED_AHS_RCVD",
  156. "CXN_KILLED_HDR_DIGEST_ERR",
  157. "CXN_KILLED_UNKNOWN_HDR",
  158. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  159. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  160. "CXN_KILLED_RST_RCVD",
  161. "CXN_KILLED_TIMED_OUT",
  162. "CXN_KILLED_RST_SENT",
  163. "CXN_KILLED_FIN_RCVD",
  164. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  165. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  166. "CXN_KILLED_OVER_RUN_RESIDUAL",
  167. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  168. "CMD_KILLED_INVALID_STATSN_RCVD",
  169. "CMD_KILLED_INVALID_R2T_RCVD",
  170. "CMD_CXN_KILLED_LUN_INVALID",
  171. "CMD_CXN_KILLED_ICD_INVALID",
  172. "CMD_CXN_KILLED_ITT_INVALID",
  173. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  174. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  175. "CXN_INVALIDATE_NOTIFY",
  176. "CXN_INVALIDATE_INDEX_NOTIFY",
  177. "CMD_INVALIDATED_NOTIFY",
  178. "UNSOL_HDR_NOTIFY",
  179. "UNSOL_DATA_NOTIFY",
  180. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  181. "DRIVERMSG_NOTIFY",
  182. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  183. "SOL_CMD_KILLED_DIF_ERR",
  184. "CXN_KILLED_SYN_RCVD",
  185. "CXN_KILLED_IMM_DATA_RCVD"
  186. };
  187. static int beiscsi_slave_configure(struct scsi_device *sdev)
  188. {
  189. blk_queue_max_segment_size(sdev->request_queue, 65536);
  190. return 0;
  191. }
  192. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  193. {
  194. struct iscsi_cls_session *cls_session;
  195. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  196. struct beiscsi_io_task *aborted_io_task;
  197. struct iscsi_conn *conn;
  198. struct beiscsi_conn *beiscsi_conn;
  199. struct beiscsi_hba *phba;
  200. struct iscsi_session *session;
  201. struct invalidate_command_table *inv_tbl;
  202. struct be_dma_mem nonemb_cmd;
  203. unsigned int cid, tag, num_invalidate;
  204. cls_session = starget_to_session(scsi_target(sc->device));
  205. session = cls_session->dd_data;
  206. spin_lock_bh(&session->lock);
  207. if (!aborted_task || !aborted_task->sc) {
  208. /* we raced */
  209. spin_unlock_bh(&session->lock);
  210. return SUCCESS;
  211. }
  212. aborted_io_task = aborted_task->dd_data;
  213. if (!aborted_io_task->scsi_cmnd) {
  214. /* raced or invalid command */
  215. spin_unlock_bh(&session->lock);
  216. return SUCCESS;
  217. }
  218. spin_unlock_bh(&session->lock);
  219. conn = aborted_task->conn;
  220. beiscsi_conn = conn->dd_data;
  221. phba = beiscsi_conn->phba;
  222. /* invalidate iocb */
  223. cid = beiscsi_conn->beiscsi_conn_cid;
  224. inv_tbl = phba->inv_tbl;
  225. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  226. inv_tbl->cid = cid;
  227. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  228. num_invalidate = 1;
  229. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  230. sizeof(struct invalidate_commands_params_in),
  231. &nonemb_cmd.dma);
  232. if (nonemb_cmd.va == NULL) {
  233. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  234. "BM_%d : Failed to allocate memory for"
  235. "mgmt_invalidate_icds\n");
  236. return FAILED;
  237. }
  238. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  239. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  240. cid, &nonemb_cmd);
  241. if (!tag) {
  242. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  243. "BM_%d : mgmt_invalidate_icds could not be"
  244. "submitted\n");
  245. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  246. nonemb_cmd.va, nonemb_cmd.dma);
  247. return FAILED;
  248. } else {
  249. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  250. phba->ctrl.mcc_numtag[tag]);
  251. free_mcc_tag(&phba->ctrl, tag);
  252. }
  253. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  254. nonemb_cmd.va, nonemb_cmd.dma);
  255. return iscsi_eh_abort(sc);
  256. }
  257. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  258. {
  259. struct iscsi_task *abrt_task;
  260. struct beiscsi_io_task *abrt_io_task;
  261. struct iscsi_conn *conn;
  262. struct beiscsi_conn *beiscsi_conn;
  263. struct beiscsi_hba *phba;
  264. struct iscsi_session *session;
  265. struct iscsi_cls_session *cls_session;
  266. struct invalidate_command_table *inv_tbl;
  267. struct be_dma_mem nonemb_cmd;
  268. unsigned int cid, tag, i, num_invalidate;
  269. /* invalidate iocbs */
  270. cls_session = starget_to_session(scsi_target(sc->device));
  271. session = cls_session->dd_data;
  272. spin_lock_bh(&session->lock);
  273. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  274. spin_unlock_bh(&session->lock);
  275. return FAILED;
  276. }
  277. conn = session->leadconn;
  278. beiscsi_conn = conn->dd_data;
  279. phba = beiscsi_conn->phba;
  280. cid = beiscsi_conn->beiscsi_conn_cid;
  281. inv_tbl = phba->inv_tbl;
  282. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  283. num_invalidate = 0;
  284. for (i = 0; i < conn->session->cmds_max; i++) {
  285. abrt_task = conn->session->cmds[i];
  286. abrt_io_task = abrt_task->dd_data;
  287. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  288. continue;
  289. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  290. continue;
  291. inv_tbl->cid = cid;
  292. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  293. num_invalidate++;
  294. inv_tbl++;
  295. }
  296. spin_unlock_bh(&session->lock);
  297. inv_tbl = phba->inv_tbl;
  298. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  299. sizeof(struct invalidate_commands_params_in),
  300. &nonemb_cmd.dma);
  301. if (nonemb_cmd.va == NULL) {
  302. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  303. "BM_%d : Failed to allocate memory for"
  304. "mgmt_invalidate_icds\n");
  305. return FAILED;
  306. }
  307. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  308. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  309. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  310. cid, &nonemb_cmd);
  311. if (!tag) {
  312. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  313. "BM_%d : mgmt_invalidate_icds could not be"
  314. " submitted\n");
  315. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  316. nonemb_cmd.va, nonemb_cmd.dma);
  317. return FAILED;
  318. } else {
  319. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  320. phba->ctrl.mcc_numtag[tag]);
  321. free_mcc_tag(&phba->ctrl, tag);
  322. }
  323. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  324. nonemb_cmd.va, nonemb_cmd.dma);
  325. return iscsi_eh_device_reset(sc);
  326. }
  327. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  328. {
  329. struct beiscsi_hba *phba = data;
  330. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  331. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  332. char *str = buf;
  333. int rc;
  334. switch (type) {
  335. case ISCSI_BOOT_TGT_NAME:
  336. rc = sprintf(buf, "%.*s\n",
  337. (int)strlen(boot_sess->target_name),
  338. (char *)&boot_sess->target_name);
  339. break;
  340. case ISCSI_BOOT_TGT_IP_ADDR:
  341. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  342. rc = sprintf(buf, "%pI4\n",
  343. (char *)&boot_conn->dest_ipaddr.addr);
  344. else
  345. rc = sprintf(str, "%pI6\n",
  346. (char *)&boot_conn->dest_ipaddr.addr);
  347. break;
  348. case ISCSI_BOOT_TGT_PORT:
  349. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  350. break;
  351. case ISCSI_BOOT_TGT_CHAP_NAME:
  352. rc = sprintf(str, "%.*s\n",
  353. boot_conn->negotiated_login_options.auth_data.chap.
  354. target_chap_name_length,
  355. (char *)&boot_conn->negotiated_login_options.
  356. auth_data.chap.target_chap_name);
  357. break;
  358. case ISCSI_BOOT_TGT_CHAP_SECRET:
  359. rc = sprintf(str, "%.*s\n",
  360. boot_conn->negotiated_login_options.auth_data.chap.
  361. target_secret_length,
  362. (char *)&boot_conn->negotiated_login_options.
  363. auth_data.chap.target_secret);
  364. break;
  365. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  366. rc = sprintf(str, "%.*s\n",
  367. boot_conn->negotiated_login_options.auth_data.chap.
  368. intr_chap_name_length,
  369. (char *)&boot_conn->negotiated_login_options.
  370. auth_data.chap.intr_chap_name);
  371. break;
  372. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  373. rc = sprintf(str, "%.*s\n",
  374. boot_conn->negotiated_login_options.auth_data.chap.
  375. intr_secret_length,
  376. (char *)&boot_conn->negotiated_login_options.
  377. auth_data.chap.intr_secret);
  378. break;
  379. case ISCSI_BOOT_TGT_FLAGS:
  380. rc = sprintf(str, "2\n");
  381. break;
  382. case ISCSI_BOOT_TGT_NIC_ASSOC:
  383. rc = sprintf(str, "0\n");
  384. break;
  385. default:
  386. rc = -ENOSYS;
  387. break;
  388. }
  389. return rc;
  390. }
  391. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  392. {
  393. struct beiscsi_hba *phba = data;
  394. char *str = buf;
  395. int rc;
  396. switch (type) {
  397. case ISCSI_BOOT_INI_INITIATOR_NAME:
  398. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  399. break;
  400. default:
  401. rc = -ENOSYS;
  402. break;
  403. }
  404. return rc;
  405. }
  406. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  407. {
  408. struct beiscsi_hba *phba = data;
  409. char *str = buf;
  410. int rc;
  411. switch (type) {
  412. case ISCSI_BOOT_ETH_FLAGS:
  413. rc = sprintf(str, "2\n");
  414. break;
  415. case ISCSI_BOOT_ETH_INDEX:
  416. rc = sprintf(str, "0\n");
  417. break;
  418. case ISCSI_BOOT_ETH_MAC:
  419. rc = beiscsi_get_macaddr(str, phba);
  420. break;
  421. default:
  422. rc = -ENOSYS;
  423. break;
  424. }
  425. return rc;
  426. }
  427. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  428. {
  429. umode_t rc;
  430. switch (type) {
  431. case ISCSI_BOOT_TGT_NAME:
  432. case ISCSI_BOOT_TGT_IP_ADDR:
  433. case ISCSI_BOOT_TGT_PORT:
  434. case ISCSI_BOOT_TGT_CHAP_NAME:
  435. case ISCSI_BOOT_TGT_CHAP_SECRET:
  436. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  437. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  438. case ISCSI_BOOT_TGT_NIC_ASSOC:
  439. case ISCSI_BOOT_TGT_FLAGS:
  440. rc = S_IRUGO;
  441. break;
  442. default:
  443. rc = 0;
  444. break;
  445. }
  446. return rc;
  447. }
  448. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  449. {
  450. umode_t rc;
  451. switch (type) {
  452. case ISCSI_BOOT_INI_INITIATOR_NAME:
  453. rc = S_IRUGO;
  454. break;
  455. default:
  456. rc = 0;
  457. break;
  458. }
  459. return rc;
  460. }
  461. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  462. {
  463. umode_t rc;
  464. switch (type) {
  465. case ISCSI_BOOT_ETH_FLAGS:
  466. case ISCSI_BOOT_ETH_MAC:
  467. case ISCSI_BOOT_ETH_INDEX:
  468. rc = S_IRUGO;
  469. break;
  470. default:
  471. rc = 0;
  472. break;
  473. }
  474. return rc;
  475. }
  476. /*------------------- PCI Driver operations and data ----------------- */
  477. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  478. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  479. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  480. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  481. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  482. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  483. { 0 }
  484. };
  485. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  486. static struct scsi_host_template beiscsi_sht = {
  487. .module = THIS_MODULE,
  488. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  489. .proc_name = DRV_NAME,
  490. .queuecommand = iscsi_queuecommand,
  491. .change_queue_depth = iscsi_change_queue_depth,
  492. .slave_configure = beiscsi_slave_configure,
  493. .target_alloc = iscsi_target_alloc,
  494. .eh_abort_handler = beiscsi_eh_abort,
  495. .eh_device_reset_handler = beiscsi_eh_device_reset,
  496. .eh_target_reset_handler = iscsi_eh_session_reset,
  497. .shost_attrs = beiscsi_attrs,
  498. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  499. .can_queue = BE2_IO_DEPTH,
  500. .this_id = -1,
  501. .max_sectors = BEISCSI_MAX_SECTORS,
  502. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  503. .use_clustering = ENABLE_CLUSTERING,
  504. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  505. };
  506. static struct scsi_transport_template *beiscsi_scsi_transport;
  507. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  508. {
  509. struct beiscsi_hba *phba;
  510. struct Scsi_Host *shost;
  511. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  512. if (!shost) {
  513. dev_err(&pcidev->dev,
  514. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  515. return NULL;
  516. }
  517. shost->dma_boundary = pcidev->dma_mask;
  518. shost->max_id = BE2_MAX_SESSIONS;
  519. shost->max_channel = 0;
  520. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  521. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  522. shost->transportt = beiscsi_scsi_transport;
  523. phba = iscsi_host_priv(shost);
  524. memset(phba, 0, sizeof(*phba));
  525. phba->shost = shost;
  526. phba->pcidev = pci_dev_get(pcidev);
  527. pci_set_drvdata(pcidev, phba);
  528. phba->interface_handle = 0xFFFFFFFF;
  529. if (iscsi_host_add(shost, &phba->pcidev->dev))
  530. goto free_devices;
  531. return phba;
  532. free_devices:
  533. pci_dev_put(phba->pcidev);
  534. iscsi_host_free(phba->shost);
  535. return NULL;
  536. }
  537. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  538. {
  539. if (phba->csr_va) {
  540. iounmap(phba->csr_va);
  541. phba->csr_va = NULL;
  542. }
  543. if (phba->db_va) {
  544. iounmap(phba->db_va);
  545. phba->db_va = NULL;
  546. }
  547. if (phba->pci_va) {
  548. iounmap(phba->pci_va);
  549. phba->pci_va = NULL;
  550. }
  551. }
  552. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  553. struct pci_dev *pcidev)
  554. {
  555. u8 __iomem *addr;
  556. int pcicfg_reg;
  557. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  558. pci_resource_len(pcidev, 2));
  559. if (addr == NULL)
  560. return -ENOMEM;
  561. phba->ctrl.csr = addr;
  562. phba->csr_va = addr;
  563. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  564. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  565. if (addr == NULL)
  566. goto pci_map_err;
  567. phba->ctrl.db = addr;
  568. phba->db_va = addr;
  569. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  570. if (phba->generation == BE_GEN2)
  571. pcicfg_reg = 1;
  572. else
  573. pcicfg_reg = 0;
  574. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  575. pci_resource_len(pcidev, pcicfg_reg));
  576. if (addr == NULL)
  577. goto pci_map_err;
  578. phba->ctrl.pcicfg = addr;
  579. phba->pci_va = addr;
  580. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  581. return 0;
  582. pci_map_err:
  583. beiscsi_unmap_pci_function(phba);
  584. return -ENOMEM;
  585. }
  586. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  587. {
  588. int ret;
  589. ret = pci_enable_device(pcidev);
  590. if (ret) {
  591. dev_err(&pcidev->dev,
  592. "beiscsi_enable_pci - enable device failed\n");
  593. return ret;
  594. }
  595. pci_set_master(pcidev);
  596. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  597. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  598. if (ret) {
  599. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  600. pci_disable_device(pcidev);
  601. return ret;
  602. }
  603. }
  604. return 0;
  605. }
  606. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  607. {
  608. struct be_ctrl_info *ctrl = &phba->ctrl;
  609. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  610. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  611. int status = 0;
  612. ctrl->pdev = pdev;
  613. status = beiscsi_map_pci_bars(phba, pdev);
  614. if (status)
  615. return status;
  616. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  617. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  618. mbox_mem_alloc->size,
  619. &mbox_mem_alloc->dma);
  620. if (!mbox_mem_alloc->va) {
  621. beiscsi_unmap_pci_function(phba);
  622. return -ENOMEM;
  623. }
  624. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  625. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  626. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  627. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  628. spin_lock_init(&ctrl->mbox_lock);
  629. spin_lock_init(&phba->ctrl.mcc_lock);
  630. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  631. return status;
  632. }
  633. static void beiscsi_get_params(struct beiscsi_hba *phba)
  634. {
  635. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  636. - (phba->fw_config.iscsi_cid_count
  637. + BE2_TMFS
  638. + BE2_NOPOUT_REQ));
  639. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  640. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  641. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  642. phba->params.num_sge_per_io = BE2_SGE;
  643. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  644. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  645. phba->params.eq_timer = 64;
  646. phba->params.num_eq_entries =
  647. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  648. + BE2_TMFS) / 512) + 1) * 512;
  649. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  650. ? 1024 : phba->params.num_eq_entries;
  651. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  652. "BM_%d : phba->params.num_eq_entries=%d\n",
  653. phba->params.num_eq_entries);
  654. phba->params.num_cq_entries =
  655. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  656. + BE2_TMFS) / 512) + 1) * 512;
  657. phba->params.wrbs_per_cxn = 256;
  658. }
  659. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  660. unsigned int id, unsigned int clr_interrupt,
  661. unsigned int num_processed,
  662. unsigned char rearm, unsigned char event)
  663. {
  664. u32 val = 0;
  665. val |= id & DB_EQ_RING_ID_MASK;
  666. if (rearm)
  667. val |= 1 << DB_EQ_REARM_SHIFT;
  668. if (clr_interrupt)
  669. val |= 1 << DB_EQ_CLR_SHIFT;
  670. if (event)
  671. val |= 1 << DB_EQ_EVNT_SHIFT;
  672. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  673. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  674. }
  675. /**
  676. * be_isr_mcc - The isr routine of the driver.
  677. * @irq: Not used
  678. * @dev_id: Pointer to host adapter structure
  679. */
  680. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  681. {
  682. struct beiscsi_hba *phba;
  683. struct be_eq_entry *eqe = NULL;
  684. struct be_queue_info *eq;
  685. struct be_queue_info *mcc;
  686. unsigned int num_eq_processed;
  687. struct be_eq_obj *pbe_eq;
  688. unsigned long flags;
  689. pbe_eq = dev_id;
  690. eq = &pbe_eq->q;
  691. phba = pbe_eq->phba;
  692. mcc = &phba->ctrl.mcc_obj.cq;
  693. eqe = queue_tail_node(eq);
  694. num_eq_processed = 0;
  695. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  696. & EQE_VALID_MASK) {
  697. if (((eqe->dw[offsetof(struct amap_eq_entry,
  698. resource_id) / 32] &
  699. EQE_RESID_MASK) >> 16) == mcc->id) {
  700. spin_lock_irqsave(&phba->isr_lock, flags);
  701. phba->todo_mcc_cq = 1;
  702. spin_unlock_irqrestore(&phba->isr_lock, flags);
  703. }
  704. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  705. queue_tail_inc(eq);
  706. eqe = queue_tail_node(eq);
  707. num_eq_processed++;
  708. }
  709. if (phba->todo_mcc_cq)
  710. queue_work(phba->wq, &phba->work_cqs);
  711. if (num_eq_processed)
  712. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  713. return IRQ_HANDLED;
  714. }
  715. /**
  716. * be_isr_msix - The isr routine of the driver.
  717. * @irq: Not used
  718. * @dev_id: Pointer to host adapter structure
  719. */
  720. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  721. {
  722. struct beiscsi_hba *phba;
  723. struct be_eq_entry *eqe = NULL;
  724. struct be_queue_info *eq;
  725. struct be_queue_info *cq;
  726. unsigned int num_eq_processed;
  727. struct be_eq_obj *pbe_eq;
  728. unsigned long flags;
  729. pbe_eq = dev_id;
  730. eq = &pbe_eq->q;
  731. cq = pbe_eq->cq;
  732. eqe = queue_tail_node(eq);
  733. phba = pbe_eq->phba;
  734. num_eq_processed = 0;
  735. if (blk_iopoll_enabled) {
  736. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  737. & EQE_VALID_MASK) {
  738. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  739. blk_iopoll_sched(&pbe_eq->iopoll);
  740. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  741. queue_tail_inc(eq);
  742. eqe = queue_tail_node(eq);
  743. num_eq_processed++;
  744. }
  745. if (num_eq_processed)
  746. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  747. return IRQ_HANDLED;
  748. } else {
  749. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  750. & EQE_VALID_MASK) {
  751. spin_lock_irqsave(&phba->isr_lock, flags);
  752. phba->todo_cq = 1;
  753. spin_unlock_irqrestore(&phba->isr_lock, flags);
  754. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  755. queue_tail_inc(eq);
  756. eqe = queue_tail_node(eq);
  757. num_eq_processed++;
  758. }
  759. if (phba->todo_cq)
  760. queue_work(phba->wq, &phba->work_cqs);
  761. if (num_eq_processed)
  762. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  763. return IRQ_HANDLED;
  764. }
  765. }
  766. /**
  767. * be_isr - The isr routine of the driver.
  768. * @irq: Not used
  769. * @dev_id: Pointer to host adapter structure
  770. */
  771. static irqreturn_t be_isr(int irq, void *dev_id)
  772. {
  773. struct beiscsi_hba *phba;
  774. struct hwi_controller *phwi_ctrlr;
  775. struct hwi_context_memory *phwi_context;
  776. struct be_eq_entry *eqe = NULL;
  777. struct be_queue_info *eq;
  778. struct be_queue_info *cq;
  779. struct be_queue_info *mcc;
  780. unsigned long flags, index;
  781. unsigned int num_mcceq_processed, num_ioeq_processed;
  782. struct be_ctrl_info *ctrl;
  783. struct be_eq_obj *pbe_eq;
  784. int isr;
  785. phba = dev_id;
  786. ctrl = &phba->ctrl;
  787. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  788. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  789. if (!isr)
  790. return IRQ_NONE;
  791. phwi_ctrlr = phba->phwi_ctrlr;
  792. phwi_context = phwi_ctrlr->phwi_ctxt;
  793. pbe_eq = &phwi_context->be_eq[0];
  794. eq = &phwi_context->be_eq[0].q;
  795. mcc = &phba->ctrl.mcc_obj.cq;
  796. index = 0;
  797. eqe = queue_tail_node(eq);
  798. num_ioeq_processed = 0;
  799. num_mcceq_processed = 0;
  800. if (blk_iopoll_enabled) {
  801. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  802. & EQE_VALID_MASK) {
  803. if (((eqe->dw[offsetof(struct amap_eq_entry,
  804. resource_id) / 32] &
  805. EQE_RESID_MASK) >> 16) == mcc->id) {
  806. spin_lock_irqsave(&phba->isr_lock, flags);
  807. phba->todo_mcc_cq = 1;
  808. spin_unlock_irqrestore(&phba->isr_lock, flags);
  809. num_mcceq_processed++;
  810. } else {
  811. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  812. blk_iopoll_sched(&pbe_eq->iopoll);
  813. num_ioeq_processed++;
  814. }
  815. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  816. queue_tail_inc(eq);
  817. eqe = queue_tail_node(eq);
  818. }
  819. if (num_ioeq_processed || num_mcceq_processed) {
  820. if (phba->todo_mcc_cq)
  821. queue_work(phba->wq, &phba->work_cqs);
  822. if ((num_mcceq_processed) && (!num_ioeq_processed))
  823. hwi_ring_eq_db(phba, eq->id, 0,
  824. (num_ioeq_processed +
  825. num_mcceq_processed) , 1, 1);
  826. else
  827. hwi_ring_eq_db(phba, eq->id, 0,
  828. (num_ioeq_processed +
  829. num_mcceq_processed), 0, 1);
  830. return IRQ_HANDLED;
  831. } else
  832. return IRQ_NONE;
  833. } else {
  834. cq = &phwi_context->be_cq[0];
  835. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  836. & EQE_VALID_MASK) {
  837. if (((eqe->dw[offsetof(struct amap_eq_entry,
  838. resource_id) / 32] &
  839. EQE_RESID_MASK) >> 16) != cq->id) {
  840. spin_lock_irqsave(&phba->isr_lock, flags);
  841. phba->todo_mcc_cq = 1;
  842. spin_unlock_irqrestore(&phba->isr_lock, flags);
  843. } else {
  844. spin_lock_irqsave(&phba->isr_lock, flags);
  845. phba->todo_cq = 1;
  846. spin_unlock_irqrestore(&phba->isr_lock, flags);
  847. }
  848. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  849. queue_tail_inc(eq);
  850. eqe = queue_tail_node(eq);
  851. num_ioeq_processed++;
  852. }
  853. if (phba->todo_cq || phba->todo_mcc_cq)
  854. queue_work(phba->wq, &phba->work_cqs);
  855. if (num_ioeq_processed) {
  856. hwi_ring_eq_db(phba, eq->id, 0,
  857. num_ioeq_processed, 1, 1);
  858. return IRQ_HANDLED;
  859. } else
  860. return IRQ_NONE;
  861. }
  862. }
  863. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  864. {
  865. struct pci_dev *pcidev = phba->pcidev;
  866. struct hwi_controller *phwi_ctrlr;
  867. struct hwi_context_memory *phwi_context;
  868. int ret, msix_vec, i, j;
  869. phwi_ctrlr = phba->phwi_ctrlr;
  870. phwi_context = phwi_ctrlr->phwi_ctxt;
  871. if (phba->msix_enabled) {
  872. for (i = 0; i < phba->num_cpus; i++) {
  873. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  874. GFP_KERNEL);
  875. if (!phba->msi_name[i]) {
  876. ret = -ENOMEM;
  877. goto free_msix_irqs;
  878. }
  879. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  880. phba->shost->host_no, i);
  881. msix_vec = phba->msix_entries[i].vector;
  882. ret = request_irq(msix_vec, be_isr_msix, 0,
  883. phba->msi_name[i],
  884. &phwi_context->be_eq[i]);
  885. if (ret) {
  886. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  887. "BM_%d : beiscsi_init_irqs-Failed to"
  888. "register msix for i = %d\n",
  889. i);
  890. kfree(phba->msi_name[i]);
  891. goto free_msix_irqs;
  892. }
  893. }
  894. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  895. if (!phba->msi_name[i]) {
  896. ret = -ENOMEM;
  897. goto free_msix_irqs;
  898. }
  899. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  900. phba->shost->host_no);
  901. msix_vec = phba->msix_entries[i].vector;
  902. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  903. &phwi_context->be_eq[i]);
  904. if (ret) {
  905. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  906. "BM_%d : beiscsi_init_irqs-"
  907. "Failed to register beiscsi_msix_mcc\n");
  908. kfree(phba->msi_name[i]);
  909. goto free_msix_irqs;
  910. }
  911. } else {
  912. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  913. "beiscsi", phba);
  914. if (ret) {
  915. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  916. "BM_%d : beiscsi_init_irqs-"
  917. "Failed to register irq\\n");
  918. return ret;
  919. }
  920. }
  921. return 0;
  922. free_msix_irqs:
  923. for (j = i - 1; j >= 0; j--) {
  924. kfree(phba->msi_name[j]);
  925. msix_vec = phba->msix_entries[j].vector;
  926. free_irq(msix_vec, &phwi_context->be_eq[j]);
  927. }
  928. return ret;
  929. }
  930. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  931. unsigned int id, unsigned int num_processed,
  932. unsigned char rearm, unsigned char event)
  933. {
  934. u32 val = 0;
  935. val |= id & DB_CQ_RING_ID_MASK;
  936. if (rearm)
  937. val |= 1 << DB_CQ_REARM_SHIFT;
  938. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  939. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  940. }
  941. static unsigned int
  942. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  943. struct beiscsi_hba *phba,
  944. unsigned short cid,
  945. struct pdu_base *ppdu,
  946. unsigned long pdu_len,
  947. void *pbuffer, unsigned long buf_len)
  948. {
  949. struct iscsi_conn *conn = beiscsi_conn->conn;
  950. struct iscsi_session *session = conn->session;
  951. struct iscsi_task *task;
  952. struct beiscsi_io_task *io_task;
  953. struct iscsi_hdr *login_hdr;
  954. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  955. PDUBASE_OPCODE_MASK) {
  956. case ISCSI_OP_NOOP_IN:
  957. pbuffer = NULL;
  958. buf_len = 0;
  959. break;
  960. case ISCSI_OP_ASYNC_EVENT:
  961. break;
  962. case ISCSI_OP_REJECT:
  963. WARN_ON(!pbuffer);
  964. WARN_ON(!(buf_len == 48));
  965. beiscsi_log(phba, KERN_ERR,
  966. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  967. "BM_%d : In ISCSI_OP_REJECT\n");
  968. break;
  969. case ISCSI_OP_LOGIN_RSP:
  970. case ISCSI_OP_TEXT_RSP:
  971. task = conn->login_task;
  972. io_task = task->dd_data;
  973. login_hdr = (struct iscsi_hdr *)ppdu;
  974. login_hdr->itt = io_task->libiscsi_itt;
  975. break;
  976. default:
  977. beiscsi_log(phba, KERN_WARNING,
  978. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  979. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  980. (ppdu->
  981. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  982. & PDUBASE_OPCODE_MASK));
  983. return 1;
  984. }
  985. spin_lock_bh(&session->lock);
  986. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  987. spin_unlock_bh(&session->lock);
  988. return 0;
  989. }
  990. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  991. {
  992. struct sgl_handle *psgl_handle;
  993. if (phba->io_sgl_hndl_avbl) {
  994. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  995. "BM_%d : In alloc_io_sgl_handle,"
  996. " io_sgl_alloc_index=%d\n",
  997. phba->io_sgl_alloc_index);
  998. psgl_handle = phba->io_sgl_hndl_base[phba->
  999. io_sgl_alloc_index];
  1000. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  1001. phba->io_sgl_hndl_avbl--;
  1002. if (phba->io_sgl_alloc_index == (phba->params.
  1003. ios_per_ctrl - 1))
  1004. phba->io_sgl_alloc_index = 0;
  1005. else
  1006. phba->io_sgl_alloc_index++;
  1007. } else
  1008. psgl_handle = NULL;
  1009. return psgl_handle;
  1010. }
  1011. static void
  1012. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1013. {
  1014. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1015. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1016. phba->io_sgl_free_index);
  1017. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1018. /*
  1019. * this can happen if clean_task is called on a task that
  1020. * failed in xmit_task or alloc_pdu.
  1021. */
  1022. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1023. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1024. "value there=%p\n", phba->io_sgl_free_index,
  1025. phba->io_sgl_hndl_base
  1026. [phba->io_sgl_free_index]);
  1027. return;
  1028. }
  1029. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1030. phba->io_sgl_hndl_avbl++;
  1031. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1032. phba->io_sgl_free_index = 0;
  1033. else
  1034. phba->io_sgl_free_index++;
  1035. }
  1036. /**
  1037. * alloc_wrb_handle - To allocate a wrb handle
  1038. * @phba: The hba pointer
  1039. * @cid: The cid to use for allocation
  1040. *
  1041. * This happens under session_lock until submission to chip
  1042. */
  1043. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1044. {
  1045. struct hwi_wrb_context *pwrb_context;
  1046. struct hwi_controller *phwi_ctrlr;
  1047. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1048. phwi_ctrlr = phba->phwi_ctrlr;
  1049. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  1050. if (pwrb_context->wrb_handles_available >= 2) {
  1051. pwrb_handle = pwrb_context->pwrb_handle_base[
  1052. pwrb_context->alloc_index];
  1053. pwrb_context->wrb_handles_available--;
  1054. if (pwrb_context->alloc_index ==
  1055. (phba->params.wrbs_per_cxn - 1))
  1056. pwrb_context->alloc_index = 0;
  1057. else
  1058. pwrb_context->alloc_index++;
  1059. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1060. pwrb_context->alloc_index];
  1061. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1062. } else
  1063. pwrb_handle = NULL;
  1064. return pwrb_handle;
  1065. }
  1066. /**
  1067. * free_wrb_handle - To free the wrb handle back to pool
  1068. * @phba: The hba pointer
  1069. * @pwrb_context: The context to free from
  1070. * @pwrb_handle: The wrb_handle to free
  1071. *
  1072. * This happens under session_lock until submission to chip
  1073. */
  1074. static void
  1075. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1076. struct wrb_handle *pwrb_handle)
  1077. {
  1078. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1079. pwrb_context->wrb_handles_available++;
  1080. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1081. pwrb_context->free_index = 0;
  1082. else
  1083. pwrb_context->free_index++;
  1084. beiscsi_log(phba, KERN_INFO,
  1085. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1086. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1087. "wrb_handles_available=%d\n",
  1088. pwrb_handle, pwrb_context->free_index,
  1089. pwrb_context->wrb_handles_available);
  1090. }
  1091. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1092. {
  1093. struct sgl_handle *psgl_handle;
  1094. if (phba->eh_sgl_hndl_avbl) {
  1095. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1096. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1097. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1098. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1099. phba->eh_sgl_alloc_index,
  1100. phba->eh_sgl_alloc_index);
  1101. phba->eh_sgl_hndl_avbl--;
  1102. if (phba->eh_sgl_alloc_index ==
  1103. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1104. 1))
  1105. phba->eh_sgl_alloc_index = 0;
  1106. else
  1107. phba->eh_sgl_alloc_index++;
  1108. } else
  1109. psgl_handle = NULL;
  1110. return psgl_handle;
  1111. }
  1112. void
  1113. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1114. {
  1115. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1116. "BM_%d : In free_mgmt_sgl_handle,"
  1117. "eh_sgl_free_index=%d\n",
  1118. phba->eh_sgl_free_index);
  1119. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1120. /*
  1121. * this can happen if clean_task is called on a task that
  1122. * failed in xmit_task or alloc_pdu.
  1123. */
  1124. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1125. "BM_%d : Double Free in eh SGL ,"
  1126. "eh_sgl_free_index=%d\n",
  1127. phba->eh_sgl_free_index);
  1128. return;
  1129. }
  1130. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1131. phba->eh_sgl_hndl_avbl++;
  1132. if (phba->eh_sgl_free_index ==
  1133. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1134. phba->eh_sgl_free_index = 0;
  1135. else
  1136. phba->eh_sgl_free_index++;
  1137. }
  1138. static void
  1139. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1140. struct iscsi_task *task, struct sol_cqe *psol)
  1141. {
  1142. struct beiscsi_io_task *io_task = task->dd_data;
  1143. struct be_status_bhs *sts_bhs =
  1144. (struct be_status_bhs *)io_task->cmd_bhs;
  1145. struct iscsi_conn *conn = beiscsi_conn->conn;
  1146. unsigned char *sense;
  1147. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1148. u8 rsp, status, flags;
  1149. exp_cmdsn = (psol->
  1150. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1151. & SOL_EXP_CMD_SN_MASK);
  1152. max_cmdsn = ((psol->
  1153. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1154. & SOL_EXP_CMD_SN_MASK) +
  1155. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1156. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1157. rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
  1158. & SOL_RESP_MASK) >> 16);
  1159. status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
  1160. & SOL_STS_MASK) >> 8);
  1161. flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1162. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1163. if (!task->sc) {
  1164. if (io_task->scsi_cmnd)
  1165. scsi_dma_unmap(io_task->scsi_cmnd);
  1166. return;
  1167. }
  1168. task->sc->result = (DID_OK << 16) | status;
  1169. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1170. task->sc->result = DID_ERROR << 16;
  1171. goto unmap;
  1172. }
  1173. /* bidi not initially supported */
  1174. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1175. resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
  1176. 32] & SOL_RES_CNT_MASK);
  1177. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1178. task->sc->result = DID_ERROR << 16;
  1179. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1180. scsi_set_resid(task->sc, resid);
  1181. if (!status && (scsi_bufflen(task->sc) - resid <
  1182. task->sc->underflow))
  1183. task->sc->result = DID_ERROR << 16;
  1184. }
  1185. }
  1186. if (status == SAM_STAT_CHECK_CONDITION) {
  1187. u16 sense_len;
  1188. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1189. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1190. sense_len = be16_to_cpu(*slen);
  1191. memcpy(task->sc->sense_buffer, sense,
  1192. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1193. }
  1194. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
  1195. if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1196. & SOL_RES_CNT_MASK)
  1197. conn->rxdata_octets += (psol->
  1198. dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1199. & SOL_RES_CNT_MASK);
  1200. }
  1201. unmap:
  1202. scsi_dma_unmap(io_task->scsi_cmnd);
  1203. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1204. }
  1205. static void
  1206. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1207. struct iscsi_task *task, struct sol_cqe *psol)
  1208. {
  1209. struct iscsi_logout_rsp *hdr;
  1210. struct beiscsi_io_task *io_task = task->dd_data;
  1211. struct iscsi_conn *conn = beiscsi_conn->conn;
  1212. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1213. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1214. hdr->t2wait = 5;
  1215. hdr->t2retain = 0;
  1216. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1217. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1218. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1219. 32] & SOL_RESP_MASK);
  1220. hdr->exp_cmdsn = cpu_to_be32(psol->
  1221. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1222. & SOL_EXP_CMD_SN_MASK);
  1223. hdr->max_cmdsn = be32_to_cpu((psol->
  1224. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1225. & SOL_EXP_CMD_SN_MASK) +
  1226. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1227. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1228. hdr->dlength[0] = 0;
  1229. hdr->dlength[1] = 0;
  1230. hdr->dlength[2] = 0;
  1231. hdr->hlength = 0;
  1232. hdr->itt = io_task->libiscsi_itt;
  1233. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1234. }
  1235. static void
  1236. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1237. struct iscsi_task *task, struct sol_cqe *psol)
  1238. {
  1239. struct iscsi_tm_rsp *hdr;
  1240. struct iscsi_conn *conn = beiscsi_conn->conn;
  1241. struct beiscsi_io_task *io_task = task->dd_data;
  1242. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1243. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1244. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1245. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1246. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1247. 32] & SOL_RESP_MASK);
  1248. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1249. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1250. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1251. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1252. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1253. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1254. hdr->itt = io_task->libiscsi_itt;
  1255. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1256. }
  1257. static void
  1258. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1259. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1260. {
  1261. struct hwi_wrb_context *pwrb_context;
  1262. struct wrb_handle *pwrb_handle = NULL;
  1263. struct hwi_controller *phwi_ctrlr;
  1264. struct iscsi_task *task;
  1265. struct beiscsi_io_task *io_task;
  1266. struct iscsi_conn *conn = beiscsi_conn->conn;
  1267. struct iscsi_session *session = conn->session;
  1268. phwi_ctrlr = phba->phwi_ctrlr;
  1269. pwrb_context = &phwi_ctrlr->wrb_context[((psol->
  1270. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1271. SOL_CID_MASK) >> 6) -
  1272. phba->fw_config.iscsi_cid_start];
  1273. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1274. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1275. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1276. task = pwrb_handle->pio_handle;
  1277. io_task = task->dd_data;
  1278. spin_lock_bh(&phba->mgmt_sgl_lock);
  1279. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1280. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1281. spin_lock_bh(&session->lock);
  1282. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1283. spin_unlock_bh(&session->lock);
  1284. }
  1285. static void
  1286. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1287. struct iscsi_task *task, struct sol_cqe *psol)
  1288. {
  1289. struct iscsi_nopin *hdr;
  1290. struct iscsi_conn *conn = beiscsi_conn->conn;
  1291. struct beiscsi_io_task *io_task = task->dd_data;
  1292. hdr = (struct iscsi_nopin *)task->hdr;
  1293. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1294. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1295. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1296. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1297. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1298. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1299. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1300. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1301. hdr->opcode = ISCSI_OP_NOOP_IN;
  1302. hdr->itt = io_task->libiscsi_itt;
  1303. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1304. }
  1305. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1306. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1307. {
  1308. struct hwi_wrb_context *pwrb_context;
  1309. struct wrb_handle *pwrb_handle;
  1310. struct iscsi_wrb *pwrb = NULL;
  1311. struct hwi_controller *phwi_ctrlr;
  1312. struct iscsi_task *task;
  1313. unsigned int type;
  1314. struct iscsi_conn *conn = beiscsi_conn->conn;
  1315. struct iscsi_session *session = conn->session;
  1316. phwi_ctrlr = phba->phwi_ctrlr;
  1317. pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
  1318. (struct amap_sol_cqe, cid) / 32]
  1319. & SOL_CID_MASK) >> 6) -
  1320. phba->fw_config.iscsi_cid_start];
  1321. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1322. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1323. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1324. task = pwrb_handle->pio_handle;
  1325. pwrb = pwrb_handle->pwrb;
  1326. type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
  1327. WRB_TYPE_MASK) >> 28;
  1328. spin_lock_bh(&session->lock);
  1329. switch (type) {
  1330. case HWH_TYPE_IO:
  1331. case HWH_TYPE_IO_RD:
  1332. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1333. ISCSI_OP_NOOP_OUT)
  1334. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1335. else
  1336. be_complete_io(beiscsi_conn, task, psol);
  1337. break;
  1338. case HWH_TYPE_LOGOUT:
  1339. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1340. be_complete_logout(beiscsi_conn, task, psol);
  1341. else
  1342. be_complete_tmf(beiscsi_conn, task, psol);
  1343. break;
  1344. case HWH_TYPE_LOGIN:
  1345. beiscsi_log(phba, KERN_ERR,
  1346. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1347. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1348. " hwi_complete_cmd- Solicited path\n");
  1349. break;
  1350. case HWH_TYPE_NOP:
  1351. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1352. break;
  1353. default:
  1354. beiscsi_log(phba, KERN_WARNING,
  1355. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1356. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1357. "wrb_index 0x%x CID 0x%x\n", type,
  1358. ((psol->dw[offsetof(struct amap_iscsi_wrb,
  1359. type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
  1360. ((psol->dw[offsetof(struct amap_sol_cqe,
  1361. cid) / 32] & SOL_CID_MASK) >> 6));
  1362. break;
  1363. }
  1364. spin_unlock_bh(&session->lock);
  1365. }
  1366. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1367. *pasync_ctx, unsigned int is_header,
  1368. unsigned int host_write_ptr)
  1369. {
  1370. if (is_header)
  1371. return &pasync_ctx->async_entry[host_write_ptr].
  1372. header_busy_list;
  1373. else
  1374. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1375. }
  1376. static struct async_pdu_handle *
  1377. hwi_get_async_handle(struct beiscsi_hba *phba,
  1378. struct beiscsi_conn *beiscsi_conn,
  1379. struct hwi_async_pdu_context *pasync_ctx,
  1380. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1381. {
  1382. struct be_bus_address phys_addr;
  1383. struct list_head *pbusy_list;
  1384. struct async_pdu_handle *pasync_handle = NULL;
  1385. unsigned char is_header = 0;
  1386. phys_addr.u.a32.address_lo =
  1387. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
  1388. ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1389. & PDUCQE_DPL_MASK) >> 16);
  1390. phys_addr.u.a32.address_hi =
  1391. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
  1392. phys_addr.u.a64.address =
  1393. *((unsigned long long *)(&phys_addr.u.a64.address));
  1394. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1395. & PDUCQE_CODE_MASK) {
  1396. case UNSOL_HDR_NOTIFY:
  1397. is_header = 1;
  1398. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
  1399. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1400. index) / 32] & PDUCQE_INDEX_MASK));
  1401. break;
  1402. case UNSOL_DATA_NOTIFY:
  1403. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
  1404. dw[offsetof(struct amap_i_t_dpdu_cqe,
  1405. index) / 32] & PDUCQE_INDEX_MASK));
  1406. break;
  1407. default:
  1408. pbusy_list = NULL;
  1409. beiscsi_log(phba, KERN_WARNING,
  1410. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1411. "BM_%d : Unexpected code=%d\n",
  1412. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1413. code) / 32] & PDUCQE_CODE_MASK);
  1414. return NULL;
  1415. }
  1416. WARN_ON(list_empty(pbusy_list));
  1417. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1418. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1419. break;
  1420. }
  1421. WARN_ON(!pasync_handle);
  1422. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1423. phba->fw_config.iscsi_cid_start;
  1424. pasync_handle->is_header = is_header;
  1425. pasync_handle->buffer_len = ((pdpdu_cqe->
  1426. dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1427. & PDUCQE_DPL_MASK) >> 16);
  1428. *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1429. index) / 32] & PDUCQE_INDEX_MASK);
  1430. return pasync_handle;
  1431. }
  1432. static unsigned int
  1433. hwi_update_async_writables(struct beiscsi_hba *phba,
  1434. struct hwi_async_pdu_context *pasync_ctx,
  1435. unsigned int is_header, unsigned int cq_index)
  1436. {
  1437. struct list_head *pbusy_list;
  1438. struct async_pdu_handle *pasync_handle;
  1439. unsigned int num_entries, writables = 0;
  1440. unsigned int *pep_read_ptr, *pwritables;
  1441. num_entries = pasync_ctx->num_entries;
  1442. if (is_header) {
  1443. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1444. pwritables = &pasync_ctx->async_header.writables;
  1445. } else {
  1446. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1447. pwritables = &pasync_ctx->async_data.writables;
  1448. }
  1449. while ((*pep_read_ptr) != cq_index) {
  1450. (*pep_read_ptr)++;
  1451. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1452. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1453. *pep_read_ptr);
  1454. if (writables == 0)
  1455. WARN_ON(list_empty(pbusy_list));
  1456. if (!list_empty(pbusy_list)) {
  1457. pasync_handle = list_entry(pbusy_list->next,
  1458. struct async_pdu_handle,
  1459. link);
  1460. WARN_ON(!pasync_handle);
  1461. pasync_handle->consumed = 1;
  1462. }
  1463. writables++;
  1464. }
  1465. if (!writables) {
  1466. beiscsi_log(phba, KERN_ERR,
  1467. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1468. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1469. cq_index);
  1470. WARN_ON(1);
  1471. }
  1472. *pwritables = *pwritables + writables;
  1473. return 0;
  1474. }
  1475. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1476. unsigned int cri)
  1477. {
  1478. struct hwi_controller *phwi_ctrlr;
  1479. struct hwi_async_pdu_context *pasync_ctx;
  1480. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1481. struct list_head *plist;
  1482. phwi_ctrlr = phba->phwi_ctrlr;
  1483. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1484. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1485. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1486. list_del(&pasync_handle->link);
  1487. if (pasync_handle->is_header) {
  1488. list_add_tail(&pasync_handle->link,
  1489. &pasync_ctx->async_header.free_list);
  1490. pasync_ctx->async_header.free_entries++;
  1491. } else {
  1492. list_add_tail(&pasync_handle->link,
  1493. &pasync_ctx->async_data.free_list);
  1494. pasync_ctx->async_data.free_entries++;
  1495. }
  1496. }
  1497. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1498. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1499. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1500. }
  1501. static struct phys_addr *
  1502. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1503. unsigned int is_header, unsigned int host_write_ptr)
  1504. {
  1505. struct phys_addr *pasync_sge = NULL;
  1506. if (is_header)
  1507. pasync_sge = pasync_ctx->async_header.ring_base;
  1508. else
  1509. pasync_sge = pasync_ctx->async_data.ring_base;
  1510. return pasync_sge + host_write_ptr;
  1511. }
  1512. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1513. unsigned int is_header)
  1514. {
  1515. struct hwi_controller *phwi_ctrlr;
  1516. struct hwi_async_pdu_context *pasync_ctx;
  1517. struct async_pdu_handle *pasync_handle;
  1518. struct list_head *pfree_link, *pbusy_list;
  1519. struct phys_addr *pasync_sge;
  1520. unsigned int ring_id, num_entries;
  1521. unsigned int host_write_num;
  1522. unsigned int writables;
  1523. unsigned int i = 0;
  1524. u32 doorbell = 0;
  1525. phwi_ctrlr = phba->phwi_ctrlr;
  1526. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1527. num_entries = pasync_ctx->num_entries;
  1528. if (is_header) {
  1529. writables = min(pasync_ctx->async_header.writables,
  1530. pasync_ctx->async_header.free_entries);
  1531. pfree_link = pasync_ctx->async_header.free_list.next;
  1532. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1533. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1534. } else {
  1535. writables = min(pasync_ctx->async_data.writables,
  1536. pasync_ctx->async_data.free_entries);
  1537. pfree_link = pasync_ctx->async_data.free_list.next;
  1538. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1539. ring_id = phwi_ctrlr->default_pdu_data.id;
  1540. }
  1541. writables = (writables / 8) * 8;
  1542. if (writables) {
  1543. for (i = 0; i < writables; i++) {
  1544. pbusy_list =
  1545. hwi_get_async_busy_list(pasync_ctx, is_header,
  1546. host_write_num);
  1547. pasync_handle =
  1548. list_entry(pfree_link, struct async_pdu_handle,
  1549. link);
  1550. WARN_ON(!pasync_handle);
  1551. pasync_handle->consumed = 0;
  1552. pfree_link = pfree_link->next;
  1553. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1554. is_header, host_write_num);
  1555. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1556. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1557. list_move(&pasync_handle->link, pbusy_list);
  1558. host_write_num++;
  1559. host_write_num = host_write_num % num_entries;
  1560. }
  1561. if (is_header) {
  1562. pasync_ctx->async_header.host_write_ptr =
  1563. host_write_num;
  1564. pasync_ctx->async_header.free_entries -= writables;
  1565. pasync_ctx->async_header.writables -= writables;
  1566. pasync_ctx->async_header.busy_entries += writables;
  1567. } else {
  1568. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1569. pasync_ctx->async_data.free_entries -= writables;
  1570. pasync_ctx->async_data.writables -= writables;
  1571. pasync_ctx->async_data.busy_entries += writables;
  1572. }
  1573. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1574. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1575. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1576. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1577. << DB_DEF_PDU_CQPROC_SHIFT;
  1578. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1579. }
  1580. }
  1581. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1582. struct beiscsi_conn *beiscsi_conn,
  1583. struct i_t_dpdu_cqe *pdpdu_cqe)
  1584. {
  1585. struct hwi_controller *phwi_ctrlr;
  1586. struct hwi_async_pdu_context *pasync_ctx;
  1587. struct async_pdu_handle *pasync_handle = NULL;
  1588. unsigned int cq_index = -1;
  1589. phwi_ctrlr = phba->phwi_ctrlr;
  1590. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1591. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1592. pdpdu_cqe, &cq_index);
  1593. BUG_ON(pasync_handle->is_header != 0);
  1594. if (pasync_handle->consumed == 0)
  1595. hwi_update_async_writables(phba, pasync_ctx,
  1596. pasync_handle->is_header, cq_index);
  1597. hwi_free_async_msg(phba, pasync_handle->cri);
  1598. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1599. }
  1600. static unsigned int
  1601. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1602. struct beiscsi_hba *phba,
  1603. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1604. {
  1605. struct list_head *plist;
  1606. struct async_pdu_handle *pasync_handle;
  1607. void *phdr = NULL;
  1608. unsigned int hdr_len = 0, buf_len = 0;
  1609. unsigned int status, index = 0, offset = 0;
  1610. void *pfirst_buffer = NULL;
  1611. unsigned int num_buf = 0;
  1612. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1613. list_for_each_entry(pasync_handle, plist, link) {
  1614. if (index == 0) {
  1615. phdr = pasync_handle->pbuffer;
  1616. hdr_len = pasync_handle->buffer_len;
  1617. } else {
  1618. buf_len = pasync_handle->buffer_len;
  1619. if (!num_buf) {
  1620. pfirst_buffer = pasync_handle->pbuffer;
  1621. num_buf++;
  1622. }
  1623. memcpy(pfirst_buffer + offset,
  1624. pasync_handle->pbuffer, buf_len);
  1625. offset += buf_len;
  1626. }
  1627. index++;
  1628. }
  1629. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1630. (beiscsi_conn->beiscsi_conn_cid -
  1631. phba->fw_config.iscsi_cid_start),
  1632. phdr, hdr_len, pfirst_buffer,
  1633. offset);
  1634. hwi_free_async_msg(phba, cri);
  1635. return 0;
  1636. }
  1637. static unsigned int
  1638. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1639. struct beiscsi_hba *phba,
  1640. struct async_pdu_handle *pasync_handle)
  1641. {
  1642. struct hwi_async_pdu_context *pasync_ctx;
  1643. struct hwi_controller *phwi_ctrlr;
  1644. unsigned int bytes_needed = 0, status = 0;
  1645. unsigned short cri = pasync_handle->cri;
  1646. struct pdu_base *ppdu;
  1647. phwi_ctrlr = phba->phwi_ctrlr;
  1648. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1649. list_del(&pasync_handle->link);
  1650. if (pasync_handle->is_header) {
  1651. pasync_ctx->async_header.busy_entries--;
  1652. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1653. hwi_free_async_msg(phba, cri);
  1654. BUG();
  1655. }
  1656. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1657. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1658. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1659. (unsigned short)pasync_handle->buffer_len;
  1660. list_add_tail(&pasync_handle->link,
  1661. &pasync_ctx->async_entry[cri].wait_queue.list);
  1662. ppdu = pasync_handle->pbuffer;
  1663. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1664. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1665. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1666. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1667. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1668. if (status == 0) {
  1669. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1670. bytes_needed;
  1671. if (bytes_needed == 0)
  1672. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1673. pasync_ctx, cri);
  1674. }
  1675. } else {
  1676. pasync_ctx->async_data.busy_entries--;
  1677. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1678. list_add_tail(&pasync_handle->link,
  1679. &pasync_ctx->async_entry[cri].wait_queue.
  1680. list);
  1681. pasync_ctx->async_entry[cri].wait_queue.
  1682. bytes_received +=
  1683. (unsigned short)pasync_handle->buffer_len;
  1684. if (pasync_ctx->async_entry[cri].wait_queue.
  1685. bytes_received >=
  1686. pasync_ctx->async_entry[cri].wait_queue.
  1687. bytes_needed)
  1688. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1689. pasync_ctx, cri);
  1690. }
  1691. }
  1692. return status;
  1693. }
  1694. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1695. struct beiscsi_hba *phba,
  1696. struct i_t_dpdu_cqe *pdpdu_cqe)
  1697. {
  1698. struct hwi_controller *phwi_ctrlr;
  1699. struct hwi_async_pdu_context *pasync_ctx;
  1700. struct async_pdu_handle *pasync_handle = NULL;
  1701. unsigned int cq_index = -1;
  1702. phwi_ctrlr = phba->phwi_ctrlr;
  1703. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1704. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1705. pdpdu_cqe, &cq_index);
  1706. if (pasync_handle->consumed == 0)
  1707. hwi_update_async_writables(phba, pasync_ctx,
  1708. pasync_handle->is_header, cq_index);
  1709. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1710. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1711. }
  1712. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1713. {
  1714. struct be_queue_info *mcc_cq;
  1715. struct be_mcc_compl *mcc_compl;
  1716. unsigned int num_processed = 0;
  1717. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1718. mcc_compl = queue_tail_node(mcc_cq);
  1719. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1720. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1721. if (num_processed >= 32) {
  1722. hwi_ring_cq_db(phba, mcc_cq->id,
  1723. num_processed, 0, 0);
  1724. num_processed = 0;
  1725. }
  1726. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1727. /* Interpret flags as an async trailer */
  1728. if (is_link_state_evt(mcc_compl->flags))
  1729. /* Interpret compl as a async link evt */
  1730. beiscsi_async_link_state_process(phba,
  1731. (struct be_async_event_link_state *) mcc_compl);
  1732. else
  1733. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1734. "BM_%d : Unsupported Async Event, flags"
  1735. " = 0x%08x\n",
  1736. mcc_compl->flags);
  1737. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1738. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1739. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1740. }
  1741. mcc_compl->flags = 0;
  1742. queue_tail_inc(mcc_cq);
  1743. mcc_compl = queue_tail_node(mcc_cq);
  1744. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1745. num_processed++;
  1746. }
  1747. if (num_processed > 0)
  1748. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1749. }
  1750. /**
  1751. * beiscsi_process_cq()- Process the Completion Queue
  1752. * @pbe_eq: Event Q on which the Completion has come
  1753. *
  1754. * return
  1755. * Number of Completion Entries processed.
  1756. **/
  1757. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1758. {
  1759. struct be_queue_info *cq;
  1760. struct sol_cqe *sol;
  1761. struct dmsg_cqe *dmsg;
  1762. unsigned int num_processed = 0;
  1763. unsigned int tot_nump = 0;
  1764. unsigned short code = 0, cid = 0;
  1765. struct beiscsi_conn *beiscsi_conn;
  1766. struct beiscsi_endpoint *beiscsi_ep;
  1767. struct iscsi_endpoint *ep;
  1768. struct beiscsi_hba *phba;
  1769. cq = pbe_eq->cq;
  1770. sol = queue_tail_node(cq);
  1771. phba = pbe_eq->phba;
  1772. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1773. CQE_VALID_MASK) {
  1774. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1775. cid = ((sol->dw[offsetof(struct amap_sol_cqe, cid)/32] &
  1776. CQE_CID_MASK) >> 6);
  1777. code = (sol->dw[offsetof(struct amap_sol_cqe, code)/32] &
  1778. CQE_CODE_MASK);
  1779. ep = phba->ep_array[cid - phba->fw_config.iscsi_cid_start];
  1780. beiscsi_ep = ep->dd_data;
  1781. beiscsi_conn = beiscsi_ep->conn;
  1782. if (num_processed >= 32) {
  1783. hwi_ring_cq_db(phba, cq->id,
  1784. num_processed, 0, 0);
  1785. tot_nump += num_processed;
  1786. num_processed = 0;
  1787. }
  1788. switch (code) {
  1789. case SOL_CMD_COMPLETE:
  1790. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1791. break;
  1792. case DRIVERMSG_NOTIFY:
  1793. beiscsi_log(phba, KERN_INFO,
  1794. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1795. "BM_%d : Received %s[%d] on CID : %d\n",
  1796. cqe_desc[code], code, cid);
  1797. dmsg = (struct dmsg_cqe *)sol;
  1798. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1799. break;
  1800. case UNSOL_HDR_NOTIFY:
  1801. beiscsi_log(phba, KERN_INFO,
  1802. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1803. "BM_%d : Received %s[%d] on CID : %d\n",
  1804. cqe_desc[code], code, cid);
  1805. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1806. (struct i_t_dpdu_cqe *)sol);
  1807. break;
  1808. case UNSOL_DATA_NOTIFY:
  1809. beiscsi_log(phba, KERN_INFO,
  1810. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1811. "BM_%d : Received %s[%d] on CID : %d\n",
  1812. cqe_desc[code], code, cid);
  1813. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1814. (struct i_t_dpdu_cqe *)sol);
  1815. break;
  1816. case CXN_INVALIDATE_INDEX_NOTIFY:
  1817. case CMD_INVALIDATED_NOTIFY:
  1818. case CXN_INVALIDATE_NOTIFY:
  1819. beiscsi_log(phba, KERN_ERR,
  1820. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1821. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1822. cqe_desc[code], code, cid);
  1823. break;
  1824. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1825. case CMD_KILLED_INVALID_STATSN_RCVD:
  1826. case CMD_KILLED_INVALID_R2T_RCVD:
  1827. case CMD_CXN_KILLED_LUN_INVALID:
  1828. case CMD_CXN_KILLED_ICD_INVALID:
  1829. case CMD_CXN_KILLED_ITT_INVALID:
  1830. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1831. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1832. beiscsi_log(phba, KERN_ERR,
  1833. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1834. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1835. cqe_desc[code], code, cid);
  1836. break;
  1837. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1838. beiscsi_log(phba, KERN_ERR,
  1839. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1840. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1841. cqe_desc[code], code, cid);
  1842. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1843. (struct i_t_dpdu_cqe *) sol);
  1844. break;
  1845. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1846. case CXN_KILLED_BURST_LEN_MISMATCH:
  1847. case CXN_KILLED_AHS_RCVD:
  1848. case CXN_KILLED_HDR_DIGEST_ERR:
  1849. case CXN_KILLED_UNKNOWN_HDR:
  1850. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1851. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1852. case CXN_KILLED_TIMED_OUT:
  1853. case CXN_KILLED_FIN_RCVD:
  1854. case CXN_KILLED_RST_SENT:
  1855. case CXN_KILLED_RST_RCVD:
  1856. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1857. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1858. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1859. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1860. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1861. beiscsi_log(phba, KERN_ERR,
  1862. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1863. "BM_%d : Event %s[%d] received on CID : %d\n",
  1864. cqe_desc[code], code, cid);
  1865. if (beiscsi_conn)
  1866. iscsi_conn_failure(beiscsi_conn->conn,
  1867. ISCSI_ERR_CONN_FAILED);
  1868. break;
  1869. default:
  1870. beiscsi_log(phba, KERN_ERR,
  1871. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1872. "BM_%d : Invalid CQE Event Received Code : %d"
  1873. "CID 0x%x...\n",
  1874. code, cid);
  1875. break;
  1876. }
  1877. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1878. queue_tail_inc(cq);
  1879. sol = queue_tail_node(cq);
  1880. num_processed++;
  1881. }
  1882. if (num_processed > 0) {
  1883. tot_nump += num_processed;
  1884. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1885. }
  1886. return tot_nump;
  1887. }
  1888. void beiscsi_process_all_cqs(struct work_struct *work)
  1889. {
  1890. unsigned long flags;
  1891. struct hwi_controller *phwi_ctrlr;
  1892. struct hwi_context_memory *phwi_context;
  1893. struct be_eq_obj *pbe_eq;
  1894. struct beiscsi_hba *phba =
  1895. container_of(work, struct beiscsi_hba, work_cqs);
  1896. phwi_ctrlr = phba->phwi_ctrlr;
  1897. phwi_context = phwi_ctrlr->phwi_ctxt;
  1898. if (phba->msix_enabled)
  1899. pbe_eq = &phwi_context->be_eq[phba->num_cpus];
  1900. else
  1901. pbe_eq = &phwi_context->be_eq[0];
  1902. if (phba->todo_mcc_cq) {
  1903. spin_lock_irqsave(&phba->isr_lock, flags);
  1904. phba->todo_mcc_cq = 0;
  1905. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1906. beiscsi_process_mcc_isr(phba);
  1907. }
  1908. if (phba->todo_cq) {
  1909. spin_lock_irqsave(&phba->isr_lock, flags);
  1910. phba->todo_cq = 0;
  1911. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1912. beiscsi_process_cq(pbe_eq);
  1913. }
  1914. }
  1915. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1916. {
  1917. static unsigned int ret;
  1918. struct beiscsi_hba *phba;
  1919. struct be_eq_obj *pbe_eq;
  1920. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1921. ret = beiscsi_process_cq(pbe_eq);
  1922. if (ret < budget) {
  1923. phba = pbe_eq->phba;
  1924. blk_iopoll_complete(iop);
  1925. beiscsi_log(phba, KERN_INFO,
  1926. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1927. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1928. pbe_eq->q.id);
  1929. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1930. }
  1931. return ret;
  1932. }
  1933. static void
  1934. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1935. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1936. {
  1937. struct iscsi_sge *psgl;
  1938. unsigned int sg_len, index;
  1939. unsigned int sge_len = 0;
  1940. unsigned long long addr;
  1941. struct scatterlist *l_sg;
  1942. unsigned int offset;
  1943. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1944. io_task->bhs_pa.u.a32.address_lo);
  1945. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1946. io_task->bhs_pa.u.a32.address_hi);
  1947. l_sg = sg;
  1948. for (index = 0; (index < num_sg) && (index < 2); index++,
  1949. sg = sg_next(sg)) {
  1950. if (index == 0) {
  1951. sg_len = sg_dma_len(sg);
  1952. addr = (u64) sg_dma_address(sg);
  1953. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1954. ((u32)(addr & 0xFFFFFFFF)));
  1955. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1956. ((u32)(addr >> 32)));
  1957. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1958. sg_len);
  1959. sge_len = sg_len;
  1960. } else {
  1961. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  1962. pwrb, sge_len);
  1963. sg_len = sg_dma_len(sg);
  1964. addr = (u64) sg_dma_address(sg);
  1965. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  1966. ((u32)(addr & 0xFFFFFFFF)));
  1967. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  1968. ((u32)(addr >> 32)));
  1969. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  1970. sg_len);
  1971. }
  1972. }
  1973. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1974. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  1975. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  1976. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1977. io_task->bhs_pa.u.a32.address_hi);
  1978. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1979. io_task->bhs_pa.u.a32.address_lo);
  1980. if (num_sg == 1) {
  1981. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1982. 1);
  1983. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1984. 0);
  1985. } else if (num_sg == 2) {
  1986. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1987. 0);
  1988. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1989. 1);
  1990. } else {
  1991. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1992. 0);
  1993. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1994. 0);
  1995. }
  1996. sg = l_sg;
  1997. psgl++;
  1998. psgl++;
  1999. offset = 0;
  2000. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2001. sg_len = sg_dma_len(sg);
  2002. addr = (u64) sg_dma_address(sg);
  2003. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2004. (addr & 0xFFFFFFFF));
  2005. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2006. (addr >> 32));
  2007. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2008. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2009. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2010. offset += sg_len;
  2011. }
  2012. psgl--;
  2013. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2014. }
  2015. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2016. {
  2017. struct iscsi_sge *psgl;
  2018. unsigned long long addr;
  2019. struct beiscsi_io_task *io_task = task->dd_data;
  2020. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2021. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2022. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2023. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2024. io_task->bhs_pa.u.a32.address_lo);
  2025. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2026. io_task->bhs_pa.u.a32.address_hi);
  2027. if (task->data) {
  2028. if (task->data_count) {
  2029. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  2030. addr = (u64) pci_map_single(phba->pcidev,
  2031. task->data,
  2032. task->data_count, 1);
  2033. } else {
  2034. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2035. addr = 0;
  2036. }
  2037. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2038. ((u32)(addr & 0xFFFFFFFF)));
  2039. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2040. ((u32)(addr >> 32)));
  2041. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2042. task->data_count);
  2043. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2044. } else {
  2045. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2046. addr = 0;
  2047. }
  2048. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2049. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2050. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2051. io_task->bhs_pa.u.a32.address_hi);
  2052. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2053. io_task->bhs_pa.u.a32.address_lo);
  2054. if (task->data) {
  2055. psgl++;
  2056. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2057. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2058. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2059. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2060. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2061. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2062. psgl++;
  2063. if (task->data) {
  2064. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2065. ((u32)(addr & 0xFFFFFFFF)));
  2066. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2067. ((u32)(addr >> 32)));
  2068. }
  2069. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2070. }
  2071. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2072. }
  2073. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2074. {
  2075. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2076. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2077. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2078. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2079. sizeof(struct sol_cqe));
  2080. num_async_pdu_buf_pages =
  2081. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2082. phba->params.defpdu_hdr_sz);
  2083. num_async_pdu_buf_sgl_pages =
  2084. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2085. sizeof(struct phys_addr));
  2086. num_async_pdu_data_pages =
  2087. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2088. phba->params.defpdu_data_sz);
  2089. num_async_pdu_data_sgl_pages =
  2090. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2091. sizeof(struct phys_addr));
  2092. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2093. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2094. BE_ISCSI_PDU_HEADER_SIZE;
  2095. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2096. sizeof(struct hwi_context_memory);
  2097. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2098. * (phba->params.wrbs_per_cxn)
  2099. * phba->params.cxns_per_ctrl;
  2100. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2101. (phba->params.wrbs_per_cxn);
  2102. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2103. phba->params.cxns_per_ctrl);
  2104. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2105. phba->params.icds_per_ctrl;
  2106. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2107. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2108. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2109. num_async_pdu_buf_pages * PAGE_SIZE;
  2110. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2111. num_async_pdu_data_pages * PAGE_SIZE;
  2112. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2113. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2114. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2115. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2116. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2117. phba->params.asyncpdus_per_ctrl *
  2118. sizeof(struct async_pdu_handle);
  2119. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2120. phba->params.asyncpdus_per_ctrl *
  2121. sizeof(struct async_pdu_handle);
  2122. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2123. sizeof(struct hwi_async_pdu_context) +
  2124. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2125. }
  2126. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2127. {
  2128. struct be_mem_descriptor *mem_descr;
  2129. dma_addr_t bus_add;
  2130. struct mem_array *mem_arr, *mem_arr_orig;
  2131. unsigned int i, j, alloc_size, curr_alloc_size;
  2132. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2133. if (!phba->phwi_ctrlr)
  2134. return -ENOMEM;
  2135. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2136. GFP_KERNEL);
  2137. if (!phba->init_mem) {
  2138. kfree(phba->phwi_ctrlr);
  2139. return -ENOMEM;
  2140. }
  2141. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2142. GFP_KERNEL);
  2143. if (!mem_arr_orig) {
  2144. kfree(phba->init_mem);
  2145. kfree(phba->phwi_ctrlr);
  2146. return -ENOMEM;
  2147. }
  2148. mem_descr = phba->init_mem;
  2149. for (i = 0; i < SE_MEM_MAX; i++) {
  2150. j = 0;
  2151. mem_arr = mem_arr_orig;
  2152. alloc_size = phba->mem_req[i];
  2153. memset(mem_arr, 0, sizeof(struct mem_array) *
  2154. BEISCSI_MAX_FRAGS_INIT);
  2155. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2156. do {
  2157. mem_arr->virtual_address = pci_alloc_consistent(
  2158. phba->pcidev,
  2159. curr_alloc_size,
  2160. &bus_add);
  2161. if (!mem_arr->virtual_address) {
  2162. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2163. goto free_mem;
  2164. if (curr_alloc_size -
  2165. rounddown_pow_of_two(curr_alloc_size))
  2166. curr_alloc_size = rounddown_pow_of_two
  2167. (curr_alloc_size);
  2168. else
  2169. curr_alloc_size = curr_alloc_size / 2;
  2170. } else {
  2171. mem_arr->bus_address.u.
  2172. a64.address = (__u64) bus_add;
  2173. mem_arr->size = curr_alloc_size;
  2174. alloc_size -= curr_alloc_size;
  2175. curr_alloc_size = min(be_max_phys_size *
  2176. 1024, alloc_size);
  2177. j++;
  2178. mem_arr++;
  2179. }
  2180. } while (alloc_size);
  2181. mem_descr->num_elements = j;
  2182. mem_descr->size_in_bytes = phba->mem_req[i];
  2183. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2184. GFP_KERNEL);
  2185. if (!mem_descr->mem_array)
  2186. goto free_mem;
  2187. memcpy(mem_descr->mem_array, mem_arr_orig,
  2188. sizeof(struct mem_array) * j);
  2189. mem_descr++;
  2190. }
  2191. kfree(mem_arr_orig);
  2192. return 0;
  2193. free_mem:
  2194. mem_descr->num_elements = j;
  2195. while ((i) || (j)) {
  2196. for (j = mem_descr->num_elements; j > 0; j--) {
  2197. pci_free_consistent(phba->pcidev,
  2198. mem_descr->mem_array[j - 1].size,
  2199. mem_descr->mem_array[j - 1].
  2200. virtual_address,
  2201. (unsigned long)mem_descr->
  2202. mem_array[j - 1].
  2203. bus_address.u.a64.address);
  2204. }
  2205. if (i) {
  2206. i--;
  2207. kfree(mem_descr->mem_array);
  2208. mem_descr--;
  2209. }
  2210. }
  2211. kfree(mem_arr_orig);
  2212. kfree(phba->init_mem);
  2213. kfree(phba->phwi_ctrlr);
  2214. return -ENOMEM;
  2215. }
  2216. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2217. {
  2218. beiscsi_find_mem_req(phba);
  2219. return beiscsi_alloc_mem(phba);
  2220. }
  2221. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2222. {
  2223. struct pdu_data_out *pdata_out;
  2224. struct pdu_nop_out *pnop_out;
  2225. struct be_mem_descriptor *mem_descr;
  2226. mem_descr = phba->init_mem;
  2227. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2228. pdata_out =
  2229. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2230. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2231. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2232. IIOC_SCSI_DATA);
  2233. pnop_out =
  2234. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2235. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2236. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2237. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2238. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2239. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2240. }
  2241. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2242. {
  2243. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2244. struct wrb_handle *pwrb_handle = NULL;
  2245. struct hwi_controller *phwi_ctrlr;
  2246. struct hwi_wrb_context *pwrb_context;
  2247. struct iscsi_wrb *pwrb = NULL;
  2248. unsigned int num_cxn_wrbh = 0;
  2249. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2250. mem_descr_wrbh = phba->init_mem;
  2251. mem_descr_wrbh += HWI_MEM_WRBH;
  2252. mem_descr_wrb = phba->init_mem;
  2253. mem_descr_wrb += HWI_MEM_WRB;
  2254. phwi_ctrlr = phba->phwi_ctrlr;
  2255. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2256. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2257. pwrb_context->pwrb_handle_base =
  2258. kzalloc(sizeof(struct wrb_handle *) *
  2259. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2260. if (!pwrb_context->pwrb_handle_base) {
  2261. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2262. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2263. goto init_wrb_hndl_failed;
  2264. }
  2265. pwrb_context->pwrb_handle_basestd =
  2266. kzalloc(sizeof(struct wrb_handle *) *
  2267. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2268. if (!pwrb_context->pwrb_handle_basestd) {
  2269. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2270. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2271. goto init_wrb_hndl_failed;
  2272. }
  2273. if (!num_cxn_wrbh) {
  2274. pwrb_handle =
  2275. mem_descr_wrbh->mem_array[idx].virtual_address;
  2276. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2277. ((sizeof(struct wrb_handle)) *
  2278. phba->params.wrbs_per_cxn));
  2279. idx++;
  2280. }
  2281. pwrb_context->alloc_index = 0;
  2282. pwrb_context->wrb_handles_available = 0;
  2283. pwrb_context->free_index = 0;
  2284. if (num_cxn_wrbh) {
  2285. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2286. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2287. pwrb_context->pwrb_handle_basestd[j] =
  2288. pwrb_handle;
  2289. pwrb_context->wrb_handles_available++;
  2290. pwrb_handle->wrb_index = j;
  2291. pwrb_handle++;
  2292. }
  2293. num_cxn_wrbh--;
  2294. }
  2295. }
  2296. idx = 0;
  2297. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2298. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2299. if (!num_cxn_wrb) {
  2300. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2301. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2302. ((sizeof(struct iscsi_wrb) *
  2303. phba->params.wrbs_per_cxn));
  2304. idx++;
  2305. }
  2306. if (num_cxn_wrb) {
  2307. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2308. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2309. pwrb_handle->pwrb = pwrb;
  2310. pwrb++;
  2311. }
  2312. num_cxn_wrb--;
  2313. }
  2314. }
  2315. return 0;
  2316. init_wrb_hndl_failed:
  2317. for (j = index; j > 0; j--) {
  2318. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2319. kfree(pwrb_context->pwrb_handle_base);
  2320. kfree(pwrb_context->pwrb_handle_basestd);
  2321. }
  2322. return -ENOMEM;
  2323. }
  2324. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2325. {
  2326. struct hwi_controller *phwi_ctrlr;
  2327. struct hba_parameters *p = &phba->params;
  2328. struct hwi_async_pdu_context *pasync_ctx;
  2329. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2330. unsigned int index, idx, num_per_mem, num_async_data;
  2331. struct be_mem_descriptor *mem_descr;
  2332. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2333. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2334. phwi_ctrlr = phba->phwi_ctrlr;
  2335. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2336. mem_descr->mem_array[0].virtual_address;
  2337. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2338. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2339. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2340. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2341. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2342. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2343. if (mem_descr->mem_array[0].virtual_address) {
  2344. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2345. "BM_%d : hwi_init_async_pdu_ctx"
  2346. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2347. mem_descr->mem_array[0].virtual_address);
  2348. } else
  2349. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2350. "BM_%d : No Virtual address\n");
  2351. pasync_ctx->async_header.va_base =
  2352. mem_descr->mem_array[0].virtual_address;
  2353. pasync_ctx->async_header.pa_base.u.a64.address =
  2354. mem_descr->mem_array[0].bus_address.u.a64.address;
  2355. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2356. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2357. if (mem_descr->mem_array[0].virtual_address) {
  2358. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2359. "BM_%d : hwi_init_async_pdu_ctx"
  2360. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2361. mem_descr->mem_array[0].virtual_address);
  2362. } else
  2363. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2364. "BM_%d : No Virtual address\n");
  2365. pasync_ctx->async_header.ring_base =
  2366. mem_descr->mem_array[0].virtual_address;
  2367. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2368. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2369. if (mem_descr->mem_array[0].virtual_address) {
  2370. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2371. "BM_%d : hwi_init_async_pdu_ctx"
  2372. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2373. mem_descr->mem_array[0].virtual_address);
  2374. } else
  2375. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2376. "BM_%d : No Virtual address\n");
  2377. pasync_ctx->async_header.handle_base =
  2378. mem_descr->mem_array[0].virtual_address;
  2379. pasync_ctx->async_header.writables = 0;
  2380. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2381. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2382. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2383. if (mem_descr->mem_array[0].virtual_address) {
  2384. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2385. "BM_%d : hwi_init_async_pdu_ctx"
  2386. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2387. mem_descr->mem_array[0].virtual_address);
  2388. } else
  2389. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2390. "BM_%d : No Virtual address\n");
  2391. pasync_ctx->async_data.ring_base =
  2392. mem_descr->mem_array[0].virtual_address;
  2393. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2394. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2395. if (!mem_descr->mem_array[0].virtual_address)
  2396. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2397. "BM_%d : No Virtual address\n");
  2398. pasync_ctx->async_data.handle_base =
  2399. mem_descr->mem_array[0].virtual_address;
  2400. pasync_ctx->async_data.writables = 0;
  2401. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2402. pasync_header_h =
  2403. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2404. pasync_data_h =
  2405. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2406. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2407. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2408. if (mem_descr->mem_array[0].virtual_address) {
  2409. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2410. "BM_%d : hwi_init_async_pdu_ctx"
  2411. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2412. mem_descr->mem_array[0].virtual_address);
  2413. } else
  2414. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2415. "BM_%d : No Virtual address\n");
  2416. idx = 0;
  2417. pasync_ctx->async_data.va_base =
  2418. mem_descr->mem_array[idx].virtual_address;
  2419. pasync_ctx->async_data.pa_base.u.a64.address =
  2420. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2421. num_async_data = ((mem_descr->mem_array[idx].size) /
  2422. phba->params.defpdu_data_sz);
  2423. num_per_mem = 0;
  2424. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2425. pasync_header_h->cri = -1;
  2426. pasync_header_h->index = (char)index;
  2427. INIT_LIST_HEAD(&pasync_header_h->link);
  2428. pasync_header_h->pbuffer =
  2429. (void *)((unsigned long)
  2430. (pasync_ctx->async_header.va_base) +
  2431. (p->defpdu_hdr_sz * index));
  2432. pasync_header_h->pa.u.a64.address =
  2433. pasync_ctx->async_header.pa_base.u.a64.address +
  2434. (p->defpdu_hdr_sz * index);
  2435. list_add_tail(&pasync_header_h->link,
  2436. &pasync_ctx->async_header.free_list);
  2437. pasync_header_h++;
  2438. pasync_ctx->async_header.free_entries++;
  2439. pasync_ctx->async_header.writables++;
  2440. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2441. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2442. header_busy_list);
  2443. pasync_data_h->cri = -1;
  2444. pasync_data_h->index = (char)index;
  2445. INIT_LIST_HEAD(&pasync_data_h->link);
  2446. if (!num_async_data) {
  2447. num_per_mem = 0;
  2448. idx++;
  2449. pasync_ctx->async_data.va_base =
  2450. mem_descr->mem_array[idx].virtual_address;
  2451. pasync_ctx->async_data.pa_base.u.a64.address =
  2452. mem_descr->mem_array[idx].
  2453. bus_address.u.a64.address;
  2454. num_async_data = ((mem_descr->mem_array[idx].size) /
  2455. phba->params.defpdu_data_sz);
  2456. }
  2457. pasync_data_h->pbuffer =
  2458. (void *)((unsigned long)
  2459. (pasync_ctx->async_data.va_base) +
  2460. (p->defpdu_data_sz * num_per_mem));
  2461. pasync_data_h->pa.u.a64.address =
  2462. pasync_ctx->async_data.pa_base.u.a64.address +
  2463. (p->defpdu_data_sz * num_per_mem);
  2464. num_per_mem++;
  2465. num_async_data--;
  2466. list_add_tail(&pasync_data_h->link,
  2467. &pasync_ctx->async_data.free_list);
  2468. pasync_data_h++;
  2469. pasync_ctx->async_data.free_entries++;
  2470. pasync_ctx->async_data.writables++;
  2471. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2472. }
  2473. pasync_ctx->async_header.host_write_ptr = 0;
  2474. pasync_ctx->async_header.ep_read_ptr = -1;
  2475. pasync_ctx->async_data.host_write_ptr = 0;
  2476. pasync_ctx->async_data.ep_read_ptr = -1;
  2477. }
  2478. static int
  2479. be_sgl_create_contiguous(void *virtual_address,
  2480. u64 physical_address, u32 length,
  2481. struct be_dma_mem *sgl)
  2482. {
  2483. WARN_ON(!virtual_address);
  2484. WARN_ON(!physical_address);
  2485. WARN_ON(!length > 0);
  2486. WARN_ON(!sgl);
  2487. sgl->va = virtual_address;
  2488. sgl->dma = (unsigned long)physical_address;
  2489. sgl->size = length;
  2490. return 0;
  2491. }
  2492. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2493. {
  2494. memset(sgl, 0, sizeof(*sgl));
  2495. }
  2496. static void
  2497. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2498. struct mem_array *pmem, struct be_dma_mem *sgl)
  2499. {
  2500. if (sgl->va)
  2501. be_sgl_destroy_contiguous(sgl);
  2502. be_sgl_create_contiguous(pmem->virtual_address,
  2503. pmem->bus_address.u.a64.address,
  2504. pmem->size, sgl);
  2505. }
  2506. static void
  2507. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2508. struct mem_array *pmem, struct be_dma_mem *sgl)
  2509. {
  2510. if (sgl->va)
  2511. be_sgl_destroy_contiguous(sgl);
  2512. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2513. pmem->bus_address.u.a64.address,
  2514. pmem->size, sgl);
  2515. }
  2516. static int be_fill_queue(struct be_queue_info *q,
  2517. u16 len, u16 entry_size, void *vaddress)
  2518. {
  2519. struct be_dma_mem *mem = &q->dma_mem;
  2520. memset(q, 0, sizeof(*q));
  2521. q->len = len;
  2522. q->entry_size = entry_size;
  2523. mem->size = len * entry_size;
  2524. mem->va = vaddress;
  2525. if (!mem->va)
  2526. return -ENOMEM;
  2527. memset(mem->va, 0, mem->size);
  2528. return 0;
  2529. }
  2530. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2531. struct hwi_context_memory *phwi_context)
  2532. {
  2533. unsigned int i, num_eq_pages;
  2534. int ret = 0, eq_for_mcc;
  2535. struct be_queue_info *eq;
  2536. struct be_dma_mem *mem;
  2537. void *eq_vaddress;
  2538. dma_addr_t paddr;
  2539. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2540. sizeof(struct be_eq_entry));
  2541. if (phba->msix_enabled)
  2542. eq_for_mcc = 1;
  2543. else
  2544. eq_for_mcc = 0;
  2545. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2546. eq = &phwi_context->be_eq[i].q;
  2547. mem = &eq->dma_mem;
  2548. phwi_context->be_eq[i].phba = phba;
  2549. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2550. num_eq_pages * PAGE_SIZE,
  2551. &paddr);
  2552. if (!eq_vaddress)
  2553. goto create_eq_error;
  2554. mem->va = eq_vaddress;
  2555. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2556. sizeof(struct be_eq_entry), eq_vaddress);
  2557. if (ret) {
  2558. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2559. "BM_%d : be_fill_queue Failed for EQ\n");
  2560. goto create_eq_error;
  2561. }
  2562. mem->dma = paddr;
  2563. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2564. phwi_context->cur_eqd);
  2565. if (ret) {
  2566. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2567. "BM_%d : beiscsi_cmd_eq_create"
  2568. "Failed for EQ\n");
  2569. goto create_eq_error;
  2570. }
  2571. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2572. "BM_%d : eqid = %d\n",
  2573. phwi_context->be_eq[i].q.id);
  2574. }
  2575. return 0;
  2576. create_eq_error:
  2577. for (i = 0; i < (phba->num_cpus + 1); i++) {
  2578. eq = &phwi_context->be_eq[i].q;
  2579. mem = &eq->dma_mem;
  2580. if (mem->va)
  2581. pci_free_consistent(phba->pcidev, num_eq_pages
  2582. * PAGE_SIZE,
  2583. mem->va, mem->dma);
  2584. }
  2585. return ret;
  2586. }
  2587. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2588. struct hwi_context_memory *phwi_context)
  2589. {
  2590. unsigned int i, num_cq_pages;
  2591. int ret = 0;
  2592. struct be_queue_info *cq, *eq;
  2593. struct be_dma_mem *mem;
  2594. struct be_eq_obj *pbe_eq;
  2595. void *cq_vaddress;
  2596. dma_addr_t paddr;
  2597. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2598. sizeof(struct sol_cqe));
  2599. for (i = 0; i < phba->num_cpus; i++) {
  2600. cq = &phwi_context->be_cq[i];
  2601. eq = &phwi_context->be_eq[i].q;
  2602. pbe_eq = &phwi_context->be_eq[i];
  2603. pbe_eq->cq = cq;
  2604. pbe_eq->phba = phba;
  2605. mem = &cq->dma_mem;
  2606. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2607. num_cq_pages * PAGE_SIZE,
  2608. &paddr);
  2609. if (!cq_vaddress)
  2610. goto create_cq_error;
  2611. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2612. sizeof(struct sol_cqe), cq_vaddress);
  2613. if (ret) {
  2614. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2615. "BM_%d : be_fill_queue Failed "
  2616. "for ISCSI CQ\n");
  2617. goto create_cq_error;
  2618. }
  2619. mem->dma = paddr;
  2620. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2621. false, 0);
  2622. if (ret) {
  2623. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2624. "BM_%d : beiscsi_cmd_eq_create"
  2625. "Failed for ISCSI CQ\n");
  2626. goto create_cq_error;
  2627. }
  2628. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2629. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2630. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2631. }
  2632. return 0;
  2633. create_cq_error:
  2634. for (i = 0; i < phba->num_cpus; i++) {
  2635. cq = &phwi_context->be_cq[i];
  2636. mem = &cq->dma_mem;
  2637. if (mem->va)
  2638. pci_free_consistent(phba->pcidev, num_cq_pages
  2639. * PAGE_SIZE,
  2640. mem->va, mem->dma);
  2641. }
  2642. return ret;
  2643. }
  2644. static int
  2645. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2646. struct hwi_context_memory *phwi_context,
  2647. struct hwi_controller *phwi_ctrlr,
  2648. unsigned int def_pdu_ring_sz)
  2649. {
  2650. unsigned int idx;
  2651. int ret;
  2652. struct be_queue_info *dq, *cq;
  2653. struct be_dma_mem *mem;
  2654. struct be_mem_descriptor *mem_descr;
  2655. void *dq_vaddress;
  2656. idx = 0;
  2657. dq = &phwi_context->be_def_hdrq;
  2658. cq = &phwi_context->be_cq[0];
  2659. mem = &dq->dma_mem;
  2660. mem_descr = phba->init_mem;
  2661. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2662. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2663. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2664. sizeof(struct phys_addr),
  2665. sizeof(struct phys_addr), dq_vaddress);
  2666. if (ret) {
  2667. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2668. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2669. return ret;
  2670. }
  2671. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2672. bus_address.u.a64.address;
  2673. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2674. def_pdu_ring_sz,
  2675. phba->params.defpdu_hdr_sz);
  2676. if (ret) {
  2677. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2678. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2679. return ret;
  2680. }
  2681. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2682. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2683. "BM_%d : iscsi def pdu id is %d\n",
  2684. phwi_context->be_def_hdrq.id);
  2685. hwi_post_async_buffers(phba, 1);
  2686. return 0;
  2687. }
  2688. static int
  2689. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2690. struct hwi_context_memory *phwi_context,
  2691. struct hwi_controller *phwi_ctrlr,
  2692. unsigned int def_pdu_ring_sz)
  2693. {
  2694. unsigned int idx;
  2695. int ret;
  2696. struct be_queue_info *dataq, *cq;
  2697. struct be_dma_mem *mem;
  2698. struct be_mem_descriptor *mem_descr;
  2699. void *dq_vaddress;
  2700. idx = 0;
  2701. dataq = &phwi_context->be_def_dataq;
  2702. cq = &phwi_context->be_cq[0];
  2703. mem = &dataq->dma_mem;
  2704. mem_descr = phba->init_mem;
  2705. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2706. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2707. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2708. sizeof(struct phys_addr),
  2709. sizeof(struct phys_addr), dq_vaddress);
  2710. if (ret) {
  2711. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2712. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2713. return ret;
  2714. }
  2715. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2716. bus_address.u.a64.address;
  2717. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2718. def_pdu_ring_sz,
  2719. phba->params.defpdu_data_sz);
  2720. if (ret) {
  2721. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2722. "BM_%d be_cmd_create_default_pdu_queue"
  2723. " Failed for DEF PDU DATA\n");
  2724. return ret;
  2725. }
  2726. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2727. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2728. "BM_%d : iscsi def data id is %d\n",
  2729. phwi_context->be_def_dataq.id);
  2730. hwi_post_async_buffers(phba, 0);
  2731. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2732. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2733. return 0;
  2734. }
  2735. static int
  2736. beiscsi_post_pages(struct beiscsi_hba *phba)
  2737. {
  2738. struct be_mem_descriptor *mem_descr;
  2739. struct mem_array *pm_arr;
  2740. unsigned int page_offset, i;
  2741. struct be_dma_mem sgl;
  2742. int status;
  2743. mem_descr = phba->init_mem;
  2744. mem_descr += HWI_MEM_SGE;
  2745. pm_arr = mem_descr->mem_array;
  2746. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2747. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2748. for (i = 0; i < mem_descr->num_elements; i++) {
  2749. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2750. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2751. page_offset,
  2752. (pm_arr->size / PAGE_SIZE));
  2753. page_offset += pm_arr->size / PAGE_SIZE;
  2754. if (status != 0) {
  2755. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2756. "BM_%d : post sgl failed.\n");
  2757. return status;
  2758. }
  2759. pm_arr++;
  2760. }
  2761. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2762. "BM_%d : POSTED PAGES\n");
  2763. return 0;
  2764. }
  2765. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2766. {
  2767. struct be_dma_mem *mem = &q->dma_mem;
  2768. if (mem->va) {
  2769. pci_free_consistent(phba->pcidev, mem->size,
  2770. mem->va, mem->dma);
  2771. mem->va = NULL;
  2772. }
  2773. }
  2774. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2775. u16 len, u16 entry_size)
  2776. {
  2777. struct be_dma_mem *mem = &q->dma_mem;
  2778. memset(q, 0, sizeof(*q));
  2779. q->len = len;
  2780. q->entry_size = entry_size;
  2781. mem->size = len * entry_size;
  2782. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2783. if (!mem->va)
  2784. return -ENOMEM;
  2785. memset(mem->va, 0, mem->size);
  2786. return 0;
  2787. }
  2788. static int
  2789. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2790. struct hwi_context_memory *phwi_context,
  2791. struct hwi_controller *phwi_ctrlr)
  2792. {
  2793. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2794. u64 pa_addr_lo;
  2795. unsigned int idx, num, i;
  2796. struct mem_array *pwrb_arr;
  2797. void *wrb_vaddr;
  2798. struct be_dma_mem sgl;
  2799. struct be_mem_descriptor *mem_descr;
  2800. int status;
  2801. idx = 0;
  2802. mem_descr = phba->init_mem;
  2803. mem_descr += HWI_MEM_WRB;
  2804. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2805. GFP_KERNEL);
  2806. if (!pwrb_arr) {
  2807. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2808. "BM_%d : Memory alloc failed in create wrb ring.\n");
  2809. return -ENOMEM;
  2810. }
  2811. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2812. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2813. num_wrb_rings = mem_descr->mem_array[idx].size /
  2814. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2815. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2816. if (num_wrb_rings) {
  2817. pwrb_arr[num].virtual_address = wrb_vaddr;
  2818. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2819. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2820. sizeof(struct iscsi_wrb);
  2821. wrb_vaddr += pwrb_arr[num].size;
  2822. pa_addr_lo += pwrb_arr[num].size;
  2823. num_wrb_rings--;
  2824. } else {
  2825. idx++;
  2826. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2827. pa_addr_lo = mem_descr->mem_array[idx].\
  2828. bus_address.u.a64.address;
  2829. num_wrb_rings = mem_descr->mem_array[idx].size /
  2830. (phba->params.wrbs_per_cxn *
  2831. sizeof(struct iscsi_wrb));
  2832. pwrb_arr[num].virtual_address = wrb_vaddr;
  2833. pwrb_arr[num].bus_address.u.a64.address\
  2834. = pa_addr_lo;
  2835. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2836. sizeof(struct iscsi_wrb);
  2837. wrb_vaddr += pwrb_arr[num].size;
  2838. pa_addr_lo += pwrb_arr[num].size;
  2839. num_wrb_rings--;
  2840. }
  2841. }
  2842. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2843. wrb_mem_index = 0;
  2844. offset = 0;
  2845. size = 0;
  2846. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2847. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2848. &phwi_context->be_wrbq[i]);
  2849. if (status != 0) {
  2850. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2851. "BM_%d : wrbq create failed.");
  2852. kfree(pwrb_arr);
  2853. return status;
  2854. }
  2855. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  2856. id;
  2857. }
  2858. kfree(pwrb_arr);
  2859. return 0;
  2860. }
  2861. static void free_wrb_handles(struct beiscsi_hba *phba)
  2862. {
  2863. unsigned int index;
  2864. struct hwi_controller *phwi_ctrlr;
  2865. struct hwi_wrb_context *pwrb_context;
  2866. phwi_ctrlr = phba->phwi_ctrlr;
  2867. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2868. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2869. kfree(pwrb_context->pwrb_handle_base);
  2870. kfree(pwrb_context->pwrb_handle_basestd);
  2871. }
  2872. }
  2873. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  2874. {
  2875. struct be_queue_info *q;
  2876. struct be_ctrl_info *ctrl = &phba->ctrl;
  2877. q = &phba->ctrl.mcc_obj.q;
  2878. if (q->created)
  2879. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  2880. be_queue_free(phba, q);
  2881. q = &phba->ctrl.mcc_obj.cq;
  2882. if (q->created)
  2883. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2884. be_queue_free(phba, q);
  2885. }
  2886. static void hwi_cleanup(struct beiscsi_hba *phba)
  2887. {
  2888. struct be_queue_info *q;
  2889. struct be_ctrl_info *ctrl = &phba->ctrl;
  2890. struct hwi_controller *phwi_ctrlr;
  2891. struct hwi_context_memory *phwi_context;
  2892. int i, eq_num;
  2893. phwi_ctrlr = phba->phwi_ctrlr;
  2894. phwi_context = phwi_ctrlr->phwi_ctxt;
  2895. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2896. q = &phwi_context->be_wrbq[i];
  2897. if (q->created)
  2898. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  2899. }
  2900. free_wrb_handles(phba);
  2901. q = &phwi_context->be_def_hdrq;
  2902. if (q->created)
  2903. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2904. q = &phwi_context->be_def_dataq;
  2905. if (q->created)
  2906. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2907. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  2908. for (i = 0; i < (phba->num_cpus); i++) {
  2909. q = &phwi_context->be_cq[i];
  2910. if (q->created)
  2911. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2912. }
  2913. if (phba->msix_enabled)
  2914. eq_num = 1;
  2915. else
  2916. eq_num = 0;
  2917. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  2918. q = &phwi_context->be_eq[i].q;
  2919. if (q->created)
  2920. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  2921. }
  2922. be_mcc_queues_destroy(phba);
  2923. }
  2924. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  2925. struct hwi_context_memory *phwi_context)
  2926. {
  2927. struct be_queue_info *q, *cq;
  2928. struct be_ctrl_info *ctrl = &phba->ctrl;
  2929. /* Alloc MCC compl queue */
  2930. cq = &phba->ctrl.mcc_obj.cq;
  2931. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  2932. sizeof(struct be_mcc_compl)))
  2933. goto err;
  2934. /* Ask BE to create MCC compl queue; */
  2935. if (phba->msix_enabled) {
  2936. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  2937. [phba->num_cpus].q, false, true, 0))
  2938. goto mcc_cq_free;
  2939. } else {
  2940. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  2941. false, true, 0))
  2942. goto mcc_cq_free;
  2943. }
  2944. /* Alloc MCC queue */
  2945. q = &phba->ctrl.mcc_obj.q;
  2946. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  2947. goto mcc_cq_destroy;
  2948. /* Ask BE to create MCC queue */
  2949. if (beiscsi_cmd_mccq_create(phba, q, cq))
  2950. goto mcc_q_free;
  2951. return 0;
  2952. mcc_q_free:
  2953. be_queue_free(phba, q);
  2954. mcc_cq_destroy:
  2955. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  2956. mcc_cq_free:
  2957. be_queue_free(phba, cq);
  2958. err:
  2959. return -ENOMEM;
  2960. }
  2961. static int find_num_cpus(void)
  2962. {
  2963. int num_cpus = 0;
  2964. num_cpus = num_online_cpus();
  2965. if (num_cpus >= MAX_CPUS)
  2966. num_cpus = MAX_CPUS - 1;
  2967. return num_cpus;
  2968. }
  2969. static int hwi_init_port(struct beiscsi_hba *phba)
  2970. {
  2971. struct hwi_controller *phwi_ctrlr;
  2972. struct hwi_context_memory *phwi_context;
  2973. unsigned int def_pdu_ring_sz;
  2974. struct be_ctrl_info *ctrl = &phba->ctrl;
  2975. int status;
  2976. def_pdu_ring_sz =
  2977. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  2978. phwi_ctrlr = phba->phwi_ctrlr;
  2979. phwi_context = phwi_ctrlr->phwi_ctxt;
  2980. phwi_context->max_eqd = 0;
  2981. phwi_context->min_eqd = 0;
  2982. phwi_context->cur_eqd = 64;
  2983. be_cmd_fw_initialize(&phba->ctrl);
  2984. status = beiscsi_create_eqs(phba, phwi_context);
  2985. if (status != 0) {
  2986. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2987. "BM_%d : EQ not created\n");
  2988. goto error;
  2989. }
  2990. status = be_mcc_queues_create(phba, phwi_context);
  2991. if (status != 0)
  2992. goto error;
  2993. status = mgmt_check_supported_fw(ctrl, phba);
  2994. if (status != 0) {
  2995. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2996. "BM_%d : Unsupported fw version\n");
  2997. goto error;
  2998. }
  2999. status = beiscsi_create_cqs(phba, phwi_context);
  3000. if (status != 0) {
  3001. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3002. "BM_%d : CQ not created\n");
  3003. goto error;
  3004. }
  3005. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  3006. def_pdu_ring_sz);
  3007. if (status != 0) {
  3008. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3009. "BM_%d : Default Header not created\n");
  3010. goto error;
  3011. }
  3012. status = beiscsi_create_def_data(phba, phwi_context,
  3013. phwi_ctrlr, def_pdu_ring_sz);
  3014. if (status != 0) {
  3015. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3016. "BM_%d : Default Data not created\n");
  3017. goto error;
  3018. }
  3019. status = beiscsi_post_pages(phba);
  3020. if (status != 0) {
  3021. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3022. "BM_%d : Post SGL Pages Failed\n");
  3023. goto error;
  3024. }
  3025. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3026. if (status != 0) {
  3027. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3028. "BM_%d : WRB Rings not created\n");
  3029. goto error;
  3030. }
  3031. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3032. "BM_%d : hwi_init_port success\n");
  3033. return 0;
  3034. error:
  3035. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3036. "BM_%d : hwi_init_port failed");
  3037. hwi_cleanup(phba);
  3038. return status;
  3039. }
  3040. static int hwi_init_controller(struct beiscsi_hba *phba)
  3041. {
  3042. struct hwi_controller *phwi_ctrlr;
  3043. phwi_ctrlr = phba->phwi_ctrlr;
  3044. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3045. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3046. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3047. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3048. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3049. phwi_ctrlr->phwi_ctxt);
  3050. } else {
  3051. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3052. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3053. "than one element.Failing to load\n");
  3054. return -ENOMEM;
  3055. }
  3056. iscsi_init_global_templates(phba);
  3057. if (beiscsi_init_wrb_handle(phba))
  3058. return -ENOMEM;
  3059. hwi_init_async_pdu_ctx(phba);
  3060. if (hwi_init_port(phba) != 0) {
  3061. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3062. "BM_%d : hwi_init_controller failed\n");
  3063. return -ENOMEM;
  3064. }
  3065. return 0;
  3066. }
  3067. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3068. {
  3069. struct be_mem_descriptor *mem_descr;
  3070. int i, j;
  3071. mem_descr = phba->init_mem;
  3072. i = 0;
  3073. j = 0;
  3074. for (i = 0; i < SE_MEM_MAX; i++) {
  3075. for (j = mem_descr->num_elements; j > 0; j--) {
  3076. pci_free_consistent(phba->pcidev,
  3077. mem_descr->mem_array[j - 1].size,
  3078. mem_descr->mem_array[j - 1].virtual_address,
  3079. (unsigned long)mem_descr->mem_array[j - 1].
  3080. bus_address.u.a64.address);
  3081. }
  3082. kfree(mem_descr->mem_array);
  3083. mem_descr++;
  3084. }
  3085. kfree(phba->init_mem);
  3086. kfree(phba->phwi_ctrlr);
  3087. }
  3088. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3089. {
  3090. int ret = -ENOMEM;
  3091. ret = beiscsi_get_memory(phba);
  3092. if (ret < 0) {
  3093. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3094. "BM_%d : beiscsi_dev_probe -"
  3095. "Failed in beiscsi_alloc_memory\n");
  3096. return ret;
  3097. }
  3098. ret = hwi_init_controller(phba);
  3099. if (ret)
  3100. goto free_init;
  3101. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3102. "BM_%d : Return success from beiscsi_init_controller");
  3103. return 0;
  3104. free_init:
  3105. beiscsi_free_mem(phba);
  3106. return ret;
  3107. }
  3108. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3109. {
  3110. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3111. struct sgl_handle *psgl_handle;
  3112. struct iscsi_sge *pfrag;
  3113. unsigned int arr_index, i, idx;
  3114. phba->io_sgl_hndl_avbl = 0;
  3115. phba->eh_sgl_hndl_avbl = 0;
  3116. mem_descr_sglh = phba->init_mem;
  3117. mem_descr_sglh += HWI_MEM_SGLH;
  3118. if (1 == mem_descr_sglh->num_elements) {
  3119. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3120. phba->params.ios_per_ctrl,
  3121. GFP_KERNEL);
  3122. if (!phba->io_sgl_hndl_base) {
  3123. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3124. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3125. return -ENOMEM;
  3126. }
  3127. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3128. (phba->params.icds_per_ctrl -
  3129. phba->params.ios_per_ctrl),
  3130. GFP_KERNEL);
  3131. if (!phba->eh_sgl_hndl_base) {
  3132. kfree(phba->io_sgl_hndl_base);
  3133. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3134. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3135. return -ENOMEM;
  3136. }
  3137. } else {
  3138. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3139. "BM_%d : HWI_MEM_SGLH is more than one element."
  3140. "Failing to load\n");
  3141. return -ENOMEM;
  3142. }
  3143. arr_index = 0;
  3144. idx = 0;
  3145. while (idx < mem_descr_sglh->num_elements) {
  3146. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3147. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3148. sizeof(struct sgl_handle)); i++) {
  3149. if (arr_index < phba->params.ios_per_ctrl) {
  3150. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3151. phba->io_sgl_hndl_avbl++;
  3152. arr_index++;
  3153. } else {
  3154. phba->eh_sgl_hndl_base[arr_index -
  3155. phba->params.ios_per_ctrl] =
  3156. psgl_handle;
  3157. arr_index++;
  3158. phba->eh_sgl_hndl_avbl++;
  3159. }
  3160. psgl_handle++;
  3161. }
  3162. idx++;
  3163. }
  3164. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3165. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3166. "phba->eh_sgl_hndl_avbl=%d\n",
  3167. phba->io_sgl_hndl_avbl,
  3168. phba->eh_sgl_hndl_avbl);
  3169. mem_descr_sg = phba->init_mem;
  3170. mem_descr_sg += HWI_MEM_SGE;
  3171. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3172. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3173. mem_descr_sg->num_elements);
  3174. arr_index = 0;
  3175. idx = 0;
  3176. while (idx < mem_descr_sg->num_elements) {
  3177. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3178. for (i = 0;
  3179. i < (mem_descr_sg->mem_array[idx].size) /
  3180. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3181. i++) {
  3182. if (arr_index < phba->params.ios_per_ctrl)
  3183. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3184. else
  3185. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3186. phba->params.ios_per_ctrl];
  3187. psgl_handle->pfrag = pfrag;
  3188. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3189. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3190. pfrag += phba->params.num_sge_per_io;
  3191. psgl_handle->sgl_index =
  3192. phba->fw_config.iscsi_icd_start + arr_index++;
  3193. }
  3194. idx++;
  3195. }
  3196. phba->io_sgl_free_index = 0;
  3197. phba->io_sgl_alloc_index = 0;
  3198. phba->eh_sgl_free_index = 0;
  3199. phba->eh_sgl_alloc_index = 0;
  3200. return 0;
  3201. }
  3202. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3203. {
  3204. int i, new_cid;
  3205. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3206. GFP_KERNEL);
  3207. if (!phba->cid_array) {
  3208. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3209. "BM_%d : Failed to allocate memory in "
  3210. "hba_setup_cid_tbls\n");
  3211. return -ENOMEM;
  3212. }
  3213. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3214. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3215. if (!phba->ep_array) {
  3216. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3217. "BM_%d : Failed to allocate memory in "
  3218. "hba_setup_cid_tbls\n");
  3219. kfree(phba->cid_array);
  3220. return -ENOMEM;
  3221. }
  3222. new_cid = phba->fw_config.iscsi_cid_start;
  3223. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3224. phba->cid_array[i] = new_cid;
  3225. new_cid += 2;
  3226. }
  3227. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3228. return 0;
  3229. }
  3230. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3231. {
  3232. struct be_ctrl_info *ctrl = &phba->ctrl;
  3233. struct hwi_controller *phwi_ctrlr;
  3234. struct hwi_context_memory *phwi_context;
  3235. struct be_queue_info *eq;
  3236. u8 __iomem *addr;
  3237. u32 reg, i;
  3238. u32 enabled;
  3239. phwi_ctrlr = phba->phwi_ctrlr;
  3240. phwi_context = phwi_ctrlr->phwi_ctxt;
  3241. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3242. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3243. reg = ioread32(addr);
  3244. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3245. if (!enabled) {
  3246. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3247. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3248. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3249. iowrite32(reg, addr);
  3250. }
  3251. if (!phba->msix_enabled) {
  3252. eq = &phwi_context->be_eq[0].q;
  3253. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3254. "BM_%d : eq->id=%d\n", eq->id);
  3255. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3256. } else {
  3257. for (i = 0; i <= phba->num_cpus; i++) {
  3258. eq = &phwi_context->be_eq[i].q;
  3259. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3260. "BM_%d : eq->id=%d\n", eq->id);
  3261. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3262. }
  3263. }
  3264. }
  3265. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3266. {
  3267. struct be_ctrl_info *ctrl = &phba->ctrl;
  3268. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3269. u32 reg = ioread32(addr);
  3270. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3271. if (enabled) {
  3272. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3273. iowrite32(reg, addr);
  3274. } else
  3275. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3276. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3277. }
  3278. /**
  3279. * beiscsi_get_boot_info()- Get the boot session info
  3280. * @phba: The device priv structure instance
  3281. *
  3282. * Get the boot target info and store in driver priv structure
  3283. *
  3284. * return values
  3285. * Success: 0
  3286. * Failure: Non-Zero Value
  3287. **/
  3288. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3289. {
  3290. struct be_cmd_get_session_resp *session_resp;
  3291. struct be_mcc_wrb *wrb;
  3292. struct be_dma_mem nonemb_cmd;
  3293. unsigned int tag, wrb_num;
  3294. unsigned short status, extd_status;
  3295. unsigned int s_handle;
  3296. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3297. int ret = -ENOMEM;
  3298. /* Get the session handle of the boot target */
  3299. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3300. if (ret) {
  3301. beiscsi_log(phba, KERN_ERR,
  3302. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3303. "BM_%d : No boot session\n");
  3304. return ret;
  3305. }
  3306. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3307. sizeof(*session_resp),
  3308. &nonemb_cmd.dma);
  3309. if (nonemb_cmd.va == NULL) {
  3310. beiscsi_log(phba, KERN_ERR,
  3311. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3312. "BM_%d : Failed to allocate memory for"
  3313. "beiscsi_get_session_info\n");
  3314. return -ENOMEM;
  3315. }
  3316. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3317. tag = mgmt_get_session_info(phba, s_handle,
  3318. &nonemb_cmd);
  3319. if (!tag) {
  3320. beiscsi_log(phba, KERN_ERR,
  3321. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3322. "BM_%d : beiscsi_get_session_info"
  3323. " Failed\n");
  3324. goto boot_freemem;
  3325. } else
  3326. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3327. phba->ctrl.mcc_numtag[tag]);
  3328. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3329. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3330. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3331. if (status || extd_status) {
  3332. beiscsi_log(phba, KERN_ERR,
  3333. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3334. "BM_%d : beiscsi_get_session_info Failed"
  3335. " status = %d extd_status = %d\n",
  3336. status, extd_status);
  3337. free_mcc_tag(&phba->ctrl, tag);
  3338. goto boot_freemem;
  3339. }
  3340. wrb = queue_get_wrb(mccq, wrb_num);
  3341. free_mcc_tag(&phba->ctrl, tag);
  3342. session_resp = nonemb_cmd.va ;
  3343. memcpy(&phba->boot_sess, &session_resp->session_info,
  3344. sizeof(struct mgmt_session_info));
  3345. ret = 0;
  3346. boot_freemem:
  3347. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3348. nonemb_cmd.va, nonemb_cmd.dma);
  3349. return ret;
  3350. }
  3351. static void beiscsi_boot_release(void *data)
  3352. {
  3353. struct beiscsi_hba *phba = data;
  3354. scsi_host_put(phba->shost);
  3355. }
  3356. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3357. {
  3358. struct iscsi_boot_kobj *boot_kobj;
  3359. /* get boot info using mgmt cmd */
  3360. if (beiscsi_get_boot_info(phba))
  3361. /* Try to see if we can carry on without this */
  3362. return 0;
  3363. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3364. if (!phba->boot_kset)
  3365. return -ENOMEM;
  3366. /* get a ref because the show function will ref the phba */
  3367. if (!scsi_host_get(phba->shost))
  3368. goto free_kset;
  3369. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3370. beiscsi_show_boot_tgt_info,
  3371. beiscsi_tgt_get_attr_visibility,
  3372. beiscsi_boot_release);
  3373. if (!boot_kobj)
  3374. goto put_shost;
  3375. if (!scsi_host_get(phba->shost))
  3376. goto free_kset;
  3377. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3378. beiscsi_show_boot_ini_info,
  3379. beiscsi_ini_get_attr_visibility,
  3380. beiscsi_boot_release);
  3381. if (!boot_kobj)
  3382. goto put_shost;
  3383. if (!scsi_host_get(phba->shost))
  3384. goto free_kset;
  3385. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3386. beiscsi_show_boot_eth_info,
  3387. beiscsi_eth_get_attr_visibility,
  3388. beiscsi_boot_release);
  3389. if (!boot_kobj)
  3390. goto put_shost;
  3391. return 0;
  3392. put_shost:
  3393. scsi_host_put(phba->shost);
  3394. free_kset:
  3395. iscsi_boot_destroy_kset(phba->boot_kset);
  3396. return -ENOMEM;
  3397. }
  3398. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3399. {
  3400. int ret;
  3401. ret = beiscsi_init_controller(phba);
  3402. if (ret < 0) {
  3403. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3404. "BM_%d : beiscsi_dev_probe - Failed in"
  3405. "beiscsi_init_controller\n");
  3406. return ret;
  3407. }
  3408. ret = beiscsi_init_sgl_handle(phba);
  3409. if (ret < 0) {
  3410. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3411. "BM_%d : beiscsi_dev_probe - Failed in"
  3412. "beiscsi_init_sgl_handle\n");
  3413. goto do_cleanup_ctrlr;
  3414. }
  3415. if (hba_setup_cid_tbls(phba)) {
  3416. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3417. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3418. kfree(phba->io_sgl_hndl_base);
  3419. kfree(phba->eh_sgl_hndl_base);
  3420. goto do_cleanup_ctrlr;
  3421. }
  3422. return ret;
  3423. do_cleanup_ctrlr:
  3424. hwi_cleanup(phba);
  3425. return ret;
  3426. }
  3427. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3428. {
  3429. struct hwi_controller *phwi_ctrlr;
  3430. struct hwi_context_memory *phwi_context;
  3431. struct be_queue_info *eq;
  3432. struct be_eq_entry *eqe = NULL;
  3433. int i, eq_msix;
  3434. unsigned int num_processed;
  3435. phwi_ctrlr = phba->phwi_ctrlr;
  3436. phwi_context = phwi_ctrlr->phwi_ctxt;
  3437. if (phba->msix_enabled)
  3438. eq_msix = 1;
  3439. else
  3440. eq_msix = 0;
  3441. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3442. eq = &phwi_context->be_eq[i].q;
  3443. eqe = queue_tail_node(eq);
  3444. num_processed = 0;
  3445. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3446. & EQE_VALID_MASK) {
  3447. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3448. queue_tail_inc(eq);
  3449. eqe = queue_tail_node(eq);
  3450. num_processed++;
  3451. }
  3452. if (num_processed)
  3453. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3454. }
  3455. }
  3456. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3457. {
  3458. int mgmt_status;
  3459. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3460. if (mgmt_status)
  3461. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3462. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3463. hwi_purge_eq(phba);
  3464. hwi_cleanup(phba);
  3465. kfree(phba->io_sgl_hndl_base);
  3466. kfree(phba->eh_sgl_hndl_base);
  3467. kfree(phba->cid_array);
  3468. kfree(phba->ep_array);
  3469. }
  3470. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3471. {
  3472. struct beiscsi_io_task *io_task = task->dd_data;
  3473. struct iscsi_conn *conn = task->conn;
  3474. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3475. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3476. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3477. struct hwi_wrb_context *pwrb_context;
  3478. struct hwi_controller *phwi_ctrlr;
  3479. phwi_ctrlr = phba->phwi_ctrlr;
  3480. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3481. - phba->fw_config.iscsi_cid_start];
  3482. if (io_task->cmd_bhs) {
  3483. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3484. io_task->bhs_pa.u.a64.address);
  3485. io_task->cmd_bhs = NULL;
  3486. }
  3487. if (task->sc) {
  3488. if (io_task->pwrb_handle) {
  3489. free_wrb_handle(phba, pwrb_context,
  3490. io_task->pwrb_handle);
  3491. io_task->pwrb_handle = NULL;
  3492. }
  3493. if (io_task->psgl_handle) {
  3494. spin_lock(&phba->io_sgl_lock);
  3495. free_io_sgl_handle(phba, io_task->psgl_handle);
  3496. spin_unlock(&phba->io_sgl_lock);
  3497. io_task->psgl_handle = NULL;
  3498. }
  3499. } else {
  3500. if (!beiscsi_conn->login_in_progress) {
  3501. if (io_task->pwrb_handle) {
  3502. free_wrb_handle(phba, pwrb_context,
  3503. io_task->pwrb_handle);
  3504. io_task->pwrb_handle = NULL;
  3505. }
  3506. if (io_task->psgl_handle) {
  3507. spin_lock(&phba->mgmt_sgl_lock);
  3508. free_mgmt_sgl_handle(phba,
  3509. io_task->psgl_handle);
  3510. spin_unlock(&phba->mgmt_sgl_lock);
  3511. io_task->psgl_handle = NULL;
  3512. }
  3513. }
  3514. }
  3515. }
  3516. void
  3517. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3518. struct beiscsi_offload_params *params)
  3519. {
  3520. struct wrb_handle *pwrb_handle;
  3521. struct iscsi_target_context_update_wrb *pwrb = NULL;
  3522. struct be_mem_descriptor *mem_descr;
  3523. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3524. struct iscsi_task *task = beiscsi_conn->task;
  3525. struct iscsi_session *session = task->conn->session;
  3526. u32 doorbell = 0;
  3527. /*
  3528. * We can always use 0 here because it is reserved by libiscsi for
  3529. * login/startup related tasks.
  3530. */
  3531. beiscsi_conn->login_in_progress = 0;
  3532. spin_lock_bh(&session->lock);
  3533. beiscsi_cleanup_task(task);
  3534. spin_unlock_bh(&session->lock);
  3535. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3536. phba->fw_config.iscsi_cid_start));
  3537. pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
  3538. memset(pwrb, 0, sizeof(*pwrb));
  3539. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3540. max_burst_length, pwrb, params->dw[offsetof
  3541. (struct amap_beiscsi_offload_params,
  3542. max_burst_length) / 32]);
  3543. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3544. max_send_data_segment_length, pwrb,
  3545. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3546. max_send_data_segment_length) / 32]);
  3547. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3548. first_burst_length,
  3549. pwrb,
  3550. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3551. first_burst_length) / 32]);
  3552. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
  3553. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3554. erl) / 32] & OFFLD_PARAMS_ERL));
  3555. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
  3556. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3557. dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
  3558. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
  3559. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3560. hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
  3561. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
  3562. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3563. ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
  3564. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
  3565. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3566. imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
  3567. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
  3568. pwrb,
  3569. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3570. exp_statsn) / 32] + 1));
  3571. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
  3572. 0x7);
  3573. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
  3574. pwrb, pwrb_handle->wrb_index);
  3575. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
  3576. pwrb, pwrb_handle->nxt_wrb_index);
  3577. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3578. session_state, pwrb, 0);
  3579. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
  3580. pwrb, 1);
  3581. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
  3582. pwrb, 0);
  3583. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
  3584. 0);
  3585. mem_descr = phba->init_mem;
  3586. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  3587. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3588. pad_buffer_addr_hi, pwrb,
  3589. mem_descr->mem_array[0].bus_address.u.a32.address_hi);
  3590. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3591. pad_buffer_addr_lo, pwrb,
  3592. mem_descr->mem_array[0].bus_address.u.a32.address_lo);
  3593. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
  3594. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3595. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3596. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3597. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3598. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3599. }
  3600. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3601. int *index, int *age)
  3602. {
  3603. *index = (int)itt;
  3604. if (age)
  3605. *age = conn->session->age;
  3606. }
  3607. /**
  3608. * beiscsi_alloc_pdu - allocates pdu and related resources
  3609. * @task: libiscsi task
  3610. * @opcode: opcode of pdu for task
  3611. *
  3612. * This is called with the session lock held. It will allocate
  3613. * the wrb and sgl if needed for the command. And it will prep
  3614. * the pdu's itt. beiscsi_parse_pdu will later translate
  3615. * the pdu itt to the libiscsi task itt.
  3616. */
  3617. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3618. {
  3619. struct beiscsi_io_task *io_task = task->dd_data;
  3620. struct iscsi_conn *conn = task->conn;
  3621. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3622. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3623. struct hwi_wrb_context *pwrb_context;
  3624. struct hwi_controller *phwi_ctrlr;
  3625. itt_t itt;
  3626. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3627. dma_addr_t paddr;
  3628. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3629. GFP_ATOMIC, &paddr);
  3630. if (!io_task->cmd_bhs)
  3631. return -ENOMEM;
  3632. io_task->bhs_pa.u.a64.address = paddr;
  3633. io_task->libiscsi_itt = (itt_t)task->itt;
  3634. io_task->conn = beiscsi_conn;
  3635. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3636. task->hdr_max = sizeof(struct be_cmd_bhs);
  3637. io_task->psgl_handle = NULL;
  3638. io_task->pwrb_handle = NULL;
  3639. if (task->sc) {
  3640. spin_lock(&phba->io_sgl_lock);
  3641. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3642. spin_unlock(&phba->io_sgl_lock);
  3643. if (!io_task->psgl_handle)
  3644. goto free_hndls;
  3645. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3646. beiscsi_conn->beiscsi_conn_cid -
  3647. phba->fw_config.iscsi_cid_start);
  3648. if (!io_task->pwrb_handle)
  3649. goto free_io_hndls;
  3650. } else {
  3651. io_task->scsi_cmnd = NULL;
  3652. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3653. if (!beiscsi_conn->login_in_progress) {
  3654. spin_lock(&phba->mgmt_sgl_lock);
  3655. io_task->psgl_handle = (struct sgl_handle *)
  3656. alloc_mgmt_sgl_handle(phba);
  3657. spin_unlock(&phba->mgmt_sgl_lock);
  3658. if (!io_task->psgl_handle)
  3659. goto free_hndls;
  3660. beiscsi_conn->login_in_progress = 1;
  3661. beiscsi_conn->plogin_sgl_handle =
  3662. io_task->psgl_handle;
  3663. io_task->pwrb_handle =
  3664. alloc_wrb_handle(phba,
  3665. beiscsi_conn->beiscsi_conn_cid -
  3666. phba->fw_config.iscsi_cid_start);
  3667. if (!io_task->pwrb_handle)
  3668. goto free_io_hndls;
  3669. beiscsi_conn->plogin_wrb_handle =
  3670. io_task->pwrb_handle;
  3671. } else {
  3672. io_task->psgl_handle =
  3673. beiscsi_conn->plogin_sgl_handle;
  3674. io_task->pwrb_handle =
  3675. beiscsi_conn->plogin_wrb_handle;
  3676. }
  3677. beiscsi_conn->task = task;
  3678. } else {
  3679. spin_lock(&phba->mgmt_sgl_lock);
  3680. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3681. spin_unlock(&phba->mgmt_sgl_lock);
  3682. if (!io_task->psgl_handle)
  3683. goto free_hndls;
  3684. io_task->pwrb_handle =
  3685. alloc_wrb_handle(phba,
  3686. beiscsi_conn->beiscsi_conn_cid -
  3687. phba->fw_config.iscsi_cid_start);
  3688. if (!io_task->pwrb_handle)
  3689. goto free_mgmt_hndls;
  3690. }
  3691. }
  3692. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3693. wrb_index << 16) | (unsigned int)
  3694. (io_task->psgl_handle->sgl_index));
  3695. io_task->pwrb_handle->pio_handle = task;
  3696. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3697. return 0;
  3698. free_io_hndls:
  3699. spin_lock(&phba->io_sgl_lock);
  3700. free_io_sgl_handle(phba, io_task->psgl_handle);
  3701. spin_unlock(&phba->io_sgl_lock);
  3702. goto free_hndls;
  3703. free_mgmt_hndls:
  3704. spin_lock(&phba->mgmt_sgl_lock);
  3705. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3706. spin_unlock(&phba->mgmt_sgl_lock);
  3707. free_hndls:
  3708. phwi_ctrlr = phba->phwi_ctrlr;
  3709. pwrb_context = &phwi_ctrlr->wrb_context[
  3710. beiscsi_conn->beiscsi_conn_cid -
  3711. phba->fw_config.iscsi_cid_start];
  3712. if (io_task->pwrb_handle)
  3713. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3714. io_task->pwrb_handle = NULL;
  3715. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3716. io_task->bhs_pa.u.a64.address);
  3717. io_task->cmd_bhs = NULL;
  3718. beiscsi_log(phba, KERN_ERR,
  3719. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3720. "BM_%d : Alloc of SGL_ICD Failed\n");
  3721. return -ENOMEM;
  3722. }
  3723. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3724. unsigned int num_sg, unsigned int xferlen,
  3725. unsigned int writedir)
  3726. {
  3727. struct beiscsi_io_task *io_task = task->dd_data;
  3728. struct iscsi_conn *conn = task->conn;
  3729. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3730. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3731. struct iscsi_wrb *pwrb = NULL;
  3732. unsigned int doorbell = 0;
  3733. pwrb = io_task->pwrb_handle->pwrb;
  3734. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3735. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3736. if (writedir) {
  3737. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3738. INI_WR_CMD);
  3739. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3740. } else {
  3741. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3742. INI_RD_CMD);
  3743. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3744. }
  3745. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3746. cpu_to_be16(*(unsigned short *)
  3747. &io_task->cmd_bhs->iscsi_hdr.lun));
  3748. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3749. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3750. io_task->pwrb_handle->wrb_index);
  3751. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3752. be32_to_cpu(task->cmdsn));
  3753. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3754. io_task->psgl_handle->sgl_index);
  3755. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3756. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3757. io_task->pwrb_handle->nxt_wrb_index);
  3758. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3759. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3760. doorbell |= (io_task->pwrb_handle->wrb_index &
  3761. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3762. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3763. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3764. return 0;
  3765. }
  3766. static int beiscsi_mtask(struct iscsi_task *task)
  3767. {
  3768. struct beiscsi_io_task *io_task = task->dd_data;
  3769. struct iscsi_conn *conn = task->conn;
  3770. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3771. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3772. struct iscsi_wrb *pwrb = NULL;
  3773. unsigned int doorbell = 0;
  3774. unsigned int cid;
  3775. cid = beiscsi_conn->beiscsi_conn_cid;
  3776. pwrb = io_task->pwrb_handle->pwrb;
  3777. memset(pwrb, 0, sizeof(*pwrb));
  3778. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3779. be32_to_cpu(task->cmdsn));
  3780. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3781. io_task->pwrb_handle->wrb_index);
  3782. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3783. io_task->psgl_handle->sgl_index);
  3784. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  3785. case ISCSI_OP_LOGIN:
  3786. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3787. TGT_DM_CMD);
  3788. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3789. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  3790. hwi_write_buffer(pwrb, task);
  3791. break;
  3792. case ISCSI_OP_NOOP_OUT:
  3793. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  3794. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3795. TGT_DM_CMD);
  3796. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
  3797. pwrb, 0);
  3798. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
  3799. } else {
  3800. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3801. INI_RD_CMD);
  3802. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3803. }
  3804. hwi_write_buffer(pwrb, task);
  3805. break;
  3806. case ISCSI_OP_TEXT:
  3807. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3808. TGT_DM_CMD);
  3809. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3810. hwi_write_buffer(pwrb, task);
  3811. break;
  3812. case ISCSI_OP_SCSI_TMFUNC:
  3813. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3814. INI_TMF_CMD);
  3815. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3816. hwi_write_buffer(pwrb, task);
  3817. break;
  3818. case ISCSI_OP_LOGOUT:
  3819. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3820. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3821. HWH_TYPE_LOGOUT);
  3822. hwi_write_buffer(pwrb, task);
  3823. break;
  3824. default:
  3825. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3826. "BM_%d : opcode =%d Not supported\n",
  3827. task->hdr->opcode & ISCSI_OPCODE_MASK);
  3828. return -EINVAL;
  3829. }
  3830. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  3831. task->data_count);
  3832. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3833. io_task->pwrb_handle->nxt_wrb_index);
  3834. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3835. doorbell |= cid & DB_WRB_POST_CID_MASK;
  3836. doorbell |= (io_task->pwrb_handle->wrb_index &
  3837. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3838. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3839. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3840. return 0;
  3841. }
  3842. static int beiscsi_task_xmit(struct iscsi_task *task)
  3843. {
  3844. struct beiscsi_io_task *io_task = task->dd_data;
  3845. struct scsi_cmnd *sc = task->sc;
  3846. struct scatterlist *sg;
  3847. int num_sg;
  3848. unsigned int writedir = 0, xferlen = 0;
  3849. if (!sc)
  3850. return beiscsi_mtask(task);
  3851. io_task->scsi_cmnd = sc;
  3852. num_sg = scsi_dma_map(sc);
  3853. if (num_sg < 0) {
  3854. struct iscsi_conn *conn = task->conn;
  3855. struct beiscsi_hba *phba = NULL;
  3856. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  3857. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  3858. "BM_%d : scsi_dma_map Failed\n");
  3859. return num_sg;
  3860. }
  3861. xferlen = scsi_bufflen(sc);
  3862. sg = scsi_sglist(sc);
  3863. if (sc->sc_data_direction == DMA_TO_DEVICE)
  3864. writedir = 1;
  3865. else
  3866. writedir = 0;
  3867. return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
  3868. }
  3869. /**
  3870. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  3871. * @job: job to handle
  3872. */
  3873. static int beiscsi_bsg_request(struct bsg_job *job)
  3874. {
  3875. struct Scsi_Host *shost;
  3876. struct beiscsi_hba *phba;
  3877. struct iscsi_bsg_request *bsg_req = job->request;
  3878. int rc = -EINVAL;
  3879. unsigned int tag;
  3880. struct be_dma_mem nonemb_cmd;
  3881. struct be_cmd_resp_hdr *resp;
  3882. struct iscsi_bsg_reply *bsg_reply = job->reply;
  3883. unsigned short status, extd_status;
  3884. shost = iscsi_job_to_shost(job);
  3885. phba = iscsi_host_priv(shost);
  3886. switch (bsg_req->msgcode) {
  3887. case ISCSI_BSG_HST_VENDOR:
  3888. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3889. job->request_payload.payload_len,
  3890. &nonemb_cmd.dma);
  3891. if (nonemb_cmd.va == NULL) {
  3892. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3893. "BM_%d : Failed to allocate memory for "
  3894. "beiscsi_bsg_request\n");
  3895. return -EIO;
  3896. }
  3897. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  3898. &nonemb_cmd);
  3899. if (!tag) {
  3900. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3901. "BM_%d : be_cmd_get_mac_addr Failed\n");
  3902. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3903. nonemb_cmd.va, nonemb_cmd.dma);
  3904. return -EAGAIN;
  3905. } else
  3906. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3907. phba->ctrl.mcc_numtag[tag]);
  3908. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3909. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3910. free_mcc_tag(&phba->ctrl, tag);
  3911. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  3912. sg_copy_from_buffer(job->reply_payload.sg_list,
  3913. job->reply_payload.sg_cnt,
  3914. nonemb_cmd.va, (resp->response_length
  3915. + sizeof(*resp)));
  3916. bsg_reply->reply_payload_rcv_len = resp->response_length;
  3917. bsg_reply->result = status;
  3918. bsg_job_done(job, bsg_reply->result,
  3919. bsg_reply->reply_payload_rcv_len);
  3920. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3921. nonemb_cmd.va, nonemb_cmd.dma);
  3922. if (status || extd_status) {
  3923. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3924. "BM_%d : be_cmd_get_mac_addr Failed"
  3925. " status = %d extd_status = %d\n",
  3926. status, extd_status);
  3927. return -EIO;
  3928. }
  3929. break;
  3930. default:
  3931. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3932. "BM_%d : Unsupported bsg command: 0x%x\n",
  3933. bsg_req->msgcode);
  3934. break;
  3935. }
  3936. return rc;
  3937. }
  3938. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  3939. {
  3940. /* Set the logging parameter */
  3941. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  3942. }
  3943. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  3944. {
  3945. struct hwi_controller *phwi_ctrlr;
  3946. struct hwi_context_memory *phwi_context;
  3947. struct be_eq_obj *pbe_eq;
  3948. unsigned int i, msix_vec;
  3949. u8 *real_offset = 0;
  3950. u32 value = 0;
  3951. phwi_ctrlr = phba->phwi_ctrlr;
  3952. phwi_context = phwi_ctrlr->phwi_ctxt;
  3953. hwi_disable_intr(phba);
  3954. if (phba->msix_enabled) {
  3955. for (i = 0; i <= phba->num_cpus; i++) {
  3956. msix_vec = phba->msix_entries[i].vector;
  3957. free_irq(msix_vec, &phwi_context->be_eq[i]);
  3958. kfree(phba->msi_name[i]);
  3959. }
  3960. } else
  3961. if (phba->pcidev->irq)
  3962. free_irq(phba->pcidev->irq, phba);
  3963. pci_disable_msix(phba->pcidev);
  3964. destroy_workqueue(phba->wq);
  3965. if (blk_iopoll_enabled)
  3966. for (i = 0; i < phba->num_cpus; i++) {
  3967. pbe_eq = &phwi_context->be_eq[i];
  3968. blk_iopoll_disable(&pbe_eq->iopoll);
  3969. }
  3970. beiscsi_clean_port(phba);
  3971. beiscsi_free_mem(phba);
  3972. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3973. value = readl((void *)real_offset);
  3974. if (value & 0x00010000) {
  3975. value &= 0xfffeffff;
  3976. writel(value, (void *)real_offset);
  3977. }
  3978. beiscsi_unmap_pci_function(phba);
  3979. pci_free_consistent(phba->pcidev,
  3980. phba->ctrl.mbox_mem_alloced.size,
  3981. phba->ctrl.mbox_mem_alloced.va,
  3982. phba->ctrl.mbox_mem_alloced.dma);
  3983. }
  3984. static void beiscsi_remove(struct pci_dev *pcidev)
  3985. {
  3986. struct beiscsi_hba *phba = NULL;
  3987. phba = pci_get_drvdata(pcidev);
  3988. if (!phba) {
  3989. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  3990. return;
  3991. }
  3992. beiscsi_destroy_def_ifaces(phba);
  3993. beiscsi_quiesce(phba);
  3994. iscsi_boot_destroy_kset(phba->boot_kset);
  3995. iscsi_host_remove(phba->shost);
  3996. pci_dev_put(phba->pcidev);
  3997. iscsi_host_free(phba->shost);
  3998. pci_disable_device(pcidev);
  3999. }
  4000. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4001. {
  4002. struct beiscsi_hba *phba = NULL;
  4003. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4004. if (!phba) {
  4005. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4006. return;
  4007. }
  4008. beiscsi_quiesce(phba);
  4009. pci_disable_device(pcidev);
  4010. }
  4011. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4012. {
  4013. int i, status;
  4014. for (i = 0; i <= phba->num_cpus; i++)
  4015. phba->msix_entries[i].entry = i;
  4016. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4017. (phba->num_cpus + 1));
  4018. if (!status)
  4019. phba->msix_enabled = true;
  4020. return;
  4021. }
  4022. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  4023. const struct pci_device_id *id)
  4024. {
  4025. struct beiscsi_hba *phba = NULL;
  4026. struct hwi_controller *phwi_ctrlr;
  4027. struct hwi_context_memory *phwi_context;
  4028. struct be_eq_obj *pbe_eq;
  4029. int ret, num_cpus, i;
  4030. u8 *real_offset = 0;
  4031. u32 value = 0;
  4032. ret = beiscsi_enable_pci(pcidev);
  4033. if (ret < 0) {
  4034. dev_err(&pcidev->dev,
  4035. "beiscsi_dev_probe - Failed to enable pci device\n");
  4036. return ret;
  4037. }
  4038. phba = beiscsi_hba_alloc(pcidev);
  4039. if (!phba) {
  4040. dev_err(&pcidev->dev,
  4041. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4042. goto disable_pci;
  4043. }
  4044. /* Initialize Driver configuration Paramters */
  4045. beiscsi_hba_attrs_init(phba);
  4046. switch (pcidev->device) {
  4047. case BE_DEVICE_ID1:
  4048. case OC_DEVICE_ID1:
  4049. case OC_DEVICE_ID2:
  4050. phba->generation = BE_GEN2;
  4051. break;
  4052. case BE_DEVICE_ID2:
  4053. case OC_DEVICE_ID3:
  4054. phba->generation = BE_GEN3;
  4055. break;
  4056. default:
  4057. phba->generation = 0;
  4058. }
  4059. if (enable_msix)
  4060. num_cpus = find_num_cpus();
  4061. else
  4062. num_cpus = 1;
  4063. phba->num_cpus = num_cpus;
  4064. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4065. "BM_%d : num_cpus = %d\n",
  4066. phba->num_cpus);
  4067. if (enable_msix) {
  4068. beiscsi_msix_enable(phba);
  4069. if (!phba->msix_enabled)
  4070. phba->num_cpus = 1;
  4071. }
  4072. ret = be_ctrl_init(phba, pcidev);
  4073. if (ret) {
  4074. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4075. "BM_%d : beiscsi_dev_probe-"
  4076. "Failed in be_ctrl_init\n");
  4077. goto hba_free;
  4078. }
  4079. if (!num_hba) {
  4080. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  4081. value = readl((void *)real_offset);
  4082. if (value & 0x00010000) {
  4083. gcrashmode++;
  4084. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4085. "BM_%d : Loading Driver in crashdump mode\n");
  4086. ret = beiscsi_cmd_reset_function(phba);
  4087. if (ret) {
  4088. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4089. "BM_%d : Reset Failed. Aborting Crashdump\n");
  4090. goto hba_free;
  4091. }
  4092. ret = be_chk_reset_complete(phba);
  4093. if (ret) {
  4094. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4095. "BM_%d : Failed to get out of reset."
  4096. "Aborting Crashdump\n");
  4097. goto hba_free;
  4098. }
  4099. } else {
  4100. value |= 0x00010000;
  4101. writel(value, (void *)real_offset);
  4102. num_hba++;
  4103. }
  4104. }
  4105. spin_lock_init(&phba->io_sgl_lock);
  4106. spin_lock_init(&phba->mgmt_sgl_lock);
  4107. spin_lock_init(&phba->isr_lock);
  4108. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4109. if (ret != 0) {
  4110. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4111. "BM_%d : Error getting fw config\n");
  4112. goto free_port;
  4113. }
  4114. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  4115. beiscsi_get_params(phba);
  4116. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4117. ret = beiscsi_init_port(phba);
  4118. if (ret < 0) {
  4119. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4120. "BM_%d : beiscsi_dev_probe-"
  4121. "Failed in beiscsi_init_port\n");
  4122. goto free_port;
  4123. }
  4124. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4125. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4126. phba->ctrl.mcc_tag[i] = i + 1;
  4127. phba->ctrl.mcc_numtag[i + 1] = 0;
  4128. phba->ctrl.mcc_tag_available++;
  4129. }
  4130. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4131. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_q_irq%u",
  4132. phba->shost->host_no);
  4133. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  4134. if (!phba->wq) {
  4135. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4136. "BM_%d : beiscsi_dev_probe-"
  4137. "Failed to allocate work queue\n");
  4138. goto free_twq;
  4139. }
  4140. INIT_WORK(&phba->work_cqs, beiscsi_process_all_cqs);
  4141. phwi_ctrlr = phba->phwi_ctrlr;
  4142. phwi_context = phwi_ctrlr->phwi_ctxt;
  4143. if (blk_iopoll_enabled) {
  4144. for (i = 0; i < phba->num_cpus; i++) {
  4145. pbe_eq = &phwi_context->be_eq[i];
  4146. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4147. be_iopoll);
  4148. blk_iopoll_enable(&pbe_eq->iopoll);
  4149. }
  4150. }
  4151. ret = beiscsi_init_irqs(phba);
  4152. if (ret < 0) {
  4153. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4154. "BM_%d : beiscsi_dev_probe-"
  4155. "Failed to beiscsi_init_irqs\n");
  4156. goto free_blkenbld;
  4157. }
  4158. hwi_enable_intr(phba);
  4159. if (beiscsi_setup_boot_info(phba))
  4160. /*
  4161. * log error but continue, because we may not be using
  4162. * iscsi boot.
  4163. */
  4164. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4165. "BM_%d : Could not set up "
  4166. "iSCSI boot info.\n");
  4167. beiscsi_create_def_ifaces(phba);
  4168. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4169. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4170. return 0;
  4171. free_blkenbld:
  4172. destroy_workqueue(phba->wq);
  4173. if (blk_iopoll_enabled)
  4174. for (i = 0; i < phba->num_cpus; i++) {
  4175. pbe_eq = &phwi_context->be_eq[i];
  4176. blk_iopoll_disable(&pbe_eq->iopoll);
  4177. }
  4178. free_twq:
  4179. beiscsi_clean_port(phba);
  4180. beiscsi_free_mem(phba);
  4181. free_port:
  4182. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  4183. value = readl((void *)real_offset);
  4184. if (value & 0x00010000) {
  4185. value &= 0xfffeffff;
  4186. writel(value, (void *)real_offset);
  4187. }
  4188. pci_free_consistent(phba->pcidev,
  4189. phba->ctrl.mbox_mem_alloced.size,
  4190. phba->ctrl.mbox_mem_alloced.va,
  4191. phba->ctrl.mbox_mem_alloced.dma);
  4192. beiscsi_unmap_pci_function(phba);
  4193. hba_free:
  4194. if (phba->msix_enabled)
  4195. pci_disable_msix(phba->pcidev);
  4196. iscsi_host_remove(phba->shost);
  4197. pci_dev_put(phba->pcidev);
  4198. iscsi_host_free(phba->shost);
  4199. disable_pci:
  4200. pci_disable_device(pcidev);
  4201. return ret;
  4202. }
  4203. struct iscsi_transport beiscsi_iscsi_transport = {
  4204. .owner = THIS_MODULE,
  4205. .name = DRV_NAME,
  4206. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4207. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4208. .create_session = beiscsi_session_create,
  4209. .destroy_session = beiscsi_session_destroy,
  4210. .create_conn = beiscsi_conn_create,
  4211. .bind_conn = beiscsi_conn_bind,
  4212. .destroy_conn = iscsi_conn_teardown,
  4213. .attr_is_visible = be2iscsi_attr_is_visible,
  4214. .set_iface_param = be2iscsi_iface_set_param,
  4215. .get_iface_param = be2iscsi_iface_get_param,
  4216. .set_param = beiscsi_set_param,
  4217. .get_conn_param = iscsi_conn_get_param,
  4218. .get_session_param = iscsi_session_get_param,
  4219. .get_host_param = beiscsi_get_host_param,
  4220. .start_conn = beiscsi_conn_start,
  4221. .stop_conn = iscsi_conn_stop,
  4222. .send_pdu = iscsi_conn_send_pdu,
  4223. .xmit_task = beiscsi_task_xmit,
  4224. .cleanup_task = beiscsi_cleanup_task,
  4225. .alloc_pdu = beiscsi_alloc_pdu,
  4226. .parse_pdu_itt = beiscsi_parse_pdu,
  4227. .get_stats = beiscsi_conn_get_stats,
  4228. .get_ep_param = beiscsi_ep_get_param,
  4229. .ep_connect = beiscsi_ep_connect,
  4230. .ep_poll = beiscsi_ep_poll,
  4231. .ep_disconnect = beiscsi_ep_disconnect,
  4232. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4233. .bsg_request = beiscsi_bsg_request,
  4234. };
  4235. static struct pci_driver beiscsi_pci_driver = {
  4236. .name = DRV_NAME,
  4237. .probe = beiscsi_dev_probe,
  4238. .remove = beiscsi_remove,
  4239. .shutdown = beiscsi_shutdown,
  4240. .id_table = beiscsi_pci_id_table
  4241. };
  4242. static int __init beiscsi_module_init(void)
  4243. {
  4244. int ret;
  4245. beiscsi_scsi_transport =
  4246. iscsi_register_transport(&beiscsi_iscsi_transport);
  4247. if (!beiscsi_scsi_transport) {
  4248. printk(KERN_ERR
  4249. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4250. return -ENOMEM;
  4251. }
  4252. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4253. &beiscsi_iscsi_transport);
  4254. ret = pci_register_driver(&beiscsi_pci_driver);
  4255. if (ret) {
  4256. printk(KERN_ERR
  4257. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4258. goto unregister_iscsi_transport;
  4259. }
  4260. return 0;
  4261. unregister_iscsi_transport:
  4262. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4263. return ret;
  4264. }
  4265. static void __exit beiscsi_module_exit(void)
  4266. {
  4267. pci_unregister_driver(&beiscsi_pci_driver);
  4268. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4269. }
  4270. module_init(beiscsi_module_init);
  4271. module_exit(beiscsi_module_exit);