mpc8568mds.dts 9.8 KB

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  1. /*
  2. * MPC8568E MDS Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /*
  12. /memreserve/ 00000000 1000000;
  13. */
  14. / {
  15. model = "MPC8568EMDS";
  16. compatible = "MPC8568EMDS", "MPC85xxMDS";
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. PowerPC,8568@0 {
  23. device_type = "cpu";
  24. reg = <0>;
  25. d-cache-line-size = <20>; // 32 bytes
  26. i-cache-line-size = <20>; // 32 bytes
  27. d-cache-size = <8000>; // L1, 32K
  28. i-cache-size = <8000>; // L1, 32K
  29. timebase-frequency = <0>;
  30. bus-frequency = <0>;
  31. clock-frequency = <0>;
  32. 32-bit;
  33. };
  34. };
  35. memory {
  36. device_type = "memory";
  37. reg = <00000000 10000000>;
  38. };
  39. bcsr@f8000000 {
  40. device_type = "board-control";
  41. reg = <f8000000 8000>;
  42. };
  43. soc8568@e0000000 {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. #interrupt-cells = <2>;
  47. device_type = "soc";
  48. ranges = <0 e0000000 00100000>;
  49. reg = <e0000000 00100000>;
  50. bus-frequency = <0>;
  51. memory-controller@2000 {
  52. compatible = "fsl,8568-memory-controller";
  53. reg = <2000 1000>;
  54. interrupt-parent = <&mpic>;
  55. interrupts = <12 2>;
  56. };
  57. l2-cache-controller@20000 {
  58. compatible = "fsl,8568-l2-cache-controller";
  59. reg = <20000 1000>;
  60. cache-line-size = <20>; // 32 bytes
  61. cache-size = <80000>; // L2, 512K
  62. interrupt-parent = <&mpic>;
  63. interrupts = <10 2>;
  64. };
  65. i2c@3000 {
  66. device_type = "i2c";
  67. compatible = "fsl-i2c";
  68. reg = <3000 100>;
  69. interrupts = <2b 2>;
  70. interrupt-parent = <&mpic>;
  71. dfsrr;
  72. };
  73. i2c@3100 {
  74. device_type = "i2c";
  75. compatible = "fsl-i2c";
  76. reg = <3100 100>;
  77. interrupts = <2b 2>;
  78. interrupt-parent = <&mpic>;
  79. dfsrr;
  80. };
  81. mdio@24520 {
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. device_type = "mdio";
  85. compatible = "gianfar";
  86. reg = <24520 20>;
  87. phy0: ethernet-phy@0 {
  88. interrupt-parent = <&mpic>;
  89. interrupts = <1 1>;
  90. reg = <0>;
  91. device_type = "ethernet-phy";
  92. };
  93. phy1: ethernet-phy@1 {
  94. interrupt-parent = <&mpic>;
  95. interrupts = <2 1>;
  96. reg = <1>;
  97. device_type = "ethernet-phy";
  98. };
  99. phy2: ethernet-phy@2 {
  100. interrupt-parent = <&mpic>;
  101. interrupts = <1 1>;
  102. reg = <2>;
  103. device_type = "ethernet-phy";
  104. };
  105. phy3: ethernet-phy@3 {
  106. interrupt-parent = <&mpic>;
  107. interrupts = <2 1>;
  108. reg = <3>;
  109. device_type = "ethernet-phy";
  110. };
  111. };
  112. ethernet@24000 {
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115. device_type = "network";
  116. model = "eTSEC";
  117. compatible = "gianfar";
  118. reg = <24000 1000>;
  119. /*
  120. * mac-address is deprecated and will be removed
  121. * in 2.6.25. Only recent versions of
  122. * U-Boot support local-mac-address, however.
  123. */
  124. mac-address = [ 00 00 00 00 00 00 ];
  125. local-mac-address = [ 00 00 00 00 00 00 ];
  126. interrupts = <1d 2 1e 2 22 2>;
  127. interrupt-parent = <&mpic>;
  128. phy-handle = <&phy2>;
  129. };
  130. ethernet@25000 {
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. device_type = "network";
  134. model = "eTSEC";
  135. compatible = "gianfar";
  136. reg = <25000 1000>;
  137. /*
  138. * mac-address is deprecated and will be removed
  139. * in 2.6.25. Only recent versions of
  140. * U-Boot support local-mac-address, however.
  141. */
  142. mac-address = [ 00 00 00 00 00 00 ];
  143. local-mac-address = [ 00 00 00 00 00 00 ];
  144. interrupts = <23 2 24 2 28 2>;
  145. interrupt-parent = <&mpic>;
  146. phy-handle = <&phy3>;
  147. };
  148. serial@4500 {
  149. device_type = "serial";
  150. compatible = "ns16550";
  151. reg = <4500 100>;
  152. clock-frequency = <0>;
  153. interrupts = <2a 2>;
  154. interrupt-parent = <&mpic>;
  155. };
  156. pci@8000 {
  157. interrupt-map-mask = <f800 0 0 7>;
  158. interrupt-map = <
  159. /* IDSEL 0x12 AD18 */
  160. 9000 0 0 1 &mpic 5 1
  161. 9000 0 0 2 &mpic 6 1
  162. 9000 0 0 3 &mpic 7 1
  163. 9000 0 0 4 &mpic 4 1
  164. /* IDSEL 0x13 AD19 */
  165. 9800 0 0 1 &mpic 6 1
  166. 9800 0 0 2 &mpic 7 1
  167. 9800 0 0 3 &mpic 4 1
  168. 9800 0 0 4 &mpic 5 1>;
  169. interrupt-parent = <&mpic>;
  170. interrupts = <18 2>;
  171. bus-range = <0 ff>;
  172. ranges = <02000000 0 80000000 80000000 0 20000000
  173. 01000000 0 00000000 e2000000 0 00800000>;
  174. clock-frequency = <3f940aa>;
  175. #interrupt-cells = <1>;
  176. #size-cells = <2>;
  177. #address-cells = <3>;
  178. reg = <8000 1000>;
  179. compatible = "fsl,mpc8540-pci";
  180. device_type = "pci";
  181. };
  182. serial@4600 {
  183. device_type = "serial";
  184. compatible = "ns16550";
  185. reg = <4600 100>;
  186. clock-frequency = <0>;
  187. interrupts = <2a 2>;
  188. interrupt-parent = <&mpic>;
  189. };
  190. crypto@30000 {
  191. device_type = "crypto";
  192. model = "SEC2";
  193. compatible = "talitos";
  194. reg = <30000 f000>;
  195. interrupts = <2d 2>;
  196. interrupt-parent = <&mpic>;
  197. num-channels = <4>;
  198. channel-fifo-len = <18>;
  199. exec-units-mask = <000000fe>;
  200. descriptor-types-mask = <012b0ebf>;
  201. };
  202. mpic: pic@40000 {
  203. clock-frequency = <0>;
  204. interrupt-controller;
  205. #address-cells = <0>;
  206. #interrupt-cells = <2>;
  207. reg = <40000 40000>;
  208. built-in;
  209. compatible = "chrp,open-pic";
  210. device_type = "open-pic";
  211. big-endian;
  212. };
  213. par_io@e0100 {
  214. reg = <e0100 100>;
  215. device_type = "par_io";
  216. num-ports = <7>;
  217. pio1: ucc_pin@01 {
  218. pio-map = <
  219. /* port pin dir open_drain assignment has_irq */
  220. 4 0a 1 0 2 0 /* TxD0 */
  221. 4 09 1 0 2 0 /* TxD1 */
  222. 4 08 1 0 2 0 /* TxD2 */
  223. 4 07 1 0 2 0 /* TxD3 */
  224. 4 17 1 0 2 0 /* TxD4 */
  225. 4 16 1 0 2 0 /* TxD5 */
  226. 4 15 1 0 2 0 /* TxD6 */
  227. 4 14 1 0 2 0 /* TxD7 */
  228. 4 0f 2 0 2 0 /* RxD0 */
  229. 4 0e 2 0 2 0 /* RxD1 */
  230. 4 0d 2 0 2 0 /* RxD2 */
  231. 4 0c 2 0 2 0 /* RxD3 */
  232. 4 1d 2 0 2 0 /* RxD4 */
  233. 4 1c 2 0 2 0 /* RxD5 */
  234. 4 1b 2 0 2 0 /* RxD6 */
  235. 4 1a 2 0 2 0 /* RxD7 */
  236. 4 0b 1 0 2 0 /* TX_EN */
  237. 4 18 1 0 2 0 /* TX_ER */
  238. 4 0f 2 0 2 0 /* RX_DV */
  239. 4 1e 2 0 2 0 /* RX_ER */
  240. 4 11 2 0 2 0 /* RX_CLK */
  241. 4 13 1 0 2 0 /* GTX_CLK */
  242. 1 1f 2 0 3 0>; /* GTX125 */
  243. };
  244. pio2: ucc_pin@02 {
  245. pio-map = <
  246. /* port pin dir open_drain assignment has_irq */
  247. 5 0a 1 0 2 0 /* TxD0 */
  248. 5 09 1 0 2 0 /* TxD1 */
  249. 5 08 1 0 2 0 /* TxD2 */
  250. 5 07 1 0 2 0 /* TxD3 */
  251. 5 17 1 0 2 0 /* TxD4 */
  252. 5 16 1 0 2 0 /* TxD5 */
  253. 5 15 1 0 2 0 /* TxD6 */
  254. 5 14 1 0 2 0 /* TxD7 */
  255. 5 0f 2 0 2 0 /* RxD0 */
  256. 5 0e 2 0 2 0 /* RxD1 */
  257. 5 0d 2 0 2 0 /* RxD2 */
  258. 5 0c 2 0 2 0 /* RxD3 */
  259. 5 1d 2 0 2 0 /* RxD4 */
  260. 5 1c 2 0 2 0 /* RxD5 */
  261. 5 1b 2 0 2 0 /* RxD6 */
  262. 5 1a 2 0 2 0 /* RxD7 */
  263. 5 0b 1 0 2 0 /* TX_EN */
  264. 5 18 1 0 2 0 /* TX_ER */
  265. 5 10 2 0 2 0 /* RX_DV */
  266. 5 1e 2 0 2 0 /* RX_ER */
  267. 5 11 2 0 2 0 /* RX_CLK */
  268. 5 13 1 0 2 0 /* GTX_CLK */
  269. 1 1f 2 0 3 0 /* GTX125 */
  270. 4 06 3 0 2 0 /* MDIO */
  271. 4 05 1 0 2 0>; /* MDC */
  272. };
  273. };
  274. };
  275. qe@e0080000 {
  276. #address-cells = <1>;
  277. #size-cells = <1>;
  278. device_type = "qe";
  279. model = "QE";
  280. ranges = <0 e0080000 00040000>;
  281. reg = <e0080000 480>;
  282. brg-frequency = <0>;
  283. bus-frequency = <179A7B00>;
  284. muram@10000 {
  285. device_type = "muram";
  286. ranges = <0 00010000 0000c000>;
  287. data-only@0{
  288. reg = <0 c000>;
  289. };
  290. };
  291. spi@4c0 {
  292. device_type = "spi";
  293. compatible = "fsl_spi";
  294. reg = <4c0 40>;
  295. interrupts = <2>;
  296. interrupt-parent = <&qeic>;
  297. mode = "cpu";
  298. };
  299. spi@500 {
  300. device_type = "spi";
  301. compatible = "fsl_spi";
  302. reg = <500 40>;
  303. interrupts = <1>;
  304. interrupt-parent = <&qeic>;
  305. mode = "cpu";
  306. };
  307. ucc@2000 {
  308. device_type = "network";
  309. compatible = "ucc_geth";
  310. model = "UCC";
  311. device-id = <1>;
  312. reg = <2000 200>;
  313. interrupts = <20>;
  314. interrupt-parent = <&qeic>;
  315. /*
  316. * mac-address is deprecated and will be removed
  317. * in 2.6.25. Only recent versions of
  318. * U-Boot support local-mac-address, however.
  319. */
  320. mac-address = [ 00 00 00 00 00 00 ];
  321. local-mac-address = [ 00 00 00 00 00 00 ];
  322. rx-clock = <0>;
  323. tx-clock = <19>;
  324. phy-handle = <&qe_phy0>;
  325. phy-connection-type = "gmii";
  326. pio-handle = <&pio1>;
  327. };
  328. ucc@3000 {
  329. device_type = "network";
  330. compatible = "ucc_geth";
  331. model = "UCC";
  332. device-id = <2>;
  333. reg = <3000 200>;
  334. interrupts = <21>;
  335. interrupt-parent = <&qeic>;
  336. /*
  337. * mac-address is deprecated and will be removed
  338. * in 2.6.25. Only recent versions of
  339. * U-Boot support local-mac-address, however.
  340. */
  341. mac-address = [ 00 00 00 00 00 00 ];
  342. local-mac-address = [ 00 00 00 00 00 00 ];
  343. rx-clock = <0>;
  344. tx-clock = <14>;
  345. phy-handle = <&qe_phy1>;
  346. phy-connection-type = "gmii";
  347. pio-handle = <&pio2>;
  348. };
  349. mdio@2120 {
  350. #address-cells = <1>;
  351. #size-cells = <0>;
  352. reg = <2120 18>;
  353. device_type = "mdio";
  354. compatible = "ucc_geth_phy";
  355. /* These are the same PHYs as on
  356. * gianfar's MDIO bus */
  357. qe_phy0: ethernet-phy@00 {
  358. interrupt-parent = <&mpic>;
  359. interrupts = <1 1>;
  360. reg = <0>;
  361. device_type = "ethernet-phy";
  362. };
  363. qe_phy1: ethernet-phy@01 {
  364. interrupt-parent = <&mpic>;
  365. interrupts = <2 1>;
  366. reg = <1>;
  367. device_type = "ethernet-phy";
  368. };
  369. qe_phy2: ethernet-phy@02 {
  370. interrupt-parent = <&mpic>;
  371. interrupts = <1 1>;
  372. reg = <2>;
  373. device_type = "ethernet-phy";
  374. };
  375. qe_phy3: ethernet-phy@03 {
  376. interrupt-parent = <&mpic>;
  377. interrupts = <2 1>;
  378. reg = <3>;
  379. device_type = "ethernet-phy";
  380. };
  381. };
  382. qeic: qeic@80 {
  383. interrupt-controller;
  384. device_type = "qeic";
  385. #address-cells = <0>;
  386. #interrupt-cells = <1>;
  387. reg = <80 80>;
  388. built-in;
  389. big-endian;
  390. interrupts = <2e 2 2e 2>; //high:30 low:30
  391. interrupt-parent = <&mpic>;
  392. };
  393. };
  394. };