pwm-imx.c 6.7 KB

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  1. /*
  2. * simple driver for PWM (Pulse Width Modulator) controller
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/err.h>
  15. #include <linux/clk.h>
  16. #include <linux/io.h>
  17. #include <linux/pwm.h>
  18. #include <mach/hardware.h>
  19. /* i.MX1 and i.MX21 share the same PWM function block: */
  20. #define MX1_PWMC 0x00 /* PWM Control Register */
  21. #define MX1_PWMS 0x04 /* PWM Sample Register */
  22. #define MX1_PWMP 0x08 /* PWM Period Register */
  23. #define MX1_PWMC_EN (1 << 4)
  24. /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
  25. #define MX3_PWMCR 0x00 /* PWM Control Register */
  26. #define MX3_PWMSAR 0x0C /* PWM Sample Register */
  27. #define MX3_PWMPR 0x10 /* PWM Period Register */
  28. #define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
  29. #define MX3_PWMCR_DOZEEN (1 << 24)
  30. #define MX3_PWMCR_WAITEN (1 << 23)
  31. #define MX3_PWMCR_DBGEN (1 << 22)
  32. #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
  33. #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
  34. #define MX3_PWMCR_EN (1 << 0)
  35. struct imx_chip {
  36. struct clk *clk;
  37. int enabled;
  38. void __iomem *mmio_base;
  39. struct pwm_chip chip;
  40. int (*config)(struct pwm_chip *chip,
  41. struct pwm_device *pwm, int duty_ns, int period_ns);
  42. void (*set_enable)(struct pwm_chip *chip, bool enable);
  43. };
  44. #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
  45. static int imx_pwm_config_v1(struct pwm_chip *chip,
  46. struct pwm_device *pwm, int duty_ns, int period_ns)
  47. {
  48. struct imx_chip *imx = to_imx_chip(chip);
  49. /*
  50. * The PWM subsystem allows for exact frequencies. However,
  51. * I cannot connect a scope on my device to the PWM line and
  52. * thus cannot provide the program the PWM controller
  53. * exactly. Instead, I'm relying on the fact that the
  54. * Bootloader (u-boot or WinCE+haret) has programmed the PWM
  55. * function group already. So I'll just modify the PWM sample
  56. * register to follow the ratio of duty_ns vs. period_ns
  57. * accordingly.
  58. *
  59. * This is good enough for programming the brightness of
  60. * the LCD backlight.
  61. *
  62. * The real implementation would divide PERCLK[0] first by
  63. * both the prescaler (/1 .. /128) and then by CLKSEL
  64. * (/2 .. /16).
  65. */
  66. u32 max = readl(imx->mmio_base + MX1_PWMP);
  67. u32 p = max * duty_ns / period_ns;
  68. writel(max - p, imx->mmio_base + MX1_PWMS);
  69. return 0;
  70. }
  71. static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
  72. {
  73. struct imx_chip *imx = to_imx_chip(chip);
  74. u32 val;
  75. val = readl(imx->mmio_base + MX1_PWMC);
  76. if (enable)
  77. val |= MX1_PWMC_EN;
  78. else
  79. val &= ~MX1_PWMC_EN;
  80. writel(val, imx->mmio_base + MX1_PWMC);
  81. }
  82. static int imx_pwm_config_v2(struct pwm_chip *chip,
  83. struct pwm_device *pwm, int duty_ns, int period_ns)
  84. {
  85. struct imx_chip *imx = to_imx_chip(chip);
  86. unsigned long long c;
  87. unsigned long period_cycles, duty_cycles, prescale;
  88. u32 cr;
  89. c = clk_get_rate(imx->clk);
  90. c = c * period_ns;
  91. do_div(c, 1000000000);
  92. period_cycles = c;
  93. prescale = period_cycles / 0x10000 + 1;
  94. period_cycles /= prescale;
  95. c = (unsigned long long)period_cycles * duty_ns;
  96. do_div(c, period_ns);
  97. duty_cycles = c;
  98. /*
  99. * according to imx pwm RM, the real period value should be
  100. * PERIOD value in PWMPR plus 2.
  101. */
  102. if (period_cycles > 2)
  103. period_cycles -= 2;
  104. else
  105. period_cycles = 0;
  106. writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
  107. writel(period_cycles, imx->mmio_base + MX3_PWMPR);
  108. cr = MX3_PWMCR_PRESCALER(prescale) |
  109. MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
  110. MX3_PWMCR_DBGEN;
  111. if (imx->enabled)
  112. cr |= MX3_PWMCR_EN;
  113. if (cpu_is_mx25())
  114. cr |= MX3_PWMCR_CLKSRC_IPG;
  115. else
  116. cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
  117. writel(cr, imx->mmio_base + MX3_PWMCR);
  118. return 0;
  119. }
  120. static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
  121. {
  122. struct imx_chip *imx = to_imx_chip(chip);
  123. u32 val;
  124. val = readl(imx->mmio_base + MX3_PWMCR);
  125. if (enable)
  126. val |= MX3_PWMCR_EN;
  127. else
  128. val &= ~MX3_PWMCR_EN;
  129. writel(val, imx->mmio_base + MX3_PWMCR);
  130. }
  131. static int imx_pwm_config(struct pwm_chip *chip,
  132. struct pwm_device *pwm, int duty_ns, int period_ns)
  133. {
  134. struct imx_chip *imx = to_imx_chip(chip);
  135. return imx->config(chip, pwm, duty_ns, period_ns);
  136. }
  137. static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  138. {
  139. struct imx_chip *imx = to_imx_chip(chip);
  140. int ret;
  141. ret = clk_prepare_enable(imx->clk);
  142. if (ret)
  143. return ret;
  144. imx->set_enable(chip, true);
  145. imx->enabled = 1;
  146. return 0;
  147. }
  148. static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  149. {
  150. struct imx_chip *imx = to_imx_chip(chip);
  151. imx->set_enable(chip, false);
  152. clk_disable_unprepare(imx->clk);
  153. imx->enabled = 0;
  154. }
  155. static struct pwm_ops imx_pwm_ops = {
  156. .enable = imx_pwm_enable,
  157. .disable = imx_pwm_disable,
  158. .config = imx_pwm_config,
  159. .owner = THIS_MODULE,
  160. };
  161. static int __devinit imx_pwm_probe(struct platform_device *pdev)
  162. {
  163. struct imx_chip *imx;
  164. struct resource *r;
  165. int ret = 0;
  166. imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
  167. if (imx == NULL) {
  168. dev_err(&pdev->dev, "failed to allocate memory\n");
  169. return -ENOMEM;
  170. }
  171. imx->clk = devm_clk_get(&pdev->dev, "pwm");
  172. if (IS_ERR(imx->clk))
  173. return PTR_ERR(imx->clk);
  174. imx->chip.ops = &imx_pwm_ops;
  175. imx->chip.dev = &pdev->dev;
  176. imx->chip.base = -1;
  177. imx->chip.npwm = 1;
  178. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  179. if (r == NULL) {
  180. dev_err(&pdev->dev, "no memory resource defined\n");
  181. return -ENODEV;
  182. }
  183. imx->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
  184. if (imx->mmio_base == NULL)
  185. return -EADDRNOTAVAIL;
  186. if (cpu_is_mx1() || cpu_is_mx21()) {
  187. imx->config = imx_pwm_config_v1;
  188. imx->set_enable = imx_pwm_set_enable_v1;
  189. } else {
  190. imx->config = imx_pwm_config_v2;
  191. imx->set_enable = imx_pwm_set_enable_v2;
  192. }
  193. ret = pwmchip_add(&imx->chip);
  194. if (ret < 0)
  195. return ret;
  196. platform_set_drvdata(pdev, imx);
  197. return 0;
  198. }
  199. static int __devexit imx_pwm_remove(struct platform_device *pdev)
  200. {
  201. struct imx_chip *imx;
  202. imx = platform_get_drvdata(pdev);
  203. if (imx == NULL)
  204. return -ENODEV;
  205. return pwmchip_remove(&imx->chip);
  206. }
  207. static struct platform_driver imx_pwm_driver = {
  208. .driver = {
  209. .name = "mxc_pwm",
  210. },
  211. .probe = imx_pwm_probe,
  212. .remove = __devexit_p(imx_pwm_remove),
  213. };
  214. static int __init imx_pwm_init(void)
  215. {
  216. return platform_driver_register(&imx_pwm_driver);
  217. }
  218. arch_initcall(imx_pwm_init);
  219. static void __exit imx_pwm_exit(void)
  220. {
  221. platform_driver_unregister(&imx_pwm_driver);
  222. }
  223. module_exit(imx_pwm_exit);
  224. MODULE_LICENSE("GPL v2");
  225. MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");