cx23885-417.c 48 KB

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  1. /*
  2. *
  3. * Support for a cx23417 mpeg encoder via cx23885 host port.
  4. *
  5. * (c) 2004 Jelle Foks <jelle@foks.us>
  6. * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
  7. * (c) 2008 Steven Toth <stoth@linuxtv.org>
  8. * - CX23885/7/8 support
  9. *
  10. * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25. */
  26. #include <linux/module.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/init.h>
  29. #include <linux/fs.h>
  30. #include <linux/delay.h>
  31. #include <linux/device.h>
  32. #include <linux/firmware.h>
  33. #include <linux/smp_lock.h>
  34. #include <media/v4l2-common.h>
  35. #include <media/v4l2-ioctl.h>
  36. #include <media/cx2341x.h>
  37. #include "cx23885.h"
  38. #define CX23885_FIRM_IMAGE_SIZE 376836
  39. #define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
  40. static unsigned int mpegbufs = 32;
  41. module_param(mpegbufs, int, 0644);
  42. MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
  43. static unsigned int mpeglines = 32;
  44. module_param(mpeglines, int, 0644);
  45. MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
  46. static unsigned int mpeglinesize = 512;
  47. module_param(mpeglinesize, int, 0644);
  48. MODULE_PARM_DESC(mpeglinesize,
  49. "number of bytes in each line of an MPEG buffer, range 512-1024");
  50. static unsigned int v4l_debug;
  51. module_param(v4l_debug, int, 0644);
  52. MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
  53. #define dprintk(level, fmt, arg...)\
  54. do { if (v4l_debug >= level) \
  55. printk(KERN_DEBUG "%s: " fmt, \
  56. (dev) ? dev->name : "cx23885[?]", ## arg); \
  57. } while (0)
  58. static struct cx23885_tvnorm cx23885_tvnorms[] = {
  59. {
  60. .name = "NTSC-M",
  61. .id = V4L2_STD_NTSC_M,
  62. }, {
  63. .name = "NTSC-JP",
  64. .id = V4L2_STD_NTSC_M_JP,
  65. }, {
  66. .name = "PAL-BG",
  67. .id = V4L2_STD_PAL_BG,
  68. }, {
  69. .name = "PAL-DK",
  70. .id = V4L2_STD_PAL_DK,
  71. }, {
  72. .name = "PAL-I",
  73. .id = V4L2_STD_PAL_I,
  74. }, {
  75. .name = "PAL-M",
  76. .id = V4L2_STD_PAL_M,
  77. }, {
  78. .name = "PAL-N",
  79. .id = V4L2_STD_PAL_N,
  80. }, {
  81. .name = "PAL-Nc",
  82. .id = V4L2_STD_PAL_Nc,
  83. }, {
  84. .name = "PAL-60",
  85. .id = V4L2_STD_PAL_60,
  86. }, {
  87. .name = "SECAM-L",
  88. .id = V4L2_STD_SECAM_L,
  89. }, {
  90. .name = "SECAM-DK",
  91. .id = V4L2_STD_SECAM_DK,
  92. }
  93. };
  94. /* ------------------------------------------------------------------ */
  95. enum cx23885_capture_type {
  96. CX23885_MPEG_CAPTURE,
  97. CX23885_RAW_CAPTURE,
  98. CX23885_RAW_PASSTHRU_CAPTURE
  99. };
  100. enum cx23885_capture_bits {
  101. CX23885_RAW_BITS_NONE = 0x00,
  102. CX23885_RAW_BITS_YUV_CAPTURE = 0x01,
  103. CX23885_RAW_BITS_PCM_CAPTURE = 0x02,
  104. CX23885_RAW_BITS_VBI_CAPTURE = 0x04,
  105. CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
  106. CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10
  107. };
  108. enum cx23885_capture_end {
  109. CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */
  110. CX23885_END_NOW, /* stop immediately, no irq */
  111. };
  112. enum cx23885_framerate {
  113. CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */
  114. CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */
  115. };
  116. enum cx23885_stream_port {
  117. CX23885_OUTPUT_PORT_MEMORY,
  118. CX23885_OUTPUT_PORT_STREAMING,
  119. CX23885_OUTPUT_PORT_SERIAL
  120. };
  121. enum cx23885_data_xfer_status {
  122. CX23885_MORE_BUFFERS_FOLLOW,
  123. CX23885_LAST_BUFFER,
  124. };
  125. enum cx23885_picture_mask {
  126. CX23885_PICTURE_MASK_NONE,
  127. CX23885_PICTURE_MASK_I_FRAMES,
  128. CX23885_PICTURE_MASK_I_P_FRAMES = 0x3,
  129. CX23885_PICTURE_MASK_ALL_FRAMES = 0x7,
  130. };
  131. enum cx23885_vbi_mode_bits {
  132. CX23885_VBI_BITS_SLICED,
  133. CX23885_VBI_BITS_RAW,
  134. };
  135. enum cx23885_vbi_insertion_bits {
  136. CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
  137. CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
  138. CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
  139. CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
  140. CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
  141. };
  142. enum cx23885_dma_unit {
  143. CX23885_DMA_BYTES,
  144. CX23885_DMA_FRAMES,
  145. };
  146. enum cx23885_dma_transfer_status_bits {
  147. CX23885_DMA_TRANSFER_BITS_DONE = 0x01,
  148. CX23885_DMA_TRANSFER_BITS_ERROR = 0x04,
  149. CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
  150. };
  151. enum cx23885_pause {
  152. CX23885_PAUSE_ENCODING,
  153. CX23885_RESUME_ENCODING,
  154. };
  155. enum cx23885_copyright {
  156. CX23885_COPYRIGHT_OFF,
  157. CX23885_COPYRIGHT_ON,
  158. };
  159. enum cx23885_notification_type {
  160. CX23885_NOTIFICATION_REFRESH,
  161. };
  162. enum cx23885_notification_status {
  163. CX23885_NOTIFICATION_OFF,
  164. CX23885_NOTIFICATION_ON,
  165. };
  166. enum cx23885_notification_mailbox {
  167. CX23885_NOTIFICATION_NO_MAILBOX = -1,
  168. };
  169. enum cx23885_field1_lines {
  170. CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */
  171. CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */
  172. CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */
  173. };
  174. enum cx23885_field2_lines {
  175. CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */
  176. CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */
  177. CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */
  178. };
  179. enum cx23885_custom_data_type {
  180. CX23885_CUSTOM_EXTENSION_USR_DATA,
  181. CX23885_CUSTOM_PRIVATE_PACKET,
  182. };
  183. enum cx23885_mute {
  184. CX23885_UNMUTE,
  185. CX23885_MUTE,
  186. };
  187. enum cx23885_mute_video_mask {
  188. CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00,
  189. CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000,
  190. CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000,
  191. };
  192. enum cx23885_mute_video_shift {
  193. CX23885_MUTE_VIDEO_V_SHIFT = 8,
  194. CX23885_MUTE_VIDEO_U_SHIFT = 16,
  195. CX23885_MUTE_VIDEO_Y_SHIFT = 24,
  196. };
  197. /* defines below are from ivtv-driver.h */
  198. #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
  199. /* Firmware API commands */
  200. #define IVTV_API_STD_TIMEOUT 500
  201. /* Registers */
  202. /* IVTV_REG_OFFSET */
  203. #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
  204. #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
  205. #define IVTV_REG_SPU (0x9050)
  206. #define IVTV_REG_HW_BLOCKS (0x9054)
  207. #define IVTV_REG_VPU (0x9058)
  208. #define IVTV_REG_APU (0xA064)
  209. /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
  210. bits 31-16
  211. +-----------+
  212. | Reserved |
  213. +-----------+
  214. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
  215. +-------+-------+-------+-------+-------+-------+-------+-------+
  216. | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
  217. +-------+-------+-------+-------+-------+-------+-------+-------+
  218. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
  219. +-------+-------+-------+-------+-------+-------+-------+-------+
  220. |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
  221. +-------+-------+-------+-------+-------+-------+-------+-------+
  222. ***/
  223. #define MC417_MIWR 0x8000
  224. #define MC417_MIRD 0x4000
  225. #define MC417_MICS 0x2000
  226. #define MC417_MIRDY 0x1000
  227. #define MC417_MIADDR 0x0F00
  228. #define MC417_MIDATA 0x00FF
  229. /* MIADDR* nibble definitions */
  230. #define MCI_MEMORY_DATA_BYTE0 0x000
  231. #define MCI_MEMORY_DATA_BYTE1 0x100
  232. #define MCI_MEMORY_DATA_BYTE2 0x200
  233. #define MCI_MEMORY_DATA_BYTE3 0x300
  234. #define MCI_MEMORY_ADDRESS_BYTE2 0x400
  235. #define MCI_MEMORY_ADDRESS_BYTE1 0x500
  236. #define MCI_MEMORY_ADDRESS_BYTE0 0x600
  237. #define MCI_REGISTER_DATA_BYTE0 0x800
  238. #define MCI_REGISTER_DATA_BYTE1 0x900
  239. #define MCI_REGISTER_DATA_BYTE2 0xA00
  240. #define MCI_REGISTER_DATA_BYTE3 0xB00
  241. #define MCI_REGISTER_ADDRESS_BYTE0 0xC00
  242. #define MCI_REGISTER_ADDRESS_BYTE1 0xD00
  243. #define MCI_REGISTER_MODE 0xE00
  244. /* Read and write modes */
  245. #define MCI_MODE_REGISTER_READ 0
  246. #define MCI_MODE_REGISTER_WRITE 1
  247. #define MCI_MODE_MEMORY_READ 0
  248. #define MCI_MODE_MEMORY_WRITE 0x40
  249. /*** Bit definitions for MC417_CTL register ****
  250. bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
  251. +--------+-------------+--------+--------------+------------+
  252. |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
  253. +--------+-------------+--------+--------------+------------+
  254. ***/
  255. #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
  256. #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
  257. #define MC417_UART_GPIO_EN 0x00000001
  258. /* Values for speed control */
  259. #define MC417_SPD_CTL_SLOW 0x1
  260. #define MC417_SPD_CTL_MEDIUM 0x0
  261. #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
  262. /* Values for GPIO select */
  263. #define MC417_GPIO_SEL_GPIO3 0x3
  264. #define MC417_GPIO_SEL_GPIO2 0x2
  265. #define MC417_GPIO_SEL_GPIO1 0x1
  266. #define MC417_GPIO_SEL_GPIO0 0x0
  267. void cx23885_mc417_init(struct cx23885_dev *dev)
  268. {
  269. u32 regval;
  270. dprintk(2, "%s()\n", __func__);
  271. /* Configure MC417_CTL register to defaults. */
  272. regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) |
  273. MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) |
  274. MC417_UART_GPIO_EN;
  275. cx_write(MC417_CTL, regval);
  276. /* Configure MC417_OEN to defaults. */
  277. regval = MC417_MIRDY;
  278. cx_write(MC417_OEN, regval);
  279. /* Configure MC417_RWD to defaults. */
  280. regval = MC417_MIWR | MC417_MIRD | MC417_MICS;
  281. cx_write(MC417_RWD, regval);
  282. }
  283. static int mc417_wait_ready(struct cx23885_dev *dev)
  284. {
  285. u32 mi_ready;
  286. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  287. for (;;) {
  288. mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
  289. if (mi_ready != 0)
  290. return 0;
  291. if (time_after(jiffies, timeout))
  292. return -1;
  293. udelay(1);
  294. }
  295. }
  296. static int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value)
  297. {
  298. u32 regval;
  299. /* Enable MC417 GPIO outputs except for MC417_MIRDY,
  300. * which is an input.
  301. */
  302. cx_write(MC417_OEN, MC417_MIRDY);
  303. /* Write data byte 0 */
  304. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |
  305. (value & 0x000000FF);
  306. cx_write(MC417_RWD, regval);
  307. /* Transition CS/WR to effect write transaction across bus. */
  308. regval |= MC417_MICS | MC417_MIWR;
  309. cx_write(MC417_RWD, regval);
  310. /* Write data byte 1 */
  311. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 |
  312. ((value >> 8) & 0x000000FF);
  313. cx_write(MC417_RWD, regval);
  314. regval |= MC417_MICS | MC417_MIWR;
  315. cx_write(MC417_RWD, regval);
  316. /* Write data byte 2 */
  317. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 |
  318. ((value >> 16) & 0x000000FF);
  319. cx_write(MC417_RWD, regval);
  320. regval |= MC417_MICS | MC417_MIWR;
  321. cx_write(MC417_RWD, regval);
  322. /* Write data byte 3 */
  323. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 |
  324. ((value >> 24) & 0x000000FF);
  325. cx_write(MC417_RWD, regval);
  326. regval |= MC417_MICS | MC417_MIWR;
  327. cx_write(MC417_RWD, regval);
  328. /* Write address byte 0 */
  329. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
  330. (address & 0xFF);
  331. cx_write(MC417_RWD, regval);
  332. regval |= MC417_MICS | MC417_MIWR;
  333. cx_write(MC417_RWD, regval);
  334. /* Write address byte 1 */
  335. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
  336. ((address >> 8) & 0xFF);
  337. cx_write(MC417_RWD, regval);
  338. regval |= MC417_MICS | MC417_MIWR;
  339. cx_write(MC417_RWD, regval);
  340. /* Indicate that this is a write. */
  341. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
  342. MCI_MODE_REGISTER_WRITE;
  343. cx_write(MC417_RWD, regval);
  344. regval |= MC417_MICS | MC417_MIWR;
  345. cx_write(MC417_RWD, regval);
  346. /* Wait for the trans to complete (MC417_MIRDY asserted). */
  347. return mc417_wait_ready(dev);
  348. }
  349. static int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value)
  350. {
  351. int retval;
  352. u32 regval;
  353. u32 tempval;
  354. u32 dataval;
  355. /* Enable MC417 GPIO outputs except for MC417_MIRDY,
  356. * which is an input.
  357. */
  358. cx_write(MC417_OEN, MC417_MIRDY);
  359. /* Write address byte 0 */
  360. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
  361. ((address & 0x00FF));
  362. cx_write(MC417_RWD, regval);
  363. regval |= MC417_MICS | MC417_MIWR;
  364. cx_write(MC417_RWD, regval);
  365. /* Write address byte 1 */
  366. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
  367. ((address >> 8) & 0xFF);
  368. cx_write(MC417_RWD, regval);
  369. regval |= MC417_MICS | MC417_MIWR;
  370. cx_write(MC417_RWD, regval);
  371. /* Indicate that this is a register read. */
  372. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
  373. MCI_MODE_REGISTER_READ;
  374. cx_write(MC417_RWD, regval);
  375. regval |= MC417_MICS | MC417_MIWR;
  376. cx_write(MC417_RWD, regval);
  377. /* Wait for the trans to complete (MC417_MIRDY asserted). */
  378. retval = mc417_wait_ready(dev);
  379. /* switch the DAT0-7 GPIO[10:3] to input mode */
  380. cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
  381. /* Read data byte 0 */
  382. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
  383. cx_write(MC417_RWD, regval);
  384. /* Transition RD to effect read transaction across bus.
  385. * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
  386. * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
  387. * input only...)
  388. */
  389. regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
  390. cx_write(MC417_RWD, regval);
  391. /* Collect byte */
  392. tempval = cx_read(MC417_RWD);
  393. dataval = tempval & 0x000000FF;
  394. /* Bring CS and RD high. */
  395. regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
  396. cx_write(MC417_RWD, regval);
  397. /* Read data byte 1 */
  398. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
  399. cx_write(MC417_RWD, regval);
  400. regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
  401. cx_write(MC417_RWD, regval);
  402. tempval = cx_read(MC417_RWD);
  403. dataval |= ((tempval & 0x000000FF) << 8);
  404. regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
  405. cx_write(MC417_RWD, regval);
  406. /* Read data byte 2 */
  407. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
  408. cx_write(MC417_RWD, regval);
  409. regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
  410. cx_write(MC417_RWD, regval);
  411. tempval = cx_read(MC417_RWD);
  412. dataval |= ((tempval & 0x000000FF) << 16);
  413. regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
  414. cx_write(MC417_RWD, regval);
  415. /* Read data byte 3 */
  416. regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
  417. cx_write(MC417_RWD, regval);
  418. regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
  419. cx_write(MC417_RWD, regval);
  420. tempval = cx_read(MC417_RWD);
  421. dataval |= ((tempval & 0x000000FF) << 24);
  422. regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
  423. cx_write(MC417_RWD, regval);
  424. *value = dataval;
  425. return retval;
  426. }
  427. int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value)
  428. {
  429. u32 regval;
  430. /* Enable MC417 GPIO outputs except for MC417_MIRDY,
  431. * which is an input.
  432. */
  433. cx_write(MC417_OEN, MC417_MIRDY);
  434. /* Write data byte 0 */
  435. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 |
  436. (value & 0x000000FF);
  437. cx_write(MC417_RWD, regval);
  438. /* Transition CS/WR to effect write transaction across bus. */
  439. regval |= MC417_MICS | MC417_MIWR;
  440. cx_write(MC417_RWD, regval);
  441. /* Write data byte 1 */
  442. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 |
  443. ((value >> 8) & 0x000000FF);
  444. cx_write(MC417_RWD, regval);
  445. regval |= MC417_MICS | MC417_MIWR;
  446. cx_write(MC417_RWD, regval);
  447. /* Write data byte 2 */
  448. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 |
  449. ((value >> 16) & 0x000000FF);
  450. cx_write(MC417_RWD, regval);
  451. regval |= MC417_MICS | MC417_MIWR;
  452. cx_write(MC417_RWD, regval);
  453. /* Write data byte 3 */
  454. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 |
  455. ((value >> 24) & 0x000000FF);
  456. cx_write(MC417_RWD, regval);
  457. regval |= MC417_MICS | MC417_MIWR;
  458. cx_write(MC417_RWD, regval);
  459. /* Write address byte 2 */
  460. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
  461. MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F);
  462. cx_write(MC417_RWD, regval);
  463. regval |= MC417_MICS | MC417_MIWR;
  464. cx_write(MC417_RWD, regval);
  465. /* Write address byte 1 */
  466. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
  467. ((address >> 8) & 0xFF);
  468. cx_write(MC417_RWD, regval);
  469. regval |= MC417_MICS | MC417_MIWR;
  470. cx_write(MC417_RWD, regval);
  471. /* Write address byte 0 */
  472. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
  473. (address & 0xFF);
  474. cx_write(MC417_RWD, regval);
  475. regval |= MC417_MICS | MC417_MIWR;
  476. cx_write(MC417_RWD, regval);
  477. /* Wait for the trans to complete (MC417_MIRDY asserted). */
  478. return mc417_wait_ready(dev);
  479. }
  480. int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value)
  481. {
  482. int retval;
  483. u32 regval;
  484. u32 tempval;
  485. u32 dataval;
  486. /* Enable MC417 GPIO outputs except for MC417_MIRDY,
  487. * which is an input.
  488. */
  489. cx_write(MC417_OEN, MC417_MIRDY);
  490. /* Write address byte 2 */
  491. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
  492. MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F);
  493. cx_write(MC417_RWD, regval);
  494. regval |= MC417_MICS | MC417_MIWR;
  495. cx_write(MC417_RWD, regval);
  496. /* Write address byte 1 */
  497. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
  498. ((address >> 8) & 0xFF);
  499. cx_write(MC417_RWD, regval);
  500. regval |= MC417_MICS | MC417_MIWR;
  501. cx_write(MC417_RWD, regval);
  502. /* Write address byte 0 */
  503. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
  504. (address & 0xFF);
  505. cx_write(MC417_RWD, regval);
  506. regval |= MC417_MICS | MC417_MIWR;
  507. cx_write(MC417_RWD, regval);
  508. /* Wait for the trans to complete (MC417_MIRDY asserted). */
  509. retval = mc417_wait_ready(dev);
  510. /* switch the DAT0-7 GPIO[10:3] to input mode */
  511. cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
  512. /* Read data byte 3 */
  513. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
  514. cx_write(MC417_RWD, regval);
  515. /* Transition RD to effect read transaction across bus. */
  516. regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
  517. cx_write(MC417_RWD, regval);
  518. /* Collect byte */
  519. tempval = cx_read(MC417_RWD);
  520. dataval = ((tempval & 0x000000FF) << 24);
  521. /* Bring CS and RD high. */
  522. regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
  523. cx_write(MC417_RWD, regval);
  524. /* Read data byte 2 */
  525. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
  526. cx_write(MC417_RWD, regval);
  527. regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
  528. cx_write(MC417_RWD, regval);
  529. tempval = cx_read(MC417_RWD);
  530. dataval |= ((tempval & 0x000000FF) << 16);
  531. regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
  532. cx_write(MC417_RWD, regval);
  533. /* Read data byte 1 */
  534. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
  535. cx_write(MC417_RWD, regval);
  536. regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
  537. cx_write(MC417_RWD, regval);
  538. tempval = cx_read(MC417_RWD);
  539. dataval |= ((tempval & 0x000000FF) << 8);
  540. regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
  541. cx_write(MC417_RWD, regval);
  542. /* Read data byte 0 */
  543. regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
  544. cx_write(MC417_RWD, regval);
  545. regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
  546. cx_write(MC417_RWD, regval);
  547. tempval = cx_read(MC417_RWD);
  548. dataval |= (tempval & 0x000000FF);
  549. regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
  550. cx_write(MC417_RWD, regval);
  551. *value = dataval;
  552. return retval;
  553. }
  554. /* ------------------------------------------------------------------ */
  555. /* MPEG encoder API */
  556. static char *cmd_to_str(int cmd)
  557. {
  558. switch (cmd) {
  559. case CX2341X_ENC_PING_FW:
  560. return "PING_FW";
  561. case CX2341X_ENC_START_CAPTURE:
  562. return "START_CAPTURE";
  563. case CX2341X_ENC_STOP_CAPTURE:
  564. return "STOP_CAPTURE";
  565. case CX2341X_ENC_SET_AUDIO_ID:
  566. return "SET_AUDIO_ID";
  567. case CX2341X_ENC_SET_VIDEO_ID:
  568. return "SET_VIDEO_ID";
  569. case CX2341X_ENC_SET_PCR_ID:
  570. return "SET_PCR_PID";
  571. case CX2341X_ENC_SET_FRAME_RATE:
  572. return "SET_FRAME_RATE";
  573. case CX2341X_ENC_SET_FRAME_SIZE:
  574. return "SET_FRAME_SIZE";
  575. case CX2341X_ENC_SET_BIT_RATE:
  576. return "SET_BIT_RATE";
  577. case CX2341X_ENC_SET_GOP_PROPERTIES:
  578. return "SET_GOP_PROPERTIES";
  579. case CX2341X_ENC_SET_ASPECT_RATIO:
  580. return "SET_ASPECT_RATIO";
  581. case CX2341X_ENC_SET_DNR_FILTER_MODE:
  582. return "SET_DNR_FILTER_PROPS";
  583. case CX2341X_ENC_SET_DNR_FILTER_PROPS:
  584. return "SET_DNR_FILTER_PROPS";
  585. case CX2341X_ENC_SET_CORING_LEVELS:
  586. return "SET_CORING_LEVELS";
  587. case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
  588. return "SET_SPATIAL_FILTER_TYPE";
  589. case CX2341X_ENC_SET_VBI_LINE:
  590. return "SET_VBI_LINE";
  591. case CX2341X_ENC_SET_STREAM_TYPE:
  592. return "SET_STREAM_TYPE";
  593. case CX2341X_ENC_SET_OUTPUT_PORT:
  594. return "SET_OUTPUT_PORT";
  595. case CX2341X_ENC_SET_AUDIO_PROPERTIES:
  596. return "SET_AUDIO_PROPERTIES";
  597. case CX2341X_ENC_HALT_FW:
  598. return "HALT_FW";
  599. case CX2341X_ENC_GET_VERSION:
  600. return "GET_VERSION";
  601. case CX2341X_ENC_SET_GOP_CLOSURE:
  602. return "SET_GOP_CLOSURE";
  603. case CX2341X_ENC_GET_SEQ_END:
  604. return "GET_SEQ_END";
  605. case CX2341X_ENC_SET_PGM_INDEX_INFO:
  606. return "SET_PGM_INDEX_INFO";
  607. case CX2341X_ENC_SET_VBI_CONFIG:
  608. return "SET_VBI_CONFIG";
  609. case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
  610. return "SET_DMA_BLOCK_SIZE";
  611. case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
  612. return "GET_PREV_DMA_INFO_MB_10";
  613. case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
  614. return "GET_PREV_DMA_INFO_MB_9";
  615. case CX2341X_ENC_SCHED_DMA_TO_HOST:
  616. return "SCHED_DMA_TO_HOST";
  617. case CX2341X_ENC_INITIALIZE_INPUT:
  618. return "INITIALIZE_INPUT";
  619. case CX2341X_ENC_SET_FRAME_DROP_RATE:
  620. return "SET_FRAME_DROP_RATE";
  621. case CX2341X_ENC_PAUSE_ENCODER:
  622. return "PAUSE_ENCODER";
  623. case CX2341X_ENC_REFRESH_INPUT:
  624. return "REFRESH_INPUT";
  625. case CX2341X_ENC_SET_COPYRIGHT:
  626. return "SET_COPYRIGHT";
  627. case CX2341X_ENC_SET_EVENT_NOTIFICATION:
  628. return "SET_EVENT_NOTIFICATION";
  629. case CX2341X_ENC_SET_NUM_VSYNC_LINES:
  630. return "SET_NUM_VSYNC_LINES";
  631. case CX2341X_ENC_SET_PLACEHOLDER:
  632. return "SET_PLACEHOLDER";
  633. case CX2341X_ENC_MUTE_VIDEO:
  634. return "MUTE_VIDEO";
  635. case CX2341X_ENC_MUTE_AUDIO:
  636. return "MUTE_AUDIO";
  637. case CX2341X_ENC_MISC:
  638. return "MISC";
  639. default:
  640. return "UNKNOWN";
  641. }
  642. }
  643. static int cx23885_mbox_func(void *priv,
  644. u32 command,
  645. int in,
  646. int out,
  647. u32 data[CX2341X_MBOX_MAX_DATA])
  648. {
  649. struct cx23885_dev *dev = priv;
  650. unsigned long timeout;
  651. u32 value, flag, retval = 0;
  652. int i;
  653. dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
  654. cmd_to_str(command));
  655. /* this may not be 100% safe if we can't read any memory location
  656. without side effects */
  657. mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
  658. if (value != 0x12345678) {
  659. printk(KERN_ERR
  660. "Firmware and/or mailbox pointer not initialized "
  661. "or corrupted, signature = 0x%x, cmd = %s\n", value,
  662. cmd_to_str(command));
  663. return -1;
  664. }
  665. /* This read looks at 32 bits, but flag is only 8 bits.
  666. * Seems we also bail if CMD or TIMEOUT bytes are set???
  667. */
  668. mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
  669. if (flag) {
  670. printk(KERN_ERR "ERROR: Mailbox appears to be in use "
  671. "(%x), cmd = %s\n", flag, cmd_to_str(command));
  672. return -1;
  673. }
  674. flag |= 1; /* tell 'em we're working on it */
  675. mc417_memory_write(dev, dev->cx23417_mailbox, flag);
  676. /* write command + args + fill remaining with zeros */
  677. /* command code */
  678. mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
  679. mc417_memory_write(dev, dev->cx23417_mailbox + 3,
  680. IVTV_API_STD_TIMEOUT); /* timeout */
  681. for (i = 0; i < in; i++) {
  682. mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
  683. dprintk(3, "API Input %d = %d\n", i, data[i]);
  684. }
  685. for (; i < CX2341X_MBOX_MAX_DATA; i++)
  686. mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
  687. flag |= 3; /* tell 'em we're done writing */
  688. mc417_memory_write(dev, dev->cx23417_mailbox, flag);
  689. /* wait for firmware to handle the API command */
  690. timeout = jiffies + msecs_to_jiffies(10);
  691. for (;;) {
  692. mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
  693. if (0 != (flag & 4))
  694. break;
  695. if (time_after(jiffies, timeout)) {
  696. printk(KERN_ERR "ERROR: API Mailbox timeout\n");
  697. return -1;
  698. }
  699. udelay(10);
  700. }
  701. /* read output values */
  702. for (i = 0; i < out; i++) {
  703. mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
  704. dprintk(3, "API Output %d = %d\n", i, data[i]);
  705. }
  706. mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
  707. dprintk(3, "API result = %d\n", retval);
  708. flag = 0;
  709. mc417_memory_write(dev, dev->cx23417_mailbox, flag);
  710. return retval;
  711. }
  712. /* We don't need to call the API often, so using just one
  713. * mailbox will probably suffice
  714. */
  715. static int cx23885_api_cmd(struct cx23885_dev *dev,
  716. u32 command,
  717. u32 inputcnt,
  718. u32 outputcnt,
  719. ...)
  720. {
  721. u32 data[CX2341X_MBOX_MAX_DATA];
  722. va_list vargs;
  723. int i, err;
  724. dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
  725. va_start(vargs, outputcnt);
  726. for (i = 0; i < inputcnt; i++)
  727. data[i] = va_arg(vargs, int);
  728. err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data);
  729. for (i = 0; i < outputcnt; i++) {
  730. int *vptr = va_arg(vargs, int *);
  731. *vptr = data[i];
  732. }
  733. va_end(vargs);
  734. return err;
  735. }
  736. static int cx23885_find_mailbox(struct cx23885_dev *dev)
  737. {
  738. u32 signature[4] = {
  739. 0x12345678, 0x34567812, 0x56781234, 0x78123456
  740. };
  741. int signaturecnt = 0;
  742. u32 value;
  743. int i;
  744. dprintk(2, "%s()\n", __func__);
  745. for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) {
  746. mc417_memory_read(dev, i, &value);
  747. if (value == signature[signaturecnt])
  748. signaturecnt++;
  749. else
  750. signaturecnt = 0;
  751. if (4 == signaturecnt) {
  752. dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
  753. return i+1;
  754. }
  755. }
  756. printk(KERN_ERR "Mailbox signature values not found!\n");
  757. return -1;
  758. }
  759. static int cx23885_load_firmware(struct cx23885_dev *dev)
  760. {
  761. static const unsigned char magic[8] = {
  762. 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
  763. };
  764. const struct firmware *firmware;
  765. int i, retval = 0;
  766. u32 value = 0;
  767. u32 gpio_output = 0;
  768. u32 checksum = 0;
  769. u32 *dataptr;
  770. dprintk(2, "%s()\n", __func__);
  771. /* Save GPIO settings before reset of APU */
  772. retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
  773. retval |= mc417_memory_read(dev, 0x900C, &value);
  774. retval = mc417_register_write(dev,
  775. IVTV_REG_VPU, 0xFFFFFFED);
  776. retval |= mc417_register_write(dev,
  777. IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
  778. retval |= mc417_register_write(dev,
  779. IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
  780. retval |= mc417_register_write(dev,
  781. IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
  782. retval |= mc417_register_write(dev,
  783. IVTV_REG_APU, 0);
  784. if (retval != 0) {
  785. printk(KERN_ERR "%s: Error with mc417_register_write\n",
  786. __func__);
  787. return -1;
  788. }
  789. retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME,
  790. &dev->pci->dev);
  791. if (retval != 0) {
  792. printk(KERN_ERR
  793. "ERROR: Hotplug firmware request failed (%s).\n",
  794. CX23885_FIRM_IMAGE_NAME);
  795. printk(KERN_ERR "Please fix your hotplug setup, the board will "
  796. "not work without firmware loaded!\n");
  797. return -1;
  798. }
  799. if (firmware->size != CX23885_FIRM_IMAGE_SIZE) {
  800. printk(KERN_ERR "ERROR: Firmware size mismatch "
  801. "(have %zd, expected %d)\n",
  802. firmware->size, CX23885_FIRM_IMAGE_SIZE);
  803. release_firmware(firmware);
  804. return -1;
  805. }
  806. if (0 != memcmp(firmware->data, magic, 8)) {
  807. printk(KERN_ERR
  808. "ERROR: Firmware magic mismatch, wrong file?\n");
  809. release_firmware(firmware);
  810. return -1;
  811. }
  812. /* transfer to the chip */
  813. dprintk(2, "Loading firmware ...\n");
  814. dataptr = (u32 *)firmware->data;
  815. for (i = 0; i < (firmware->size >> 2); i++) {
  816. value = *dataptr;
  817. checksum += ~value;
  818. if (mc417_memory_write(dev, i, value) != 0) {
  819. printk(KERN_ERR "ERROR: Loading firmware failed!\n");
  820. release_firmware(firmware);
  821. return -1;
  822. }
  823. dataptr++;
  824. }
  825. /* read back to verify with the checksum */
  826. dprintk(1, "Verifying firmware ...\n");
  827. for (i--; i >= 0; i--) {
  828. if (mc417_memory_read(dev, i, &value) != 0) {
  829. printk(KERN_ERR "ERROR: Reading firmware failed!\n");
  830. release_firmware(firmware);
  831. return -1;
  832. }
  833. checksum -= ~value;
  834. }
  835. if (checksum) {
  836. printk(KERN_ERR
  837. "ERROR: Firmware load failed (checksum mismatch).\n");
  838. release_firmware(firmware);
  839. return -1;
  840. }
  841. release_firmware(firmware);
  842. dprintk(1, "Firmware upload successful.\n");
  843. retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
  844. IVTV_CMD_HW_BLOCKS_RST);
  845. /* Restore GPIO settings, make sure EIO14 is enabled as an output. */
  846. dprintk(2, "%s: GPIO output EIO 0-15 was = 0x%x\n",
  847. __func__, gpio_output);
  848. /* Power-up seems to have GPIOs AFU. This was causing digital side
  849. * to fail at power-up. Seems GPIOs should be set to 0x10ff0411 at
  850. * power-up.
  851. * gpio_output |= (1<<14);
  852. */
  853. /* Note: GPIO14 is specific to the HVR1800 here */
  854. gpio_output = 0x10ff0411 | (1<<14);
  855. retval |= mc417_register_write(dev, 0x9020, gpio_output | (1<<14));
  856. dprintk(2, "%s: GPIO output EIO 0-15 now = 0x%x\n",
  857. __func__, gpio_output);
  858. dprintk(1, "%s: GPIO value EIO 0-15 was = 0x%x\n",
  859. __func__, value);
  860. value |= (1<<14);
  861. dprintk(1, "%s: GPIO value EIO 0-15 now = 0x%x\n",
  862. __func__, value);
  863. retval |= mc417_register_write(dev, 0x900C, value);
  864. retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
  865. retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
  866. if (retval < 0)
  867. printk(KERN_ERR "%s: Error with mc417_register_write\n",
  868. __func__);
  869. return 0;
  870. }
  871. void cx23885_417_check_encoder(struct cx23885_dev *dev)
  872. {
  873. u32 status, seq;
  874. status = seq = 0;
  875. cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
  876. dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
  877. }
  878. static void cx23885_codec_settings(struct cx23885_dev *dev)
  879. {
  880. dprintk(1, "%s()\n", __func__);
  881. /* assign frame size */
  882. cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
  883. dev->ts1.height, dev->ts1.width);
  884. dev->mpeg_params.width = dev->ts1.width;
  885. dev->mpeg_params.height = dev->ts1.height;
  886. dev->mpeg_params.is_50hz =
  887. (dev->encodernorm.id & V4L2_STD_625_50) != 0;
  888. cx2341x_update(dev, cx23885_mbox_func, NULL, &dev->mpeg_params);
  889. cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
  890. cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
  891. }
  892. static int cx23885_initialize_codec(struct cx23885_dev *dev)
  893. {
  894. int version;
  895. int retval;
  896. u32 i, data[7];
  897. dprintk(1, "%s()\n", __func__);
  898. retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
  899. if (retval < 0) {
  900. dprintk(2, "%s() PING OK\n", __func__);
  901. retval = cx23885_load_firmware(dev);
  902. if (retval < 0) {
  903. printk(KERN_ERR "%s() f/w load failed\n", __func__);
  904. return retval;
  905. }
  906. retval = cx23885_find_mailbox(dev);
  907. if (retval < 0) {
  908. printk(KERN_ERR "%s() mailbox < 0, error\n",
  909. __func__);
  910. return -1;
  911. }
  912. dev->cx23417_mailbox = retval;
  913. retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
  914. if (retval < 0) {
  915. printk(KERN_ERR
  916. "ERROR: cx23417 firmware ping failed!\n");
  917. return -1;
  918. }
  919. retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
  920. &version);
  921. if (retval < 0) {
  922. printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
  923. "version failed!\n");
  924. return -1;
  925. }
  926. dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
  927. msleep(200);
  928. }
  929. cx23885_codec_settings(dev);
  930. msleep(60);
  931. cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
  932. CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115);
  933. cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
  934. CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  935. 0, 0);
  936. /* Setup to capture VBI */
  937. data[0] = 0x0001BD00;
  938. data[1] = 1; /* frames per interrupt */
  939. data[2] = 4; /* total bufs */
  940. data[3] = 0x91559155; /* start codes */
  941. data[4] = 0x206080C0; /* stop codes */
  942. data[5] = 6; /* lines */
  943. data[6] = 64; /* BPL */
  944. cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
  945. data[2], data[3], data[4], data[5], data[6]);
  946. for (i = 2; i <= 24; i++) {
  947. int valid;
  948. valid = ((i >= 19) && (i <= 21));
  949. cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
  950. valid, 0 , 0, 0);
  951. cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
  952. i | 0x80000000, valid, 0, 0, 0);
  953. }
  954. cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE);
  955. msleep(60);
  956. /* initialize the video input */
  957. cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
  958. msleep(60);
  959. /* Enable VIP style pixel invalidation so we work with scaled mode */
  960. mc417_memory_write(dev, 2120, 0x00000080);
  961. /* start capturing to the host interface */
  962. cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
  963. CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE);
  964. msleep(10);
  965. return 0;
  966. }
  967. /* ------------------------------------------------------------------ */
  968. static int bb_buf_setup(struct videobuf_queue *q,
  969. unsigned int *count, unsigned int *size)
  970. {
  971. struct cx23885_fh *fh = q->priv_data;
  972. fh->dev->ts1.ts_packet_size = mpeglinesize;
  973. fh->dev->ts1.ts_packet_count = mpeglines;
  974. *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
  975. *count = mpegbufs;
  976. return 0;
  977. }
  978. static int bb_buf_prepare(struct videobuf_queue *q,
  979. struct videobuf_buffer *vb, enum v4l2_field field)
  980. {
  981. struct cx23885_fh *fh = q->priv_data;
  982. return cx23885_buf_prepare(q, &fh->dev->ts1,
  983. (struct cx23885_buffer *)vb,
  984. field);
  985. }
  986. static void bb_buf_queue(struct videobuf_queue *q,
  987. struct videobuf_buffer *vb)
  988. {
  989. struct cx23885_fh *fh = q->priv_data;
  990. cx23885_buf_queue(&fh->dev->ts1, (struct cx23885_buffer *)vb);
  991. }
  992. static void bb_buf_release(struct videobuf_queue *q,
  993. struct videobuf_buffer *vb)
  994. {
  995. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  996. }
  997. static struct videobuf_queue_ops cx23885_qops = {
  998. .buf_setup = bb_buf_setup,
  999. .buf_prepare = bb_buf_prepare,
  1000. .buf_queue = bb_buf_queue,
  1001. .buf_release = bb_buf_release,
  1002. };
  1003. /* ------------------------------------------------------------------ */
  1004. static const u32 *ctrl_classes[] = {
  1005. cx2341x_mpeg_ctrls,
  1006. NULL
  1007. };
  1008. static int cx23885_queryctrl(struct cx23885_dev *dev,
  1009. struct v4l2_queryctrl *qctrl)
  1010. {
  1011. qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
  1012. if (qctrl->id == 0)
  1013. return -EINVAL;
  1014. /* MPEG V4L2 controls */
  1015. if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
  1016. qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
  1017. return 0;
  1018. }
  1019. static int cx23885_querymenu(struct cx23885_dev *dev,
  1020. struct v4l2_querymenu *qmenu)
  1021. {
  1022. struct v4l2_queryctrl qctrl;
  1023. qctrl.id = qmenu->id;
  1024. cx23885_queryctrl(dev, &qctrl);
  1025. return v4l2_ctrl_query_menu(qmenu, &qctrl,
  1026. cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
  1027. }
  1028. static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
  1029. {
  1030. struct cx23885_fh *fh = file->private_data;
  1031. struct cx23885_dev *dev = fh->dev;
  1032. unsigned int i;
  1033. for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++)
  1034. if (*id & cx23885_tvnorms[i].id)
  1035. break;
  1036. if (i == ARRAY_SIZE(cx23885_tvnorms))
  1037. return -EINVAL;
  1038. dev->encodernorm = cx23885_tvnorms[i];
  1039. return 0;
  1040. }
  1041. static int vidioc_enum_input(struct file *file, void *priv,
  1042. struct v4l2_input *i)
  1043. {
  1044. struct cx23885_fh *fh = file->private_data;
  1045. struct cx23885_dev *dev = fh->dev;
  1046. struct cx23885_input *input;
  1047. int n;
  1048. if (i->index >= 4)
  1049. return -EINVAL;
  1050. input = &cx23885_boards[dev->board].input[i->index];
  1051. if (input->type == 0)
  1052. return -EINVAL;
  1053. /* FIXME
  1054. * strcpy(i->name, input->name); */
  1055. strcpy(i->name, "unset");
  1056. if (input->type == CX23885_VMUX_TELEVISION ||
  1057. input->type == CX23885_VMUX_CABLE)
  1058. i->type = V4L2_INPUT_TYPE_TUNER;
  1059. else
  1060. i->type = V4L2_INPUT_TYPE_CAMERA;
  1061. for (n = 0; n < ARRAY_SIZE(cx23885_tvnorms); n++)
  1062. i->std |= cx23885_tvnorms[n].id;
  1063. return 0;
  1064. }
  1065. static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
  1066. {
  1067. struct cx23885_fh *fh = file->private_data;
  1068. struct cx23885_dev *dev = fh->dev;
  1069. *i = dev->input;
  1070. return 0;
  1071. }
  1072. static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
  1073. {
  1074. if (i >= 4)
  1075. return -EINVAL;
  1076. return 0;
  1077. }
  1078. static int vidioc_g_tuner(struct file *file, void *priv,
  1079. struct v4l2_tuner *t)
  1080. {
  1081. struct cx23885_fh *fh = file->private_data;
  1082. struct cx23885_dev *dev = fh->dev;
  1083. if (UNSET == dev->tuner_type)
  1084. return -EINVAL;
  1085. if (0 != t->index)
  1086. return -EINVAL;
  1087. strcpy(t->name, "Television");
  1088. call_all(dev, tuner, g_tuner, t);
  1089. dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type);
  1090. return 0;
  1091. }
  1092. static int vidioc_s_tuner(struct file *file, void *priv,
  1093. struct v4l2_tuner *t)
  1094. {
  1095. struct cx23885_fh *fh = file->private_data;
  1096. struct cx23885_dev *dev = fh->dev;
  1097. if (UNSET == dev->tuner_type)
  1098. return -EINVAL;
  1099. /* Update the A/V core */
  1100. call_all(dev, tuner, s_tuner, t);
  1101. return 0;
  1102. }
  1103. static int vidioc_g_frequency(struct file *file, void *priv,
  1104. struct v4l2_frequency *f)
  1105. {
  1106. struct cx23885_fh *fh = file->private_data;
  1107. struct cx23885_dev *dev = fh->dev;
  1108. if (UNSET == dev->tuner_type)
  1109. return -EINVAL;
  1110. f->type = V4L2_TUNER_ANALOG_TV;
  1111. f->frequency = dev->freq;
  1112. call_all(dev, tuner, g_frequency, f);
  1113. return 0;
  1114. }
  1115. static int vidioc_s_frequency(struct file *file, void *priv,
  1116. struct v4l2_frequency *f)
  1117. {
  1118. struct cx23885_fh *fh = file->private_data;
  1119. struct cx23885_dev *dev = fh->dev;
  1120. cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
  1121. CX23885_END_NOW, CX23885_MPEG_CAPTURE,
  1122. CX23885_RAW_BITS_NONE);
  1123. dprintk(1, "VIDIOC_S_FREQUENCY: dev type %d, f\n",
  1124. dev->tuner_type);
  1125. dprintk(1, "VIDIOC_S_FREQUENCY: f tuner %d, f type %d\n",
  1126. f->tuner, f->type);
  1127. if (UNSET == dev->tuner_type)
  1128. return -EINVAL;
  1129. if (f->tuner != 0)
  1130. return -EINVAL;
  1131. if (f->type != V4L2_TUNER_ANALOG_TV)
  1132. return -EINVAL;
  1133. dev->freq = f->frequency;
  1134. call_all(dev, tuner, s_frequency, f);
  1135. cx23885_initialize_codec(dev);
  1136. return 0;
  1137. }
  1138. static int vidioc_s_ctrl(struct file *file, void *priv,
  1139. struct v4l2_control *ctl)
  1140. {
  1141. struct cx23885_fh *fh = file->private_data;
  1142. struct cx23885_dev *dev = fh->dev;
  1143. /* Update the A/V core */
  1144. call_all(dev, core, s_ctrl, ctl);
  1145. return 0;
  1146. }
  1147. static int vidioc_querycap(struct file *file, void *priv,
  1148. struct v4l2_capability *cap)
  1149. {
  1150. struct cx23885_fh *fh = file->private_data;
  1151. struct cx23885_dev *dev = fh->dev;
  1152. struct cx23885_tsport *tsport = &dev->ts1;
  1153. strcpy(cap->driver, dev->name);
  1154. strlcpy(cap->card, cx23885_boards[tsport->dev->board].name,
  1155. sizeof(cap->card));
  1156. sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
  1157. cap->version = CX23885_VERSION_CODE;
  1158. cap->capabilities =
  1159. V4L2_CAP_VIDEO_CAPTURE |
  1160. V4L2_CAP_READWRITE |
  1161. V4L2_CAP_STREAMING |
  1162. 0;
  1163. if (UNSET != dev->tuner_type)
  1164. cap->capabilities |= V4L2_CAP_TUNER;
  1165. return 0;
  1166. }
  1167. static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
  1168. struct v4l2_fmtdesc *f)
  1169. {
  1170. if (f->index != 0)
  1171. return -EINVAL;
  1172. strlcpy(f->description, "MPEG", sizeof(f->description));
  1173. f->pixelformat = V4L2_PIX_FMT_MPEG;
  1174. return 0;
  1175. }
  1176. static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
  1177. struct v4l2_format *f)
  1178. {
  1179. struct cx23885_fh *fh = file->private_data;
  1180. struct cx23885_dev *dev = fh->dev;
  1181. f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
  1182. f->fmt.pix.bytesperline = 0;
  1183. f->fmt.pix.sizeimage =
  1184. dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
  1185. f->fmt.pix.colorspace = 0;
  1186. f->fmt.pix.width = dev->ts1.width;
  1187. f->fmt.pix.height = dev->ts1.height;
  1188. f->fmt.pix.field = fh->mpegq.field;
  1189. dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
  1190. dev->ts1.width, dev->ts1.height, fh->mpegq.field);
  1191. return 0;
  1192. }
  1193. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  1194. struct v4l2_format *f)
  1195. {
  1196. struct cx23885_fh *fh = file->private_data;
  1197. struct cx23885_dev *dev = fh->dev;
  1198. f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
  1199. f->fmt.pix.bytesperline = 0;
  1200. f->fmt.pix.sizeimage =
  1201. dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
  1202. f->fmt.pix.colorspace = 0;
  1203. dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
  1204. dev->ts1.width, dev->ts1.height, fh->mpegq.field);
  1205. return 0;
  1206. }
  1207. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  1208. struct v4l2_format *f)
  1209. {
  1210. struct cx23885_fh *fh = file->private_data;
  1211. struct cx23885_dev *dev = fh->dev;
  1212. f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
  1213. f->fmt.pix.bytesperline = 0;
  1214. f->fmt.pix.sizeimage =
  1215. dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
  1216. f->fmt.pix.colorspace = 0;
  1217. dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n",
  1218. f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field);
  1219. return 0;
  1220. }
  1221. static int vidioc_reqbufs(struct file *file, void *priv,
  1222. struct v4l2_requestbuffers *p)
  1223. {
  1224. struct cx23885_fh *fh = file->private_data;
  1225. return videobuf_reqbufs(&fh->mpegq, p);
  1226. }
  1227. static int vidioc_querybuf(struct file *file, void *priv,
  1228. struct v4l2_buffer *p)
  1229. {
  1230. struct cx23885_fh *fh = file->private_data;
  1231. return videobuf_querybuf(&fh->mpegq, p);
  1232. }
  1233. static int vidioc_qbuf(struct file *file, void *priv,
  1234. struct v4l2_buffer *p)
  1235. {
  1236. struct cx23885_fh *fh = file->private_data;
  1237. return videobuf_qbuf(&fh->mpegq, p);
  1238. }
  1239. static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
  1240. {
  1241. struct cx23885_fh *fh = priv;
  1242. return videobuf_dqbuf(&fh->mpegq, b, file->f_flags & O_NONBLOCK);
  1243. }
  1244. static int vidioc_streamon(struct file *file, void *priv,
  1245. enum v4l2_buf_type i)
  1246. {
  1247. struct cx23885_fh *fh = file->private_data;
  1248. return videobuf_streamon(&fh->mpegq);
  1249. }
  1250. static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
  1251. {
  1252. struct cx23885_fh *fh = file->private_data;
  1253. return videobuf_streamoff(&fh->mpegq);
  1254. }
  1255. static int vidioc_g_ext_ctrls(struct file *file, void *priv,
  1256. struct v4l2_ext_controls *f)
  1257. {
  1258. struct cx23885_fh *fh = priv;
  1259. struct cx23885_dev *dev = fh->dev;
  1260. if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
  1261. return -EINVAL;
  1262. return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
  1263. }
  1264. static int vidioc_s_ext_ctrls(struct file *file, void *priv,
  1265. struct v4l2_ext_controls *f)
  1266. {
  1267. struct cx23885_fh *fh = priv;
  1268. struct cx23885_dev *dev = fh->dev;
  1269. struct cx2341x_mpeg_params p;
  1270. int err;
  1271. if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
  1272. return -EINVAL;
  1273. p = dev->mpeg_params;
  1274. err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_S_EXT_CTRLS);
  1275. if (err == 0) {
  1276. err = cx2341x_update(dev, cx23885_mbox_func,
  1277. &dev->mpeg_params, &p);
  1278. dev->mpeg_params = p;
  1279. }
  1280. return err;
  1281. }
  1282. static int vidioc_try_ext_ctrls(struct file *file, void *priv,
  1283. struct v4l2_ext_controls *f)
  1284. {
  1285. struct cx23885_fh *fh = priv;
  1286. struct cx23885_dev *dev = fh->dev;
  1287. struct cx2341x_mpeg_params p;
  1288. int err;
  1289. if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
  1290. return -EINVAL;
  1291. p = dev->mpeg_params;
  1292. err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
  1293. return err;
  1294. }
  1295. static int vidioc_log_status(struct file *file, void *priv)
  1296. {
  1297. struct cx23885_fh *fh = priv;
  1298. struct cx23885_dev *dev = fh->dev;
  1299. char name[32 + 2];
  1300. snprintf(name, sizeof(name), "%s/2", dev->name);
  1301. printk(KERN_INFO
  1302. "%s/2: ============ START LOG STATUS ============\n",
  1303. dev->name);
  1304. call_all(dev, core, log_status);
  1305. cx2341x_log_status(&dev->mpeg_params, name);
  1306. printk(KERN_INFO
  1307. "%s/2: ============= END LOG STATUS =============\n",
  1308. dev->name);
  1309. return 0;
  1310. }
  1311. static int vidioc_querymenu(struct file *file, void *priv,
  1312. struct v4l2_querymenu *a)
  1313. {
  1314. struct cx23885_fh *fh = priv;
  1315. struct cx23885_dev *dev = fh->dev;
  1316. return cx23885_querymenu(dev, a);
  1317. }
  1318. static int vidioc_queryctrl(struct file *file, void *priv,
  1319. struct v4l2_queryctrl *c)
  1320. {
  1321. struct cx23885_fh *fh = priv;
  1322. struct cx23885_dev *dev = fh->dev;
  1323. return cx23885_queryctrl(dev, c);
  1324. }
  1325. static int mpeg_open(struct file *file)
  1326. {
  1327. int minor = video_devdata(file)->minor;
  1328. struct cx23885_dev *h, *dev = NULL;
  1329. struct list_head *list;
  1330. struct cx23885_fh *fh;
  1331. dprintk(2, "%s()\n", __func__);
  1332. lock_kernel();
  1333. list_for_each(list, &cx23885_devlist) {
  1334. h = list_entry(list, struct cx23885_dev, devlist);
  1335. if (h->v4l_device &&
  1336. h->v4l_device->minor == minor) {
  1337. dev = h;
  1338. break;
  1339. }
  1340. }
  1341. if (dev == NULL) {
  1342. unlock_kernel();
  1343. return -ENODEV;
  1344. }
  1345. /* allocate + initialize per filehandle data */
  1346. fh = kzalloc(sizeof(*fh), GFP_KERNEL);
  1347. if (NULL == fh) {
  1348. unlock_kernel();
  1349. return -ENOMEM;
  1350. }
  1351. file->private_data = fh;
  1352. fh->dev = dev;
  1353. videobuf_queue_sg_init(&fh->mpegq, &cx23885_qops,
  1354. &dev->pci->dev, &dev->ts1.slock,
  1355. V4L2_BUF_TYPE_VIDEO_CAPTURE,
  1356. V4L2_FIELD_INTERLACED,
  1357. sizeof(struct cx23885_buffer),
  1358. fh);
  1359. unlock_kernel();
  1360. return 0;
  1361. }
  1362. static int mpeg_release(struct file *file)
  1363. {
  1364. struct cx23885_fh *fh = file->private_data;
  1365. struct cx23885_dev *dev = fh->dev;
  1366. dprintk(2, "%s()\n", __func__);
  1367. /* FIXME: Review this crap */
  1368. /* Shut device down on last close */
  1369. if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
  1370. if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
  1371. /* stop mpeg capture */
  1372. cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
  1373. CX23885_END_NOW, CX23885_MPEG_CAPTURE,
  1374. CX23885_RAW_BITS_NONE);
  1375. msleep(500);
  1376. cx23885_417_check_encoder(dev);
  1377. cx23885_cancel_buffers(&fh->dev->ts1);
  1378. }
  1379. }
  1380. if (fh->mpegq.streaming)
  1381. videobuf_streamoff(&fh->mpegq);
  1382. if (fh->mpegq.reading)
  1383. videobuf_read_stop(&fh->mpegq);
  1384. videobuf_mmap_free(&fh->mpegq);
  1385. file->private_data = NULL;
  1386. kfree(fh);
  1387. return 0;
  1388. }
  1389. static ssize_t mpeg_read(struct file *file, char __user *data,
  1390. size_t count, loff_t *ppos)
  1391. {
  1392. struct cx23885_fh *fh = file->private_data;
  1393. struct cx23885_dev *dev = fh->dev;
  1394. dprintk(2, "%s()\n", __func__);
  1395. /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
  1396. /* Start mpeg encoder on first read. */
  1397. if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
  1398. if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
  1399. if (cx23885_initialize_codec(dev) < 0)
  1400. return -EINVAL;
  1401. }
  1402. }
  1403. return videobuf_read_stream(&fh->mpegq, data, count, ppos, 0,
  1404. file->f_flags & O_NONBLOCK);
  1405. }
  1406. static unsigned int mpeg_poll(struct file *file,
  1407. struct poll_table_struct *wait)
  1408. {
  1409. struct cx23885_fh *fh = file->private_data;
  1410. struct cx23885_dev *dev = fh->dev;
  1411. dprintk(2, "%s\n", __func__);
  1412. return videobuf_poll_stream(file, &fh->mpegq, wait);
  1413. }
  1414. static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
  1415. {
  1416. struct cx23885_fh *fh = file->private_data;
  1417. struct cx23885_dev *dev = fh->dev;
  1418. dprintk(2, "%s()\n", __func__);
  1419. return videobuf_mmap_mapper(&fh->mpegq, vma);
  1420. }
  1421. static struct v4l2_file_operations mpeg_fops = {
  1422. .owner = THIS_MODULE,
  1423. .open = mpeg_open,
  1424. .release = mpeg_release,
  1425. .read = mpeg_read,
  1426. .poll = mpeg_poll,
  1427. .mmap = mpeg_mmap,
  1428. .ioctl = video_ioctl2,
  1429. };
  1430. static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
  1431. .vidioc_s_std = vidioc_s_std,
  1432. .vidioc_enum_input = vidioc_enum_input,
  1433. .vidioc_g_input = vidioc_g_input,
  1434. .vidioc_s_input = vidioc_s_input,
  1435. .vidioc_g_tuner = vidioc_g_tuner,
  1436. .vidioc_s_tuner = vidioc_s_tuner,
  1437. .vidioc_g_frequency = vidioc_g_frequency,
  1438. .vidioc_s_frequency = vidioc_s_frequency,
  1439. .vidioc_s_ctrl = vidioc_s_ctrl,
  1440. .vidioc_querycap = vidioc_querycap,
  1441. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  1442. .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
  1443. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  1444. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  1445. .vidioc_reqbufs = vidioc_reqbufs,
  1446. .vidioc_querybuf = vidioc_querybuf,
  1447. .vidioc_qbuf = vidioc_qbuf,
  1448. .vidioc_dqbuf = vidioc_dqbuf,
  1449. .vidioc_streamon = vidioc_streamon,
  1450. .vidioc_streamoff = vidioc_streamoff,
  1451. .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
  1452. .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls,
  1453. .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls,
  1454. .vidioc_log_status = vidioc_log_status,
  1455. .vidioc_querymenu = vidioc_querymenu,
  1456. .vidioc_queryctrl = vidioc_queryctrl,
  1457. };
  1458. static struct video_device cx23885_mpeg_template = {
  1459. .name = "cx23885",
  1460. .fops = &mpeg_fops,
  1461. .ioctl_ops = &mpeg_ioctl_ops,
  1462. .minor = -1,
  1463. .tvnorms = CX23885_NORMS,
  1464. .current_norm = V4L2_STD_NTSC_M,
  1465. };
  1466. void cx23885_417_unregister(struct cx23885_dev *dev)
  1467. {
  1468. dprintk(1, "%s()\n", __func__);
  1469. if (dev->v4l_device) {
  1470. if (-1 != dev->v4l_device->minor)
  1471. video_unregister_device(dev->v4l_device);
  1472. else
  1473. video_device_release(dev->v4l_device);
  1474. dev->v4l_device = NULL;
  1475. }
  1476. }
  1477. static struct video_device *cx23885_video_dev_alloc(
  1478. struct cx23885_tsport *tsport,
  1479. struct pci_dev *pci,
  1480. struct video_device *template,
  1481. char *type)
  1482. {
  1483. struct video_device *vfd;
  1484. struct cx23885_dev *dev = tsport->dev;
  1485. dprintk(1, "%s()\n", __func__);
  1486. vfd = video_device_alloc();
  1487. if (NULL == vfd)
  1488. return NULL;
  1489. *vfd = *template;
  1490. snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
  1491. type, cx23885_boards[tsport->dev->board].name);
  1492. vfd->parent = &pci->dev;
  1493. vfd->release = video_device_release;
  1494. return vfd;
  1495. }
  1496. int cx23885_417_register(struct cx23885_dev *dev)
  1497. {
  1498. /* FIXME: Port1 hardcoded here */
  1499. int err = -ENODEV;
  1500. struct cx23885_tsport *tsport = &dev->ts1;
  1501. dprintk(1, "%s()\n", __func__);
  1502. if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER)
  1503. return err;
  1504. /* Set default TV standard */
  1505. dev->encodernorm = cx23885_tvnorms[0];
  1506. if (dev->encodernorm.id & V4L2_STD_525_60)
  1507. tsport->height = 480;
  1508. else
  1509. tsport->height = 576;
  1510. tsport->width = 720;
  1511. cx2341x_fill_defaults(&dev->mpeg_params);
  1512. dev->mpeg_params.port = CX2341X_PORT_SERIAL;
  1513. /* Allocate and initialize V4L video device */
  1514. dev->v4l_device = cx23885_video_dev_alloc(tsport,
  1515. dev->pci, &cx23885_mpeg_template, "mpeg");
  1516. err = video_register_device(dev->v4l_device,
  1517. VFL_TYPE_GRABBER, -1);
  1518. if (err < 0) {
  1519. printk(KERN_INFO "%s: can't register mpeg device\n", dev->name);
  1520. return err;
  1521. }
  1522. /* Initialize MC417 registers */
  1523. cx23885_mc417_init(dev);
  1524. printk(KERN_INFO "%s: registered device video%d [mpeg]\n",
  1525. dev->name, dev->v4l_device->num);
  1526. return 0;
  1527. }