udc.c 43 KB

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  1. /*
  2. * udc.c - ChipIdea UDC driver
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/dmapool.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/module.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <linux/irq.h>
  22. #include <linux/kernel.h>
  23. #include <linux/slab.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/usb/ch9.h>
  26. #include <linux/usb/gadget.h>
  27. #include <linux/usb/otg.h>
  28. #include <linux/usb/chipidea.h>
  29. #include "ci.h"
  30. #include "udc.h"
  31. #include "bits.h"
  32. #include "debug.h"
  33. /* control endpoint description */
  34. static const struct usb_endpoint_descriptor
  35. ctrl_endpt_out_desc = {
  36. .bLength = USB_DT_ENDPOINT_SIZE,
  37. .bDescriptorType = USB_DT_ENDPOINT,
  38. .bEndpointAddress = USB_DIR_OUT,
  39. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  40. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  41. };
  42. static const struct usb_endpoint_descriptor
  43. ctrl_endpt_in_desc = {
  44. .bLength = USB_DT_ENDPOINT_SIZE,
  45. .bDescriptorType = USB_DT_ENDPOINT,
  46. .bEndpointAddress = USB_DIR_IN,
  47. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  48. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  49. };
  50. /**
  51. * hw_ep_bit: calculates the bit number
  52. * @num: endpoint number
  53. * @dir: endpoint direction
  54. *
  55. * This function returns bit number
  56. */
  57. static inline int hw_ep_bit(int num, int dir)
  58. {
  59. return num + (dir ? 16 : 0);
  60. }
  61. static inline int ep_to_bit(struct ci13xxx *udc, int n)
  62. {
  63. int fill = 16 - udc->hw_ep_max / 2;
  64. if (n >= udc->hw_ep_max / 2)
  65. n += fill;
  66. return n;
  67. }
  68. /**
  69. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  70. * without interruption)
  71. * @dma: 0 => disable, !0 => enable and set dma engine
  72. *
  73. * This function returns an error code
  74. */
  75. static int hw_device_state(struct ci13xxx *udc, u32 dma)
  76. {
  77. if (dma) {
  78. hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
  79. /* interrupt, error, port change, reset, sleep/suspend */
  80. hw_write(udc, OP_USBINTR, ~0,
  81. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  82. hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  83. } else {
  84. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  85. hw_write(udc, OP_USBINTR, ~0, 0);
  86. }
  87. return 0;
  88. }
  89. /**
  90. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  91. * @num: endpoint number
  92. * @dir: endpoint direction
  93. *
  94. * This function returns an error code
  95. */
  96. static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
  97. {
  98. int n = hw_ep_bit(num, dir);
  99. do {
  100. /* flush any pending transfer */
  101. hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
  102. while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
  103. cpu_relax();
  104. } while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
  105. return 0;
  106. }
  107. /**
  108. * hw_ep_disable: disables endpoint (execute without interruption)
  109. * @num: endpoint number
  110. * @dir: endpoint direction
  111. *
  112. * This function returns an error code
  113. */
  114. static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
  115. {
  116. hw_ep_flush(udc, num, dir);
  117. hw_write(udc, OP_ENDPTCTRL + num,
  118. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  119. return 0;
  120. }
  121. /**
  122. * hw_ep_enable: enables endpoint (execute without interruption)
  123. * @num: endpoint number
  124. * @dir: endpoint direction
  125. * @type: endpoint type
  126. *
  127. * This function returns an error code
  128. */
  129. static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
  130. {
  131. u32 mask, data;
  132. if (dir) {
  133. mask = ENDPTCTRL_TXT; /* type */
  134. data = type << ffs_nr(mask);
  135. mask |= ENDPTCTRL_TXS; /* unstall */
  136. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  137. data |= ENDPTCTRL_TXR;
  138. mask |= ENDPTCTRL_TXE; /* enable */
  139. data |= ENDPTCTRL_TXE;
  140. } else {
  141. mask = ENDPTCTRL_RXT; /* type */
  142. data = type << ffs_nr(mask);
  143. mask |= ENDPTCTRL_RXS; /* unstall */
  144. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  145. data |= ENDPTCTRL_RXR;
  146. mask |= ENDPTCTRL_RXE; /* enable */
  147. data |= ENDPTCTRL_RXE;
  148. }
  149. hw_write(udc, OP_ENDPTCTRL + num, mask, data);
  150. return 0;
  151. }
  152. /**
  153. * hw_ep_get_halt: return endpoint halt status
  154. * @num: endpoint number
  155. * @dir: endpoint direction
  156. *
  157. * This function returns 1 if endpoint halted
  158. */
  159. static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
  160. {
  161. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  162. return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  163. }
  164. /**
  165. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  166. * interruption)
  167. * @n: endpoint number
  168. *
  169. * This function returns setup status
  170. */
  171. static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
  172. {
  173. n = ep_to_bit(udc, n);
  174. return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
  175. }
  176. /**
  177. * hw_ep_prime: primes endpoint (execute without interruption)
  178. * @num: endpoint number
  179. * @dir: endpoint direction
  180. * @is_ctrl: true if control endpoint
  181. *
  182. * This function returns an error code
  183. */
  184. static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
  185. {
  186. int n = hw_ep_bit(num, dir);
  187. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  188. return -EAGAIN;
  189. hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
  190. while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  191. cpu_relax();
  192. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  193. return -EAGAIN;
  194. /* status shoult be tested according with manual but it doesn't work */
  195. return 0;
  196. }
  197. /**
  198. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  199. * without interruption)
  200. * @num: endpoint number
  201. * @dir: endpoint direction
  202. * @value: true => stall, false => unstall
  203. *
  204. * This function returns an error code
  205. */
  206. static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
  207. {
  208. if (value != 0 && value != 1)
  209. return -EINVAL;
  210. do {
  211. enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
  212. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  213. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  214. /* data toggle - reserved for EP0 but it's in ESS */
  215. hw_write(udc, reg, mask_xs|mask_xr,
  216. value ? mask_xs : mask_xr);
  217. } while (value != hw_ep_get_halt(udc, num, dir));
  218. return 0;
  219. }
  220. /**
  221. * hw_is_port_high_speed: test if port is high speed
  222. *
  223. * This function returns true if high speed port
  224. */
  225. static int hw_port_is_high_speed(struct ci13xxx *udc)
  226. {
  227. return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
  228. hw_read(udc, OP_PORTSC, PORTSC_HSP);
  229. }
  230. /**
  231. * hw_read_intr_enable: returns interrupt enable register
  232. *
  233. * This function returns register data
  234. */
  235. static u32 hw_read_intr_enable(struct ci13xxx *udc)
  236. {
  237. return hw_read(udc, OP_USBINTR, ~0);
  238. }
  239. /**
  240. * hw_read_intr_status: returns interrupt status register
  241. *
  242. * This function returns register data
  243. */
  244. static u32 hw_read_intr_status(struct ci13xxx *udc)
  245. {
  246. return hw_read(udc, OP_USBSTS, ~0);
  247. }
  248. /**
  249. * hw_test_and_clear_complete: test & clear complete status (execute without
  250. * interruption)
  251. * @n: endpoint number
  252. *
  253. * This function returns complete status
  254. */
  255. static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
  256. {
  257. n = ep_to_bit(udc, n);
  258. return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
  259. }
  260. /**
  261. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  262. * without interruption)
  263. *
  264. * This function returns active interrutps
  265. */
  266. static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
  267. {
  268. u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
  269. hw_write(udc, OP_USBSTS, ~0, reg);
  270. return reg;
  271. }
  272. /**
  273. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  274. * interruption)
  275. *
  276. * This function returns guard value
  277. */
  278. static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
  279. {
  280. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
  281. }
  282. /**
  283. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  284. * interruption)
  285. *
  286. * This function returns guard value
  287. */
  288. static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
  289. {
  290. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  291. }
  292. /**
  293. * hw_usb_set_address: configures USB address (execute without interruption)
  294. * @value: new USB address
  295. *
  296. * This function explicitly sets the address, without the "USBADRA" (advance)
  297. * feature, which is not supported by older versions of the controller.
  298. */
  299. static void hw_usb_set_address(struct ci13xxx *udc, u8 value)
  300. {
  301. hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR,
  302. value << ffs_nr(DEVICEADDR_USBADR));
  303. }
  304. /**
  305. * hw_usb_reset: restart device after a bus reset (execute without
  306. * interruption)
  307. *
  308. * This function returns an error code
  309. */
  310. static int hw_usb_reset(struct ci13xxx *udc)
  311. {
  312. hw_usb_set_address(udc, 0);
  313. /* ESS flushes only at end?!? */
  314. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  315. /* clear setup token semaphores */
  316. hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
  317. /* clear complete status */
  318. hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
  319. /* wait until all bits cleared */
  320. while (hw_read(udc, OP_ENDPTPRIME, ~0))
  321. udelay(10); /* not RTOS friendly */
  322. /* reset all endpoints ? */
  323. /* reset internal status and wait for further instructions
  324. no need to verify the port reset status (ESS does it) */
  325. return 0;
  326. }
  327. /******************************************************************************
  328. * UTIL block
  329. *****************************************************************************/
  330. /**
  331. * _usb_addr: calculates endpoint address from direction & number
  332. * @ep: endpoint
  333. */
  334. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  335. {
  336. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  337. }
  338. /**
  339. * _hardware_queue: configures a request at hardware level
  340. * @gadget: gadget
  341. * @mEp: endpoint
  342. *
  343. * This function returns an error code
  344. */
  345. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  346. {
  347. struct ci13xxx *udc = mEp->udc;
  348. unsigned i;
  349. int ret = 0;
  350. unsigned length = mReq->req.length;
  351. /* don't queue twice */
  352. if (mReq->req.status == -EALREADY)
  353. return -EALREADY;
  354. mReq->req.status = -EALREADY;
  355. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  356. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  357. &mReq->zdma);
  358. if (mReq->zptr == NULL)
  359. return -ENOMEM;
  360. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  361. mReq->zptr->next = TD_TERMINATE;
  362. mReq->zptr->token = TD_STATUS_ACTIVE;
  363. if (!mReq->req.no_interrupt)
  364. mReq->zptr->token |= TD_IOC;
  365. }
  366. ret = usb_gadget_map_request(&udc->gadget, &mReq->req, mEp->dir);
  367. if (ret)
  368. return ret;
  369. /*
  370. * TD configuration
  371. * TODO - handle requests which spawns into several TDs
  372. */
  373. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  374. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  375. mReq->ptr->token &= TD_TOTAL_BYTES;
  376. mReq->ptr->token |= TD_STATUS_ACTIVE;
  377. if (mReq->zptr) {
  378. mReq->ptr->next = mReq->zdma;
  379. } else {
  380. mReq->ptr->next = TD_TERMINATE;
  381. if (!mReq->req.no_interrupt)
  382. mReq->ptr->token |= TD_IOC;
  383. }
  384. mReq->ptr->page[0] = mReq->req.dma;
  385. for (i = 1; i < 5; i++)
  386. mReq->ptr->page[i] =
  387. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  388. if (!list_empty(&mEp->qh.queue)) {
  389. struct ci13xxx_req *mReqPrev;
  390. int n = hw_ep_bit(mEp->num, mEp->dir);
  391. int tmp_stat;
  392. mReqPrev = list_entry(mEp->qh.queue.prev,
  393. struct ci13xxx_req, queue);
  394. if (mReqPrev->zptr)
  395. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  396. else
  397. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  398. wmb();
  399. if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  400. goto done;
  401. do {
  402. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  403. tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
  404. } while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
  405. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
  406. if (tmp_stat)
  407. goto done;
  408. }
  409. /* QH configuration */
  410. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  411. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  412. mEp->qh.ptr->cap |= QH_ZLT;
  413. wmb(); /* synchronize before ep prime */
  414. ret = hw_ep_prime(udc, mEp->num, mEp->dir,
  415. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  416. done:
  417. return ret;
  418. }
  419. /**
  420. * _hardware_dequeue: handles a request at hardware level
  421. * @gadget: gadget
  422. * @mEp: endpoint
  423. *
  424. * This function returns an error code
  425. */
  426. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  427. {
  428. if (mReq->req.status != -EALREADY)
  429. return -EINVAL;
  430. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  431. return -EBUSY;
  432. if (mReq->zptr) {
  433. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  434. return -EBUSY;
  435. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  436. mReq->zptr = NULL;
  437. }
  438. mReq->req.status = 0;
  439. usb_gadget_unmap_request(&mEp->udc->gadget, &mReq->req, mEp->dir);
  440. mReq->req.status = mReq->ptr->token & TD_STATUS;
  441. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  442. mReq->req.status = -1;
  443. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  444. mReq->req.status = -1;
  445. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  446. mReq->req.status = -1;
  447. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  448. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  449. mReq->req.actual = mReq->req.length - mReq->req.actual;
  450. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  451. return mReq->req.actual;
  452. }
  453. /**
  454. * _ep_nuke: dequeues all endpoint requests
  455. * @mEp: endpoint
  456. *
  457. * This function returns an error code
  458. * Caller must hold lock
  459. */
  460. static int _ep_nuke(struct ci13xxx_ep *mEp)
  461. __releases(mEp->lock)
  462. __acquires(mEp->lock)
  463. {
  464. if (mEp == NULL)
  465. return -EINVAL;
  466. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  467. while (!list_empty(&mEp->qh.queue)) {
  468. /* pop oldest request */
  469. struct ci13xxx_req *mReq = \
  470. list_entry(mEp->qh.queue.next,
  471. struct ci13xxx_req, queue);
  472. list_del_init(&mReq->queue);
  473. mReq->req.status = -ESHUTDOWN;
  474. if (mReq->req.complete != NULL) {
  475. spin_unlock(mEp->lock);
  476. mReq->req.complete(&mEp->ep, &mReq->req);
  477. spin_lock(mEp->lock);
  478. }
  479. }
  480. return 0;
  481. }
  482. /**
  483. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  484. * @gadget: gadget
  485. *
  486. * This function returns an error code
  487. */
  488. static int _gadget_stop_activity(struct usb_gadget *gadget)
  489. {
  490. struct usb_ep *ep;
  491. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  492. unsigned long flags;
  493. spin_lock_irqsave(&udc->lock, flags);
  494. udc->gadget.speed = USB_SPEED_UNKNOWN;
  495. udc->remote_wakeup = 0;
  496. udc->suspended = 0;
  497. spin_unlock_irqrestore(&udc->lock, flags);
  498. /* flush all endpoints */
  499. gadget_for_each_ep(ep, gadget) {
  500. usb_ep_fifo_flush(ep);
  501. }
  502. usb_ep_fifo_flush(&udc->ep0out->ep);
  503. usb_ep_fifo_flush(&udc->ep0in->ep);
  504. if (udc->driver)
  505. udc->driver->disconnect(gadget);
  506. /* make sure to disable all endpoints */
  507. gadget_for_each_ep(ep, gadget) {
  508. usb_ep_disable(ep);
  509. }
  510. if (udc->status != NULL) {
  511. usb_ep_free_request(&udc->ep0in->ep, udc->status);
  512. udc->status = NULL;
  513. }
  514. return 0;
  515. }
  516. /******************************************************************************
  517. * ISR block
  518. *****************************************************************************/
  519. /**
  520. * isr_reset_handler: USB reset interrupt handler
  521. * @udc: UDC device
  522. *
  523. * This function resets USB engine after a bus reset occurred
  524. */
  525. static void isr_reset_handler(struct ci13xxx *udc)
  526. __releases(udc->lock)
  527. __acquires(udc->lock)
  528. {
  529. int retval;
  530. dbg_event(0xFF, "BUS RST", 0);
  531. spin_unlock(&udc->lock);
  532. retval = _gadget_stop_activity(&udc->gadget);
  533. if (retval)
  534. goto done;
  535. retval = hw_usb_reset(udc);
  536. if (retval)
  537. goto done;
  538. udc->status = usb_ep_alloc_request(&udc->ep0in->ep, GFP_ATOMIC);
  539. if (udc->status == NULL)
  540. retval = -ENOMEM;
  541. done:
  542. spin_lock(&udc->lock);
  543. if (retval)
  544. dev_err(udc->dev, "error: %i\n", retval);
  545. }
  546. /**
  547. * isr_get_status_complete: get_status request complete function
  548. * @ep: endpoint
  549. * @req: request handled
  550. *
  551. * Caller must release lock
  552. */
  553. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  554. {
  555. if (ep == NULL || req == NULL)
  556. return;
  557. kfree(req->buf);
  558. usb_ep_free_request(ep, req);
  559. }
  560. /**
  561. * isr_get_status_response: get_status request response
  562. * @udc: udc struct
  563. * @setup: setup request packet
  564. *
  565. * This function returns an error code
  566. */
  567. static int isr_get_status_response(struct ci13xxx *udc,
  568. struct usb_ctrlrequest *setup)
  569. __releases(mEp->lock)
  570. __acquires(mEp->lock)
  571. {
  572. struct ci13xxx_ep *mEp = udc->ep0in;
  573. struct usb_request *req = NULL;
  574. gfp_t gfp_flags = GFP_ATOMIC;
  575. int dir, num, retval;
  576. if (mEp == NULL || setup == NULL)
  577. return -EINVAL;
  578. spin_unlock(mEp->lock);
  579. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  580. spin_lock(mEp->lock);
  581. if (req == NULL)
  582. return -ENOMEM;
  583. req->complete = isr_get_status_complete;
  584. req->length = 2;
  585. req->buf = kzalloc(req->length, gfp_flags);
  586. if (req->buf == NULL) {
  587. retval = -ENOMEM;
  588. goto err_free_req;
  589. }
  590. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  591. /* Assume that device is bus powered for now. */
  592. *(u16 *)req->buf = udc->remote_wakeup << 1;
  593. retval = 0;
  594. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  595. == USB_RECIP_ENDPOINT) {
  596. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  597. TX : RX;
  598. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  599. *(u16 *)req->buf = hw_ep_get_halt(udc, num, dir);
  600. }
  601. /* else do nothing; reserved for future use */
  602. spin_unlock(mEp->lock);
  603. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  604. spin_lock(mEp->lock);
  605. if (retval)
  606. goto err_free_buf;
  607. return 0;
  608. err_free_buf:
  609. kfree(req->buf);
  610. err_free_req:
  611. spin_unlock(mEp->lock);
  612. usb_ep_free_request(&mEp->ep, req);
  613. spin_lock(mEp->lock);
  614. return retval;
  615. }
  616. /**
  617. * isr_setup_status_complete: setup_status request complete function
  618. * @ep: endpoint
  619. * @req: request handled
  620. *
  621. * Caller must release lock. Put the port in test mode if test mode
  622. * feature is selected.
  623. */
  624. static void
  625. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  626. {
  627. struct ci13xxx *udc = req->context;
  628. unsigned long flags;
  629. if (udc->setaddr) {
  630. hw_usb_set_address(udc, udc->address);
  631. udc->setaddr = false;
  632. }
  633. spin_lock_irqsave(&udc->lock, flags);
  634. if (udc->test_mode)
  635. hw_port_test_set(udc, udc->test_mode);
  636. spin_unlock_irqrestore(&udc->lock, flags);
  637. }
  638. /**
  639. * isr_setup_status_phase: queues the status phase of a setup transation
  640. * @udc: udc struct
  641. *
  642. * This function returns an error code
  643. */
  644. static int isr_setup_status_phase(struct ci13xxx *udc)
  645. __releases(mEp->lock)
  646. __acquires(mEp->lock)
  647. {
  648. int retval;
  649. struct ci13xxx_ep *mEp;
  650. mEp = (udc->ep0_dir == TX) ? udc->ep0out : udc->ep0in;
  651. udc->status->context = udc;
  652. udc->status->complete = isr_setup_status_complete;
  653. spin_unlock(mEp->lock);
  654. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  655. spin_lock(mEp->lock);
  656. return retval;
  657. }
  658. /**
  659. * isr_tr_complete_low: transaction complete low level handler
  660. * @mEp: endpoint
  661. *
  662. * This function returns an error code
  663. * Caller must hold lock
  664. */
  665. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  666. __releases(mEp->lock)
  667. __acquires(mEp->lock)
  668. {
  669. struct ci13xxx_req *mReq, *mReqTemp;
  670. struct ci13xxx_ep *mEpTemp = mEp;
  671. int uninitialized_var(retval);
  672. if (list_empty(&mEp->qh.queue))
  673. return -EINVAL;
  674. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  675. queue) {
  676. retval = _hardware_dequeue(mEp, mReq);
  677. if (retval < 0)
  678. break;
  679. list_del_init(&mReq->queue);
  680. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  681. if (mReq->req.complete != NULL) {
  682. spin_unlock(mEp->lock);
  683. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  684. mReq->req.length)
  685. mEpTemp = mEp->udc->ep0in;
  686. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  687. spin_lock(mEp->lock);
  688. }
  689. }
  690. if (retval == -EBUSY)
  691. retval = 0;
  692. if (retval < 0)
  693. dbg_event(_usb_addr(mEp), "DONE", retval);
  694. return retval;
  695. }
  696. /**
  697. * isr_tr_complete_handler: transaction complete interrupt handler
  698. * @udc: UDC descriptor
  699. *
  700. * This function handles traffic events
  701. */
  702. static void isr_tr_complete_handler(struct ci13xxx *udc)
  703. __releases(udc->lock)
  704. __acquires(udc->lock)
  705. {
  706. unsigned i;
  707. u8 tmode = 0;
  708. for (i = 0; i < udc->hw_ep_max; i++) {
  709. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  710. int type, num, dir, err = -EINVAL;
  711. struct usb_ctrlrequest req;
  712. if (mEp->ep.desc == NULL)
  713. continue; /* not configured */
  714. if (hw_test_and_clear_complete(udc, i)) {
  715. err = isr_tr_complete_low(mEp);
  716. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  717. if (err > 0) /* needs status phase */
  718. err = isr_setup_status_phase(udc);
  719. if (err < 0) {
  720. dbg_event(_usb_addr(mEp),
  721. "ERROR", err);
  722. spin_unlock(&udc->lock);
  723. if (usb_ep_set_halt(&mEp->ep))
  724. dev_err(udc->dev,
  725. "error: ep_set_halt\n");
  726. spin_lock(&udc->lock);
  727. }
  728. }
  729. }
  730. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  731. !hw_test_and_clear_setup_status(udc, i))
  732. continue;
  733. if (i != 0) {
  734. dev_warn(udc->dev, "ctrl traffic at endpoint %d\n", i);
  735. continue;
  736. }
  737. /*
  738. * Flush data and handshake transactions of previous
  739. * setup packet.
  740. */
  741. _ep_nuke(udc->ep0out);
  742. _ep_nuke(udc->ep0in);
  743. /* read_setup_packet */
  744. do {
  745. hw_test_and_set_setup_guard(udc);
  746. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  747. } while (!hw_test_and_clear_setup_guard(udc));
  748. type = req.bRequestType;
  749. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  750. dbg_setup(_usb_addr(mEp), &req);
  751. switch (req.bRequest) {
  752. case USB_REQ_CLEAR_FEATURE:
  753. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  754. le16_to_cpu(req.wValue) ==
  755. USB_ENDPOINT_HALT) {
  756. if (req.wLength != 0)
  757. break;
  758. num = le16_to_cpu(req.wIndex);
  759. dir = num & USB_ENDPOINT_DIR_MASK;
  760. num &= USB_ENDPOINT_NUMBER_MASK;
  761. if (dir) /* TX */
  762. num += udc->hw_ep_max/2;
  763. if (!udc->ci13xxx_ep[num].wedge) {
  764. spin_unlock(&udc->lock);
  765. err = usb_ep_clear_halt(
  766. &udc->ci13xxx_ep[num].ep);
  767. spin_lock(&udc->lock);
  768. if (err)
  769. break;
  770. }
  771. err = isr_setup_status_phase(udc);
  772. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  773. le16_to_cpu(req.wValue) ==
  774. USB_DEVICE_REMOTE_WAKEUP) {
  775. if (req.wLength != 0)
  776. break;
  777. udc->remote_wakeup = 0;
  778. err = isr_setup_status_phase(udc);
  779. } else {
  780. goto delegate;
  781. }
  782. break;
  783. case USB_REQ_GET_STATUS:
  784. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  785. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  786. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  787. goto delegate;
  788. if (le16_to_cpu(req.wLength) != 2 ||
  789. le16_to_cpu(req.wValue) != 0)
  790. break;
  791. err = isr_get_status_response(udc, &req);
  792. break;
  793. case USB_REQ_SET_ADDRESS:
  794. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  795. goto delegate;
  796. if (le16_to_cpu(req.wLength) != 0 ||
  797. le16_to_cpu(req.wIndex) != 0)
  798. break;
  799. udc->address = (u8)le16_to_cpu(req.wValue);
  800. udc->setaddr = true;
  801. err = isr_setup_status_phase(udc);
  802. break;
  803. case USB_REQ_SET_FEATURE:
  804. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  805. le16_to_cpu(req.wValue) ==
  806. USB_ENDPOINT_HALT) {
  807. if (req.wLength != 0)
  808. break;
  809. num = le16_to_cpu(req.wIndex);
  810. dir = num & USB_ENDPOINT_DIR_MASK;
  811. num &= USB_ENDPOINT_NUMBER_MASK;
  812. if (dir) /* TX */
  813. num += udc->hw_ep_max/2;
  814. spin_unlock(&udc->lock);
  815. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  816. spin_lock(&udc->lock);
  817. if (!err)
  818. isr_setup_status_phase(udc);
  819. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  820. if (req.wLength != 0)
  821. break;
  822. switch (le16_to_cpu(req.wValue)) {
  823. case USB_DEVICE_REMOTE_WAKEUP:
  824. udc->remote_wakeup = 1;
  825. err = isr_setup_status_phase(udc);
  826. break;
  827. case USB_DEVICE_TEST_MODE:
  828. tmode = le16_to_cpu(req.wIndex) >> 8;
  829. switch (tmode) {
  830. case TEST_J:
  831. case TEST_K:
  832. case TEST_SE0_NAK:
  833. case TEST_PACKET:
  834. case TEST_FORCE_EN:
  835. udc->test_mode = tmode;
  836. err = isr_setup_status_phase(
  837. udc);
  838. break;
  839. default:
  840. break;
  841. }
  842. default:
  843. goto delegate;
  844. }
  845. } else {
  846. goto delegate;
  847. }
  848. break;
  849. default:
  850. delegate:
  851. if (req.wLength == 0) /* no data phase */
  852. udc->ep0_dir = TX;
  853. spin_unlock(&udc->lock);
  854. err = udc->driver->setup(&udc->gadget, &req);
  855. spin_lock(&udc->lock);
  856. break;
  857. }
  858. if (err < 0) {
  859. dbg_event(_usb_addr(mEp), "ERROR", err);
  860. spin_unlock(&udc->lock);
  861. if (usb_ep_set_halt(&mEp->ep))
  862. dev_err(udc->dev, "error: ep_set_halt\n");
  863. spin_lock(&udc->lock);
  864. }
  865. }
  866. }
  867. /******************************************************************************
  868. * ENDPT block
  869. *****************************************************************************/
  870. /**
  871. * ep_enable: configure endpoint, making it usable
  872. *
  873. * Check usb_ep_enable() at "usb_gadget.h" for details
  874. */
  875. static int ep_enable(struct usb_ep *ep,
  876. const struct usb_endpoint_descriptor *desc)
  877. {
  878. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  879. int retval = 0;
  880. unsigned long flags;
  881. if (ep == NULL || desc == NULL)
  882. return -EINVAL;
  883. spin_lock_irqsave(mEp->lock, flags);
  884. /* only internal SW should enable ctrl endpts */
  885. mEp->ep.desc = desc;
  886. if (!list_empty(&mEp->qh.queue))
  887. dev_warn(mEp->udc->dev, "enabling a non-empty endpoint!\n");
  888. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  889. mEp->num = usb_endpoint_num(desc);
  890. mEp->type = usb_endpoint_type(desc);
  891. mEp->ep.maxpacket = usb_endpoint_maxp(desc);
  892. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  893. mEp->qh.ptr->cap = 0;
  894. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  895. mEp->qh.ptr->cap |= QH_IOS;
  896. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  897. mEp->qh.ptr->cap &= ~QH_MULT;
  898. else
  899. mEp->qh.ptr->cap &= ~QH_ZLT;
  900. mEp->qh.ptr->cap |=
  901. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  902. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  903. /*
  904. * Enable endpoints in the HW other than ep0 as ep0
  905. * is always enabled
  906. */
  907. if (mEp->num)
  908. retval |= hw_ep_enable(mEp->udc, mEp->num, mEp->dir, mEp->type);
  909. spin_unlock_irqrestore(mEp->lock, flags);
  910. return retval;
  911. }
  912. /**
  913. * ep_disable: endpoint is no longer usable
  914. *
  915. * Check usb_ep_disable() at "usb_gadget.h" for details
  916. */
  917. static int ep_disable(struct usb_ep *ep)
  918. {
  919. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  920. int direction, retval = 0;
  921. unsigned long flags;
  922. if (ep == NULL)
  923. return -EINVAL;
  924. else if (mEp->ep.desc == NULL)
  925. return -EBUSY;
  926. spin_lock_irqsave(mEp->lock, flags);
  927. /* only internal SW should disable ctrl endpts */
  928. direction = mEp->dir;
  929. do {
  930. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  931. retval |= _ep_nuke(mEp);
  932. retval |= hw_ep_disable(mEp->udc, mEp->num, mEp->dir);
  933. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  934. mEp->dir = (mEp->dir == TX) ? RX : TX;
  935. } while (mEp->dir != direction);
  936. mEp->ep.desc = NULL;
  937. spin_unlock_irqrestore(mEp->lock, flags);
  938. return retval;
  939. }
  940. /**
  941. * ep_alloc_request: allocate a request object to use with this endpoint
  942. *
  943. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  944. */
  945. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  946. {
  947. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  948. struct ci13xxx_req *mReq = NULL;
  949. if (ep == NULL)
  950. return NULL;
  951. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  952. if (mReq != NULL) {
  953. INIT_LIST_HEAD(&mReq->queue);
  954. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  955. &mReq->dma);
  956. if (mReq->ptr == NULL) {
  957. kfree(mReq);
  958. mReq = NULL;
  959. }
  960. }
  961. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  962. return (mReq == NULL) ? NULL : &mReq->req;
  963. }
  964. /**
  965. * ep_free_request: frees a request object
  966. *
  967. * Check usb_ep_free_request() at "usb_gadget.h" for details
  968. */
  969. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  970. {
  971. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  972. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  973. unsigned long flags;
  974. if (ep == NULL || req == NULL) {
  975. return;
  976. } else if (!list_empty(&mReq->queue)) {
  977. dev_err(mEp->udc->dev, "freeing queued request\n");
  978. return;
  979. }
  980. spin_lock_irqsave(mEp->lock, flags);
  981. if (mReq->ptr)
  982. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  983. kfree(mReq);
  984. dbg_event(_usb_addr(mEp), "FREE", 0);
  985. spin_unlock_irqrestore(mEp->lock, flags);
  986. }
  987. /**
  988. * ep_queue: queues (submits) an I/O request to an endpoint
  989. *
  990. * Check usb_ep_queue()* at usb_gadget.h" for details
  991. */
  992. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  993. gfp_t __maybe_unused gfp_flags)
  994. {
  995. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  996. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  997. struct ci13xxx *udc = mEp->udc;
  998. int retval = 0;
  999. unsigned long flags;
  1000. if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
  1001. return -EINVAL;
  1002. spin_lock_irqsave(mEp->lock, flags);
  1003. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1004. if (req->length)
  1005. mEp = (udc->ep0_dir == RX) ?
  1006. udc->ep0out : udc->ep0in;
  1007. if (!list_empty(&mEp->qh.queue)) {
  1008. _ep_nuke(mEp);
  1009. retval = -EOVERFLOW;
  1010. dev_warn(mEp->udc->dev, "endpoint ctrl %X nuked\n",
  1011. _usb_addr(mEp));
  1012. }
  1013. }
  1014. /* first nuke then test link, e.g. previous status has not sent */
  1015. if (!list_empty(&mReq->queue)) {
  1016. retval = -EBUSY;
  1017. dev_err(mEp->udc->dev, "request already in queue\n");
  1018. goto done;
  1019. }
  1020. if (req->length > 4 * CI13XXX_PAGE_SIZE) {
  1021. req->length = 4 * CI13XXX_PAGE_SIZE;
  1022. retval = -EMSGSIZE;
  1023. dev_warn(mEp->udc->dev, "request length truncated\n");
  1024. }
  1025. dbg_queue(_usb_addr(mEp), req, retval);
  1026. /* push request */
  1027. mReq->req.status = -EINPROGRESS;
  1028. mReq->req.actual = 0;
  1029. retval = _hardware_enqueue(mEp, mReq);
  1030. if (retval == -EALREADY) {
  1031. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1032. retval = 0;
  1033. }
  1034. if (!retval)
  1035. list_add_tail(&mReq->queue, &mEp->qh.queue);
  1036. done:
  1037. spin_unlock_irqrestore(mEp->lock, flags);
  1038. return retval;
  1039. }
  1040. /**
  1041. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1042. *
  1043. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1044. */
  1045. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1046. {
  1047. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1048. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1049. unsigned long flags;
  1050. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  1051. mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
  1052. list_empty(&mEp->qh.queue))
  1053. return -EINVAL;
  1054. spin_lock_irqsave(mEp->lock, flags);
  1055. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  1056. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  1057. /* pop request */
  1058. list_del_init(&mReq->queue);
  1059. usb_gadget_unmap_request(&mEp->udc->gadget, req, mEp->dir);
  1060. req->status = -ECONNRESET;
  1061. if (mReq->req.complete != NULL) {
  1062. spin_unlock(mEp->lock);
  1063. mReq->req.complete(&mEp->ep, &mReq->req);
  1064. spin_lock(mEp->lock);
  1065. }
  1066. spin_unlock_irqrestore(mEp->lock, flags);
  1067. return 0;
  1068. }
  1069. /**
  1070. * ep_set_halt: sets the endpoint halt feature
  1071. *
  1072. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  1073. */
  1074. static int ep_set_halt(struct usb_ep *ep, int value)
  1075. {
  1076. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1077. int direction, retval = 0;
  1078. unsigned long flags;
  1079. if (ep == NULL || mEp->ep.desc == NULL)
  1080. return -EINVAL;
  1081. spin_lock_irqsave(mEp->lock, flags);
  1082. #ifndef STALL_IN
  1083. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  1084. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  1085. !list_empty(&mEp->qh.queue)) {
  1086. spin_unlock_irqrestore(mEp->lock, flags);
  1087. return -EAGAIN;
  1088. }
  1089. #endif
  1090. direction = mEp->dir;
  1091. do {
  1092. dbg_event(_usb_addr(mEp), "HALT", value);
  1093. retval |= hw_ep_set_halt(mEp->udc, mEp->num, mEp->dir, value);
  1094. if (!value)
  1095. mEp->wedge = 0;
  1096. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1097. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1098. } while (mEp->dir != direction);
  1099. spin_unlock_irqrestore(mEp->lock, flags);
  1100. return retval;
  1101. }
  1102. /**
  1103. * ep_set_wedge: sets the halt feature and ignores clear requests
  1104. *
  1105. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  1106. */
  1107. static int ep_set_wedge(struct usb_ep *ep)
  1108. {
  1109. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1110. unsigned long flags;
  1111. if (ep == NULL || mEp->ep.desc == NULL)
  1112. return -EINVAL;
  1113. spin_lock_irqsave(mEp->lock, flags);
  1114. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  1115. mEp->wedge = 1;
  1116. spin_unlock_irqrestore(mEp->lock, flags);
  1117. return usb_ep_set_halt(ep);
  1118. }
  1119. /**
  1120. * ep_fifo_flush: flushes contents of a fifo
  1121. *
  1122. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  1123. */
  1124. static void ep_fifo_flush(struct usb_ep *ep)
  1125. {
  1126. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1127. unsigned long flags;
  1128. if (ep == NULL) {
  1129. dev_err(mEp->udc->dev, "%02X: -EINVAL\n", _usb_addr(mEp));
  1130. return;
  1131. }
  1132. spin_lock_irqsave(mEp->lock, flags);
  1133. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  1134. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  1135. spin_unlock_irqrestore(mEp->lock, flags);
  1136. }
  1137. /**
  1138. * Endpoint-specific part of the API to the USB controller hardware
  1139. * Check "usb_gadget.h" for details
  1140. */
  1141. static const struct usb_ep_ops usb_ep_ops = {
  1142. .enable = ep_enable,
  1143. .disable = ep_disable,
  1144. .alloc_request = ep_alloc_request,
  1145. .free_request = ep_free_request,
  1146. .queue = ep_queue,
  1147. .dequeue = ep_dequeue,
  1148. .set_halt = ep_set_halt,
  1149. .set_wedge = ep_set_wedge,
  1150. .fifo_flush = ep_fifo_flush,
  1151. };
  1152. /******************************************************************************
  1153. * GADGET block
  1154. *****************************************************************************/
  1155. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  1156. {
  1157. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  1158. unsigned long flags;
  1159. int gadget_ready = 0;
  1160. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  1161. return -EOPNOTSUPP;
  1162. spin_lock_irqsave(&udc->lock, flags);
  1163. udc->vbus_active = is_active;
  1164. if (udc->driver)
  1165. gadget_ready = 1;
  1166. spin_unlock_irqrestore(&udc->lock, flags);
  1167. if (gadget_ready) {
  1168. if (is_active) {
  1169. pm_runtime_get_sync(&_gadget->dev);
  1170. hw_device_reset(udc, USBMODE_CM_DC);
  1171. hw_device_state(udc, udc->ep0out->qh.dma);
  1172. } else {
  1173. hw_device_state(udc, 0);
  1174. if (udc->udc_driver->notify_event)
  1175. udc->udc_driver->notify_event(udc,
  1176. CI13XXX_CONTROLLER_STOPPED_EVENT);
  1177. _gadget_stop_activity(&udc->gadget);
  1178. pm_runtime_put_sync(&_gadget->dev);
  1179. }
  1180. }
  1181. return 0;
  1182. }
  1183. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  1184. {
  1185. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  1186. unsigned long flags;
  1187. int ret = 0;
  1188. spin_lock_irqsave(&udc->lock, flags);
  1189. if (!udc->remote_wakeup) {
  1190. ret = -EOPNOTSUPP;
  1191. goto out;
  1192. }
  1193. if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
  1194. ret = -EINVAL;
  1195. goto out;
  1196. }
  1197. hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  1198. out:
  1199. spin_unlock_irqrestore(&udc->lock, flags);
  1200. return ret;
  1201. }
  1202. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  1203. {
  1204. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  1205. if (udc->transceiver)
  1206. return usb_phy_set_power(udc->transceiver, mA);
  1207. return -ENOTSUPP;
  1208. }
  1209. static int ci13xxx_start(struct usb_gadget *gadget,
  1210. struct usb_gadget_driver *driver);
  1211. static int ci13xxx_stop(struct usb_gadget *gadget,
  1212. struct usb_gadget_driver *driver);
  1213. /**
  1214. * Device operations part of the API to the USB controller hardware,
  1215. * which don't involve endpoints (or i/o)
  1216. * Check "usb_gadget.h" for details
  1217. */
  1218. static const struct usb_gadget_ops usb_gadget_ops = {
  1219. .vbus_session = ci13xxx_vbus_session,
  1220. .wakeup = ci13xxx_wakeup,
  1221. .vbus_draw = ci13xxx_vbus_draw,
  1222. .udc_start = ci13xxx_start,
  1223. .udc_stop = ci13xxx_stop,
  1224. };
  1225. static int init_eps(struct ci13xxx *udc)
  1226. {
  1227. int retval = 0, i, j;
  1228. for (i = 0; i < udc->hw_ep_max/2; i++)
  1229. for (j = RX; j <= TX; j++) {
  1230. int k = i + j * udc->hw_ep_max/2;
  1231. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  1232. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  1233. (j == TX) ? "in" : "out");
  1234. mEp->udc = udc;
  1235. mEp->lock = &udc->lock;
  1236. mEp->td_pool = udc->td_pool;
  1237. mEp->ep.name = mEp->name;
  1238. mEp->ep.ops = &usb_ep_ops;
  1239. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  1240. INIT_LIST_HEAD(&mEp->qh.queue);
  1241. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  1242. &mEp->qh.dma);
  1243. if (mEp->qh.ptr == NULL)
  1244. retval = -ENOMEM;
  1245. else
  1246. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  1247. /*
  1248. * set up shorthands for ep0 out and in endpoints,
  1249. * don't add to gadget's ep_list
  1250. */
  1251. if (i == 0) {
  1252. if (j == RX)
  1253. udc->ep0out = mEp;
  1254. else
  1255. udc->ep0in = mEp;
  1256. continue;
  1257. }
  1258. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  1259. }
  1260. return retval;
  1261. }
  1262. /**
  1263. * ci13xxx_start: register a gadget driver
  1264. * @gadget: our gadget
  1265. * @driver: the driver being registered
  1266. *
  1267. * Interrupts are enabled here.
  1268. */
  1269. static int ci13xxx_start(struct usb_gadget *gadget,
  1270. struct usb_gadget_driver *driver)
  1271. {
  1272. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1273. unsigned long flags;
  1274. int retval = -ENOMEM;
  1275. if (driver->disconnect == NULL)
  1276. return -EINVAL;
  1277. udc->ep0out->ep.desc = &ctrl_endpt_out_desc;
  1278. retval = usb_ep_enable(&udc->ep0out->ep);
  1279. if (retval)
  1280. return retval;
  1281. udc->ep0in->ep.desc = &ctrl_endpt_in_desc;
  1282. retval = usb_ep_enable(&udc->ep0in->ep);
  1283. if (retval)
  1284. return retval;
  1285. spin_lock_irqsave(&udc->lock, flags);
  1286. udc->driver = driver;
  1287. pm_runtime_get_sync(&udc->gadget.dev);
  1288. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  1289. if (udc->vbus_active) {
  1290. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  1291. hw_device_reset(udc, USBMODE_CM_DC);
  1292. } else {
  1293. pm_runtime_put_sync(&udc->gadget.dev);
  1294. goto done;
  1295. }
  1296. }
  1297. retval = hw_device_state(udc, udc->ep0out->qh.dma);
  1298. if (retval)
  1299. pm_runtime_put_sync(&udc->gadget.dev);
  1300. done:
  1301. spin_unlock_irqrestore(&udc->lock, flags);
  1302. return retval;
  1303. }
  1304. /**
  1305. * ci13xxx_stop: unregister a gadget driver
  1306. */
  1307. static int ci13xxx_stop(struct usb_gadget *gadget,
  1308. struct usb_gadget_driver *driver)
  1309. {
  1310. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1311. unsigned long flags;
  1312. spin_lock_irqsave(&udc->lock, flags);
  1313. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  1314. udc->vbus_active) {
  1315. hw_device_state(udc, 0);
  1316. if (udc->udc_driver->notify_event)
  1317. udc->udc_driver->notify_event(udc,
  1318. CI13XXX_CONTROLLER_STOPPED_EVENT);
  1319. udc->driver = NULL;
  1320. spin_unlock_irqrestore(&udc->lock, flags);
  1321. _gadget_stop_activity(&udc->gadget);
  1322. spin_lock_irqsave(&udc->lock, flags);
  1323. pm_runtime_put(&udc->gadget.dev);
  1324. }
  1325. spin_unlock_irqrestore(&udc->lock, flags);
  1326. return 0;
  1327. }
  1328. /******************************************************************************
  1329. * BUS block
  1330. *****************************************************************************/
  1331. /**
  1332. * udc_irq: udc interrupt handler
  1333. *
  1334. * This function returns IRQ_HANDLED if the IRQ has been handled
  1335. * It locks access to registers
  1336. */
  1337. static irqreturn_t udc_irq(struct ci13xxx *udc)
  1338. {
  1339. irqreturn_t retval;
  1340. u32 intr;
  1341. if (udc == NULL)
  1342. return IRQ_HANDLED;
  1343. spin_lock(&udc->lock);
  1344. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  1345. if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
  1346. USBMODE_CM_DC) {
  1347. spin_unlock(&udc->lock);
  1348. return IRQ_NONE;
  1349. }
  1350. }
  1351. intr = hw_test_and_clear_intr_active(udc);
  1352. dbg_interrupt(intr);
  1353. if (intr) {
  1354. /* order defines priority - do NOT change it */
  1355. if (USBi_URI & intr)
  1356. isr_reset_handler(udc);
  1357. if (USBi_PCI & intr) {
  1358. udc->gadget.speed = hw_port_is_high_speed(udc) ?
  1359. USB_SPEED_HIGH : USB_SPEED_FULL;
  1360. if (udc->suspended && udc->driver->resume) {
  1361. spin_unlock(&udc->lock);
  1362. udc->driver->resume(&udc->gadget);
  1363. spin_lock(&udc->lock);
  1364. udc->suspended = 0;
  1365. }
  1366. }
  1367. if (USBi_UI & intr)
  1368. isr_tr_complete_handler(udc);
  1369. if (USBi_SLI & intr) {
  1370. if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
  1371. udc->driver->suspend) {
  1372. udc->suspended = 1;
  1373. spin_unlock(&udc->lock);
  1374. udc->driver->suspend(&udc->gadget);
  1375. spin_lock(&udc->lock);
  1376. }
  1377. }
  1378. retval = IRQ_HANDLED;
  1379. } else {
  1380. retval = IRQ_NONE;
  1381. }
  1382. spin_unlock(&udc->lock);
  1383. return retval;
  1384. }
  1385. /**
  1386. * udc_release: driver release function
  1387. * @dev: device
  1388. *
  1389. * Currently does nothing
  1390. */
  1391. static void udc_release(struct device *dev)
  1392. {
  1393. }
  1394. /**
  1395. * udc_start: initialize gadget role
  1396. * @udc: chipidea controller
  1397. */
  1398. static int udc_start(struct ci13xxx *udc)
  1399. {
  1400. struct device *dev = udc->dev;
  1401. int retval = 0;
  1402. if (!udc)
  1403. return -EINVAL;
  1404. spin_lock_init(&udc->lock);
  1405. udc->gadget.ops = &usb_gadget_ops;
  1406. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1407. udc->gadget.max_speed = USB_SPEED_HIGH;
  1408. udc->gadget.is_otg = 0;
  1409. udc->gadget.name = udc->udc_driver->name;
  1410. INIT_LIST_HEAD(&udc->gadget.ep_list);
  1411. dev_set_name(&udc->gadget.dev, "gadget");
  1412. udc->gadget.dev.dma_mask = dev->dma_mask;
  1413. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  1414. udc->gadget.dev.parent = dev;
  1415. udc->gadget.dev.release = udc_release;
  1416. /* alloc resources */
  1417. udc->qh_pool = dma_pool_create("ci13xxx_qh", dev,
  1418. sizeof(struct ci13xxx_qh),
  1419. 64, CI13XXX_PAGE_SIZE);
  1420. if (udc->qh_pool == NULL)
  1421. return -ENOMEM;
  1422. udc->td_pool = dma_pool_create("ci13xxx_td", dev,
  1423. sizeof(struct ci13xxx_td),
  1424. 64, CI13XXX_PAGE_SIZE);
  1425. if (udc->td_pool == NULL) {
  1426. retval = -ENOMEM;
  1427. goto free_qh_pool;
  1428. }
  1429. retval = init_eps(udc);
  1430. if (retval)
  1431. goto free_pools;
  1432. udc->gadget.ep0 = &udc->ep0in->ep;
  1433. udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
  1434. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  1435. if (udc->transceiver == NULL) {
  1436. retval = -ENODEV;
  1437. goto free_pools;
  1438. }
  1439. }
  1440. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  1441. retval = hw_device_reset(udc, USBMODE_CM_DC);
  1442. if (retval)
  1443. goto put_transceiver;
  1444. }
  1445. retval = device_register(&udc->gadget.dev);
  1446. if (retval) {
  1447. put_device(&udc->gadget.dev);
  1448. goto put_transceiver;
  1449. }
  1450. retval = dbg_create_files(&udc->gadget.dev);
  1451. if (retval)
  1452. goto unreg_device;
  1453. if (udc->transceiver) {
  1454. retval = otg_set_peripheral(udc->transceiver->otg,
  1455. &udc->gadget);
  1456. if (retval)
  1457. goto remove_dbg;
  1458. }
  1459. retval = usb_add_gadget_udc(dev, &udc->gadget);
  1460. if (retval)
  1461. goto remove_trans;
  1462. pm_runtime_no_callbacks(&udc->gadget.dev);
  1463. pm_runtime_enable(&udc->gadget.dev);
  1464. return retval;
  1465. remove_trans:
  1466. if (udc->transceiver) {
  1467. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  1468. usb_put_phy(udc->transceiver);
  1469. }
  1470. dev_err(dev, "error = %i\n", retval);
  1471. remove_dbg:
  1472. dbg_remove_files(&udc->gadget.dev);
  1473. unreg_device:
  1474. device_unregister(&udc->gadget.dev);
  1475. put_transceiver:
  1476. if (udc->transceiver)
  1477. usb_put_phy(udc->transceiver);
  1478. free_pools:
  1479. dma_pool_destroy(udc->td_pool);
  1480. free_qh_pool:
  1481. dma_pool_destroy(udc->qh_pool);
  1482. return retval;
  1483. }
  1484. /**
  1485. * udc_remove: parent remove must call this to remove UDC
  1486. *
  1487. * No interrupts active, the IRQ has been released
  1488. */
  1489. static void udc_stop(struct ci13xxx *udc)
  1490. {
  1491. int i;
  1492. if (udc == NULL)
  1493. return;
  1494. usb_del_gadget_udc(&udc->gadget);
  1495. for (i = 0; i < udc->hw_ep_max; i++) {
  1496. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1497. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  1498. }
  1499. dma_pool_destroy(udc->td_pool);
  1500. dma_pool_destroy(udc->qh_pool);
  1501. if (udc->transceiver) {
  1502. otg_set_peripheral(udc->transceiver->otg, NULL);
  1503. usb_put_phy(udc->transceiver);
  1504. }
  1505. dbg_remove_files(&udc->gadget.dev);
  1506. device_unregister(&udc->gadget.dev);
  1507. /* my kobject is dynamic, I swear! */
  1508. memset(&udc->gadget, 0, sizeof(udc->gadget));
  1509. }
  1510. /**
  1511. * ci_hdrc_gadget_init - initialize device related bits
  1512. * ci: the controller
  1513. *
  1514. * This function enables the gadget role, if the device is "device capable".
  1515. */
  1516. int ci_hdrc_gadget_init(struct ci13xxx *ci)
  1517. {
  1518. struct ci_role_driver *rdrv;
  1519. if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DC))
  1520. return -ENXIO;
  1521. rdrv = devm_kzalloc(ci->dev, sizeof(struct ci_role_driver), GFP_KERNEL);
  1522. if (!rdrv)
  1523. return -ENOMEM;
  1524. rdrv->start = udc_start;
  1525. rdrv->stop = udc_stop;
  1526. rdrv->irq = udc_irq;
  1527. rdrv->name = "gadget";
  1528. ci->roles[CI_ROLE_GADGET] = rdrv;
  1529. return 0;
  1530. }