intel_display.c 299 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include <drm/drmP.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "i915_trace.h"
  39. #include <drm/drm_dp_helper.h>
  40. #include <drm/drm_crtc_helper.h>
  41. #include <linux/dma_remapping.h>
  42. static void intel_increase_pllclock(struct drm_crtc *crtc);
  43. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  44. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  45. struct intel_crtc_config *pipe_config);
  46. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  47. struct intel_crtc_config *pipe_config);
  48. static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  49. int x, int y, struct drm_framebuffer *old_fb);
  50. typedef struct {
  51. int min, max;
  52. } intel_range_t;
  53. typedef struct {
  54. int dot_limit;
  55. int p2_slow, p2_fast;
  56. } intel_p2_t;
  57. typedef struct intel_limit intel_limit_t;
  58. struct intel_limit {
  59. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  60. intel_p2_t p2;
  61. };
  62. int
  63. intel_pch_rawclk(struct drm_device *dev)
  64. {
  65. struct drm_i915_private *dev_priv = dev->dev_private;
  66. WARN_ON(!HAS_PCH_SPLIT(dev));
  67. return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  68. }
  69. static inline u32 /* units of 100MHz */
  70. intel_fdi_link_freq(struct drm_device *dev)
  71. {
  72. if (IS_GEN5(dev)) {
  73. struct drm_i915_private *dev_priv = dev->dev_private;
  74. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  75. } else
  76. return 27;
  77. }
  78. static const intel_limit_t intel_limits_i8xx_dac = {
  79. .dot = { .min = 25000, .max = 350000 },
  80. .vco = { .min = 930000, .max = 1400000 },
  81. .n = { .min = 3, .max = 16 },
  82. .m = { .min = 96, .max = 140 },
  83. .m1 = { .min = 18, .max = 26 },
  84. .m2 = { .min = 6, .max = 16 },
  85. .p = { .min = 4, .max = 128 },
  86. .p1 = { .min = 2, .max = 33 },
  87. .p2 = { .dot_limit = 165000,
  88. .p2_slow = 4, .p2_fast = 2 },
  89. };
  90. static const intel_limit_t intel_limits_i8xx_dvo = {
  91. .dot = { .min = 25000, .max = 350000 },
  92. .vco = { .min = 930000, .max = 1400000 },
  93. .n = { .min = 3, .max = 16 },
  94. .m = { .min = 96, .max = 140 },
  95. .m1 = { .min = 18, .max = 26 },
  96. .m2 = { .min = 6, .max = 16 },
  97. .p = { .min = 4, .max = 128 },
  98. .p1 = { .min = 2, .max = 33 },
  99. .p2 = { .dot_limit = 165000,
  100. .p2_slow = 4, .p2_fast = 4 },
  101. };
  102. static const intel_limit_t intel_limits_i8xx_lvds = {
  103. .dot = { .min = 25000, .max = 350000 },
  104. .vco = { .min = 930000, .max = 1400000 },
  105. .n = { .min = 3, .max = 16 },
  106. .m = { .min = 96, .max = 140 },
  107. .m1 = { .min = 18, .max = 26 },
  108. .m2 = { .min = 6, .max = 16 },
  109. .p = { .min = 4, .max = 128 },
  110. .p1 = { .min = 1, .max = 6 },
  111. .p2 = { .dot_limit = 165000,
  112. .p2_slow = 14, .p2_fast = 7 },
  113. };
  114. static const intel_limit_t intel_limits_i9xx_sdvo = {
  115. .dot = { .min = 20000, .max = 400000 },
  116. .vco = { .min = 1400000, .max = 2800000 },
  117. .n = { .min = 1, .max = 6 },
  118. .m = { .min = 70, .max = 120 },
  119. .m1 = { .min = 8, .max = 18 },
  120. .m2 = { .min = 3, .max = 7 },
  121. .p = { .min = 5, .max = 80 },
  122. .p1 = { .min = 1, .max = 8 },
  123. .p2 = { .dot_limit = 200000,
  124. .p2_slow = 10, .p2_fast = 5 },
  125. };
  126. static const intel_limit_t intel_limits_i9xx_lvds = {
  127. .dot = { .min = 20000, .max = 400000 },
  128. .vco = { .min = 1400000, .max = 2800000 },
  129. .n = { .min = 1, .max = 6 },
  130. .m = { .min = 70, .max = 120 },
  131. .m1 = { .min = 8, .max = 18 },
  132. .m2 = { .min = 3, .max = 7 },
  133. .p = { .min = 7, .max = 98 },
  134. .p1 = { .min = 1, .max = 8 },
  135. .p2 = { .dot_limit = 112000,
  136. .p2_slow = 14, .p2_fast = 7 },
  137. };
  138. static const intel_limit_t intel_limits_g4x_sdvo = {
  139. .dot = { .min = 25000, .max = 270000 },
  140. .vco = { .min = 1750000, .max = 3500000},
  141. .n = { .min = 1, .max = 4 },
  142. .m = { .min = 104, .max = 138 },
  143. .m1 = { .min = 17, .max = 23 },
  144. .m2 = { .min = 5, .max = 11 },
  145. .p = { .min = 10, .max = 30 },
  146. .p1 = { .min = 1, .max = 3},
  147. .p2 = { .dot_limit = 270000,
  148. .p2_slow = 10,
  149. .p2_fast = 10
  150. },
  151. };
  152. static const intel_limit_t intel_limits_g4x_hdmi = {
  153. .dot = { .min = 22000, .max = 400000 },
  154. .vco = { .min = 1750000, .max = 3500000},
  155. .n = { .min = 1, .max = 4 },
  156. .m = { .min = 104, .max = 138 },
  157. .m1 = { .min = 16, .max = 23 },
  158. .m2 = { .min = 5, .max = 11 },
  159. .p = { .min = 5, .max = 80 },
  160. .p1 = { .min = 1, .max = 8},
  161. .p2 = { .dot_limit = 165000,
  162. .p2_slow = 10, .p2_fast = 5 },
  163. };
  164. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  165. .dot = { .min = 20000, .max = 115000 },
  166. .vco = { .min = 1750000, .max = 3500000 },
  167. .n = { .min = 1, .max = 3 },
  168. .m = { .min = 104, .max = 138 },
  169. .m1 = { .min = 17, .max = 23 },
  170. .m2 = { .min = 5, .max = 11 },
  171. .p = { .min = 28, .max = 112 },
  172. .p1 = { .min = 2, .max = 8 },
  173. .p2 = { .dot_limit = 0,
  174. .p2_slow = 14, .p2_fast = 14
  175. },
  176. };
  177. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  178. .dot = { .min = 80000, .max = 224000 },
  179. .vco = { .min = 1750000, .max = 3500000 },
  180. .n = { .min = 1, .max = 3 },
  181. .m = { .min = 104, .max = 138 },
  182. .m1 = { .min = 17, .max = 23 },
  183. .m2 = { .min = 5, .max = 11 },
  184. .p = { .min = 14, .max = 42 },
  185. .p1 = { .min = 2, .max = 6 },
  186. .p2 = { .dot_limit = 0,
  187. .p2_slow = 7, .p2_fast = 7
  188. },
  189. };
  190. static const intel_limit_t intel_limits_pineview_sdvo = {
  191. .dot = { .min = 20000, .max = 400000},
  192. .vco = { .min = 1700000, .max = 3500000 },
  193. /* Pineview's Ncounter is a ring counter */
  194. .n = { .min = 3, .max = 6 },
  195. .m = { .min = 2, .max = 256 },
  196. /* Pineview only has one combined m divider, which we treat as m2. */
  197. .m1 = { .min = 0, .max = 0 },
  198. .m2 = { .min = 0, .max = 254 },
  199. .p = { .min = 5, .max = 80 },
  200. .p1 = { .min = 1, .max = 8 },
  201. .p2 = { .dot_limit = 200000,
  202. .p2_slow = 10, .p2_fast = 5 },
  203. };
  204. static const intel_limit_t intel_limits_pineview_lvds = {
  205. .dot = { .min = 20000, .max = 400000 },
  206. .vco = { .min = 1700000, .max = 3500000 },
  207. .n = { .min = 3, .max = 6 },
  208. .m = { .min = 2, .max = 256 },
  209. .m1 = { .min = 0, .max = 0 },
  210. .m2 = { .min = 0, .max = 254 },
  211. .p = { .min = 7, .max = 112 },
  212. .p1 = { .min = 1, .max = 8 },
  213. .p2 = { .dot_limit = 112000,
  214. .p2_slow = 14, .p2_fast = 14 },
  215. };
  216. /* Ironlake / Sandybridge
  217. *
  218. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  219. * the range value for them is (actual_value - 2).
  220. */
  221. static const intel_limit_t intel_limits_ironlake_dac = {
  222. .dot = { .min = 25000, .max = 350000 },
  223. .vco = { .min = 1760000, .max = 3510000 },
  224. .n = { .min = 1, .max = 5 },
  225. .m = { .min = 79, .max = 127 },
  226. .m1 = { .min = 12, .max = 22 },
  227. .m2 = { .min = 5, .max = 9 },
  228. .p = { .min = 5, .max = 80 },
  229. .p1 = { .min = 1, .max = 8 },
  230. .p2 = { .dot_limit = 225000,
  231. .p2_slow = 10, .p2_fast = 5 },
  232. };
  233. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  234. .dot = { .min = 25000, .max = 350000 },
  235. .vco = { .min = 1760000, .max = 3510000 },
  236. .n = { .min = 1, .max = 3 },
  237. .m = { .min = 79, .max = 118 },
  238. .m1 = { .min = 12, .max = 22 },
  239. .m2 = { .min = 5, .max = 9 },
  240. .p = { .min = 28, .max = 112 },
  241. .p1 = { .min = 2, .max = 8 },
  242. .p2 = { .dot_limit = 225000,
  243. .p2_slow = 14, .p2_fast = 14 },
  244. };
  245. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  246. .dot = { .min = 25000, .max = 350000 },
  247. .vco = { .min = 1760000, .max = 3510000 },
  248. .n = { .min = 1, .max = 3 },
  249. .m = { .min = 79, .max = 127 },
  250. .m1 = { .min = 12, .max = 22 },
  251. .m2 = { .min = 5, .max = 9 },
  252. .p = { .min = 14, .max = 56 },
  253. .p1 = { .min = 2, .max = 8 },
  254. .p2 = { .dot_limit = 225000,
  255. .p2_slow = 7, .p2_fast = 7 },
  256. };
  257. /* LVDS 100mhz refclk limits. */
  258. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  259. .dot = { .min = 25000, .max = 350000 },
  260. .vco = { .min = 1760000, .max = 3510000 },
  261. .n = { .min = 1, .max = 2 },
  262. .m = { .min = 79, .max = 126 },
  263. .m1 = { .min = 12, .max = 22 },
  264. .m2 = { .min = 5, .max = 9 },
  265. .p = { .min = 28, .max = 112 },
  266. .p1 = { .min = 2, .max = 8 },
  267. .p2 = { .dot_limit = 225000,
  268. .p2_slow = 14, .p2_fast = 14 },
  269. };
  270. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  271. .dot = { .min = 25000, .max = 350000 },
  272. .vco = { .min = 1760000, .max = 3510000 },
  273. .n = { .min = 1, .max = 3 },
  274. .m = { .min = 79, .max = 126 },
  275. .m1 = { .min = 12, .max = 22 },
  276. .m2 = { .min = 5, .max = 9 },
  277. .p = { .min = 14, .max = 42 },
  278. .p1 = { .min = 2, .max = 6 },
  279. .p2 = { .dot_limit = 225000,
  280. .p2_slow = 7, .p2_fast = 7 },
  281. };
  282. static const intel_limit_t intel_limits_vlv_dac = {
  283. .dot = { .min = 25000, .max = 270000 },
  284. .vco = { .min = 4000000, .max = 6000000 },
  285. .n = { .min = 1, .max = 7 },
  286. .m = { .min = 22, .max = 450 }, /* guess */
  287. .m1 = { .min = 2, .max = 3 },
  288. .m2 = { .min = 11, .max = 156 },
  289. .p = { .min = 10, .max = 30 },
  290. .p1 = { .min = 1, .max = 3 },
  291. .p2 = { .dot_limit = 270000,
  292. .p2_slow = 2, .p2_fast = 20 },
  293. };
  294. static const intel_limit_t intel_limits_vlv_hdmi = {
  295. .dot = { .min = 25000, .max = 270000 },
  296. .vco = { .min = 4000000, .max = 6000000 },
  297. .n = { .min = 1, .max = 7 },
  298. .m = { .min = 60, .max = 300 }, /* guess */
  299. .m1 = { .min = 2, .max = 3 },
  300. .m2 = { .min = 11, .max = 156 },
  301. .p = { .min = 10, .max = 30 },
  302. .p1 = { .min = 2, .max = 3 },
  303. .p2 = { .dot_limit = 270000,
  304. .p2_slow = 2, .p2_fast = 20 },
  305. };
  306. /**
  307. * Returns whether any output on the specified pipe is of the specified type
  308. */
  309. static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  310. {
  311. struct drm_device *dev = crtc->dev;
  312. struct intel_encoder *encoder;
  313. for_each_encoder_on_crtc(dev, crtc, encoder)
  314. if (encoder->type == type)
  315. return true;
  316. return false;
  317. }
  318. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  319. int refclk)
  320. {
  321. struct drm_device *dev = crtc->dev;
  322. const intel_limit_t *limit;
  323. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  324. if (intel_is_dual_link_lvds(dev)) {
  325. if (refclk == 100000)
  326. limit = &intel_limits_ironlake_dual_lvds_100m;
  327. else
  328. limit = &intel_limits_ironlake_dual_lvds;
  329. } else {
  330. if (refclk == 100000)
  331. limit = &intel_limits_ironlake_single_lvds_100m;
  332. else
  333. limit = &intel_limits_ironlake_single_lvds;
  334. }
  335. } else
  336. limit = &intel_limits_ironlake_dac;
  337. return limit;
  338. }
  339. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  340. {
  341. struct drm_device *dev = crtc->dev;
  342. const intel_limit_t *limit;
  343. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  344. if (intel_is_dual_link_lvds(dev))
  345. limit = &intel_limits_g4x_dual_channel_lvds;
  346. else
  347. limit = &intel_limits_g4x_single_channel_lvds;
  348. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  349. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  350. limit = &intel_limits_g4x_hdmi;
  351. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  352. limit = &intel_limits_g4x_sdvo;
  353. } else /* The option is for other outputs */
  354. limit = &intel_limits_i9xx_sdvo;
  355. return limit;
  356. }
  357. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  358. {
  359. struct drm_device *dev = crtc->dev;
  360. const intel_limit_t *limit;
  361. if (HAS_PCH_SPLIT(dev))
  362. limit = intel_ironlake_limit(crtc, refclk);
  363. else if (IS_G4X(dev)) {
  364. limit = intel_g4x_limit(crtc);
  365. } else if (IS_PINEVIEW(dev)) {
  366. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  367. limit = &intel_limits_pineview_lvds;
  368. else
  369. limit = &intel_limits_pineview_sdvo;
  370. } else if (IS_VALLEYVIEW(dev)) {
  371. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  372. limit = &intel_limits_vlv_dac;
  373. else
  374. limit = &intel_limits_vlv_hdmi;
  375. } else if (!IS_GEN2(dev)) {
  376. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  377. limit = &intel_limits_i9xx_lvds;
  378. else
  379. limit = &intel_limits_i9xx_sdvo;
  380. } else {
  381. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  382. limit = &intel_limits_i8xx_lvds;
  383. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
  384. limit = &intel_limits_i8xx_dvo;
  385. else
  386. limit = &intel_limits_i8xx_dac;
  387. }
  388. return limit;
  389. }
  390. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  391. static void pineview_clock(int refclk, intel_clock_t *clock)
  392. {
  393. clock->m = clock->m2 + 2;
  394. clock->p = clock->p1 * clock->p2;
  395. clock->vco = refclk * clock->m / clock->n;
  396. clock->dot = clock->vco / clock->p;
  397. }
  398. static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
  399. {
  400. return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
  401. }
  402. static void i9xx_clock(int refclk, intel_clock_t *clock)
  403. {
  404. clock->m = i9xx_dpll_compute_m(clock);
  405. clock->p = clock->p1 * clock->p2;
  406. clock->vco = refclk * clock->m / (clock->n + 2);
  407. clock->dot = clock->vco / clock->p;
  408. }
  409. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  410. /**
  411. * Returns whether the given set of divisors are valid for a given refclk with
  412. * the given connectors.
  413. */
  414. static bool intel_PLL_is_valid(struct drm_device *dev,
  415. const intel_limit_t *limit,
  416. const intel_clock_t *clock)
  417. {
  418. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  419. INTELPllInvalid("p1 out of range\n");
  420. if (clock->p < limit->p.min || limit->p.max < clock->p)
  421. INTELPllInvalid("p out of range\n");
  422. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  423. INTELPllInvalid("m2 out of range\n");
  424. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  425. INTELPllInvalid("m1 out of range\n");
  426. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  427. INTELPllInvalid("m1 <= m2\n");
  428. if (clock->m < limit->m.min || limit->m.max < clock->m)
  429. INTELPllInvalid("m out of range\n");
  430. if (clock->n < limit->n.min || limit->n.max < clock->n)
  431. INTELPllInvalid("n out of range\n");
  432. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  433. INTELPllInvalid("vco out of range\n");
  434. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  435. * connector, etc., rather than just a single range.
  436. */
  437. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  438. INTELPllInvalid("dot out of range\n");
  439. return true;
  440. }
  441. static bool
  442. i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  443. int target, int refclk, intel_clock_t *match_clock,
  444. intel_clock_t *best_clock)
  445. {
  446. struct drm_device *dev = crtc->dev;
  447. intel_clock_t clock;
  448. int err = target;
  449. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  450. /*
  451. * For LVDS just rely on its current settings for dual-channel.
  452. * We haven't figured out how to reliably set up different
  453. * single/dual channel state, if we even can.
  454. */
  455. if (intel_is_dual_link_lvds(dev))
  456. clock.p2 = limit->p2.p2_fast;
  457. else
  458. clock.p2 = limit->p2.p2_slow;
  459. } else {
  460. if (target < limit->p2.dot_limit)
  461. clock.p2 = limit->p2.p2_slow;
  462. else
  463. clock.p2 = limit->p2.p2_fast;
  464. }
  465. memset(best_clock, 0, sizeof(*best_clock));
  466. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  467. clock.m1++) {
  468. for (clock.m2 = limit->m2.min;
  469. clock.m2 <= limit->m2.max; clock.m2++) {
  470. if (clock.m2 >= clock.m1)
  471. break;
  472. for (clock.n = limit->n.min;
  473. clock.n <= limit->n.max; clock.n++) {
  474. for (clock.p1 = limit->p1.min;
  475. clock.p1 <= limit->p1.max; clock.p1++) {
  476. int this_err;
  477. i9xx_clock(refclk, &clock);
  478. if (!intel_PLL_is_valid(dev, limit,
  479. &clock))
  480. continue;
  481. if (match_clock &&
  482. clock.p != match_clock->p)
  483. continue;
  484. this_err = abs(clock.dot - target);
  485. if (this_err < err) {
  486. *best_clock = clock;
  487. err = this_err;
  488. }
  489. }
  490. }
  491. }
  492. }
  493. return (err != target);
  494. }
  495. static bool
  496. pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  497. int target, int refclk, intel_clock_t *match_clock,
  498. intel_clock_t *best_clock)
  499. {
  500. struct drm_device *dev = crtc->dev;
  501. intel_clock_t clock;
  502. int err = target;
  503. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  504. /*
  505. * For LVDS just rely on its current settings for dual-channel.
  506. * We haven't figured out how to reliably set up different
  507. * single/dual channel state, if we even can.
  508. */
  509. if (intel_is_dual_link_lvds(dev))
  510. clock.p2 = limit->p2.p2_fast;
  511. else
  512. clock.p2 = limit->p2.p2_slow;
  513. } else {
  514. if (target < limit->p2.dot_limit)
  515. clock.p2 = limit->p2.p2_slow;
  516. else
  517. clock.p2 = limit->p2.p2_fast;
  518. }
  519. memset(best_clock, 0, sizeof(*best_clock));
  520. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  521. clock.m1++) {
  522. for (clock.m2 = limit->m2.min;
  523. clock.m2 <= limit->m2.max; clock.m2++) {
  524. for (clock.n = limit->n.min;
  525. clock.n <= limit->n.max; clock.n++) {
  526. for (clock.p1 = limit->p1.min;
  527. clock.p1 <= limit->p1.max; clock.p1++) {
  528. int this_err;
  529. pineview_clock(refclk, &clock);
  530. if (!intel_PLL_is_valid(dev, limit,
  531. &clock))
  532. continue;
  533. if (match_clock &&
  534. clock.p != match_clock->p)
  535. continue;
  536. this_err = abs(clock.dot - target);
  537. if (this_err < err) {
  538. *best_clock = clock;
  539. err = this_err;
  540. }
  541. }
  542. }
  543. }
  544. }
  545. return (err != target);
  546. }
  547. static bool
  548. g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  549. int target, int refclk, intel_clock_t *match_clock,
  550. intel_clock_t *best_clock)
  551. {
  552. struct drm_device *dev = crtc->dev;
  553. intel_clock_t clock;
  554. int max_n;
  555. bool found;
  556. /* approximately equals target * 0.00585 */
  557. int err_most = (target >> 8) + (target >> 9);
  558. found = false;
  559. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  560. if (intel_is_dual_link_lvds(dev))
  561. clock.p2 = limit->p2.p2_fast;
  562. else
  563. clock.p2 = limit->p2.p2_slow;
  564. } else {
  565. if (target < limit->p2.dot_limit)
  566. clock.p2 = limit->p2.p2_slow;
  567. else
  568. clock.p2 = limit->p2.p2_fast;
  569. }
  570. memset(best_clock, 0, sizeof(*best_clock));
  571. max_n = limit->n.max;
  572. /* based on hardware requirement, prefer smaller n to precision */
  573. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  574. /* based on hardware requirement, prefere larger m1,m2 */
  575. for (clock.m1 = limit->m1.max;
  576. clock.m1 >= limit->m1.min; clock.m1--) {
  577. for (clock.m2 = limit->m2.max;
  578. clock.m2 >= limit->m2.min; clock.m2--) {
  579. for (clock.p1 = limit->p1.max;
  580. clock.p1 >= limit->p1.min; clock.p1--) {
  581. int this_err;
  582. i9xx_clock(refclk, &clock);
  583. if (!intel_PLL_is_valid(dev, limit,
  584. &clock))
  585. continue;
  586. this_err = abs(clock.dot - target);
  587. if (this_err < err_most) {
  588. *best_clock = clock;
  589. err_most = this_err;
  590. max_n = clock.n;
  591. found = true;
  592. }
  593. }
  594. }
  595. }
  596. }
  597. return found;
  598. }
  599. static bool
  600. vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  601. int target, int refclk, intel_clock_t *match_clock,
  602. intel_clock_t *best_clock)
  603. {
  604. u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
  605. u32 m, n, fastclk;
  606. u32 updrate, minupdate, p;
  607. unsigned long bestppm, ppm, absppm;
  608. int dotclk, flag;
  609. flag = 0;
  610. dotclk = target * 1000;
  611. bestppm = 1000000;
  612. ppm = absppm = 0;
  613. fastclk = dotclk / (2*100);
  614. updrate = 0;
  615. minupdate = 19200;
  616. n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
  617. bestm1 = bestm2 = bestp1 = bestp2 = 0;
  618. /* based on hardware requirement, prefer smaller n to precision */
  619. for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
  620. updrate = refclk / n;
  621. for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
  622. for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
  623. if (p2 > 10)
  624. p2 = p2 - 1;
  625. p = p1 * p2;
  626. /* based on hardware requirement, prefer bigger m1,m2 values */
  627. for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
  628. m2 = (((2*(fastclk * p * n / m1 )) +
  629. refclk) / (2*refclk));
  630. m = m1 * m2;
  631. vco = updrate * m;
  632. if (vco >= limit->vco.min && vco < limit->vco.max) {
  633. ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
  634. absppm = (ppm > 0) ? ppm : (-ppm);
  635. if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
  636. bestppm = 0;
  637. flag = 1;
  638. }
  639. if (absppm < bestppm - 10) {
  640. bestppm = absppm;
  641. flag = 1;
  642. }
  643. if (flag) {
  644. bestn = n;
  645. bestm1 = m1;
  646. bestm2 = m2;
  647. bestp1 = p1;
  648. bestp2 = p2;
  649. flag = 0;
  650. }
  651. }
  652. }
  653. }
  654. }
  655. }
  656. best_clock->n = bestn;
  657. best_clock->m1 = bestm1;
  658. best_clock->m2 = bestm2;
  659. best_clock->p1 = bestp1;
  660. best_clock->p2 = bestp2;
  661. return true;
  662. }
  663. bool intel_crtc_active(struct drm_crtc *crtc)
  664. {
  665. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  666. /* Be paranoid as we can arrive here with only partial
  667. * state retrieved from the hardware during setup.
  668. *
  669. * We can ditch the adjusted_mode.clock check as soon
  670. * as Haswell has gained clock readout/fastboot support.
  671. *
  672. * We can ditch the crtc->fb check as soon as we can
  673. * properly reconstruct framebuffers.
  674. */
  675. return intel_crtc->active && crtc->fb &&
  676. intel_crtc->config.adjusted_mode.clock;
  677. }
  678. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  679. enum pipe pipe)
  680. {
  681. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  682. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  683. return intel_crtc->config.cpu_transcoder;
  684. }
  685. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  686. {
  687. struct drm_i915_private *dev_priv = dev->dev_private;
  688. u32 frame, frame_reg = PIPEFRAME(pipe);
  689. frame = I915_READ(frame_reg);
  690. if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  691. DRM_DEBUG_KMS("vblank wait timed out\n");
  692. }
  693. /**
  694. * intel_wait_for_vblank - wait for vblank on a given pipe
  695. * @dev: drm device
  696. * @pipe: pipe to wait for
  697. *
  698. * Wait for vblank to occur on a given pipe. Needed for various bits of
  699. * mode setting code.
  700. */
  701. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  702. {
  703. struct drm_i915_private *dev_priv = dev->dev_private;
  704. int pipestat_reg = PIPESTAT(pipe);
  705. if (INTEL_INFO(dev)->gen >= 5) {
  706. ironlake_wait_for_vblank(dev, pipe);
  707. return;
  708. }
  709. /* Clear existing vblank status. Note this will clear any other
  710. * sticky status fields as well.
  711. *
  712. * This races with i915_driver_irq_handler() with the result
  713. * that either function could miss a vblank event. Here it is not
  714. * fatal, as we will either wait upon the next vblank interrupt or
  715. * timeout. Generally speaking intel_wait_for_vblank() is only
  716. * called during modeset at which time the GPU should be idle and
  717. * should *not* be performing page flips and thus not waiting on
  718. * vblanks...
  719. * Currently, the result of us stealing a vblank from the irq
  720. * handler is that a single frame will be skipped during swapbuffers.
  721. */
  722. I915_WRITE(pipestat_reg,
  723. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  724. /* Wait for vblank interrupt bit to set */
  725. if (wait_for(I915_READ(pipestat_reg) &
  726. PIPE_VBLANK_INTERRUPT_STATUS,
  727. 50))
  728. DRM_DEBUG_KMS("vblank wait timed out\n");
  729. }
  730. /*
  731. * intel_wait_for_pipe_off - wait for pipe to turn off
  732. * @dev: drm device
  733. * @pipe: pipe to wait for
  734. *
  735. * After disabling a pipe, we can't wait for vblank in the usual way,
  736. * spinning on the vblank interrupt status bit, since we won't actually
  737. * see an interrupt when the pipe is disabled.
  738. *
  739. * On Gen4 and above:
  740. * wait for the pipe register state bit to turn off
  741. *
  742. * Otherwise:
  743. * wait for the display line value to settle (it usually
  744. * ends up stopping at the start of the next frame).
  745. *
  746. */
  747. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  748. {
  749. struct drm_i915_private *dev_priv = dev->dev_private;
  750. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  751. pipe);
  752. if (INTEL_INFO(dev)->gen >= 4) {
  753. int reg = PIPECONF(cpu_transcoder);
  754. /* Wait for the Pipe State to go off */
  755. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  756. 100))
  757. WARN(1, "pipe_off wait timed out\n");
  758. } else {
  759. u32 last_line, line_mask;
  760. int reg = PIPEDSL(pipe);
  761. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  762. if (IS_GEN2(dev))
  763. line_mask = DSL_LINEMASK_GEN2;
  764. else
  765. line_mask = DSL_LINEMASK_GEN3;
  766. /* Wait for the display line to settle */
  767. do {
  768. last_line = I915_READ(reg) & line_mask;
  769. mdelay(5);
  770. } while (((I915_READ(reg) & line_mask) != last_line) &&
  771. time_after(timeout, jiffies));
  772. if (time_after(jiffies, timeout))
  773. WARN(1, "pipe_off wait timed out\n");
  774. }
  775. }
  776. /*
  777. * ibx_digital_port_connected - is the specified port connected?
  778. * @dev_priv: i915 private structure
  779. * @port: the port to test
  780. *
  781. * Returns true if @port is connected, false otherwise.
  782. */
  783. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  784. struct intel_digital_port *port)
  785. {
  786. u32 bit;
  787. if (HAS_PCH_IBX(dev_priv->dev)) {
  788. switch(port->port) {
  789. case PORT_B:
  790. bit = SDE_PORTB_HOTPLUG;
  791. break;
  792. case PORT_C:
  793. bit = SDE_PORTC_HOTPLUG;
  794. break;
  795. case PORT_D:
  796. bit = SDE_PORTD_HOTPLUG;
  797. break;
  798. default:
  799. return true;
  800. }
  801. } else {
  802. switch(port->port) {
  803. case PORT_B:
  804. bit = SDE_PORTB_HOTPLUG_CPT;
  805. break;
  806. case PORT_C:
  807. bit = SDE_PORTC_HOTPLUG_CPT;
  808. break;
  809. case PORT_D:
  810. bit = SDE_PORTD_HOTPLUG_CPT;
  811. break;
  812. default:
  813. return true;
  814. }
  815. }
  816. return I915_READ(SDEISR) & bit;
  817. }
  818. static const char *state_string(bool enabled)
  819. {
  820. return enabled ? "on" : "off";
  821. }
  822. /* Only for pre-ILK configs */
  823. void assert_pll(struct drm_i915_private *dev_priv,
  824. enum pipe pipe, bool state)
  825. {
  826. int reg;
  827. u32 val;
  828. bool cur_state;
  829. reg = DPLL(pipe);
  830. val = I915_READ(reg);
  831. cur_state = !!(val & DPLL_VCO_ENABLE);
  832. WARN(cur_state != state,
  833. "PLL state assertion failure (expected %s, current %s)\n",
  834. state_string(state), state_string(cur_state));
  835. }
  836. /* XXX: the dsi pll is shared between MIPI DSI ports */
  837. static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
  838. {
  839. u32 val;
  840. bool cur_state;
  841. mutex_lock(&dev_priv->dpio_lock);
  842. val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
  843. mutex_unlock(&dev_priv->dpio_lock);
  844. cur_state = val & DSI_PLL_VCO_EN;
  845. WARN(cur_state != state,
  846. "DSI PLL state assertion failure (expected %s, current %s)\n",
  847. state_string(state), state_string(cur_state));
  848. }
  849. #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
  850. #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
  851. struct intel_shared_dpll *
  852. intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
  853. {
  854. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  855. if (crtc->config.shared_dpll < 0)
  856. return NULL;
  857. return &dev_priv->shared_dplls[crtc->config.shared_dpll];
  858. }
  859. /* For ILK+ */
  860. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  861. struct intel_shared_dpll *pll,
  862. bool state)
  863. {
  864. bool cur_state;
  865. struct intel_dpll_hw_state hw_state;
  866. if (HAS_PCH_LPT(dev_priv->dev)) {
  867. DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  868. return;
  869. }
  870. if (WARN (!pll,
  871. "asserting DPLL %s with no DPLL\n", state_string(state)))
  872. return;
  873. cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
  874. WARN(cur_state != state,
  875. "%s assertion failure (expected %s, current %s)\n",
  876. pll->name, state_string(state), state_string(cur_state));
  877. }
  878. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  879. enum pipe pipe, bool state)
  880. {
  881. int reg;
  882. u32 val;
  883. bool cur_state;
  884. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  885. pipe);
  886. if (HAS_DDI(dev_priv->dev)) {
  887. /* DDI does not have a specific FDI_TX register */
  888. reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  889. val = I915_READ(reg);
  890. cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  891. } else {
  892. reg = FDI_TX_CTL(pipe);
  893. val = I915_READ(reg);
  894. cur_state = !!(val & FDI_TX_ENABLE);
  895. }
  896. WARN(cur_state != state,
  897. "FDI TX state assertion failure (expected %s, current %s)\n",
  898. state_string(state), state_string(cur_state));
  899. }
  900. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  901. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  902. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  903. enum pipe pipe, bool state)
  904. {
  905. int reg;
  906. u32 val;
  907. bool cur_state;
  908. reg = FDI_RX_CTL(pipe);
  909. val = I915_READ(reg);
  910. cur_state = !!(val & FDI_RX_ENABLE);
  911. WARN(cur_state != state,
  912. "FDI RX state assertion failure (expected %s, current %s)\n",
  913. state_string(state), state_string(cur_state));
  914. }
  915. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  916. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  917. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  918. enum pipe pipe)
  919. {
  920. int reg;
  921. u32 val;
  922. /* ILK FDI PLL is always enabled */
  923. if (dev_priv->info->gen == 5)
  924. return;
  925. /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  926. if (HAS_DDI(dev_priv->dev))
  927. return;
  928. reg = FDI_TX_CTL(pipe);
  929. val = I915_READ(reg);
  930. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  931. }
  932. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  933. enum pipe pipe, bool state)
  934. {
  935. int reg;
  936. u32 val;
  937. bool cur_state;
  938. reg = FDI_RX_CTL(pipe);
  939. val = I915_READ(reg);
  940. cur_state = !!(val & FDI_RX_PLL_ENABLE);
  941. WARN(cur_state != state,
  942. "FDI RX PLL assertion failure (expected %s, current %s)\n",
  943. state_string(state), state_string(cur_state));
  944. }
  945. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  946. enum pipe pipe)
  947. {
  948. int pp_reg, lvds_reg;
  949. u32 val;
  950. enum pipe panel_pipe = PIPE_A;
  951. bool locked = true;
  952. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  953. pp_reg = PCH_PP_CONTROL;
  954. lvds_reg = PCH_LVDS;
  955. } else {
  956. pp_reg = PP_CONTROL;
  957. lvds_reg = LVDS;
  958. }
  959. val = I915_READ(pp_reg);
  960. if (!(val & PANEL_POWER_ON) ||
  961. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  962. locked = false;
  963. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  964. panel_pipe = PIPE_B;
  965. WARN(panel_pipe == pipe && locked,
  966. "panel assertion failure, pipe %c regs locked\n",
  967. pipe_name(pipe));
  968. }
  969. static void assert_cursor(struct drm_i915_private *dev_priv,
  970. enum pipe pipe, bool state)
  971. {
  972. struct drm_device *dev = dev_priv->dev;
  973. bool cur_state;
  974. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  975. cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
  976. else if (IS_845G(dev) || IS_I865G(dev))
  977. cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
  978. else
  979. cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
  980. WARN(cur_state != state,
  981. "cursor on pipe %c assertion failure (expected %s, current %s)\n",
  982. pipe_name(pipe), state_string(state), state_string(cur_state));
  983. }
  984. #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
  985. #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
  986. void assert_pipe(struct drm_i915_private *dev_priv,
  987. enum pipe pipe, bool state)
  988. {
  989. int reg;
  990. u32 val;
  991. bool cur_state;
  992. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  993. pipe);
  994. /* if we need the pipe A quirk it must be always on */
  995. if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  996. state = true;
  997. if (!intel_display_power_enabled(dev_priv->dev,
  998. POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
  999. cur_state = false;
  1000. } else {
  1001. reg = PIPECONF(cpu_transcoder);
  1002. val = I915_READ(reg);
  1003. cur_state = !!(val & PIPECONF_ENABLE);
  1004. }
  1005. WARN(cur_state != state,
  1006. "pipe %c assertion failure (expected %s, current %s)\n",
  1007. pipe_name(pipe), state_string(state), state_string(cur_state));
  1008. }
  1009. static void assert_plane(struct drm_i915_private *dev_priv,
  1010. enum plane plane, bool state)
  1011. {
  1012. int reg;
  1013. u32 val;
  1014. bool cur_state;
  1015. reg = DSPCNTR(plane);
  1016. val = I915_READ(reg);
  1017. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1018. WARN(cur_state != state,
  1019. "plane %c assertion failure (expected %s, current %s)\n",
  1020. plane_name(plane), state_string(state), state_string(cur_state));
  1021. }
  1022. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1023. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1024. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1025. enum pipe pipe)
  1026. {
  1027. struct drm_device *dev = dev_priv->dev;
  1028. int reg, i;
  1029. u32 val;
  1030. int cur_pipe;
  1031. /* Primary planes are fixed to pipes on gen4+ */
  1032. if (INTEL_INFO(dev)->gen >= 4) {
  1033. reg = DSPCNTR(pipe);
  1034. val = I915_READ(reg);
  1035. WARN((val & DISPLAY_PLANE_ENABLE),
  1036. "plane %c assertion failure, should be disabled but not\n",
  1037. plane_name(pipe));
  1038. return;
  1039. }
  1040. /* Need to check both planes against the pipe */
  1041. for_each_pipe(i) {
  1042. reg = DSPCNTR(i);
  1043. val = I915_READ(reg);
  1044. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1045. DISPPLANE_SEL_PIPE_SHIFT;
  1046. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1047. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1048. plane_name(i), pipe_name(pipe));
  1049. }
  1050. }
  1051. static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
  1052. enum pipe pipe)
  1053. {
  1054. struct drm_device *dev = dev_priv->dev;
  1055. int reg, i;
  1056. u32 val;
  1057. if (IS_VALLEYVIEW(dev)) {
  1058. for (i = 0; i < dev_priv->num_plane; i++) {
  1059. reg = SPCNTR(pipe, i);
  1060. val = I915_READ(reg);
  1061. WARN((val & SP_ENABLE),
  1062. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1063. sprite_name(pipe, i), pipe_name(pipe));
  1064. }
  1065. } else if (INTEL_INFO(dev)->gen >= 7) {
  1066. reg = SPRCTL(pipe);
  1067. val = I915_READ(reg);
  1068. WARN((val & SPRITE_ENABLE),
  1069. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1070. plane_name(pipe), pipe_name(pipe));
  1071. } else if (INTEL_INFO(dev)->gen >= 5) {
  1072. reg = DVSCNTR(pipe);
  1073. val = I915_READ(reg);
  1074. WARN((val & DVS_ENABLE),
  1075. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1076. plane_name(pipe), pipe_name(pipe));
  1077. }
  1078. }
  1079. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1080. {
  1081. u32 val;
  1082. bool enabled;
  1083. if (HAS_PCH_LPT(dev_priv->dev)) {
  1084. DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1085. return;
  1086. }
  1087. val = I915_READ(PCH_DREF_CONTROL);
  1088. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1089. DREF_SUPERSPREAD_SOURCE_MASK));
  1090. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1091. }
  1092. static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
  1093. enum pipe pipe)
  1094. {
  1095. int reg;
  1096. u32 val;
  1097. bool enabled;
  1098. reg = PCH_TRANSCONF(pipe);
  1099. val = I915_READ(reg);
  1100. enabled = !!(val & TRANS_ENABLE);
  1101. WARN(enabled,
  1102. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1103. pipe_name(pipe));
  1104. }
  1105. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1106. enum pipe pipe, u32 port_sel, u32 val)
  1107. {
  1108. if ((val & DP_PORT_EN) == 0)
  1109. return false;
  1110. if (HAS_PCH_CPT(dev_priv->dev)) {
  1111. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1112. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1113. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1114. return false;
  1115. } else {
  1116. if ((val & DP_PIPE_MASK) != (pipe << 30))
  1117. return false;
  1118. }
  1119. return true;
  1120. }
  1121. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1122. enum pipe pipe, u32 val)
  1123. {
  1124. if ((val & SDVO_ENABLE) == 0)
  1125. return false;
  1126. if (HAS_PCH_CPT(dev_priv->dev)) {
  1127. if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
  1128. return false;
  1129. } else {
  1130. if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
  1131. return false;
  1132. }
  1133. return true;
  1134. }
  1135. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1136. enum pipe pipe, u32 val)
  1137. {
  1138. if ((val & LVDS_PORT_EN) == 0)
  1139. return false;
  1140. if (HAS_PCH_CPT(dev_priv->dev)) {
  1141. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1142. return false;
  1143. } else {
  1144. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1145. return false;
  1146. }
  1147. return true;
  1148. }
  1149. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1150. enum pipe pipe, u32 val)
  1151. {
  1152. if ((val & ADPA_DAC_ENABLE) == 0)
  1153. return false;
  1154. if (HAS_PCH_CPT(dev_priv->dev)) {
  1155. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1156. return false;
  1157. } else {
  1158. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1159. return false;
  1160. }
  1161. return true;
  1162. }
  1163. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1164. enum pipe pipe, int reg, u32 port_sel)
  1165. {
  1166. u32 val = I915_READ(reg);
  1167. WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1168. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1169. reg, pipe_name(pipe));
  1170. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
  1171. && (val & DP_PIPEB_SELECT),
  1172. "IBX PCH dp port still using transcoder B\n");
  1173. }
  1174. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1175. enum pipe pipe, int reg)
  1176. {
  1177. u32 val = I915_READ(reg);
  1178. WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1179. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1180. reg, pipe_name(pipe));
  1181. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
  1182. && (val & SDVO_PIPE_B_SELECT),
  1183. "IBX PCH hdmi port still using transcoder B\n");
  1184. }
  1185. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1186. enum pipe pipe)
  1187. {
  1188. int reg;
  1189. u32 val;
  1190. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1191. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1192. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1193. reg = PCH_ADPA;
  1194. val = I915_READ(reg);
  1195. WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1196. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1197. pipe_name(pipe));
  1198. reg = PCH_LVDS;
  1199. val = I915_READ(reg);
  1200. WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1201. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1202. pipe_name(pipe));
  1203. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
  1204. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
  1205. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
  1206. }
  1207. static void vlv_enable_pll(struct intel_crtc *crtc)
  1208. {
  1209. struct drm_device *dev = crtc->base.dev;
  1210. struct drm_i915_private *dev_priv = dev->dev_private;
  1211. int reg = DPLL(crtc->pipe);
  1212. u32 dpll = crtc->config.dpll_hw_state.dpll;
  1213. assert_pipe_disabled(dev_priv, crtc->pipe);
  1214. /* No really, not for ILK+ */
  1215. BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
  1216. /* PLL is protected by panel, make sure we can write it */
  1217. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1218. assert_panel_unlocked(dev_priv, crtc->pipe);
  1219. I915_WRITE(reg, dpll);
  1220. POSTING_READ(reg);
  1221. udelay(150);
  1222. if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1223. DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
  1224. I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
  1225. POSTING_READ(DPLL_MD(crtc->pipe));
  1226. /* We do this three times for luck */
  1227. I915_WRITE(reg, dpll);
  1228. POSTING_READ(reg);
  1229. udelay(150); /* wait for warmup */
  1230. I915_WRITE(reg, dpll);
  1231. POSTING_READ(reg);
  1232. udelay(150); /* wait for warmup */
  1233. I915_WRITE(reg, dpll);
  1234. POSTING_READ(reg);
  1235. udelay(150); /* wait for warmup */
  1236. }
  1237. static void i9xx_enable_pll(struct intel_crtc *crtc)
  1238. {
  1239. struct drm_device *dev = crtc->base.dev;
  1240. struct drm_i915_private *dev_priv = dev->dev_private;
  1241. int reg = DPLL(crtc->pipe);
  1242. u32 dpll = crtc->config.dpll_hw_state.dpll;
  1243. assert_pipe_disabled(dev_priv, crtc->pipe);
  1244. /* No really, not for ILK+ */
  1245. BUG_ON(dev_priv->info->gen >= 5);
  1246. /* PLL is protected by panel, make sure we can write it */
  1247. if (IS_MOBILE(dev) && !IS_I830(dev))
  1248. assert_panel_unlocked(dev_priv, crtc->pipe);
  1249. I915_WRITE(reg, dpll);
  1250. /* Wait for the clocks to stabilize. */
  1251. POSTING_READ(reg);
  1252. udelay(150);
  1253. if (INTEL_INFO(dev)->gen >= 4) {
  1254. I915_WRITE(DPLL_MD(crtc->pipe),
  1255. crtc->config.dpll_hw_state.dpll_md);
  1256. } else {
  1257. /* The pixel multiplier can only be updated once the
  1258. * DPLL is enabled and the clocks are stable.
  1259. *
  1260. * So write it again.
  1261. */
  1262. I915_WRITE(reg, dpll);
  1263. }
  1264. /* We do this three times for luck */
  1265. I915_WRITE(reg, dpll);
  1266. POSTING_READ(reg);
  1267. udelay(150); /* wait for warmup */
  1268. I915_WRITE(reg, dpll);
  1269. POSTING_READ(reg);
  1270. udelay(150); /* wait for warmup */
  1271. I915_WRITE(reg, dpll);
  1272. POSTING_READ(reg);
  1273. udelay(150); /* wait for warmup */
  1274. }
  1275. /**
  1276. * i9xx_disable_pll - disable a PLL
  1277. * @dev_priv: i915 private structure
  1278. * @pipe: pipe PLL to disable
  1279. *
  1280. * Disable the PLL for @pipe, making sure the pipe is off first.
  1281. *
  1282. * Note! This is for pre-ILK only.
  1283. */
  1284. static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1285. {
  1286. /* Don't disable pipe A or pipe A PLLs if needed */
  1287. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1288. return;
  1289. /* Make sure the pipe isn't still relying on us */
  1290. assert_pipe_disabled(dev_priv, pipe);
  1291. I915_WRITE(DPLL(pipe), 0);
  1292. POSTING_READ(DPLL(pipe));
  1293. }
  1294. void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
  1295. {
  1296. u32 port_mask;
  1297. if (!port)
  1298. port_mask = DPLL_PORTB_READY_MASK;
  1299. else
  1300. port_mask = DPLL_PORTC_READY_MASK;
  1301. if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
  1302. WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
  1303. 'B' + port, I915_READ(DPLL(0)));
  1304. }
  1305. /**
  1306. * ironlake_enable_shared_dpll - enable PCH PLL
  1307. * @dev_priv: i915 private structure
  1308. * @pipe: pipe PLL to enable
  1309. *
  1310. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1311. * drives the transcoder clock.
  1312. */
  1313. static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
  1314. {
  1315. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1316. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1317. /* PCH PLLs only available on ILK, SNB and IVB */
  1318. BUG_ON(dev_priv->info->gen < 5);
  1319. if (WARN_ON(pll == NULL))
  1320. return;
  1321. if (WARN_ON(pll->refcount == 0))
  1322. return;
  1323. DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
  1324. pll->name, pll->active, pll->on,
  1325. crtc->base.base.id);
  1326. if (pll->active++) {
  1327. WARN_ON(!pll->on);
  1328. assert_shared_dpll_enabled(dev_priv, pll);
  1329. return;
  1330. }
  1331. WARN_ON(pll->on);
  1332. DRM_DEBUG_KMS("enabling %s\n", pll->name);
  1333. pll->enable(dev_priv, pll);
  1334. pll->on = true;
  1335. }
  1336. static void intel_disable_shared_dpll(struct intel_crtc *crtc)
  1337. {
  1338. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1339. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1340. /* PCH only available on ILK+ */
  1341. BUG_ON(dev_priv->info->gen < 5);
  1342. if (WARN_ON(pll == NULL))
  1343. return;
  1344. if (WARN_ON(pll->refcount == 0))
  1345. return;
  1346. DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
  1347. pll->name, pll->active, pll->on,
  1348. crtc->base.base.id);
  1349. if (WARN_ON(pll->active == 0)) {
  1350. assert_shared_dpll_disabled(dev_priv, pll);
  1351. return;
  1352. }
  1353. assert_shared_dpll_enabled(dev_priv, pll);
  1354. WARN_ON(!pll->on);
  1355. if (--pll->active)
  1356. return;
  1357. DRM_DEBUG_KMS("disabling %s\n", pll->name);
  1358. pll->disable(dev_priv, pll);
  1359. pll->on = false;
  1360. }
  1361. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1362. enum pipe pipe)
  1363. {
  1364. struct drm_device *dev = dev_priv->dev;
  1365. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1366. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1367. uint32_t reg, val, pipeconf_val;
  1368. /* PCH only available on ILK+ */
  1369. BUG_ON(dev_priv->info->gen < 5);
  1370. /* Make sure PCH DPLL is enabled */
  1371. assert_shared_dpll_enabled(dev_priv,
  1372. intel_crtc_to_shared_dpll(intel_crtc));
  1373. /* FDI must be feeding us bits for PCH ports */
  1374. assert_fdi_tx_enabled(dev_priv, pipe);
  1375. assert_fdi_rx_enabled(dev_priv, pipe);
  1376. if (HAS_PCH_CPT(dev)) {
  1377. /* Workaround: Set the timing override bit before enabling the
  1378. * pch transcoder. */
  1379. reg = TRANS_CHICKEN2(pipe);
  1380. val = I915_READ(reg);
  1381. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1382. I915_WRITE(reg, val);
  1383. }
  1384. reg = PCH_TRANSCONF(pipe);
  1385. val = I915_READ(reg);
  1386. pipeconf_val = I915_READ(PIPECONF(pipe));
  1387. if (HAS_PCH_IBX(dev_priv->dev)) {
  1388. /*
  1389. * make the BPC in transcoder be consistent with
  1390. * that in pipeconf reg.
  1391. */
  1392. val &= ~PIPECONF_BPC_MASK;
  1393. val |= pipeconf_val & PIPECONF_BPC_MASK;
  1394. }
  1395. val &= ~TRANS_INTERLACE_MASK;
  1396. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1397. if (HAS_PCH_IBX(dev_priv->dev) &&
  1398. intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1399. val |= TRANS_LEGACY_INTERLACED_ILK;
  1400. else
  1401. val |= TRANS_INTERLACED;
  1402. else
  1403. val |= TRANS_PROGRESSIVE;
  1404. I915_WRITE(reg, val | TRANS_ENABLE);
  1405. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1406. DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
  1407. }
  1408. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1409. enum transcoder cpu_transcoder)
  1410. {
  1411. u32 val, pipeconf_val;
  1412. /* PCH only available on ILK+ */
  1413. BUG_ON(dev_priv->info->gen < 5);
  1414. /* FDI must be feeding us bits for PCH ports */
  1415. assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  1416. assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  1417. /* Workaround: set timing override bit. */
  1418. val = I915_READ(_TRANSA_CHICKEN2);
  1419. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1420. I915_WRITE(_TRANSA_CHICKEN2, val);
  1421. val = TRANS_ENABLE;
  1422. pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  1423. if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  1424. PIPECONF_INTERLACED_ILK)
  1425. val |= TRANS_INTERLACED;
  1426. else
  1427. val |= TRANS_PROGRESSIVE;
  1428. I915_WRITE(LPT_TRANSCONF, val);
  1429. if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
  1430. DRM_ERROR("Failed to enable PCH transcoder\n");
  1431. }
  1432. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  1433. enum pipe pipe)
  1434. {
  1435. struct drm_device *dev = dev_priv->dev;
  1436. uint32_t reg, val;
  1437. /* FDI relies on the transcoder */
  1438. assert_fdi_tx_disabled(dev_priv, pipe);
  1439. assert_fdi_rx_disabled(dev_priv, pipe);
  1440. /* Ports must be off as well */
  1441. assert_pch_ports_disabled(dev_priv, pipe);
  1442. reg = PCH_TRANSCONF(pipe);
  1443. val = I915_READ(reg);
  1444. val &= ~TRANS_ENABLE;
  1445. I915_WRITE(reg, val);
  1446. /* wait for PCH transcoder off, transcoder state */
  1447. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1448. DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  1449. if (!HAS_PCH_IBX(dev)) {
  1450. /* Workaround: Clear the timing override chicken bit again. */
  1451. reg = TRANS_CHICKEN2(pipe);
  1452. val = I915_READ(reg);
  1453. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1454. I915_WRITE(reg, val);
  1455. }
  1456. }
  1457. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  1458. {
  1459. u32 val;
  1460. val = I915_READ(LPT_TRANSCONF);
  1461. val &= ~TRANS_ENABLE;
  1462. I915_WRITE(LPT_TRANSCONF, val);
  1463. /* wait for PCH transcoder off, transcoder state */
  1464. if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
  1465. DRM_ERROR("Failed to disable PCH transcoder\n");
  1466. /* Workaround: clear timing override bit. */
  1467. val = I915_READ(_TRANSA_CHICKEN2);
  1468. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1469. I915_WRITE(_TRANSA_CHICKEN2, val);
  1470. }
  1471. /**
  1472. * intel_enable_pipe - enable a pipe, asserting requirements
  1473. * @dev_priv: i915 private structure
  1474. * @pipe: pipe to enable
  1475. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1476. *
  1477. * Enable @pipe, making sure that various hardware specific requirements
  1478. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1479. *
  1480. * @pipe should be %PIPE_A or %PIPE_B.
  1481. *
  1482. * Will wait until the pipe is actually running (i.e. first vblank) before
  1483. * returning.
  1484. */
  1485. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1486. bool pch_port, bool dsi)
  1487. {
  1488. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1489. pipe);
  1490. enum pipe pch_transcoder;
  1491. int reg;
  1492. u32 val;
  1493. assert_planes_disabled(dev_priv, pipe);
  1494. assert_cursor_disabled(dev_priv, pipe);
  1495. assert_sprites_disabled(dev_priv, pipe);
  1496. if (HAS_PCH_LPT(dev_priv->dev))
  1497. pch_transcoder = TRANSCODER_A;
  1498. else
  1499. pch_transcoder = pipe;
  1500. /*
  1501. * A pipe without a PLL won't actually be able to drive bits from
  1502. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1503. * need the check.
  1504. */
  1505. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1506. if (dsi)
  1507. assert_dsi_pll_enabled(dev_priv);
  1508. else
  1509. assert_pll_enabled(dev_priv, pipe);
  1510. else {
  1511. if (pch_port) {
  1512. /* if driving the PCH, we need FDI enabled */
  1513. assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  1514. assert_fdi_tx_pll_enabled(dev_priv,
  1515. (enum pipe) cpu_transcoder);
  1516. }
  1517. /* FIXME: assert CPU port conditions for SNB+ */
  1518. }
  1519. reg = PIPECONF(cpu_transcoder);
  1520. val = I915_READ(reg);
  1521. if (val & PIPECONF_ENABLE)
  1522. return;
  1523. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1524. intel_wait_for_vblank(dev_priv->dev, pipe);
  1525. }
  1526. /**
  1527. * intel_disable_pipe - disable a pipe, asserting requirements
  1528. * @dev_priv: i915 private structure
  1529. * @pipe: pipe to disable
  1530. *
  1531. * Disable @pipe, making sure that various hardware specific requirements
  1532. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1533. *
  1534. * @pipe should be %PIPE_A or %PIPE_B.
  1535. *
  1536. * Will wait until the pipe has shut down before returning.
  1537. */
  1538. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1539. enum pipe pipe)
  1540. {
  1541. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1542. pipe);
  1543. int reg;
  1544. u32 val;
  1545. /*
  1546. * Make sure planes won't keep trying to pump pixels to us,
  1547. * or we might hang the display.
  1548. */
  1549. assert_planes_disabled(dev_priv, pipe);
  1550. assert_cursor_disabled(dev_priv, pipe);
  1551. assert_sprites_disabled(dev_priv, pipe);
  1552. /* Don't disable pipe A or pipe A PLLs if needed */
  1553. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1554. return;
  1555. reg = PIPECONF(cpu_transcoder);
  1556. val = I915_READ(reg);
  1557. if ((val & PIPECONF_ENABLE) == 0)
  1558. return;
  1559. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1560. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1561. }
  1562. /*
  1563. * Plane regs are double buffered, going from enabled->disabled needs a
  1564. * trigger in order to latch. The display address reg provides this.
  1565. */
  1566. void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1567. enum plane plane)
  1568. {
  1569. if (dev_priv->info->gen >= 4)
  1570. I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1571. else
  1572. I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1573. }
  1574. /**
  1575. * intel_enable_plane - enable a display plane on a given pipe
  1576. * @dev_priv: i915 private structure
  1577. * @plane: plane to enable
  1578. * @pipe: pipe being fed
  1579. *
  1580. * Enable @plane on @pipe, making sure that @pipe is running first.
  1581. */
  1582. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1583. enum plane plane, enum pipe pipe)
  1584. {
  1585. int reg;
  1586. u32 val;
  1587. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1588. assert_pipe_enabled(dev_priv, pipe);
  1589. reg = DSPCNTR(plane);
  1590. val = I915_READ(reg);
  1591. if (val & DISPLAY_PLANE_ENABLE)
  1592. return;
  1593. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1594. intel_flush_display_plane(dev_priv, plane);
  1595. intel_wait_for_vblank(dev_priv->dev, pipe);
  1596. }
  1597. /**
  1598. * intel_disable_plane - disable a display plane
  1599. * @dev_priv: i915 private structure
  1600. * @plane: plane to disable
  1601. * @pipe: pipe consuming the data
  1602. *
  1603. * Disable @plane; should be an independent operation.
  1604. */
  1605. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1606. enum plane plane, enum pipe pipe)
  1607. {
  1608. int reg;
  1609. u32 val;
  1610. reg = DSPCNTR(plane);
  1611. val = I915_READ(reg);
  1612. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1613. return;
  1614. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1615. intel_flush_display_plane(dev_priv, plane);
  1616. intel_wait_for_vblank(dev_priv->dev, pipe);
  1617. }
  1618. static bool need_vtd_wa(struct drm_device *dev)
  1619. {
  1620. #ifdef CONFIG_INTEL_IOMMU
  1621. if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
  1622. return true;
  1623. #endif
  1624. return false;
  1625. }
  1626. int
  1627. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1628. struct drm_i915_gem_object *obj,
  1629. struct intel_ring_buffer *pipelined)
  1630. {
  1631. struct drm_i915_private *dev_priv = dev->dev_private;
  1632. u32 alignment;
  1633. int ret;
  1634. switch (obj->tiling_mode) {
  1635. case I915_TILING_NONE:
  1636. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1637. alignment = 128 * 1024;
  1638. else if (INTEL_INFO(dev)->gen >= 4)
  1639. alignment = 4 * 1024;
  1640. else
  1641. alignment = 64 * 1024;
  1642. break;
  1643. case I915_TILING_X:
  1644. /* pin() will align the object as required by fence */
  1645. alignment = 0;
  1646. break;
  1647. case I915_TILING_Y:
  1648. /* Despite that we check this in framebuffer_init userspace can
  1649. * screw us over and change the tiling after the fact. Only
  1650. * pinned buffers can't change their tiling. */
  1651. DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
  1652. return -EINVAL;
  1653. default:
  1654. BUG();
  1655. }
  1656. /* Note that the w/a also requires 64 PTE of padding following the
  1657. * bo. We currently fill all unused PTE with the shadow page and so
  1658. * we should always have valid PTE following the scanout preventing
  1659. * the VT-d warning.
  1660. */
  1661. if (need_vtd_wa(dev) && alignment < 256 * 1024)
  1662. alignment = 256 * 1024;
  1663. dev_priv->mm.interruptible = false;
  1664. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1665. if (ret)
  1666. goto err_interruptible;
  1667. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1668. * fence, whereas 965+ only requires a fence if using
  1669. * framebuffer compression. For simplicity, we always install
  1670. * a fence as the cost is not that onerous.
  1671. */
  1672. ret = i915_gem_object_get_fence(obj);
  1673. if (ret)
  1674. goto err_unpin;
  1675. i915_gem_object_pin_fence(obj);
  1676. dev_priv->mm.interruptible = true;
  1677. return 0;
  1678. err_unpin:
  1679. i915_gem_object_unpin_from_display_plane(obj);
  1680. err_interruptible:
  1681. dev_priv->mm.interruptible = true;
  1682. return ret;
  1683. }
  1684. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1685. {
  1686. i915_gem_object_unpin_fence(obj);
  1687. i915_gem_object_unpin_from_display_plane(obj);
  1688. }
  1689. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1690. * is assumed to be a power-of-two. */
  1691. unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  1692. unsigned int tiling_mode,
  1693. unsigned int cpp,
  1694. unsigned int pitch)
  1695. {
  1696. if (tiling_mode != I915_TILING_NONE) {
  1697. unsigned int tile_rows, tiles;
  1698. tile_rows = *y / 8;
  1699. *y %= 8;
  1700. tiles = *x / (512/cpp);
  1701. *x %= 512/cpp;
  1702. return tile_rows * pitch * 8 + tiles * 4096;
  1703. } else {
  1704. unsigned int offset;
  1705. offset = *y * pitch + *x * cpp;
  1706. *y = 0;
  1707. *x = (offset & 4095) / cpp;
  1708. return offset & -4096;
  1709. }
  1710. }
  1711. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1712. int x, int y)
  1713. {
  1714. struct drm_device *dev = crtc->dev;
  1715. struct drm_i915_private *dev_priv = dev->dev_private;
  1716. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1717. struct intel_framebuffer *intel_fb;
  1718. struct drm_i915_gem_object *obj;
  1719. int plane = intel_crtc->plane;
  1720. unsigned long linear_offset;
  1721. u32 dspcntr;
  1722. u32 reg;
  1723. switch (plane) {
  1724. case 0:
  1725. case 1:
  1726. break;
  1727. default:
  1728. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1729. return -EINVAL;
  1730. }
  1731. intel_fb = to_intel_framebuffer(fb);
  1732. obj = intel_fb->obj;
  1733. reg = DSPCNTR(plane);
  1734. dspcntr = I915_READ(reg);
  1735. /* Mask out pixel format bits in case we change it */
  1736. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1737. switch (fb->pixel_format) {
  1738. case DRM_FORMAT_C8:
  1739. dspcntr |= DISPPLANE_8BPP;
  1740. break;
  1741. case DRM_FORMAT_XRGB1555:
  1742. case DRM_FORMAT_ARGB1555:
  1743. dspcntr |= DISPPLANE_BGRX555;
  1744. break;
  1745. case DRM_FORMAT_RGB565:
  1746. dspcntr |= DISPPLANE_BGRX565;
  1747. break;
  1748. case DRM_FORMAT_XRGB8888:
  1749. case DRM_FORMAT_ARGB8888:
  1750. dspcntr |= DISPPLANE_BGRX888;
  1751. break;
  1752. case DRM_FORMAT_XBGR8888:
  1753. case DRM_FORMAT_ABGR8888:
  1754. dspcntr |= DISPPLANE_RGBX888;
  1755. break;
  1756. case DRM_FORMAT_XRGB2101010:
  1757. case DRM_FORMAT_ARGB2101010:
  1758. dspcntr |= DISPPLANE_BGRX101010;
  1759. break;
  1760. case DRM_FORMAT_XBGR2101010:
  1761. case DRM_FORMAT_ABGR2101010:
  1762. dspcntr |= DISPPLANE_RGBX101010;
  1763. break;
  1764. default:
  1765. BUG();
  1766. }
  1767. if (INTEL_INFO(dev)->gen >= 4) {
  1768. if (obj->tiling_mode != I915_TILING_NONE)
  1769. dspcntr |= DISPPLANE_TILED;
  1770. else
  1771. dspcntr &= ~DISPPLANE_TILED;
  1772. }
  1773. if (IS_G4X(dev))
  1774. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1775. I915_WRITE(reg, dspcntr);
  1776. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1777. if (INTEL_INFO(dev)->gen >= 4) {
  1778. intel_crtc->dspaddr_offset =
  1779. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1780. fb->bits_per_pixel / 8,
  1781. fb->pitches[0]);
  1782. linear_offset -= intel_crtc->dspaddr_offset;
  1783. } else {
  1784. intel_crtc->dspaddr_offset = linear_offset;
  1785. }
  1786. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1787. i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  1788. fb->pitches[0]);
  1789. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1790. if (INTEL_INFO(dev)->gen >= 4) {
  1791. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1792. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  1793. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1794. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1795. } else
  1796. I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
  1797. POSTING_READ(reg);
  1798. return 0;
  1799. }
  1800. static int ironlake_update_plane(struct drm_crtc *crtc,
  1801. struct drm_framebuffer *fb, int x, int y)
  1802. {
  1803. struct drm_device *dev = crtc->dev;
  1804. struct drm_i915_private *dev_priv = dev->dev_private;
  1805. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1806. struct intel_framebuffer *intel_fb;
  1807. struct drm_i915_gem_object *obj;
  1808. int plane = intel_crtc->plane;
  1809. unsigned long linear_offset;
  1810. u32 dspcntr;
  1811. u32 reg;
  1812. switch (plane) {
  1813. case 0:
  1814. case 1:
  1815. case 2:
  1816. break;
  1817. default:
  1818. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1819. return -EINVAL;
  1820. }
  1821. intel_fb = to_intel_framebuffer(fb);
  1822. obj = intel_fb->obj;
  1823. reg = DSPCNTR(plane);
  1824. dspcntr = I915_READ(reg);
  1825. /* Mask out pixel format bits in case we change it */
  1826. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1827. switch (fb->pixel_format) {
  1828. case DRM_FORMAT_C8:
  1829. dspcntr |= DISPPLANE_8BPP;
  1830. break;
  1831. case DRM_FORMAT_RGB565:
  1832. dspcntr |= DISPPLANE_BGRX565;
  1833. break;
  1834. case DRM_FORMAT_XRGB8888:
  1835. case DRM_FORMAT_ARGB8888:
  1836. dspcntr |= DISPPLANE_BGRX888;
  1837. break;
  1838. case DRM_FORMAT_XBGR8888:
  1839. case DRM_FORMAT_ABGR8888:
  1840. dspcntr |= DISPPLANE_RGBX888;
  1841. break;
  1842. case DRM_FORMAT_XRGB2101010:
  1843. case DRM_FORMAT_ARGB2101010:
  1844. dspcntr |= DISPPLANE_BGRX101010;
  1845. break;
  1846. case DRM_FORMAT_XBGR2101010:
  1847. case DRM_FORMAT_ABGR2101010:
  1848. dspcntr |= DISPPLANE_RGBX101010;
  1849. break;
  1850. default:
  1851. BUG();
  1852. }
  1853. if (obj->tiling_mode != I915_TILING_NONE)
  1854. dspcntr |= DISPPLANE_TILED;
  1855. else
  1856. dspcntr &= ~DISPPLANE_TILED;
  1857. if (IS_HASWELL(dev))
  1858. dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
  1859. else
  1860. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1861. I915_WRITE(reg, dspcntr);
  1862. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1863. intel_crtc->dspaddr_offset =
  1864. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1865. fb->bits_per_pixel / 8,
  1866. fb->pitches[0]);
  1867. linear_offset -= intel_crtc->dspaddr_offset;
  1868. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1869. i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  1870. fb->pitches[0]);
  1871. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1872. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1873. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  1874. if (IS_HASWELL(dev)) {
  1875. I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  1876. } else {
  1877. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1878. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1879. }
  1880. POSTING_READ(reg);
  1881. return 0;
  1882. }
  1883. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1884. static int
  1885. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1886. int x, int y, enum mode_set_atomic state)
  1887. {
  1888. struct drm_device *dev = crtc->dev;
  1889. struct drm_i915_private *dev_priv = dev->dev_private;
  1890. if (dev_priv->display.disable_fbc)
  1891. dev_priv->display.disable_fbc(dev);
  1892. intel_increase_pllclock(crtc);
  1893. return dev_priv->display.update_plane(crtc, fb, x, y);
  1894. }
  1895. void intel_display_handle_reset(struct drm_device *dev)
  1896. {
  1897. struct drm_i915_private *dev_priv = dev->dev_private;
  1898. struct drm_crtc *crtc;
  1899. /*
  1900. * Flips in the rings have been nuked by the reset,
  1901. * so complete all pending flips so that user space
  1902. * will get its events and not get stuck.
  1903. *
  1904. * Also update the base address of all primary
  1905. * planes to the the last fb to make sure we're
  1906. * showing the correct fb after a reset.
  1907. *
  1908. * Need to make two loops over the crtcs so that we
  1909. * don't try to grab a crtc mutex before the
  1910. * pending_flip_queue really got woken up.
  1911. */
  1912. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1913. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1914. enum plane plane = intel_crtc->plane;
  1915. intel_prepare_page_flip(dev, plane);
  1916. intel_finish_page_flip_plane(dev, plane);
  1917. }
  1918. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1919. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1920. mutex_lock(&crtc->mutex);
  1921. if (intel_crtc->active)
  1922. dev_priv->display.update_plane(crtc, crtc->fb,
  1923. crtc->x, crtc->y);
  1924. mutex_unlock(&crtc->mutex);
  1925. }
  1926. }
  1927. static int
  1928. intel_finish_fb(struct drm_framebuffer *old_fb)
  1929. {
  1930. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1931. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1932. bool was_interruptible = dev_priv->mm.interruptible;
  1933. int ret;
  1934. /* Big Hammer, we also need to ensure that any pending
  1935. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  1936. * current scanout is retired before unpinning the old
  1937. * framebuffer.
  1938. *
  1939. * This should only fail upon a hung GPU, in which case we
  1940. * can safely continue.
  1941. */
  1942. dev_priv->mm.interruptible = false;
  1943. ret = i915_gem_object_finish_gpu(obj);
  1944. dev_priv->mm.interruptible = was_interruptible;
  1945. return ret;
  1946. }
  1947. static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
  1948. {
  1949. struct drm_device *dev = crtc->dev;
  1950. struct drm_i915_master_private *master_priv;
  1951. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1952. if (!dev->primary->master)
  1953. return;
  1954. master_priv = dev->primary->master->driver_priv;
  1955. if (!master_priv->sarea_priv)
  1956. return;
  1957. switch (intel_crtc->pipe) {
  1958. case 0:
  1959. master_priv->sarea_priv->pipeA_x = x;
  1960. master_priv->sarea_priv->pipeA_y = y;
  1961. break;
  1962. case 1:
  1963. master_priv->sarea_priv->pipeB_x = x;
  1964. master_priv->sarea_priv->pipeB_y = y;
  1965. break;
  1966. default:
  1967. break;
  1968. }
  1969. }
  1970. static int
  1971. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1972. struct drm_framebuffer *fb)
  1973. {
  1974. struct drm_device *dev = crtc->dev;
  1975. struct drm_i915_private *dev_priv = dev->dev_private;
  1976. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1977. struct drm_framebuffer *old_fb;
  1978. int ret;
  1979. /* no fb bound */
  1980. if (!fb) {
  1981. DRM_ERROR("No FB bound\n");
  1982. return 0;
  1983. }
  1984. if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
  1985. DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
  1986. plane_name(intel_crtc->plane),
  1987. INTEL_INFO(dev)->num_pipes);
  1988. return -EINVAL;
  1989. }
  1990. mutex_lock(&dev->struct_mutex);
  1991. ret = intel_pin_and_fence_fb_obj(dev,
  1992. to_intel_framebuffer(fb)->obj,
  1993. NULL);
  1994. if (ret != 0) {
  1995. mutex_unlock(&dev->struct_mutex);
  1996. DRM_ERROR("pin & fence failed\n");
  1997. return ret;
  1998. }
  1999. /* Update pipe size and adjust fitter if needed */
  2000. if (i915_fastboot) {
  2001. I915_WRITE(PIPESRC(intel_crtc->pipe),
  2002. ((crtc->mode.hdisplay - 1) << 16) |
  2003. (crtc->mode.vdisplay - 1));
  2004. if (!intel_crtc->config.pch_pfit.enabled &&
  2005. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
  2006. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2007. I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
  2008. I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
  2009. I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
  2010. }
  2011. }
  2012. ret = dev_priv->display.update_plane(crtc, fb, x, y);
  2013. if (ret) {
  2014. intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
  2015. mutex_unlock(&dev->struct_mutex);
  2016. DRM_ERROR("failed to update base address\n");
  2017. return ret;
  2018. }
  2019. old_fb = crtc->fb;
  2020. crtc->fb = fb;
  2021. crtc->x = x;
  2022. crtc->y = y;
  2023. if (old_fb) {
  2024. if (intel_crtc->active && old_fb != fb)
  2025. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2026. intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  2027. }
  2028. intel_update_fbc(dev);
  2029. intel_edp_psr_update(dev);
  2030. mutex_unlock(&dev->struct_mutex);
  2031. intel_crtc_update_sarea_pos(crtc, x, y);
  2032. return 0;
  2033. }
  2034. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2035. {
  2036. struct drm_device *dev = crtc->dev;
  2037. struct drm_i915_private *dev_priv = dev->dev_private;
  2038. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2039. int pipe = intel_crtc->pipe;
  2040. u32 reg, temp;
  2041. /* enable normal train */
  2042. reg = FDI_TX_CTL(pipe);
  2043. temp = I915_READ(reg);
  2044. if (IS_IVYBRIDGE(dev)) {
  2045. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2046. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2047. } else {
  2048. temp &= ~FDI_LINK_TRAIN_NONE;
  2049. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2050. }
  2051. I915_WRITE(reg, temp);
  2052. reg = FDI_RX_CTL(pipe);
  2053. temp = I915_READ(reg);
  2054. if (HAS_PCH_CPT(dev)) {
  2055. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2056. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2057. } else {
  2058. temp &= ~FDI_LINK_TRAIN_NONE;
  2059. temp |= FDI_LINK_TRAIN_NONE;
  2060. }
  2061. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2062. /* wait one idle pattern time */
  2063. POSTING_READ(reg);
  2064. udelay(1000);
  2065. /* IVB wants error correction enabled */
  2066. if (IS_IVYBRIDGE(dev))
  2067. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2068. FDI_FE_ERRC_ENABLE);
  2069. }
  2070. static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
  2071. {
  2072. return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
  2073. }
  2074. static void ivb_modeset_global_resources(struct drm_device *dev)
  2075. {
  2076. struct drm_i915_private *dev_priv = dev->dev_private;
  2077. struct intel_crtc *pipe_B_crtc =
  2078. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  2079. struct intel_crtc *pipe_C_crtc =
  2080. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
  2081. uint32_t temp;
  2082. /*
  2083. * When everything is off disable fdi C so that we could enable fdi B
  2084. * with all lanes. Note that we don't care about enabled pipes without
  2085. * an enabled pch encoder.
  2086. */
  2087. if (!pipe_has_enabled_pch(pipe_B_crtc) &&
  2088. !pipe_has_enabled_pch(pipe_C_crtc)) {
  2089. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  2090. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  2091. temp = I915_READ(SOUTH_CHICKEN1);
  2092. temp &= ~FDI_BC_BIFURCATION_SELECT;
  2093. DRM_DEBUG_KMS("disabling fdi C rx\n");
  2094. I915_WRITE(SOUTH_CHICKEN1, temp);
  2095. }
  2096. }
  2097. /* The FDI link training functions for ILK/Ibexpeak. */
  2098. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2099. {
  2100. struct drm_device *dev = crtc->dev;
  2101. struct drm_i915_private *dev_priv = dev->dev_private;
  2102. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2103. int pipe = intel_crtc->pipe;
  2104. int plane = intel_crtc->plane;
  2105. u32 reg, temp, tries;
  2106. /* FDI needs bits from pipe & plane first */
  2107. assert_pipe_enabled(dev_priv, pipe);
  2108. assert_plane_enabled(dev_priv, plane);
  2109. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2110. for train result */
  2111. reg = FDI_RX_IMR(pipe);
  2112. temp = I915_READ(reg);
  2113. temp &= ~FDI_RX_SYMBOL_LOCK;
  2114. temp &= ~FDI_RX_BIT_LOCK;
  2115. I915_WRITE(reg, temp);
  2116. I915_READ(reg);
  2117. udelay(150);
  2118. /* enable CPU FDI TX and PCH FDI RX */
  2119. reg = FDI_TX_CTL(pipe);
  2120. temp = I915_READ(reg);
  2121. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2122. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2123. temp &= ~FDI_LINK_TRAIN_NONE;
  2124. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2125. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2126. reg = FDI_RX_CTL(pipe);
  2127. temp = I915_READ(reg);
  2128. temp &= ~FDI_LINK_TRAIN_NONE;
  2129. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2130. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2131. POSTING_READ(reg);
  2132. udelay(150);
  2133. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2134. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2135. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2136. FDI_RX_PHASE_SYNC_POINTER_EN);
  2137. reg = FDI_RX_IIR(pipe);
  2138. for (tries = 0; tries < 5; tries++) {
  2139. temp = I915_READ(reg);
  2140. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2141. if ((temp & FDI_RX_BIT_LOCK)) {
  2142. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2143. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2144. break;
  2145. }
  2146. }
  2147. if (tries == 5)
  2148. DRM_ERROR("FDI train 1 fail!\n");
  2149. /* Train 2 */
  2150. reg = FDI_TX_CTL(pipe);
  2151. temp = I915_READ(reg);
  2152. temp &= ~FDI_LINK_TRAIN_NONE;
  2153. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2154. I915_WRITE(reg, temp);
  2155. reg = FDI_RX_CTL(pipe);
  2156. temp = I915_READ(reg);
  2157. temp &= ~FDI_LINK_TRAIN_NONE;
  2158. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2159. I915_WRITE(reg, temp);
  2160. POSTING_READ(reg);
  2161. udelay(150);
  2162. reg = FDI_RX_IIR(pipe);
  2163. for (tries = 0; tries < 5; tries++) {
  2164. temp = I915_READ(reg);
  2165. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2166. if (temp & FDI_RX_SYMBOL_LOCK) {
  2167. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2168. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2169. break;
  2170. }
  2171. }
  2172. if (tries == 5)
  2173. DRM_ERROR("FDI train 2 fail!\n");
  2174. DRM_DEBUG_KMS("FDI train done\n");
  2175. }
  2176. static const int snb_b_fdi_train_param[] = {
  2177. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2178. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2179. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2180. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2181. };
  2182. /* The FDI link training functions for SNB/Cougarpoint. */
  2183. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2184. {
  2185. struct drm_device *dev = crtc->dev;
  2186. struct drm_i915_private *dev_priv = dev->dev_private;
  2187. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2188. int pipe = intel_crtc->pipe;
  2189. u32 reg, temp, i, retry;
  2190. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2191. for train result */
  2192. reg = FDI_RX_IMR(pipe);
  2193. temp = I915_READ(reg);
  2194. temp &= ~FDI_RX_SYMBOL_LOCK;
  2195. temp &= ~FDI_RX_BIT_LOCK;
  2196. I915_WRITE(reg, temp);
  2197. POSTING_READ(reg);
  2198. udelay(150);
  2199. /* enable CPU FDI TX and PCH FDI RX */
  2200. reg = FDI_TX_CTL(pipe);
  2201. temp = I915_READ(reg);
  2202. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2203. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2204. temp &= ~FDI_LINK_TRAIN_NONE;
  2205. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2206. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2207. /* SNB-B */
  2208. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2209. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2210. I915_WRITE(FDI_RX_MISC(pipe),
  2211. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2212. reg = FDI_RX_CTL(pipe);
  2213. temp = I915_READ(reg);
  2214. if (HAS_PCH_CPT(dev)) {
  2215. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2216. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2217. } else {
  2218. temp &= ~FDI_LINK_TRAIN_NONE;
  2219. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2220. }
  2221. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2222. POSTING_READ(reg);
  2223. udelay(150);
  2224. for (i = 0; i < 4; i++) {
  2225. reg = FDI_TX_CTL(pipe);
  2226. temp = I915_READ(reg);
  2227. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2228. temp |= snb_b_fdi_train_param[i];
  2229. I915_WRITE(reg, temp);
  2230. POSTING_READ(reg);
  2231. udelay(500);
  2232. for (retry = 0; retry < 5; retry++) {
  2233. reg = FDI_RX_IIR(pipe);
  2234. temp = I915_READ(reg);
  2235. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2236. if (temp & FDI_RX_BIT_LOCK) {
  2237. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2238. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2239. break;
  2240. }
  2241. udelay(50);
  2242. }
  2243. if (retry < 5)
  2244. break;
  2245. }
  2246. if (i == 4)
  2247. DRM_ERROR("FDI train 1 fail!\n");
  2248. /* Train 2 */
  2249. reg = FDI_TX_CTL(pipe);
  2250. temp = I915_READ(reg);
  2251. temp &= ~FDI_LINK_TRAIN_NONE;
  2252. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2253. if (IS_GEN6(dev)) {
  2254. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2255. /* SNB-B */
  2256. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2257. }
  2258. I915_WRITE(reg, temp);
  2259. reg = FDI_RX_CTL(pipe);
  2260. temp = I915_READ(reg);
  2261. if (HAS_PCH_CPT(dev)) {
  2262. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2263. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2264. } else {
  2265. temp &= ~FDI_LINK_TRAIN_NONE;
  2266. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2267. }
  2268. I915_WRITE(reg, temp);
  2269. POSTING_READ(reg);
  2270. udelay(150);
  2271. for (i = 0; i < 4; i++) {
  2272. reg = FDI_TX_CTL(pipe);
  2273. temp = I915_READ(reg);
  2274. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2275. temp |= snb_b_fdi_train_param[i];
  2276. I915_WRITE(reg, temp);
  2277. POSTING_READ(reg);
  2278. udelay(500);
  2279. for (retry = 0; retry < 5; retry++) {
  2280. reg = FDI_RX_IIR(pipe);
  2281. temp = I915_READ(reg);
  2282. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2283. if (temp & FDI_RX_SYMBOL_LOCK) {
  2284. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2285. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2286. break;
  2287. }
  2288. udelay(50);
  2289. }
  2290. if (retry < 5)
  2291. break;
  2292. }
  2293. if (i == 4)
  2294. DRM_ERROR("FDI train 2 fail!\n");
  2295. DRM_DEBUG_KMS("FDI train done.\n");
  2296. }
  2297. /* Manual link training for Ivy Bridge A0 parts */
  2298. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2299. {
  2300. struct drm_device *dev = crtc->dev;
  2301. struct drm_i915_private *dev_priv = dev->dev_private;
  2302. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2303. int pipe = intel_crtc->pipe;
  2304. u32 reg, temp, i, j;
  2305. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2306. for train result */
  2307. reg = FDI_RX_IMR(pipe);
  2308. temp = I915_READ(reg);
  2309. temp &= ~FDI_RX_SYMBOL_LOCK;
  2310. temp &= ~FDI_RX_BIT_LOCK;
  2311. I915_WRITE(reg, temp);
  2312. POSTING_READ(reg);
  2313. udelay(150);
  2314. DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  2315. I915_READ(FDI_RX_IIR(pipe)));
  2316. /* Try each vswing and preemphasis setting twice before moving on */
  2317. for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
  2318. /* disable first in case we need to retry */
  2319. reg = FDI_TX_CTL(pipe);
  2320. temp = I915_READ(reg);
  2321. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2322. temp &= ~FDI_TX_ENABLE;
  2323. I915_WRITE(reg, temp);
  2324. reg = FDI_RX_CTL(pipe);
  2325. temp = I915_READ(reg);
  2326. temp &= ~FDI_LINK_TRAIN_AUTO;
  2327. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2328. temp &= ~FDI_RX_ENABLE;
  2329. I915_WRITE(reg, temp);
  2330. /* enable CPU FDI TX and PCH FDI RX */
  2331. reg = FDI_TX_CTL(pipe);
  2332. temp = I915_READ(reg);
  2333. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2334. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2335. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2336. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2337. temp |= snb_b_fdi_train_param[j/2];
  2338. temp |= FDI_COMPOSITE_SYNC;
  2339. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2340. I915_WRITE(FDI_RX_MISC(pipe),
  2341. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2342. reg = FDI_RX_CTL(pipe);
  2343. temp = I915_READ(reg);
  2344. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2345. temp |= FDI_COMPOSITE_SYNC;
  2346. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2347. POSTING_READ(reg);
  2348. udelay(1); /* should be 0.5us */
  2349. for (i = 0; i < 4; i++) {
  2350. reg = FDI_RX_IIR(pipe);
  2351. temp = I915_READ(reg);
  2352. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2353. if (temp & FDI_RX_BIT_LOCK ||
  2354. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2355. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2356. DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
  2357. i);
  2358. break;
  2359. }
  2360. udelay(1); /* should be 0.5us */
  2361. }
  2362. if (i == 4) {
  2363. DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
  2364. continue;
  2365. }
  2366. /* Train 2 */
  2367. reg = FDI_TX_CTL(pipe);
  2368. temp = I915_READ(reg);
  2369. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2370. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2371. I915_WRITE(reg, temp);
  2372. reg = FDI_RX_CTL(pipe);
  2373. temp = I915_READ(reg);
  2374. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2375. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2376. I915_WRITE(reg, temp);
  2377. POSTING_READ(reg);
  2378. udelay(2); /* should be 1.5us */
  2379. for (i = 0; i < 4; i++) {
  2380. reg = FDI_RX_IIR(pipe);
  2381. temp = I915_READ(reg);
  2382. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2383. if (temp & FDI_RX_SYMBOL_LOCK ||
  2384. (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
  2385. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2386. DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
  2387. i);
  2388. goto train_done;
  2389. }
  2390. udelay(2); /* should be 1.5us */
  2391. }
  2392. if (i == 4)
  2393. DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
  2394. }
  2395. train_done:
  2396. DRM_DEBUG_KMS("FDI train done.\n");
  2397. }
  2398. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  2399. {
  2400. struct drm_device *dev = intel_crtc->base.dev;
  2401. struct drm_i915_private *dev_priv = dev->dev_private;
  2402. int pipe = intel_crtc->pipe;
  2403. u32 reg, temp;
  2404. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2405. reg = FDI_RX_CTL(pipe);
  2406. temp = I915_READ(reg);
  2407. temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
  2408. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2409. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2410. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2411. POSTING_READ(reg);
  2412. udelay(200);
  2413. /* Switch from Rawclk to PCDclk */
  2414. temp = I915_READ(reg);
  2415. I915_WRITE(reg, temp | FDI_PCDCLK);
  2416. POSTING_READ(reg);
  2417. udelay(200);
  2418. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2419. reg = FDI_TX_CTL(pipe);
  2420. temp = I915_READ(reg);
  2421. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2422. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2423. POSTING_READ(reg);
  2424. udelay(100);
  2425. }
  2426. }
  2427. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  2428. {
  2429. struct drm_device *dev = intel_crtc->base.dev;
  2430. struct drm_i915_private *dev_priv = dev->dev_private;
  2431. int pipe = intel_crtc->pipe;
  2432. u32 reg, temp;
  2433. /* Switch from PCDclk to Rawclk */
  2434. reg = FDI_RX_CTL(pipe);
  2435. temp = I915_READ(reg);
  2436. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2437. /* Disable CPU FDI TX PLL */
  2438. reg = FDI_TX_CTL(pipe);
  2439. temp = I915_READ(reg);
  2440. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2441. POSTING_READ(reg);
  2442. udelay(100);
  2443. reg = FDI_RX_CTL(pipe);
  2444. temp = I915_READ(reg);
  2445. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2446. /* Wait for the clocks to turn off. */
  2447. POSTING_READ(reg);
  2448. udelay(100);
  2449. }
  2450. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2451. {
  2452. struct drm_device *dev = crtc->dev;
  2453. struct drm_i915_private *dev_priv = dev->dev_private;
  2454. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2455. int pipe = intel_crtc->pipe;
  2456. u32 reg, temp;
  2457. /* disable CPU FDI tx and PCH FDI rx */
  2458. reg = FDI_TX_CTL(pipe);
  2459. temp = I915_READ(reg);
  2460. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2461. POSTING_READ(reg);
  2462. reg = FDI_RX_CTL(pipe);
  2463. temp = I915_READ(reg);
  2464. temp &= ~(0x7 << 16);
  2465. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2466. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2467. POSTING_READ(reg);
  2468. udelay(100);
  2469. /* Ironlake workaround, disable clock pointer after downing FDI */
  2470. if (HAS_PCH_IBX(dev)) {
  2471. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2472. }
  2473. /* still set train pattern 1 */
  2474. reg = FDI_TX_CTL(pipe);
  2475. temp = I915_READ(reg);
  2476. temp &= ~FDI_LINK_TRAIN_NONE;
  2477. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2478. I915_WRITE(reg, temp);
  2479. reg = FDI_RX_CTL(pipe);
  2480. temp = I915_READ(reg);
  2481. if (HAS_PCH_CPT(dev)) {
  2482. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2483. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2484. } else {
  2485. temp &= ~FDI_LINK_TRAIN_NONE;
  2486. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2487. }
  2488. /* BPC in FDI rx is consistent with that in PIPECONF */
  2489. temp &= ~(0x07 << 16);
  2490. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2491. I915_WRITE(reg, temp);
  2492. POSTING_READ(reg);
  2493. udelay(100);
  2494. }
  2495. static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
  2496. {
  2497. struct drm_device *dev = crtc->dev;
  2498. struct drm_i915_private *dev_priv = dev->dev_private;
  2499. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2500. unsigned long flags;
  2501. bool pending;
  2502. if (i915_reset_in_progress(&dev_priv->gpu_error) ||
  2503. intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  2504. return false;
  2505. spin_lock_irqsave(&dev->event_lock, flags);
  2506. pending = to_intel_crtc(crtc)->unpin_work != NULL;
  2507. spin_unlock_irqrestore(&dev->event_lock, flags);
  2508. return pending;
  2509. }
  2510. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2511. {
  2512. struct drm_device *dev = crtc->dev;
  2513. struct drm_i915_private *dev_priv = dev->dev_private;
  2514. if (crtc->fb == NULL)
  2515. return;
  2516. WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  2517. wait_event(dev_priv->pending_flip_queue,
  2518. !intel_crtc_has_pending_flip(crtc));
  2519. mutex_lock(&dev->struct_mutex);
  2520. intel_finish_fb(crtc->fb);
  2521. mutex_unlock(&dev->struct_mutex);
  2522. }
  2523. /* Program iCLKIP clock to the desired frequency */
  2524. static void lpt_program_iclkip(struct drm_crtc *crtc)
  2525. {
  2526. struct drm_device *dev = crtc->dev;
  2527. struct drm_i915_private *dev_priv = dev->dev_private;
  2528. int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
  2529. u32 divsel, phaseinc, auxdiv, phasedir = 0;
  2530. u32 temp;
  2531. mutex_lock(&dev_priv->dpio_lock);
  2532. /* It is necessary to ungate the pixclk gate prior to programming
  2533. * the divisors, and gate it back when it is done.
  2534. */
  2535. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  2536. /* Disable SSCCTL */
  2537. intel_sbi_write(dev_priv, SBI_SSCCTL6,
  2538. intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
  2539. SBI_SSCCTL_DISABLE,
  2540. SBI_ICLK);
  2541. /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  2542. if (clock == 20000) {
  2543. auxdiv = 1;
  2544. divsel = 0x41;
  2545. phaseinc = 0x20;
  2546. } else {
  2547. /* The iCLK virtual clock root frequency is in MHz,
  2548. * but the adjusted_mode->clock in in KHz. To get the divisors,
  2549. * it is necessary to divide one by another, so we
  2550. * convert the virtual clock precision to KHz here for higher
  2551. * precision.
  2552. */
  2553. u32 iclk_virtual_root_freq = 172800 * 1000;
  2554. u32 iclk_pi_range = 64;
  2555. u32 desired_divisor, msb_divisor_value, pi_value;
  2556. desired_divisor = (iclk_virtual_root_freq / clock);
  2557. msb_divisor_value = desired_divisor / iclk_pi_range;
  2558. pi_value = desired_divisor % iclk_pi_range;
  2559. auxdiv = 0;
  2560. divsel = msb_divisor_value - 2;
  2561. phaseinc = pi_value;
  2562. }
  2563. /* This should not happen with any sane values */
  2564. WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  2565. ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  2566. WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  2567. ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  2568. DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  2569. clock,
  2570. auxdiv,
  2571. divsel,
  2572. phasedir,
  2573. phaseinc);
  2574. /* Program SSCDIVINTPHASE6 */
  2575. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  2576. temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  2577. temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  2578. temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  2579. temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  2580. temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  2581. temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  2582. intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
  2583. /* Program SSCAUXDIV */
  2584. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  2585. temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  2586. temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  2587. intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
  2588. /* Enable modulator and associated divider */
  2589. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  2590. temp &= ~SBI_SSCCTL_DISABLE;
  2591. intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  2592. /* Wait for initialization time */
  2593. udelay(24);
  2594. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  2595. mutex_unlock(&dev_priv->dpio_lock);
  2596. }
  2597. static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
  2598. enum pipe pch_transcoder)
  2599. {
  2600. struct drm_device *dev = crtc->base.dev;
  2601. struct drm_i915_private *dev_priv = dev->dev_private;
  2602. enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
  2603. I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
  2604. I915_READ(HTOTAL(cpu_transcoder)));
  2605. I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
  2606. I915_READ(HBLANK(cpu_transcoder)));
  2607. I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
  2608. I915_READ(HSYNC(cpu_transcoder)));
  2609. I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
  2610. I915_READ(VTOTAL(cpu_transcoder)));
  2611. I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
  2612. I915_READ(VBLANK(cpu_transcoder)));
  2613. I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
  2614. I915_READ(VSYNC(cpu_transcoder)));
  2615. I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
  2616. I915_READ(VSYNCSHIFT(cpu_transcoder)));
  2617. }
  2618. /*
  2619. * Enable PCH resources required for PCH ports:
  2620. * - PCH PLLs
  2621. * - FDI training & RX/TX
  2622. * - update transcoder timings
  2623. * - DP transcoding bits
  2624. * - transcoder
  2625. */
  2626. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2627. {
  2628. struct drm_device *dev = crtc->dev;
  2629. struct drm_i915_private *dev_priv = dev->dev_private;
  2630. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2631. int pipe = intel_crtc->pipe;
  2632. u32 reg, temp;
  2633. assert_pch_transcoder_disabled(dev_priv, pipe);
  2634. /* Write the TU size bits before fdi link training, so that error
  2635. * detection works. */
  2636. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2637. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2638. /* For PCH output, training FDI link */
  2639. dev_priv->display.fdi_link_train(crtc);
  2640. /* We need to program the right clock selection before writing the pixel
  2641. * mutliplier into the DPLL. */
  2642. if (HAS_PCH_CPT(dev)) {
  2643. u32 sel;
  2644. temp = I915_READ(PCH_DPLL_SEL);
  2645. temp |= TRANS_DPLL_ENABLE(pipe);
  2646. sel = TRANS_DPLLB_SEL(pipe);
  2647. if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
  2648. temp |= sel;
  2649. else
  2650. temp &= ~sel;
  2651. I915_WRITE(PCH_DPLL_SEL, temp);
  2652. }
  2653. /* XXX: pch pll's can be enabled any time before we enable the PCH
  2654. * transcoder, and we actually should do this to not upset any PCH
  2655. * transcoder that already use the clock when we share it.
  2656. *
  2657. * Note that enable_shared_dpll tries to do the right thing, but
  2658. * get_shared_dpll unconditionally resets the pll - we need that to have
  2659. * the right LVDS enable sequence. */
  2660. ironlake_enable_shared_dpll(intel_crtc);
  2661. /* set transcoder timing, panel must allow it */
  2662. assert_panel_unlocked(dev_priv, pipe);
  2663. ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
  2664. intel_fdi_normal_train(crtc);
  2665. /* For PCH DP, enable TRANS_DP_CTL */
  2666. if (HAS_PCH_CPT(dev) &&
  2667. (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  2668. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2669. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
  2670. reg = TRANS_DP_CTL(pipe);
  2671. temp = I915_READ(reg);
  2672. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2673. TRANS_DP_SYNC_MASK |
  2674. TRANS_DP_BPC_MASK);
  2675. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2676. TRANS_DP_ENH_FRAMING);
  2677. temp |= bpc << 9; /* same format but at 11:9 */
  2678. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2679. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2680. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2681. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2682. switch (intel_trans_dp_port_sel(crtc)) {
  2683. case PCH_DP_B:
  2684. temp |= TRANS_DP_PORT_SEL_B;
  2685. break;
  2686. case PCH_DP_C:
  2687. temp |= TRANS_DP_PORT_SEL_C;
  2688. break;
  2689. case PCH_DP_D:
  2690. temp |= TRANS_DP_PORT_SEL_D;
  2691. break;
  2692. default:
  2693. BUG();
  2694. }
  2695. I915_WRITE(reg, temp);
  2696. }
  2697. ironlake_enable_pch_transcoder(dev_priv, pipe);
  2698. }
  2699. static void lpt_pch_enable(struct drm_crtc *crtc)
  2700. {
  2701. struct drm_device *dev = crtc->dev;
  2702. struct drm_i915_private *dev_priv = dev->dev_private;
  2703. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2704. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  2705. assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
  2706. lpt_program_iclkip(crtc);
  2707. /* Set transcoder timing. */
  2708. ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
  2709. lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
  2710. }
  2711. static void intel_put_shared_dpll(struct intel_crtc *crtc)
  2712. {
  2713. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  2714. if (pll == NULL)
  2715. return;
  2716. if (pll->refcount == 0) {
  2717. WARN(1, "bad %s refcount\n", pll->name);
  2718. return;
  2719. }
  2720. if (--pll->refcount == 0) {
  2721. WARN_ON(pll->on);
  2722. WARN_ON(pll->active);
  2723. }
  2724. crtc->config.shared_dpll = DPLL_ID_PRIVATE;
  2725. }
  2726. static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
  2727. {
  2728. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  2729. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  2730. enum intel_dpll_id i;
  2731. if (pll) {
  2732. DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
  2733. crtc->base.base.id, pll->name);
  2734. intel_put_shared_dpll(crtc);
  2735. }
  2736. if (HAS_PCH_IBX(dev_priv->dev)) {
  2737. /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  2738. i = (enum intel_dpll_id) crtc->pipe;
  2739. pll = &dev_priv->shared_dplls[i];
  2740. DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
  2741. crtc->base.base.id, pll->name);
  2742. goto found;
  2743. }
  2744. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  2745. pll = &dev_priv->shared_dplls[i];
  2746. /* Only want to check enabled timings first */
  2747. if (pll->refcount == 0)
  2748. continue;
  2749. if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
  2750. sizeof(pll->hw_state)) == 0) {
  2751. DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
  2752. crtc->base.base.id,
  2753. pll->name, pll->refcount, pll->active);
  2754. goto found;
  2755. }
  2756. }
  2757. /* Ok no matching timings, maybe there's a free one? */
  2758. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  2759. pll = &dev_priv->shared_dplls[i];
  2760. if (pll->refcount == 0) {
  2761. DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
  2762. crtc->base.base.id, pll->name);
  2763. goto found;
  2764. }
  2765. }
  2766. return NULL;
  2767. found:
  2768. crtc->config.shared_dpll = i;
  2769. DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
  2770. pipe_name(crtc->pipe));
  2771. if (pll->active == 0) {
  2772. memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
  2773. sizeof(pll->hw_state));
  2774. DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
  2775. WARN_ON(pll->on);
  2776. assert_shared_dpll_disabled(dev_priv, pll);
  2777. pll->mode_set(dev_priv, pll);
  2778. }
  2779. pll->refcount++;
  2780. return pll;
  2781. }
  2782. static void cpt_verify_modeset(struct drm_device *dev, int pipe)
  2783. {
  2784. struct drm_i915_private *dev_priv = dev->dev_private;
  2785. int dslreg = PIPEDSL(pipe);
  2786. u32 temp;
  2787. temp = I915_READ(dslreg);
  2788. udelay(500);
  2789. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  2790. if (wait_for(I915_READ(dslreg) != temp, 5))
  2791. DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
  2792. }
  2793. }
  2794. static void ironlake_pfit_enable(struct intel_crtc *crtc)
  2795. {
  2796. struct drm_device *dev = crtc->base.dev;
  2797. struct drm_i915_private *dev_priv = dev->dev_private;
  2798. int pipe = crtc->pipe;
  2799. if (crtc->config.pch_pfit.enabled) {
  2800. /* Force use of hard-coded filter coefficients
  2801. * as some pre-programmed values are broken,
  2802. * e.g. x201.
  2803. */
  2804. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  2805. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  2806. PF_PIPE_SEL_IVB(pipe));
  2807. else
  2808. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2809. I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
  2810. I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
  2811. }
  2812. }
  2813. static void intel_enable_planes(struct drm_crtc *crtc)
  2814. {
  2815. struct drm_device *dev = crtc->dev;
  2816. enum pipe pipe = to_intel_crtc(crtc)->pipe;
  2817. struct intel_plane *intel_plane;
  2818. list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  2819. if (intel_plane->pipe == pipe)
  2820. intel_plane_restore(&intel_plane->base);
  2821. }
  2822. static void intel_disable_planes(struct drm_crtc *crtc)
  2823. {
  2824. struct drm_device *dev = crtc->dev;
  2825. enum pipe pipe = to_intel_crtc(crtc)->pipe;
  2826. struct intel_plane *intel_plane;
  2827. list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  2828. if (intel_plane->pipe == pipe)
  2829. intel_plane_disable(&intel_plane->base);
  2830. }
  2831. static void hsw_enable_ips(struct intel_crtc *crtc)
  2832. {
  2833. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  2834. if (!crtc->config.ips_enabled)
  2835. return;
  2836. /* We can only enable IPS after we enable a plane and wait for a vblank.
  2837. * We guarantee that the plane is enabled by calling intel_enable_ips
  2838. * only after intel_enable_plane. And intel_enable_plane already waits
  2839. * for a vblank, so all we need to do here is to enable the IPS bit. */
  2840. assert_plane_enabled(dev_priv, crtc->plane);
  2841. I915_WRITE(IPS_CTL, IPS_ENABLE);
  2842. }
  2843. static void hsw_disable_ips(struct intel_crtc *crtc)
  2844. {
  2845. struct drm_device *dev = crtc->base.dev;
  2846. struct drm_i915_private *dev_priv = dev->dev_private;
  2847. if (!crtc->config.ips_enabled)
  2848. return;
  2849. assert_plane_enabled(dev_priv, crtc->plane);
  2850. I915_WRITE(IPS_CTL, 0);
  2851. POSTING_READ(IPS_CTL);
  2852. /* We need to wait for a vblank before we can disable the plane. */
  2853. intel_wait_for_vblank(dev, crtc->pipe);
  2854. }
  2855. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  2856. static void intel_crtc_load_lut(struct drm_crtc *crtc)
  2857. {
  2858. struct drm_device *dev = crtc->dev;
  2859. struct drm_i915_private *dev_priv = dev->dev_private;
  2860. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2861. enum pipe pipe = intel_crtc->pipe;
  2862. int palreg = PALETTE(pipe);
  2863. int i;
  2864. bool reenable_ips = false;
  2865. /* The clocks have to be on to load the palette. */
  2866. if (!crtc->enabled || !intel_crtc->active)
  2867. return;
  2868. if (!HAS_PCH_SPLIT(dev_priv->dev)) {
  2869. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
  2870. assert_dsi_pll_enabled(dev_priv);
  2871. else
  2872. assert_pll_enabled(dev_priv, pipe);
  2873. }
  2874. /* use legacy palette for Ironlake */
  2875. if (HAS_PCH_SPLIT(dev))
  2876. palreg = LGC_PALETTE(pipe);
  2877. /* Workaround : Do not read or write the pipe palette/gamma data while
  2878. * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
  2879. */
  2880. if (intel_crtc->config.ips_enabled &&
  2881. ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
  2882. GAMMA_MODE_MODE_SPLIT)) {
  2883. hsw_disable_ips(intel_crtc);
  2884. reenable_ips = true;
  2885. }
  2886. for (i = 0; i < 256; i++) {
  2887. I915_WRITE(palreg + 4 * i,
  2888. (intel_crtc->lut_r[i] << 16) |
  2889. (intel_crtc->lut_g[i] << 8) |
  2890. intel_crtc->lut_b[i]);
  2891. }
  2892. if (reenable_ips)
  2893. hsw_enable_ips(intel_crtc);
  2894. }
  2895. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2896. {
  2897. struct drm_device *dev = crtc->dev;
  2898. struct drm_i915_private *dev_priv = dev->dev_private;
  2899. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2900. struct intel_encoder *encoder;
  2901. int pipe = intel_crtc->pipe;
  2902. int plane = intel_crtc->plane;
  2903. WARN_ON(!crtc->enabled);
  2904. if (intel_crtc->active)
  2905. return;
  2906. intel_crtc->active = true;
  2907. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  2908. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  2909. for_each_encoder_on_crtc(dev, crtc, encoder)
  2910. if (encoder->pre_enable)
  2911. encoder->pre_enable(encoder);
  2912. if (intel_crtc->config.has_pch_encoder) {
  2913. /* Note: FDI PLL enabling _must_ be done before we enable the
  2914. * cpu pipes, hence this is separate from all the other fdi/pch
  2915. * enabling. */
  2916. ironlake_fdi_pll_enable(intel_crtc);
  2917. } else {
  2918. assert_fdi_tx_disabled(dev_priv, pipe);
  2919. assert_fdi_rx_disabled(dev_priv, pipe);
  2920. }
  2921. ironlake_pfit_enable(intel_crtc);
  2922. /*
  2923. * On ILK+ LUT must be loaded before the pipe is running but with
  2924. * clocks enabled
  2925. */
  2926. intel_crtc_load_lut(crtc);
  2927. intel_update_watermarks(crtc);
  2928. intel_enable_pipe(dev_priv, pipe,
  2929. intel_crtc->config.has_pch_encoder, false);
  2930. intel_enable_plane(dev_priv, plane, pipe);
  2931. intel_enable_planes(crtc);
  2932. intel_crtc_update_cursor(crtc, true);
  2933. if (intel_crtc->config.has_pch_encoder)
  2934. ironlake_pch_enable(crtc);
  2935. mutex_lock(&dev->struct_mutex);
  2936. intel_update_fbc(dev);
  2937. mutex_unlock(&dev->struct_mutex);
  2938. for_each_encoder_on_crtc(dev, crtc, encoder)
  2939. encoder->enable(encoder);
  2940. if (HAS_PCH_CPT(dev))
  2941. cpt_verify_modeset(dev, intel_crtc->pipe);
  2942. /*
  2943. * There seems to be a race in PCH platform hw (at least on some
  2944. * outputs) where an enabled pipe still completes any pageflip right
  2945. * away (as if the pipe is off) instead of waiting for vblank. As soon
  2946. * as the first vblank happend, everything works as expected. Hence just
  2947. * wait for one vblank before returning to avoid strange things
  2948. * happening.
  2949. */
  2950. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2951. }
  2952. /* IPS only exists on ULT machines and is tied to pipe A. */
  2953. static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
  2954. {
  2955. return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
  2956. }
  2957. static void haswell_crtc_enable(struct drm_crtc *crtc)
  2958. {
  2959. struct drm_device *dev = crtc->dev;
  2960. struct drm_i915_private *dev_priv = dev->dev_private;
  2961. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2962. struct intel_encoder *encoder;
  2963. int pipe = intel_crtc->pipe;
  2964. int plane = intel_crtc->plane;
  2965. WARN_ON(!crtc->enabled);
  2966. if (intel_crtc->active)
  2967. return;
  2968. intel_crtc->active = true;
  2969. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  2970. if (intel_crtc->config.has_pch_encoder)
  2971. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  2972. if (intel_crtc->config.has_pch_encoder)
  2973. dev_priv->display.fdi_link_train(crtc);
  2974. for_each_encoder_on_crtc(dev, crtc, encoder)
  2975. if (encoder->pre_enable)
  2976. encoder->pre_enable(encoder);
  2977. intel_ddi_enable_pipe_clock(intel_crtc);
  2978. ironlake_pfit_enable(intel_crtc);
  2979. /*
  2980. * On ILK+ LUT must be loaded before the pipe is running but with
  2981. * clocks enabled
  2982. */
  2983. intel_crtc_load_lut(crtc);
  2984. intel_ddi_set_pipe_settings(crtc);
  2985. intel_ddi_enable_transcoder_func(crtc);
  2986. intel_update_watermarks(crtc);
  2987. intel_enable_pipe(dev_priv, pipe,
  2988. intel_crtc->config.has_pch_encoder, false);
  2989. intel_enable_plane(dev_priv, plane, pipe);
  2990. intel_enable_planes(crtc);
  2991. intel_crtc_update_cursor(crtc, true);
  2992. hsw_enable_ips(intel_crtc);
  2993. if (intel_crtc->config.has_pch_encoder)
  2994. lpt_pch_enable(crtc);
  2995. mutex_lock(&dev->struct_mutex);
  2996. intel_update_fbc(dev);
  2997. mutex_unlock(&dev->struct_mutex);
  2998. for_each_encoder_on_crtc(dev, crtc, encoder) {
  2999. encoder->enable(encoder);
  3000. intel_opregion_notify_encoder(encoder, true);
  3001. }
  3002. /*
  3003. * There seems to be a race in PCH platform hw (at least on some
  3004. * outputs) where an enabled pipe still completes any pageflip right
  3005. * away (as if the pipe is off) instead of waiting for vblank. As soon
  3006. * as the first vblank happend, everything works as expected. Hence just
  3007. * wait for one vblank before returning to avoid strange things
  3008. * happening.
  3009. */
  3010. intel_wait_for_vblank(dev, intel_crtc->pipe);
  3011. }
  3012. static void ironlake_pfit_disable(struct intel_crtc *crtc)
  3013. {
  3014. struct drm_device *dev = crtc->base.dev;
  3015. struct drm_i915_private *dev_priv = dev->dev_private;
  3016. int pipe = crtc->pipe;
  3017. /* To avoid upsetting the power well on haswell only disable the pfit if
  3018. * it's in use. The hw state code will make sure we get this right. */
  3019. if (crtc->config.pch_pfit.enabled) {
  3020. I915_WRITE(PF_CTL(pipe), 0);
  3021. I915_WRITE(PF_WIN_POS(pipe), 0);
  3022. I915_WRITE(PF_WIN_SZ(pipe), 0);
  3023. }
  3024. }
  3025. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  3026. {
  3027. struct drm_device *dev = crtc->dev;
  3028. struct drm_i915_private *dev_priv = dev->dev_private;
  3029. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3030. struct intel_encoder *encoder;
  3031. int pipe = intel_crtc->pipe;
  3032. int plane = intel_crtc->plane;
  3033. u32 reg, temp;
  3034. if (!intel_crtc->active)
  3035. return;
  3036. for_each_encoder_on_crtc(dev, crtc, encoder)
  3037. encoder->disable(encoder);
  3038. intel_crtc_wait_for_pending_flips(crtc);
  3039. drm_vblank_off(dev, pipe);
  3040. if (dev_priv->fbc.plane == plane)
  3041. intel_disable_fbc(dev);
  3042. intel_crtc_update_cursor(crtc, false);
  3043. intel_disable_planes(crtc);
  3044. intel_disable_plane(dev_priv, plane, pipe);
  3045. if (intel_crtc->config.has_pch_encoder)
  3046. intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
  3047. intel_disable_pipe(dev_priv, pipe);
  3048. ironlake_pfit_disable(intel_crtc);
  3049. for_each_encoder_on_crtc(dev, crtc, encoder)
  3050. if (encoder->post_disable)
  3051. encoder->post_disable(encoder);
  3052. if (intel_crtc->config.has_pch_encoder) {
  3053. ironlake_fdi_disable(crtc);
  3054. ironlake_disable_pch_transcoder(dev_priv, pipe);
  3055. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  3056. if (HAS_PCH_CPT(dev)) {
  3057. /* disable TRANS_DP_CTL */
  3058. reg = TRANS_DP_CTL(pipe);
  3059. temp = I915_READ(reg);
  3060. temp &= ~(TRANS_DP_OUTPUT_ENABLE |
  3061. TRANS_DP_PORT_SEL_MASK);
  3062. temp |= TRANS_DP_PORT_SEL_NONE;
  3063. I915_WRITE(reg, temp);
  3064. /* disable DPLL_SEL */
  3065. temp = I915_READ(PCH_DPLL_SEL);
  3066. temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
  3067. I915_WRITE(PCH_DPLL_SEL, temp);
  3068. }
  3069. /* disable PCH DPLL */
  3070. intel_disable_shared_dpll(intel_crtc);
  3071. ironlake_fdi_pll_disable(intel_crtc);
  3072. }
  3073. intel_crtc->active = false;
  3074. intel_update_watermarks(crtc);
  3075. mutex_lock(&dev->struct_mutex);
  3076. intel_update_fbc(dev);
  3077. mutex_unlock(&dev->struct_mutex);
  3078. }
  3079. static void haswell_crtc_disable(struct drm_crtc *crtc)
  3080. {
  3081. struct drm_device *dev = crtc->dev;
  3082. struct drm_i915_private *dev_priv = dev->dev_private;
  3083. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3084. struct intel_encoder *encoder;
  3085. int pipe = intel_crtc->pipe;
  3086. int plane = intel_crtc->plane;
  3087. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3088. if (!intel_crtc->active)
  3089. return;
  3090. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3091. intel_opregion_notify_encoder(encoder, false);
  3092. encoder->disable(encoder);
  3093. }
  3094. intel_crtc_wait_for_pending_flips(crtc);
  3095. drm_vblank_off(dev, pipe);
  3096. /* FBC must be disabled before disabling the plane on HSW. */
  3097. if (dev_priv->fbc.plane == plane)
  3098. intel_disable_fbc(dev);
  3099. hsw_disable_ips(intel_crtc);
  3100. intel_crtc_update_cursor(crtc, false);
  3101. intel_disable_planes(crtc);
  3102. intel_disable_plane(dev_priv, plane, pipe);
  3103. if (intel_crtc->config.has_pch_encoder)
  3104. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
  3105. intel_disable_pipe(dev_priv, pipe);
  3106. intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
  3107. ironlake_pfit_disable(intel_crtc);
  3108. intel_ddi_disable_pipe_clock(intel_crtc);
  3109. for_each_encoder_on_crtc(dev, crtc, encoder)
  3110. if (encoder->post_disable)
  3111. encoder->post_disable(encoder);
  3112. if (intel_crtc->config.has_pch_encoder) {
  3113. lpt_disable_pch_transcoder(dev_priv);
  3114. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  3115. intel_ddi_fdi_disable(crtc);
  3116. }
  3117. intel_crtc->active = false;
  3118. intel_update_watermarks(crtc);
  3119. mutex_lock(&dev->struct_mutex);
  3120. intel_update_fbc(dev);
  3121. mutex_unlock(&dev->struct_mutex);
  3122. }
  3123. static void ironlake_crtc_off(struct drm_crtc *crtc)
  3124. {
  3125. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3126. intel_put_shared_dpll(intel_crtc);
  3127. }
  3128. static void haswell_crtc_off(struct drm_crtc *crtc)
  3129. {
  3130. intel_ddi_put_crtc_pll(crtc);
  3131. }
  3132. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  3133. {
  3134. if (!enable && intel_crtc->overlay) {
  3135. struct drm_device *dev = intel_crtc->base.dev;
  3136. struct drm_i915_private *dev_priv = dev->dev_private;
  3137. mutex_lock(&dev->struct_mutex);
  3138. dev_priv->mm.interruptible = false;
  3139. (void) intel_overlay_switch_off(intel_crtc->overlay);
  3140. dev_priv->mm.interruptible = true;
  3141. mutex_unlock(&dev->struct_mutex);
  3142. }
  3143. /* Let userspace switch the overlay on again. In most cases userspace
  3144. * has to recompute where to put it anyway.
  3145. */
  3146. }
  3147. /**
  3148. * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
  3149. * cursor plane briefly if not already running after enabling the display
  3150. * plane.
  3151. * This workaround avoids occasional blank screens when self refresh is
  3152. * enabled.
  3153. */
  3154. static void
  3155. g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
  3156. {
  3157. u32 cntl = I915_READ(CURCNTR(pipe));
  3158. if ((cntl & CURSOR_MODE) == 0) {
  3159. u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
  3160. I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
  3161. I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
  3162. intel_wait_for_vblank(dev_priv->dev, pipe);
  3163. I915_WRITE(CURCNTR(pipe), cntl);
  3164. I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
  3165. I915_WRITE(FW_BLC_SELF, fw_bcl_self);
  3166. }
  3167. }
  3168. static void i9xx_pfit_enable(struct intel_crtc *crtc)
  3169. {
  3170. struct drm_device *dev = crtc->base.dev;
  3171. struct drm_i915_private *dev_priv = dev->dev_private;
  3172. struct intel_crtc_config *pipe_config = &crtc->config;
  3173. if (!crtc->config.gmch_pfit.control)
  3174. return;
  3175. /*
  3176. * The panel fitter should only be adjusted whilst the pipe is disabled,
  3177. * according to register description and PRM.
  3178. */
  3179. WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
  3180. assert_pipe_disabled(dev_priv, crtc->pipe);
  3181. I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
  3182. I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
  3183. /* Border color in case we don't scale up to the full screen. Black by
  3184. * default, change to something else for debugging. */
  3185. I915_WRITE(BCLRPAT(crtc->pipe), 0);
  3186. }
  3187. static void valleyview_crtc_enable(struct drm_crtc *crtc)
  3188. {
  3189. struct drm_device *dev = crtc->dev;
  3190. struct drm_i915_private *dev_priv = dev->dev_private;
  3191. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3192. struct intel_encoder *encoder;
  3193. int pipe = intel_crtc->pipe;
  3194. int plane = intel_crtc->plane;
  3195. bool is_dsi;
  3196. WARN_ON(!crtc->enabled);
  3197. if (intel_crtc->active)
  3198. return;
  3199. intel_crtc->active = true;
  3200. for_each_encoder_on_crtc(dev, crtc, encoder)
  3201. if (encoder->pre_pll_enable)
  3202. encoder->pre_pll_enable(encoder);
  3203. is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
  3204. if (!is_dsi)
  3205. vlv_enable_pll(intel_crtc);
  3206. for_each_encoder_on_crtc(dev, crtc, encoder)
  3207. if (encoder->pre_enable)
  3208. encoder->pre_enable(encoder);
  3209. i9xx_pfit_enable(intel_crtc);
  3210. intel_crtc_load_lut(crtc);
  3211. intel_update_watermarks(crtc);
  3212. intel_enable_pipe(dev_priv, pipe, false, is_dsi);
  3213. intel_enable_plane(dev_priv, plane, pipe);
  3214. intel_enable_planes(crtc);
  3215. intel_crtc_update_cursor(crtc, true);
  3216. intel_update_fbc(dev);
  3217. for_each_encoder_on_crtc(dev, crtc, encoder)
  3218. encoder->enable(encoder);
  3219. }
  3220. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  3221. {
  3222. struct drm_device *dev = crtc->dev;
  3223. struct drm_i915_private *dev_priv = dev->dev_private;
  3224. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3225. struct intel_encoder *encoder;
  3226. int pipe = intel_crtc->pipe;
  3227. int plane = intel_crtc->plane;
  3228. WARN_ON(!crtc->enabled);
  3229. if (intel_crtc->active)
  3230. return;
  3231. intel_crtc->active = true;
  3232. for_each_encoder_on_crtc(dev, crtc, encoder)
  3233. if (encoder->pre_enable)
  3234. encoder->pre_enable(encoder);
  3235. i9xx_enable_pll(intel_crtc);
  3236. i9xx_pfit_enable(intel_crtc);
  3237. intel_crtc_load_lut(crtc);
  3238. intel_update_watermarks(crtc);
  3239. intel_enable_pipe(dev_priv, pipe, false, false);
  3240. intel_enable_plane(dev_priv, plane, pipe);
  3241. intel_enable_planes(crtc);
  3242. /* The fixup needs to happen before cursor is enabled */
  3243. if (IS_G4X(dev))
  3244. g4x_fixup_plane(dev_priv, pipe);
  3245. intel_crtc_update_cursor(crtc, true);
  3246. /* Give the overlay scaler a chance to enable if it's on this pipe */
  3247. intel_crtc_dpms_overlay(intel_crtc, true);
  3248. intel_update_fbc(dev);
  3249. for_each_encoder_on_crtc(dev, crtc, encoder)
  3250. encoder->enable(encoder);
  3251. }
  3252. static void i9xx_pfit_disable(struct intel_crtc *crtc)
  3253. {
  3254. struct drm_device *dev = crtc->base.dev;
  3255. struct drm_i915_private *dev_priv = dev->dev_private;
  3256. if (!crtc->config.gmch_pfit.control)
  3257. return;
  3258. assert_pipe_disabled(dev_priv, crtc->pipe);
  3259. DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
  3260. I915_READ(PFIT_CONTROL));
  3261. I915_WRITE(PFIT_CONTROL, 0);
  3262. }
  3263. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  3264. {
  3265. struct drm_device *dev = crtc->dev;
  3266. struct drm_i915_private *dev_priv = dev->dev_private;
  3267. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3268. struct intel_encoder *encoder;
  3269. int pipe = intel_crtc->pipe;
  3270. int plane = intel_crtc->plane;
  3271. if (!intel_crtc->active)
  3272. return;
  3273. for_each_encoder_on_crtc(dev, crtc, encoder)
  3274. encoder->disable(encoder);
  3275. /* Give the overlay scaler a chance to disable if it's on this pipe */
  3276. intel_crtc_wait_for_pending_flips(crtc);
  3277. drm_vblank_off(dev, pipe);
  3278. if (dev_priv->fbc.plane == plane)
  3279. intel_disable_fbc(dev);
  3280. intel_crtc_dpms_overlay(intel_crtc, false);
  3281. intel_crtc_update_cursor(crtc, false);
  3282. intel_disable_planes(crtc);
  3283. intel_disable_plane(dev_priv, plane, pipe);
  3284. intel_disable_pipe(dev_priv, pipe);
  3285. i9xx_pfit_disable(intel_crtc);
  3286. for_each_encoder_on_crtc(dev, crtc, encoder)
  3287. if (encoder->post_disable)
  3288. encoder->post_disable(encoder);
  3289. if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
  3290. i9xx_disable_pll(dev_priv, pipe);
  3291. intel_crtc->active = false;
  3292. intel_update_watermarks(crtc);
  3293. intel_update_fbc(dev);
  3294. }
  3295. static void i9xx_crtc_off(struct drm_crtc *crtc)
  3296. {
  3297. }
  3298. static void intel_crtc_update_sarea(struct drm_crtc *crtc,
  3299. bool enabled)
  3300. {
  3301. struct drm_device *dev = crtc->dev;
  3302. struct drm_i915_master_private *master_priv;
  3303. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3304. int pipe = intel_crtc->pipe;
  3305. if (!dev->primary->master)
  3306. return;
  3307. master_priv = dev->primary->master->driver_priv;
  3308. if (!master_priv->sarea_priv)
  3309. return;
  3310. switch (pipe) {
  3311. case 0:
  3312. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  3313. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  3314. break;
  3315. case 1:
  3316. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  3317. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  3318. break;
  3319. default:
  3320. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  3321. break;
  3322. }
  3323. }
  3324. /**
  3325. * Sets the power management mode of the pipe and plane.
  3326. */
  3327. void intel_crtc_update_dpms(struct drm_crtc *crtc)
  3328. {
  3329. struct drm_device *dev = crtc->dev;
  3330. struct drm_i915_private *dev_priv = dev->dev_private;
  3331. struct intel_encoder *intel_encoder;
  3332. bool enable = false;
  3333. for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  3334. enable |= intel_encoder->connectors_active;
  3335. if (enable)
  3336. dev_priv->display.crtc_enable(crtc);
  3337. else
  3338. dev_priv->display.crtc_disable(crtc);
  3339. intel_crtc_update_sarea(crtc, enable);
  3340. }
  3341. static void intel_crtc_disable(struct drm_crtc *crtc)
  3342. {
  3343. struct drm_device *dev = crtc->dev;
  3344. struct drm_connector *connector;
  3345. struct drm_i915_private *dev_priv = dev->dev_private;
  3346. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3347. /* crtc should still be enabled when we disable it. */
  3348. WARN_ON(!crtc->enabled);
  3349. dev_priv->display.crtc_disable(crtc);
  3350. intel_crtc->eld_vld = false;
  3351. intel_crtc_update_sarea(crtc, false);
  3352. dev_priv->display.off(crtc);
  3353. assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  3354. assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
  3355. assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  3356. if (crtc->fb) {
  3357. mutex_lock(&dev->struct_mutex);
  3358. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  3359. mutex_unlock(&dev->struct_mutex);
  3360. crtc->fb = NULL;
  3361. }
  3362. /* Update computed state. */
  3363. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3364. if (!connector->encoder || !connector->encoder->crtc)
  3365. continue;
  3366. if (connector->encoder->crtc != crtc)
  3367. continue;
  3368. connector->dpms = DRM_MODE_DPMS_OFF;
  3369. to_intel_encoder(connector->encoder)->connectors_active = false;
  3370. }
  3371. }
  3372. void intel_encoder_destroy(struct drm_encoder *encoder)
  3373. {
  3374. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3375. drm_encoder_cleanup(encoder);
  3376. kfree(intel_encoder);
  3377. }
  3378. /* Simple dpms helper for encoders with just one connector, no cloning and only
  3379. * one kind of off state. It clamps all !ON modes to fully OFF and changes the
  3380. * state of the entire output pipe. */
  3381. static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
  3382. {
  3383. if (mode == DRM_MODE_DPMS_ON) {
  3384. encoder->connectors_active = true;
  3385. intel_crtc_update_dpms(encoder->base.crtc);
  3386. } else {
  3387. encoder->connectors_active = false;
  3388. intel_crtc_update_dpms(encoder->base.crtc);
  3389. }
  3390. }
  3391. /* Cross check the actual hw state with our own modeset state tracking (and it's
  3392. * internal consistency). */
  3393. static void intel_connector_check_state(struct intel_connector *connector)
  3394. {
  3395. if (connector->get_hw_state(connector)) {
  3396. struct intel_encoder *encoder = connector->encoder;
  3397. struct drm_crtc *crtc;
  3398. bool encoder_enabled;
  3399. enum pipe pipe;
  3400. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  3401. connector->base.base.id,
  3402. drm_get_connector_name(&connector->base));
  3403. WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
  3404. "wrong connector dpms state\n");
  3405. WARN(connector->base.encoder != &encoder->base,
  3406. "active connector not linked to encoder\n");
  3407. WARN(!encoder->connectors_active,
  3408. "encoder->connectors_active not set\n");
  3409. encoder_enabled = encoder->get_hw_state(encoder, &pipe);
  3410. WARN(!encoder_enabled, "encoder not enabled\n");
  3411. if (WARN_ON(!encoder->base.crtc))
  3412. return;
  3413. crtc = encoder->base.crtc;
  3414. WARN(!crtc->enabled, "crtc not enabled\n");
  3415. WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
  3416. WARN(pipe != to_intel_crtc(crtc)->pipe,
  3417. "encoder active on the wrong pipe\n");
  3418. }
  3419. }
  3420. /* Even simpler default implementation, if there's really no special case to
  3421. * consider. */
  3422. void intel_connector_dpms(struct drm_connector *connector, int mode)
  3423. {
  3424. struct intel_encoder *encoder = intel_attached_encoder(connector);
  3425. /* All the simple cases only support two dpms states. */
  3426. if (mode != DRM_MODE_DPMS_ON)
  3427. mode = DRM_MODE_DPMS_OFF;
  3428. if (mode == connector->dpms)
  3429. return;
  3430. connector->dpms = mode;
  3431. /* Only need to change hw state when actually enabled */
  3432. if (encoder->base.crtc)
  3433. intel_encoder_dpms(encoder, mode);
  3434. else
  3435. WARN_ON(encoder->connectors_active != false);
  3436. intel_modeset_check_state(connector->dev);
  3437. }
  3438. /* Simple connector->get_hw_state implementation for encoders that support only
  3439. * one connector and no cloning and hence the encoder state determines the state
  3440. * of the connector. */
  3441. bool intel_connector_get_hw_state(struct intel_connector *connector)
  3442. {
  3443. enum pipe pipe = 0;
  3444. struct intel_encoder *encoder = connector->encoder;
  3445. return encoder->get_hw_state(encoder, &pipe);
  3446. }
  3447. static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
  3448. struct intel_crtc_config *pipe_config)
  3449. {
  3450. struct drm_i915_private *dev_priv = dev->dev_private;
  3451. struct intel_crtc *pipe_B_crtc =
  3452. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  3453. DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
  3454. pipe_name(pipe), pipe_config->fdi_lanes);
  3455. if (pipe_config->fdi_lanes > 4) {
  3456. DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
  3457. pipe_name(pipe), pipe_config->fdi_lanes);
  3458. return false;
  3459. }
  3460. if (IS_HASWELL(dev)) {
  3461. if (pipe_config->fdi_lanes > 2) {
  3462. DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
  3463. pipe_config->fdi_lanes);
  3464. return false;
  3465. } else {
  3466. return true;
  3467. }
  3468. }
  3469. if (INTEL_INFO(dev)->num_pipes == 2)
  3470. return true;
  3471. /* Ivybridge 3 pipe is really complicated */
  3472. switch (pipe) {
  3473. case PIPE_A:
  3474. return true;
  3475. case PIPE_B:
  3476. if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
  3477. pipe_config->fdi_lanes > 2) {
  3478. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  3479. pipe_name(pipe), pipe_config->fdi_lanes);
  3480. return false;
  3481. }
  3482. return true;
  3483. case PIPE_C:
  3484. if (!pipe_has_enabled_pch(pipe_B_crtc) ||
  3485. pipe_B_crtc->config.fdi_lanes <= 2) {
  3486. if (pipe_config->fdi_lanes > 2) {
  3487. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  3488. pipe_name(pipe), pipe_config->fdi_lanes);
  3489. return false;
  3490. }
  3491. } else {
  3492. DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
  3493. return false;
  3494. }
  3495. return true;
  3496. default:
  3497. BUG();
  3498. }
  3499. }
  3500. #define RETRY 1
  3501. static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
  3502. struct intel_crtc_config *pipe_config)
  3503. {
  3504. struct drm_device *dev = intel_crtc->base.dev;
  3505. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  3506. int lane, link_bw, fdi_dotclock;
  3507. bool setup_ok, needs_recompute = false;
  3508. retry:
  3509. /* FDI is a binary signal running at ~2.7GHz, encoding
  3510. * each output octet as 10 bits. The actual frequency
  3511. * is stored as a divider into a 100MHz clock, and the
  3512. * mode pixel clock is stored in units of 1KHz.
  3513. * Hence the bw of each lane in terms of the mode signal
  3514. * is:
  3515. */
  3516. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  3517. fdi_dotclock = adjusted_mode->clock;
  3518. lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
  3519. pipe_config->pipe_bpp);
  3520. pipe_config->fdi_lanes = lane;
  3521. intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
  3522. link_bw, &pipe_config->fdi_m_n);
  3523. setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
  3524. intel_crtc->pipe, pipe_config);
  3525. if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
  3526. pipe_config->pipe_bpp -= 2*3;
  3527. DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
  3528. pipe_config->pipe_bpp);
  3529. needs_recompute = true;
  3530. pipe_config->bw_constrained = true;
  3531. goto retry;
  3532. }
  3533. if (needs_recompute)
  3534. return RETRY;
  3535. return setup_ok ? 0 : -EINVAL;
  3536. }
  3537. static void hsw_compute_ips_config(struct intel_crtc *crtc,
  3538. struct intel_crtc_config *pipe_config)
  3539. {
  3540. pipe_config->ips_enabled = i915_enable_ips &&
  3541. hsw_crtc_supports_ips(crtc) &&
  3542. pipe_config->pipe_bpp <= 24;
  3543. }
  3544. static int intel_crtc_compute_config(struct intel_crtc *crtc,
  3545. struct intel_crtc_config *pipe_config)
  3546. {
  3547. struct drm_device *dev = crtc->base.dev;
  3548. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  3549. /* FIXME should check pixel clock limits on all platforms */
  3550. if (INTEL_INFO(dev)->gen < 4) {
  3551. struct drm_i915_private *dev_priv = dev->dev_private;
  3552. int clock_limit =
  3553. dev_priv->display.get_display_clock_speed(dev);
  3554. /*
  3555. * Enable pixel doubling when the dot clock
  3556. * is > 90% of the (display) core speed.
  3557. *
  3558. * GDG double wide on either pipe,
  3559. * otherwise pipe A only.
  3560. */
  3561. if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
  3562. adjusted_mode->clock > clock_limit * 9 / 10) {
  3563. clock_limit *= 2;
  3564. pipe_config->double_wide = true;
  3565. }
  3566. if (adjusted_mode->clock > clock_limit * 9 / 10)
  3567. return -EINVAL;
  3568. }
  3569. /*
  3570. * Pipe horizontal size must be even in:
  3571. * - DVO ganged mode
  3572. * - LVDS dual channel mode
  3573. * - Double wide pipe
  3574. */
  3575. if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3576. intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
  3577. pipe_config->pipe_src_w &= ~1;
  3578. /* Cantiga+ cannot handle modes with a hsync front porch of 0.
  3579. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
  3580. */
  3581. if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  3582. adjusted_mode->hsync_start == adjusted_mode->hdisplay)
  3583. return -EINVAL;
  3584. if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
  3585. pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
  3586. } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
  3587. /* only a 8bpc pipe, with 6bpc dither through the panel fitter
  3588. * for lvds. */
  3589. pipe_config->pipe_bpp = 8*3;
  3590. }
  3591. if (HAS_IPS(dev))
  3592. hsw_compute_ips_config(crtc, pipe_config);
  3593. /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
  3594. * clock survives for now. */
  3595. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  3596. pipe_config->shared_dpll = crtc->config.shared_dpll;
  3597. if (pipe_config->has_pch_encoder)
  3598. return ironlake_fdi_compute_config(crtc, pipe_config);
  3599. return 0;
  3600. }
  3601. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  3602. {
  3603. return 400000; /* FIXME */
  3604. }
  3605. static int i945_get_display_clock_speed(struct drm_device *dev)
  3606. {
  3607. return 400000;
  3608. }
  3609. static int i915_get_display_clock_speed(struct drm_device *dev)
  3610. {
  3611. return 333000;
  3612. }
  3613. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  3614. {
  3615. return 200000;
  3616. }
  3617. static int pnv_get_display_clock_speed(struct drm_device *dev)
  3618. {
  3619. u16 gcfgc = 0;
  3620. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3621. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3622. case GC_DISPLAY_CLOCK_267_MHZ_PNV:
  3623. return 267000;
  3624. case GC_DISPLAY_CLOCK_333_MHZ_PNV:
  3625. return 333000;
  3626. case GC_DISPLAY_CLOCK_444_MHZ_PNV:
  3627. return 444000;
  3628. case GC_DISPLAY_CLOCK_200_MHZ_PNV:
  3629. return 200000;
  3630. default:
  3631. DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
  3632. case GC_DISPLAY_CLOCK_133_MHZ_PNV:
  3633. return 133000;
  3634. case GC_DISPLAY_CLOCK_167_MHZ_PNV:
  3635. return 167000;
  3636. }
  3637. }
  3638. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  3639. {
  3640. u16 gcfgc = 0;
  3641. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3642. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  3643. return 133000;
  3644. else {
  3645. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3646. case GC_DISPLAY_CLOCK_333_MHZ:
  3647. return 333000;
  3648. default:
  3649. case GC_DISPLAY_CLOCK_190_200_MHZ:
  3650. return 190000;
  3651. }
  3652. }
  3653. }
  3654. static int i865_get_display_clock_speed(struct drm_device *dev)
  3655. {
  3656. return 266000;
  3657. }
  3658. static int i855_get_display_clock_speed(struct drm_device *dev)
  3659. {
  3660. u16 hpllcc = 0;
  3661. /* Assume that the hardware is in the high speed state. This
  3662. * should be the default.
  3663. */
  3664. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  3665. case GC_CLOCK_133_200:
  3666. case GC_CLOCK_100_200:
  3667. return 200000;
  3668. case GC_CLOCK_166_250:
  3669. return 250000;
  3670. case GC_CLOCK_100_133:
  3671. return 133000;
  3672. }
  3673. /* Shouldn't happen */
  3674. return 0;
  3675. }
  3676. static int i830_get_display_clock_speed(struct drm_device *dev)
  3677. {
  3678. return 133000;
  3679. }
  3680. static void
  3681. intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
  3682. {
  3683. while (*num > DATA_LINK_M_N_MASK ||
  3684. *den > DATA_LINK_M_N_MASK) {
  3685. *num >>= 1;
  3686. *den >>= 1;
  3687. }
  3688. }
  3689. static void compute_m_n(unsigned int m, unsigned int n,
  3690. uint32_t *ret_m, uint32_t *ret_n)
  3691. {
  3692. *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
  3693. *ret_m = div_u64((uint64_t) m * *ret_n, n);
  3694. intel_reduce_m_n_ratio(ret_m, ret_n);
  3695. }
  3696. void
  3697. intel_link_compute_m_n(int bits_per_pixel, int nlanes,
  3698. int pixel_clock, int link_clock,
  3699. struct intel_link_m_n *m_n)
  3700. {
  3701. m_n->tu = 64;
  3702. compute_m_n(bits_per_pixel * pixel_clock,
  3703. link_clock * nlanes * 8,
  3704. &m_n->gmch_m, &m_n->gmch_n);
  3705. compute_m_n(pixel_clock, link_clock,
  3706. &m_n->link_m, &m_n->link_n);
  3707. }
  3708. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3709. {
  3710. if (i915_panel_use_ssc >= 0)
  3711. return i915_panel_use_ssc != 0;
  3712. return dev_priv->vbt.lvds_use_ssc
  3713. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3714. }
  3715. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  3716. {
  3717. struct drm_device *dev = crtc->dev;
  3718. struct drm_i915_private *dev_priv = dev->dev_private;
  3719. int refclk;
  3720. if (IS_VALLEYVIEW(dev)) {
  3721. refclk = 100000;
  3722. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3723. intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3724. refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
  3725. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3726. refclk / 1000);
  3727. } else if (!IS_GEN2(dev)) {
  3728. refclk = 96000;
  3729. } else {
  3730. refclk = 48000;
  3731. }
  3732. return refclk;
  3733. }
  3734. static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
  3735. {
  3736. return (1 << dpll->n) << 16 | dpll->m2;
  3737. }
  3738. static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
  3739. {
  3740. return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
  3741. }
  3742. static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
  3743. intel_clock_t *reduced_clock)
  3744. {
  3745. struct drm_device *dev = crtc->base.dev;
  3746. struct drm_i915_private *dev_priv = dev->dev_private;
  3747. int pipe = crtc->pipe;
  3748. u32 fp, fp2 = 0;
  3749. if (IS_PINEVIEW(dev)) {
  3750. fp = pnv_dpll_compute_fp(&crtc->config.dpll);
  3751. if (reduced_clock)
  3752. fp2 = pnv_dpll_compute_fp(reduced_clock);
  3753. } else {
  3754. fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
  3755. if (reduced_clock)
  3756. fp2 = i9xx_dpll_compute_fp(reduced_clock);
  3757. }
  3758. I915_WRITE(FP0(pipe), fp);
  3759. crtc->config.dpll_hw_state.fp0 = fp;
  3760. crtc->lowfreq_avail = false;
  3761. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3762. reduced_clock && i915_powersave) {
  3763. I915_WRITE(FP1(pipe), fp2);
  3764. crtc->config.dpll_hw_state.fp1 = fp2;
  3765. crtc->lowfreq_avail = true;
  3766. } else {
  3767. I915_WRITE(FP1(pipe), fp);
  3768. crtc->config.dpll_hw_state.fp1 = fp;
  3769. }
  3770. }
  3771. static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
  3772. pipe)
  3773. {
  3774. u32 reg_val;
  3775. /*
  3776. * PLLB opamp always calibrates to max value of 0x3f, force enable it
  3777. * and set it to a reasonable value instead.
  3778. */
  3779. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
  3780. reg_val &= 0xffffff00;
  3781. reg_val |= 0x00000030;
  3782. vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
  3783. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
  3784. reg_val &= 0x8cffffff;
  3785. reg_val = 0x8c000000;
  3786. vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
  3787. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
  3788. reg_val &= 0xffffff00;
  3789. vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
  3790. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
  3791. reg_val &= 0x00ffffff;
  3792. reg_val |= 0xb0000000;
  3793. vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
  3794. }
  3795. static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  3796. struct intel_link_m_n *m_n)
  3797. {
  3798. struct drm_device *dev = crtc->base.dev;
  3799. struct drm_i915_private *dev_priv = dev->dev_private;
  3800. int pipe = crtc->pipe;
  3801. I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3802. I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
  3803. I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
  3804. I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
  3805. }
  3806. static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  3807. struct intel_link_m_n *m_n)
  3808. {
  3809. struct drm_device *dev = crtc->base.dev;
  3810. struct drm_i915_private *dev_priv = dev->dev_private;
  3811. int pipe = crtc->pipe;
  3812. enum transcoder transcoder = crtc->config.cpu_transcoder;
  3813. if (INTEL_INFO(dev)->gen >= 5) {
  3814. I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3815. I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
  3816. I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
  3817. I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
  3818. } else {
  3819. I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3820. I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
  3821. I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
  3822. I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
  3823. }
  3824. }
  3825. static void intel_dp_set_m_n(struct intel_crtc *crtc)
  3826. {
  3827. if (crtc->config.has_pch_encoder)
  3828. intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3829. else
  3830. intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3831. }
  3832. static void vlv_update_pll(struct intel_crtc *crtc)
  3833. {
  3834. struct drm_device *dev = crtc->base.dev;
  3835. struct drm_i915_private *dev_priv = dev->dev_private;
  3836. int pipe = crtc->pipe;
  3837. u32 dpll, mdiv;
  3838. u32 bestn, bestm1, bestm2, bestp1, bestp2;
  3839. u32 coreclk, reg_val, dpll_md;
  3840. mutex_lock(&dev_priv->dpio_lock);
  3841. bestn = crtc->config.dpll.n;
  3842. bestm1 = crtc->config.dpll.m1;
  3843. bestm2 = crtc->config.dpll.m2;
  3844. bestp1 = crtc->config.dpll.p1;
  3845. bestp2 = crtc->config.dpll.p2;
  3846. /* See eDP HDMI DPIO driver vbios notes doc */
  3847. /* PLL B needs special handling */
  3848. if (pipe)
  3849. vlv_pllb_recal_opamp(dev_priv, pipe);
  3850. /* Set up Tx target for periodic Rcomp update */
  3851. vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
  3852. /* Disable target IRef on PLL */
  3853. reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
  3854. reg_val &= 0x00ffffff;
  3855. vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
  3856. /* Disable fast lock */
  3857. vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
  3858. /* Set idtafcrecal before PLL is enabled */
  3859. mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  3860. mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  3861. mdiv |= ((bestn << DPIO_N_SHIFT));
  3862. mdiv |= (1 << DPIO_K_SHIFT);
  3863. /*
  3864. * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
  3865. * but we don't support that).
  3866. * Note: don't use the DAC post divider as it seems unstable.
  3867. */
  3868. mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
  3869. vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
  3870. mdiv |= DPIO_ENABLE_CALIBRATION;
  3871. vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
  3872. /* Set HBR and RBR LPF coefficients */
  3873. if (crtc->config.port_clock == 162000 ||
  3874. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
  3875. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
  3876. vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
  3877. 0x009f0003);
  3878. else
  3879. vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
  3880. 0x00d0000f);
  3881. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
  3882. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
  3883. /* Use SSC source */
  3884. if (!pipe)
  3885. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3886. 0x0df40000);
  3887. else
  3888. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3889. 0x0df70000);
  3890. } else { /* HDMI or VGA */
  3891. /* Use bend source */
  3892. if (!pipe)
  3893. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3894. 0x0df70000);
  3895. else
  3896. vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
  3897. 0x0df40000);
  3898. }
  3899. coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
  3900. coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
  3901. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
  3902. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
  3903. coreclk |= 0x01000000;
  3904. vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
  3905. vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
  3906. /* Enable DPIO clock input */
  3907. dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
  3908. DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
  3909. if (pipe)
  3910. dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  3911. dpll |= DPLL_VCO_ENABLE;
  3912. crtc->config.dpll_hw_state.dpll = dpll;
  3913. dpll_md = (crtc->config.pixel_multiplier - 1)
  3914. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3915. crtc->config.dpll_hw_state.dpll_md = dpll_md;
  3916. if (crtc->config.has_dp_encoder)
  3917. intel_dp_set_m_n(crtc);
  3918. mutex_unlock(&dev_priv->dpio_lock);
  3919. }
  3920. static void i9xx_update_pll(struct intel_crtc *crtc,
  3921. intel_clock_t *reduced_clock,
  3922. int num_connectors)
  3923. {
  3924. struct drm_device *dev = crtc->base.dev;
  3925. struct drm_i915_private *dev_priv = dev->dev_private;
  3926. u32 dpll;
  3927. bool is_sdvo;
  3928. struct dpll *clock = &crtc->config.dpll;
  3929. i9xx_update_pll_dividers(crtc, reduced_clock);
  3930. is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
  3931. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
  3932. dpll = DPLL_VGA_MODE_DIS;
  3933. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
  3934. dpll |= DPLLB_MODE_LVDS;
  3935. else
  3936. dpll |= DPLLB_MODE_DAC_SERIAL;
  3937. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  3938. dpll |= (crtc->config.pixel_multiplier - 1)
  3939. << SDVO_MULTIPLIER_SHIFT_HIRES;
  3940. }
  3941. if (is_sdvo)
  3942. dpll |= DPLL_SDVO_HIGH_SPEED;
  3943. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
  3944. dpll |= DPLL_SDVO_HIGH_SPEED;
  3945. /* compute bitmask from p1 value */
  3946. if (IS_PINEVIEW(dev))
  3947. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3948. else {
  3949. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3950. if (IS_G4X(dev) && reduced_clock)
  3951. dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3952. }
  3953. switch (clock->p2) {
  3954. case 5:
  3955. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3956. break;
  3957. case 7:
  3958. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3959. break;
  3960. case 10:
  3961. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3962. break;
  3963. case 14:
  3964. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3965. break;
  3966. }
  3967. if (INTEL_INFO(dev)->gen >= 4)
  3968. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3969. if (crtc->config.sdvo_tv_clock)
  3970. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3971. else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3972. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3973. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3974. else
  3975. dpll |= PLL_REF_INPUT_DREFCLK;
  3976. dpll |= DPLL_VCO_ENABLE;
  3977. crtc->config.dpll_hw_state.dpll = dpll;
  3978. if (INTEL_INFO(dev)->gen >= 4) {
  3979. u32 dpll_md = (crtc->config.pixel_multiplier - 1)
  3980. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3981. crtc->config.dpll_hw_state.dpll_md = dpll_md;
  3982. }
  3983. if (crtc->config.has_dp_encoder)
  3984. intel_dp_set_m_n(crtc);
  3985. }
  3986. static void i8xx_update_pll(struct intel_crtc *crtc,
  3987. intel_clock_t *reduced_clock,
  3988. int num_connectors)
  3989. {
  3990. struct drm_device *dev = crtc->base.dev;
  3991. struct drm_i915_private *dev_priv = dev->dev_private;
  3992. u32 dpll;
  3993. struct dpll *clock = &crtc->config.dpll;
  3994. i9xx_update_pll_dividers(crtc, reduced_clock);
  3995. dpll = DPLL_VGA_MODE_DIS;
  3996. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
  3997. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3998. } else {
  3999. if (clock->p1 == 2)
  4000. dpll |= PLL_P1_DIVIDE_BY_TWO;
  4001. else
  4002. dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4003. if (clock->p2 == 4)
  4004. dpll |= PLL_P2_DIVIDE_BY_4;
  4005. }
  4006. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
  4007. dpll |= DPLL_DVO_2X_MODE;
  4008. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  4009. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4010. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4011. else
  4012. dpll |= PLL_REF_INPUT_DREFCLK;
  4013. dpll |= DPLL_VCO_ENABLE;
  4014. crtc->config.dpll_hw_state.dpll = dpll;
  4015. }
  4016. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
  4017. {
  4018. struct drm_device *dev = intel_crtc->base.dev;
  4019. struct drm_i915_private *dev_priv = dev->dev_private;
  4020. enum pipe pipe = intel_crtc->pipe;
  4021. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  4022. struct drm_display_mode *adjusted_mode =
  4023. &intel_crtc->config.adjusted_mode;
  4024. uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
  4025. /* We need to be careful not to changed the adjusted mode, for otherwise
  4026. * the hw state checker will get angry at the mismatch. */
  4027. crtc_vtotal = adjusted_mode->crtc_vtotal;
  4028. crtc_vblank_end = adjusted_mode->crtc_vblank_end;
  4029. if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4030. /* the chip adds 2 halflines automatically */
  4031. crtc_vtotal -= 1;
  4032. crtc_vblank_end -= 1;
  4033. vsyncshift = adjusted_mode->crtc_hsync_start
  4034. - adjusted_mode->crtc_htotal / 2;
  4035. } else {
  4036. vsyncshift = 0;
  4037. }
  4038. if (INTEL_INFO(dev)->gen > 3)
  4039. I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
  4040. I915_WRITE(HTOTAL(cpu_transcoder),
  4041. (adjusted_mode->crtc_hdisplay - 1) |
  4042. ((adjusted_mode->crtc_htotal - 1) << 16));
  4043. I915_WRITE(HBLANK(cpu_transcoder),
  4044. (adjusted_mode->crtc_hblank_start - 1) |
  4045. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4046. I915_WRITE(HSYNC(cpu_transcoder),
  4047. (adjusted_mode->crtc_hsync_start - 1) |
  4048. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4049. I915_WRITE(VTOTAL(cpu_transcoder),
  4050. (adjusted_mode->crtc_vdisplay - 1) |
  4051. ((crtc_vtotal - 1) << 16));
  4052. I915_WRITE(VBLANK(cpu_transcoder),
  4053. (adjusted_mode->crtc_vblank_start - 1) |
  4054. ((crtc_vblank_end - 1) << 16));
  4055. I915_WRITE(VSYNC(cpu_transcoder),
  4056. (adjusted_mode->crtc_vsync_start - 1) |
  4057. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4058. /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
  4059. * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
  4060. * documented on the DDI_FUNC_CTL register description, EDP Input Select
  4061. * bits. */
  4062. if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
  4063. (pipe == PIPE_B || pipe == PIPE_C))
  4064. I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  4065. /* pipesrc controls the size that is scaled from, which should
  4066. * always be the user's requested size.
  4067. */
  4068. I915_WRITE(PIPESRC(pipe),
  4069. ((intel_crtc->config.pipe_src_w - 1) << 16) |
  4070. (intel_crtc->config.pipe_src_h - 1));
  4071. }
  4072. static void intel_get_pipe_timings(struct intel_crtc *crtc,
  4073. struct intel_crtc_config *pipe_config)
  4074. {
  4075. struct drm_device *dev = crtc->base.dev;
  4076. struct drm_i915_private *dev_priv = dev->dev_private;
  4077. enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
  4078. uint32_t tmp;
  4079. tmp = I915_READ(HTOTAL(cpu_transcoder));
  4080. pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
  4081. pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
  4082. tmp = I915_READ(HBLANK(cpu_transcoder));
  4083. pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
  4084. pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
  4085. tmp = I915_READ(HSYNC(cpu_transcoder));
  4086. pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
  4087. pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
  4088. tmp = I915_READ(VTOTAL(cpu_transcoder));
  4089. pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
  4090. pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
  4091. tmp = I915_READ(VBLANK(cpu_transcoder));
  4092. pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
  4093. pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
  4094. tmp = I915_READ(VSYNC(cpu_transcoder));
  4095. pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
  4096. pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
  4097. if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
  4098. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
  4099. pipe_config->adjusted_mode.crtc_vtotal += 1;
  4100. pipe_config->adjusted_mode.crtc_vblank_end += 1;
  4101. }
  4102. tmp = I915_READ(PIPESRC(crtc->pipe));
  4103. pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
  4104. pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
  4105. pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
  4106. pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
  4107. }
  4108. static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
  4109. struct intel_crtc_config *pipe_config)
  4110. {
  4111. struct drm_crtc *crtc = &intel_crtc->base;
  4112. crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
  4113. crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
  4114. crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
  4115. crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
  4116. crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
  4117. crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
  4118. crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
  4119. crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
  4120. crtc->mode.flags = pipe_config->adjusted_mode.flags;
  4121. crtc->mode.clock = pipe_config->adjusted_mode.clock;
  4122. crtc->mode.flags |= pipe_config->adjusted_mode.flags;
  4123. }
  4124. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
  4125. {
  4126. struct drm_device *dev = intel_crtc->base.dev;
  4127. struct drm_i915_private *dev_priv = dev->dev_private;
  4128. uint32_t pipeconf;
  4129. pipeconf = 0;
  4130. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  4131. I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
  4132. pipeconf |= PIPECONF_ENABLE;
  4133. if (intel_crtc->config.double_wide)
  4134. pipeconf |= PIPECONF_DOUBLE_WIDE;
  4135. /* only g4x and later have fancy bpc/dither controls */
  4136. if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  4137. /* Bspec claims that we can't use dithering for 30bpp pipes. */
  4138. if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
  4139. pipeconf |= PIPECONF_DITHER_EN |
  4140. PIPECONF_DITHER_TYPE_SP;
  4141. switch (intel_crtc->config.pipe_bpp) {
  4142. case 18:
  4143. pipeconf |= PIPECONF_6BPC;
  4144. break;
  4145. case 24:
  4146. pipeconf |= PIPECONF_8BPC;
  4147. break;
  4148. case 30:
  4149. pipeconf |= PIPECONF_10BPC;
  4150. break;
  4151. default:
  4152. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4153. BUG();
  4154. }
  4155. }
  4156. if (HAS_PIPE_CXSR(dev)) {
  4157. if (intel_crtc->lowfreq_avail) {
  4158. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4159. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4160. } else {
  4161. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4162. }
  4163. }
  4164. if (!IS_GEN2(dev) &&
  4165. intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4166. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4167. else
  4168. pipeconf |= PIPECONF_PROGRESSIVE;
  4169. if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
  4170. pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
  4171. I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
  4172. POSTING_READ(PIPECONF(intel_crtc->pipe));
  4173. }
  4174. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  4175. int x, int y,
  4176. struct drm_framebuffer *fb)
  4177. {
  4178. struct drm_device *dev = crtc->dev;
  4179. struct drm_i915_private *dev_priv = dev->dev_private;
  4180. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4181. int pipe = intel_crtc->pipe;
  4182. int plane = intel_crtc->plane;
  4183. int refclk, num_connectors = 0;
  4184. intel_clock_t clock, reduced_clock;
  4185. u32 dspcntr;
  4186. bool ok, has_reduced_clock = false;
  4187. bool is_lvds = false, is_dsi = false;
  4188. struct intel_encoder *encoder;
  4189. const intel_limit_t *limit;
  4190. int ret;
  4191. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4192. switch (encoder->type) {
  4193. case INTEL_OUTPUT_LVDS:
  4194. is_lvds = true;
  4195. break;
  4196. case INTEL_OUTPUT_DSI:
  4197. is_dsi = true;
  4198. break;
  4199. }
  4200. num_connectors++;
  4201. }
  4202. if (is_dsi)
  4203. goto skip_dpll;
  4204. if (!intel_crtc->config.clock_set) {
  4205. refclk = i9xx_get_refclk(crtc, num_connectors);
  4206. /*
  4207. * Returns a set of divisors for the desired target clock with
  4208. * the given refclk, or FALSE. The returned values represent
  4209. * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
  4210. * 2) / p1 / p2.
  4211. */
  4212. limit = intel_limit(crtc, refclk);
  4213. ok = dev_priv->display.find_dpll(limit, crtc,
  4214. intel_crtc->config.port_clock,
  4215. refclk, NULL, &clock);
  4216. if (!ok) {
  4217. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4218. return -EINVAL;
  4219. }
  4220. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4221. /*
  4222. * Ensure we match the reduced clock's P to the target
  4223. * clock. If the clocks don't match, we can't switch
  4224. * the display clock by using the FP0/FP1. In such case
  4225. * we will disable the LVDS downclock feature.
  4226. */
  4227. has_reduced_clock =
  4228. dev_priv->display.find_dpll(limit, crtc,
  4229. dev_priv->lvds_downclock,
  4230. refclk, &clock,
  4231. &reduced_clock);
  4232. }
  4233. /* Compat-code for transition, will disappear. */
  4234. intel_crtc->config.dpll.n = clock.n;
  4235. intel_crtc->config.dpll.m1 = clock.m1;
  4236. intel_crtc->config.dpll.m2 = clock.m2;
  4237. intel_crtc->config.dpll.p1 = clock.p1;
  4238. intel_crtc->config.dpll.p2 = clock.p2;
  4239. }
  4240. if (IS_GEN2(dev)) {
  4241. i8xx_update_pll(intel_crtc,
  4242. has_reduced_clock ? &reduced_clock : NULL,
  4243. num_connectors);
  4244. } else if (IS_VALLEYVIEW(dev)) {
  4245. vlv_update_pll(intel_crtc);
  4246. } else {
  4247. i9xx_update_pll(intel_crtc,
  4248. has_reduced_clock ? &reduced_clock : NULL,
  4249. num_connectors);
  4250. }
  4251. skip_dpll:
  4252. /* Set up the display plane register */
  4253. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4254. if (!IS_VALLEYVIEW(dev)) {
  4255. if (pipe == 0)
  4256. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  4257. else
  4258. dspcntr |= DISPPLANE_SEL_PIPE_B;
  4259. }
  4260. intel_set_pipe_timings(intel_crtc);
  4261. /* pipesrc and dspsize control the size that is scaled from,
  4262. * which should always be the user's requested size.
  4263. */
  4264. I915_WRITE(DSPSIZE(plane),
  4265. ((intel_crtc->config.pipe_src_h - 1) << 16) |
  4266. (intel_crtc->config.pipe_src_w - 1));
  4267. I915_WRITE(DSPPOS(plane), 0);
  4268. i9xx_set_pipeconf(intel_crtc);
  4269. I915_WRITE(DSPCNTR(plane), dspcntr);
  4270. POSTING_READ(DSPCNTR(plane));
  4271. ret = intel_pipe_set_base(crtc, x, y, fb);
  4272. return ret;
  4273. }
  4274. static void i9xx_get_pfit_config(struct intel_crtc *crtc,
  4275. struct intel_crtc_config *pipe_config)
  4276. {
  4277. struct drm_device *dev = crtc->base.dev;
  4278. struct drm_i915_private *dev_priv = dev->dev_private;
  4279. uint32_t tmp;
  4280. tmp = I915_READ(PFIT_CONTROL);
  4281. if (!(tmp & PFIT_ENABLE))
  4282. return;
  4283. /* Check whether the pfit is attached to our pipe. */
  4284. if (INTEL_INFO(dev)->gen < 4) {
  4285. if (crtc->pipe != PIPE_B)
  4286. return;
  4287. } else {
  4288. if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
  4289. return;
  4290. }
  4291. pipe_config->gmch_pfit.control = tmp;
  4292. pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
  4293. if (INTEL_INFO(dev)->gen < 5)
  4294. pipe_config->gmch_pfit.lvds_border_bits =
  4295. I915_READ(LVDS) & LVDS_BORDER_ENABLE;
  4296. }
  4297. static void vlv_crtc_clock_get(struct intel_crtc *crtc,
  4298. struct intel_crtc_config *pipe_config)
  4299. {
  4300. struct drm_device *dev = crtc->base.dev;
  4301. struct drm_i915_private *dev_priv = dev->dev_private;
  4302. int pipe = pipe_config->cpu_transcoder;
  4303. intel_clock_t clock;
  4304. u32 mdiv;
  4305. int refclk = 100000;
  4306. mutex_lock(&dev_priv->dpio_lock);
  4307. mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
  4308. mutex_unlock(&dev_priv->dpio_lock);
  4309. clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
  4310. clock.m2 = mdiv & DPIO_M2DIV_MASK;
  4311. clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
  4312. clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
  4313. clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
  4314. clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
  4315. clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
  4316. pipe_config->port_clock = clock.dot / 10;
  4317. }
  4318. static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
  4319. struct intel_crtc_config *pipe_config)
  4320. {
  4321. struct drm_device *dev = crtc->base.dev;
  4322. struct drm_i915_private *dev_priv = dev->dev_private;
  4323. uint32_t tmp;
  4324. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  4325. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  4326. tmp = I915_READ(PIPECONF(crtc->pipe));
  4327. if (!(tmp & PIPECONF_ENABLE))
  4328. return false;
  4329. if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  4330. switch (tmp & PIPECONF_BPC_MASK) {
  4331. case PIPECONF_6BPC:
  4332. pipe_config->pipe_bpp = 18;
  4333. break;
  4334. case PIPECONF_8BPC:
  4335. pipe_config->pipe_bpp = 24;
  4336. break;
  4337. case PIPECONF_10BPC:
  4338. pipe_config->pipe_bpp = 30;
  4339. break;
  4340. default:
  4341. break;
  4342. }
  4343. }
  4344. if (INTEL_INFO(dev)->gen < 4)
  4345. pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
  4346. intel_get_pipe_timings(crtc, pipe_config);
  4347. i9xx_get_pfit_config(crtc, pipe_config);
  4348. if (INTEL_INFO(dev)->gen >= 4) {
  4349. tmp = I915_READ(DPLL_MD(crtc->pipe));
  4350. pipe_config->pixel_multiplier =
  4351. ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
  4352. >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
  4353. pipe_config->dpll_hw_state.dpll_md = tmp;
  4354. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  4355. tmp = I915_READ(DPLL(crtc->pipe));
  4356. pipe_config->pixel_multiplier =
  4357. ((tmp & SDVO_MULTIPLIER_MASK)
  4358. >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
  4359. } else {
  4360. /* Note that on i915G/GM the pixel multiplier is in the sdvo
  4361. * port and will be fixed up in the encoder->get_config
  4362. * function. */
  4363. pipe_config->pixel_multiplier = 1;
  4364. }
  4365. pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
  4366. if (!IS_VALLEYVIEW(dev)) {
  4367. pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
  4368. pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
  4369. } else {
  4370. /* Mask out read-only status bits. */
  4371. pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
  4372. DPLL_PORTC_READY_MASK |
  4373. DPLL_PORTB_READY_MASK);
  4374. }
  4375. if (IS_VALLEYVIEW(dev))
  4376. vlv_crtc_clock_get(crtc, pipe_config);
  4377. else
  4378. i9xx_crtc_clock_get(crtc, pipe_config);
  4379. return true;
  4380. }
  4381. static void ironlake_init_pch_refclk(struct drm_device *dev)
  4382. {
  4383. struct drm_i915_private *dev_priv = dev->dev_private;
  4384. struct drm_mode_config *mode_config = &dev->mode_config;
  4385. struct intel_encoder *encoder;
  4386. u32 val, final;
  4387. bool has_lvds = false;
  4388. bool has_cpu_edp = false;
  4389. bool has_panel = false;
  4390. bool has_ck505 = false;
  4391. bool can_ssc = false;
  4392. /* We need to take the global config into account */
  4393. list_for_each_entry(encoder, &mode_config->encoder_list,
  4394. base.head) {
  4395. switch (encoder->type) {
  4396. case INTEL_OUTPUT_LVDS:
  4397. has_panel = true;
  4398. has_lvds = true;
  4399. break;
  4400. case INTEL_OUTPUT_EDP:
  4401. has_panel = true;
  4402. if (enc_to_dig_port(&encoder->base)->port == PORT_A)
  4403. has_cpu_edp = true;
  4404. break;
  4405. }
  4406. }
  4407. if (HAS_PCH_IBX(dev)) {
  4408. has_ck505 = dev_priv->vbt.display_clock_mode;
  4409. can_ssc = has_ck505;
  4410. } else {
  4411. has_ck505 = false;
  4412. can_ssc = true;
  4413. }
  4414. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
  4415. has_panel, has_lvds, has_ck505);
  4416. /* Ironlake: try to setup display ref clock before DPLL
  4417. * enabling. This is only under driver's control after
  4418. * PCH B stepping, previous chipset stepping should be
  4419. * ignoring this setting.
  4420. */
  4421. val = I915_READ(PCH_DREF_CONTROL);
  4422. /* As we must carefully and slowly disable/enable each source in turn,
  4423. * compute the final state we want first and check if we need to
  4424. * make any changes at all.
  4425. */
  4426. final = val;
  4427. final &= ~DREF_NONSPREAD_SOURCE_MASK;
  4428. if (has_ck505)
  4429. final |= DREF_NONSPREAD_CK505_ENABLE;
  4430. else
  4431. final |= DREF_NONSPREAD_SOURCE_ENABLE;
  4432. final &= ~DREF_SSC_SOURCE_MASK;
  4433. final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4434. final &= ~DREF_SSC1_ENABLE;
  4435. if (has_panel) {
  4436. final |= DREF_SSC_SOURCE_ENABLE;
  4437. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4438. final |= DREF_SSC1_ENABLE;
  4439. if (has_cpu_edp) {
  4440. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4441. final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4442. else
  4443. final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4444. } else
  4445. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4446. } else {
  4447. final |= DREF_SSC_SOURCE_DISABLE;
  4448. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4449. }
  4450. if (final == val)
  4451. return;
  4452. /* Always enable nonspread source */
  4453. val &= ~DREF_NONSPREAD_SOURCE_MASK;
  4454. if (has_ck505)
  4455. val |= DREF_NONSPREAD_CK505_ENABLE;
  4456. else
  4457. val |= DREF_NONSPREAD_SOURCE_ENABLE;
  4458. if (has_panel) {
  4459. val &= ~DREF_SSC_SOURCE_MASK;
  4460. val |= DREF_SSC_SOURCE_ENABLE;
  4461. /* SSC must be turned on before enabling the CPU output */
  4462. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4463. DRM_DEBUG_KMS("Using SSC on panel\n");
  4464. val |= DREF_SSC1_ENABLE;
  4465. } else
  4466. val &= ~DREF_SSC1_ENABLE;
  4467. /* Get SSC going before enabling the outputs */
  4468. I915_WRITE(PCH_DREF_CONTROL, val);
  4469. POSTING_READ(PCH_DREF_CONTROL);
  4470. udelay(200);
  4471. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4472. /* Enable CPU source on CPU attached eDP */
  4473. if (has_cpu_edp) {
  4474. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4475. DRM_DEBUG_KMS("Using SSC on eDP\n");
  4476. val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4477. }
  4478. else
  4479. val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4480. } else
  4481. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4482. I915_WRITE(PCH_DREF_CONTROL, val);
  4483. POSTING_READ(PCH_DREF_CONTROL);
  4484. udelay(200);
  4485. } else {
  4486. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  4487. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4488. /* Turn off CPU output */
  4489. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4490. I915_WRITE(PCH_DREF_CONTROL, val);
  4491. POSTING_READ(PCH_DREF_CONTROL);
  4492. udelay(200);
  4493. /* Turn off the SSC source */
  4494. val &= ~DREF_SSC_SOURCE_MASK;
  4495. val |= DREF_SSC_SOURCE_DISABLE;
  4496. /* Turn off SSC1 */
  4497. val &= ~DREF_SSC1_ENABLE;
  4498. I915_WRITE(PCH_DREF_CONTROL, val);
  4499. POSTING_READ(PCH_DREF_CONTROL);
  4500. udelay(200);
  4501. }
  4502. BUG_ON(val != final);
  4503. }
  4504. static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
  4505. {
  4506. uint32_t tmp;
  4507. tmp = I915_READ(SOUTH_CHICKEN2);
  4508. tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
  4509. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4510. if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
  4511. FDI_MPHY_IOSFSB_RESET_STATUS, 100))
  4512. DRM_ERROR("FDI mPHY reset assert timeout\n");
  4513. tmp = I915_READ(SOUTH_CHICKEN2);
  4514. tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
  4515. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4516. if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
  4517. FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
  4518. DRM_ERROR("FDI mPHY reset de-assert timeout\n");
  4519. }
  4520. /* WaMPhyProgramming:hsw */
  4521. static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
  4522. {
  4523. uint32_t tmp;
  4524. tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
  4525. tmp &= ~(0xFF << 24);
  4526. tmp |= (0x12 << 24);
  4527. intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
  4528. tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
  4529. tmp |= (1 << 11);
  4530. intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
  4531. tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
  4532. tmp |= (1 << 11);
  4533. intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
  4534. tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
  4535. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4536. intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
  4537. tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
  4538. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4539. intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
  4540. tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
  4541. tmp &= ~(7 << 13);
  4542. tmp |= (5 << 13);
  4543. intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
  4544. tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
  4545. tmp &= ~(7 << 13);
  4546. tmp |= (5 << 13);
  4547. intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
  4548. tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
  4549. tmp &= ~0xFF;
  4550. tmp |= 0x1C;
  4551. intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
  4552. tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
  4553. tmp &= ~0xFF;
  4554. tmp |= 0x1C;
  4555. intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
  4556. tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
  4557. tmp &= ~(0xFF << 16);
  4558. tmp |= (0x1C << 16);
  4559. intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
  4560. tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
  4561. tmp &= ~(0xFF << 16);
  4562. tmp |= (0x1C << 16);
  4563. intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
  4564. tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
  4565. tmp |= (1 << 27);
  4566. intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
  4567. tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
  4568. tmp |= (1 << 27);
  4569. intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
  4570. tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
  4571. tmp &= ~(0xF << 28);
  4572. tmp |= (4 << 28);
  4573. intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
  4574. tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
  4575. tmp &= ~(0xF << 28);
  4576. tmp |= (4 << 28);
  4577. intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
  4578. }
  4579. /* Implements 3 different sequences from BSpec chapter "Display iCLK
  4580. * Programming" based on the parameters passed:
  4581. * - Sequence to enable CLKOUT_DP
  4582. * - Sequence to enable CLKOUT_DP without spread
  4583. * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
  4584. */
  4585. static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
  4586. bool with_fdi)
  4587. {
  4588. struct drm_i915_private *dev_priv = dev->dev_private;
  4589. uint32_t reg, tmp;
  4590. if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
  4591. with_spread = true;
  4592. if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
  4593. with_fdi, "LP PCH doesn't have FDI\n"))
  4594. with_fdi = false;
  4595. mutex_lock(&dev_priv->dpio_lock);
  4596. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4597. tmp &= ~SBI_SSCCTL_DISABLE;
  4598. tmp |= SBI_SSCCTL_PATHALT;
  4599. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4600. udelay(24);
  4601. if (with_spread) {
  4602. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4603. tmp &= ~SBI_SSCCTL_PATHALT;
  4604. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4605. if (with_fdi) {
  4606. lpt_reset_fdi_mphy(dev_priv);
  4607. lpt_program_fdi_mphy(dev_priv);
  4608. }
  4609. }
  4610. reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  4611. SBI_GEN0 : SBI_DBUFF0;
  4612. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  4613. tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  4614. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  4615. mutex_unlock(&dev_priv->dpio_lock);
  4616. }
  4617. /* Sequence to disable CLKOUT_DP */
  4618. static void lpt_disable_clkout_dp(struct drm_device *dev)
  4619. {
  4620. struct drm_i915_private *dev_priv = dev->dev_private;
  4621. uint32_t reg, tmp;
  4622. mutex_lock(&dev_priv->dpio_lock);
  4623. reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  4624. SBI_GEN0 : SBI_DBUFF0;
  4625. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  4626. tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  4627. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  4628. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4629. if (!(tmp & SBI_SSCCTL_DISABLE)) {
  4630. if (!(tmp & SBI_SSCCTL_PATHALT)) {
  4631. tmp |= SBI_SSCCTL_PATHALT;
  4632. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4633. udelay(32);
  4634. }
  4635. tmp |= SBI_SSCCTL_DISABLE;
  4636. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4637. }
  4638. mutex_unlock(&dev_priv->dpio_lock);
  4639. }
  4640. static void lpt_init_pch_refclk(struct drm_device *dev)
  4641. {
  4642. struct drm_mode_config *mode_config = &dev->mode_config;
  4643. struct intel_encoder *encoder;
  4644. bool has_vga = false;
  4645. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4646. switch (encoder->type) {
  4647. case INTEL_OUTPUT_ANALOG:
  4648. has_vga = true;
  4649. break;
  4650. }
  4651. }
  4652. if (has_vga)
  4653. lpt_enable_clkout_dp(dev, true, true);
  4654. else
  4655. lpt_disable_clkout_dp(dev);
  4656. }
  4657. /*
  4658. * Initialize reference clocks when the driver loads
  4659. */
  4660. void intel_init_pch_refclk(struct drm_device *dev)
  4661. {
  4662. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  4663. ironlake_init_pch_refclk(dev);
  4664. else if (HAS_PCH_LPT(dev))
  4665. lpt_init_pch_refclk(dev);
  4666. }
  4667. static int ironlake_get_refclk(struct drm_crtc *crtc)
  4668. {
  4669. struct drm_device *dev = crtc->dev;
  4670. struct drm_i915_private *dev_priv = dev->dev_private;
  4671. struct intel_encoder *encoder;
  4672. int num_connectors = 0;
  4673. bool is_lvds = false;
  4674. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4675. switch (encoder->type) {
  4676. case INTEL_OUTPUT_LVDS:
  4677. is_lvds = true;
  4678. break;
  4679. }
  4680. num_connectors++;
  4681. }
  4682. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4683. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4684. dev_priv->vbt.lvds_ssc_freq);
  4685. return dev_priv->vbt.lvds_ssc_freq * 1000;
  4686. }
  4687. return 120000;
  4688. }
  4689. static void ironlake_set_pipeconf(struct drm_crtc *crtc)
  4690. {
  4691. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4692. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4693. int pipe = intel_crtc->pipe;
  4694. uint32_t val;
  4695. val = 0;
  4696. switch (intel_crtc->config.pipe_bpp) {
  4697. case 18:
  4698. val |= PIPECONF_6BPC;
  4699. break;
  4700. case 24:
  4701. val |= PIPECONF_8BPC;
  4702. break;
  4703. case 30:
  4704. val |= PIPECONF_10BPC;
  4705. break;
  4706. case 36:
  4707. val |= PIPECONF_12BPC;
  4708. break;
  4709. default:
  4710. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4711. BUG();
  4712. }
  4713. if (intel_crtc->config.dither)
  4714. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4715. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4716. val |= PIPECONF_INTERLACED_ILK;
  4717. else
  4718. val |= PIPECONF_PROGRESSIVE;
  4719. if (intel_crtc->config.limited_color_range)
  4720. val |= PIPECONF_COLOR_RANGE_SELECT;
  4721. I915_WRITE(PIPECONF(pipe), val);
  4722. POSTING_READ(PIPECONF(pipe));
  4723. }
  4724. /*
  4725. * Set up the pipe CSC unit.
  4726. *
  4727. * Currently only full range RGB to limited range RGB conversion
  4728. * is supported, but eventually this should handle various
  4729. * RGB<->YCbCr scenarios as well.
  4730. */
  4731. static void intel_set_pipe_csc(struct drm_crtc *crtc)
  4732. {
  4733. struct drm_device *dev = crtc->dev;
  4734. struct drm_i915_private *dev_priv = dev->dev_private;
  4735. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4736. int pipe = intel_crtc->pipe;
  4737. uint16_t coeff = 0x7800; /* 1.0 */
  4738. /*
  4739. * TODO: Check what kind of values actually come out of the pipe
  4740. * with these coeff/postoff values and adjust to get the best
  4741. * accuracy. Perhaps we even need to take the bpc value into
  4742. * consideration.
  4743. */
  4744. if (intel_crtc->config.limited_color_range)
  4745. coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
  4746. /*
  4747. * GY/GU and RY/RU should be the other way around according
  4748. * to BSpec, but reality doesn't agree. Just set them up in
  4749. * a way that results in the correct picture.
  4750. */
  4751. I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
  4752. I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
  4753. I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
  4754. I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
  4755. I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
  4756. I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
  4757. I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
  4758. I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
  4759. I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
  4760. if (INTEL_INFO(dev)->gen > 6) {
  4761. uint16_t postoff = 0;
  4762. if (intel_crtc->config.limited_color_range)
  4763. postoff = (16 * (1 << 13) / 255) & 0x1fff;
  4764. I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
  4765. I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
  4766. I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
  4767. I915_WRITE(PIPE_CSC_MODE(pipe), 0);
  4768. } else {
  4769. uint32_t mode = CSC_MODE_YUV_TO_RGB;
  4770. if (intel_crtc->config.limited_color_range)
  4771. mode |= CSC_BLACK_SCREEN_OFFSET;
  4772. I915_WRITE(PIPE_CSC_MODE(pipe), mode);
  4773. }
  4774. }
  4775. static void haswell_set_pipeconf(struct drm_crtc *crtc)
  4776. {
  4777. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4778. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4779. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  4780. uint32_t val;
  4781. val = 0;
  4782. if (intel_crtc->config.dither)
  4783. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4784. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4785. val |= PIPECONF_INTERLACED_ILK;
  4786. else
  4787. val |= PIPECONF_PROGRESSIVE;
  4788. I915_WRITE(PIPECONF(cpu_transcoder), val);
  4789. POSTING_READ(PIPECONF(cpu_transcoder));
  4790. I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
  4791. POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
  4792. }
  4793. static bool ironlake_compute_clocks(struct drm_crtc *crtc,
  4794. intel_clock_t *clock,
  4795. bool *has_reduced_clock,
  4796. intel_clock_t *reduced_clock)
  4797. {
  4798. struct drm_device *dev = crtc->dev;
  4799. struct drm_i915_private *dev_priv = dev->dev_private;
  4800. struct intel_encoder *intel_encoder;
  4801. int refclk;
  4802. const intel_limit_t *limit;
  4803. bool ret, is_lvds = false;
  4804. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4805. switch (intel_encoder->type) {
  4806. case INTEL_OUTPUT_LVDS:
  4807. is_lvds = true;
  4808. break;
  4809. }
  4810. }
  4811. refclk = ironlake_get_refclk(crtc);
  4812. /*
  4813. * Returns a set of divisors for the desired target clock with the given
  4814. * refclk, or FALSE. The returned values represent the clock equation:
  4815. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4816. */
  4817. limit = intel_limit(crtc, refclk);
  4818. ret = dev_priv->display.find_dpll(limit, crtc,
  4819. to_intel_crtc(crtc)->config.port_clock,
  4820. refclk, NULL, clock);
  4821. if (!ret)
  4822. return false;
  4823. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4824. /*
  4825. * Ensure we match the reduced clock's P to the target clock.
  4826. * If the clocks don't match, we can't switch the display clock
  4827. * by using the FP0/FP1. In such case we will disable the LVDS
  4828. * downclock feature.
  4829. */
  4830. *has_reduced_clock =
  4831. dev_priv->display.find_dpll(limit, crtc,
  4832. dev_priv->lvds_downclock,
  4833. refclk, clock,
  4834. reduced_clock);
  4835. }
  4836. return true;
  4837. }
  4838. static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
  4839. {
  4840. struct drm_i915_private *dev_priv = dev->dev_private;
  4841. uint32_t temp;
  4842. temp = I915_READ(SOUTH_CHICKEN1);
  4843. if (temp & FDI_BC_BIFURCATION_SELECT)
  4844. return;
  4845. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  4846. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  4847. temp |= FDI_BC_BIFURCATION_SELECT;
  4848. DRM_DEBUG_KMS("enabling fdi C rx\n");
  4849. I915_WRITE(SOUTH_CHICKEN1, temp);
  4850. POSTING_READ(SOUTH_CHICKEN1);
  4851. }
  4852. static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
  4853. {
  4854. struct drm_device *dev = intel_crtc->base.dev;
  4855. struct drm_i915_private *dev_priv = dev->dev_private;
  4856. switch (intel_crtc->pipe) {
  4857. case PIPE_A:
  4858. break;
  4859. case PIPE_B:
  4860. if (intel_crtc->config.fdi_lanes > 2)
  4861. WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
  4862. else
  4863. cpt_enable_fdi_bc_bifurcation(dev);
  4864. break;
  4865. case PIPE_C:
  4866. cpt_enable_fdi_bc_bifurcation(dev);
  4867. break;
  4868. default:
  4869. BUG();
  4870. }
  4871. }
  4872. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
  4873. {
  4874. /*
  4875. * Account for spread spectrum to avoid
  4876. * oversubscribing the link. Max center spread
  4877. * is 2.5%; use 5% for safety's sake.
  4878. */
  4879. u32 bps = target_clock * bpp * 21 / 20;
  4880. return bps / (link_bw * 8) + 1;
  4881. }
  4882. static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
  4883. {
  4884. return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
  4885. }
  4886. static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
  4887. u32 *fp,
  4888. intel_clock_t *reduced_clock, u32 *fp2)
  4889. {
  4890. struct drm_crtc *crtc = &intel_crtc->base;
  4891. struct drm_device *dev = crtc->dev;
  4892. struct drm_i915_private *dev_priv = dev->dev_private;
  4893. struct intel_encoder *intel_encoder;
  4894. uint32_t dpll;
  4895. int factor, num_connectors = 0;
  4896. bool is_lvds = false, is_sdvo = false;
  4897. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4898. switch (intel_encoder->type) {
  4899. case INTEL_OUTPUT_LVDS:
  4900. is_lvds = true;
  4901. break;
  4902. case INTEL_OUTPUT_SDVO:
  4903. case INTEL_OUTPUT_HDMI:
  4904. is_sdvo = true;
  4905. break;
  4906. }
  4907. num_connectors++;
  4908. }
  4909. /* Enable autotuning of the PLL clock (if permissible) */
  4910. factor = 21;
  4911. if (is_lvds) {
  4912. if ((intel_panel_use_ssc(dev_priv) &&
  4913. dev_priv->vbt.lvds_ssc_freq == 100) ||
  4914. (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
  4915. factor = 25;
  4916. } else if (intel_crtc->config.sdvo_tv_clock)
  4917. factor = 20;
  4918. if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
  4919. *fp |= FP_CB_TUNE;
  4920. if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
  4921. *fp2 |= FP_CB_TUNE;
  4922. dpll = 0;
  4923. if (is_lvds)
  4924. dpll |= DPLLB_MODE_LVDS;
  4925. else
  4926. dpll |= DPLLB_MODE_DAC_SERIAL;
  4927. dpll |= (intel_crtc->config.pixel_multiplier - 1)
  4928. << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  4929. if (is_sdvo)
  4930. dpll |= DPLL_SDVO_HIGH_SPEED;
  4931. if (intel_crtc->config.has_dp_encoder)
  4932. dpll |= DPLL_SDVO_HIGH_SPEED;
  4933. /* compute bitmask from p1 value */
  4934. dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4935. /* also FPA1 */
  4936. dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4937. switch (intel_crtc->config.dpll.p2) {
  4938. case 5:
  4939. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4940. break;
  4941. case 7:
  4942. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4943. break;
  4944. case 10:
  4945. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4946. break;
  4947. case 14:
  4948. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4949. break;
  4950. }
  4951. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4952. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4953. else
  4954. dpll |= PLL_REF_INPUT_DREFCLK;
  4955. return dpll | DPLL_VCO_ENABLE;
  4956. }
  4957. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  4958. int x, int y,
  4959. struct drm_framebuffer *fb)
  4960. {
  4961. struct drm_device *dev = crtc->dev;
  4962. struct drm_i915_private *dev_priv = dev->dev_private;
  4963. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4964. int pipe = intel_crtc->pipe;
  4965. int plane = intel_crtc->plane;
  4966. int num_connectors = 0;
  4967. intel_clock_t clock, reduced_clock;
  4968. u32 dpll = 0, fp = 0, fp2 = 0;
  4969. bool ok, has_reduced_clock = false;
  4970. bool is_lvds = false;
  4971. struct intel_encoder *encoder;
  4972. struct intel_shared_dpll *pll;
  4973. int ret;
  4974. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4975. switch (encoder->type) {
  4976. case INTEL_OUTPUT_LVDS:
  4977. is_lvds = true;
  4978. break;
  4979. }
  4980. num_connectors++;
  4981. }
  4982. WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
  4983. "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
  4984. ok = ironlake_compute_clocks(crtc, &clock,
  4985. &has_reduced_clock, &reduced_clock);
  4986. if (!ok && !intel_crtc->config.clock_set) {
  4987. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4988. return -EINVAL;
  4989. }
  4990. /* Compat-code for transition, will disappear. */
  4991. if (!intel_crtc->config.clock_set) {
  4992. intel_crtc->config.dpll.n = clock.n;
  4993. intel_crtc->config.dpll.m1 = clock.m1;
  4994. intel_crtc->config.dpll.m2 = clock.m2;
  4995. intel_crtc->config.dpll.p1 = clock.p1;
  4996. intel_crtc->config.dpll.p2 = clock.p2;
  4997. }
  4998. /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
  4999. if (intel_crtc->config.has_pch_encoder) {
  5000. fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
  5001. if (has_reduced_clock)
  5002. fp2 = i9xx_dpll_compute_fp(&reduced_clock);
  5003. dpll = ironlake_compute_dpll(intel_crtc,
  5004. &fp, &reduced_clock,
  5005. has_reduced_clock ? &fp2 : NULL);
  5006. intel_crtc->config.dpll_hw_state.dpll = dpll;
  5007. intel_crtc->config.dpll_hw_state.fp0 = fp;
  5008. if (has_reduced_clock)
  5009. intel_crtc->config.dpll_hw_state.fp1 = fp2;
  5010. else
  5011. intel_crtc->config.dpll_hw_state.fp1 = fp;
  5012. pll = intel_get_shared_dpll(intel_crtc);
  5013. if (pll == NULL) {
  5014. DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
  5015. pipe_name(pipe));
  5016. return -EINVAL;
  5017. }
  5018. } else
  5019. intel_put_shared_dpll(intel_crtc);
  5020. if (intel_crtc->config.has_dp_encoder)
  5021. intel_dp_set_m_n(intel_crtc);
  5022. if (is_lvds && has_reduced_clock && i915_powersave)
  5023. intel_crtc->lowfreq_avail = true;
  5024. else
  5025. intel_crtc->lowfreq_avail = false;
  5026. if (intel_crtc->config.has_pch_encoder) {
  5027. pll = intel_crtc_to_shared_dpll(intel_crtc);
  5028. }
  5029. intel_set_pipe_timings(intel_crtc);
  5030. if (intel_crtc->config.has_pch_encoder) {
  5031. intel_cpu_transcoder_set_m_n(intel_crtc,
  5032. &intel_crtc->config.fdi_m_n);
  5033. }
  5034. if (IS_IVYBRIDGE(dev))
  5035. ivybridge_update_fdi_bc_bifurcation(intel_crtc);
  5036. ironlake_set_pipeconf(crtc);
  5037. /* Set up the display plane register */
  5038. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
  5039. POSTING_READ(DSPCNTR(plane));
  5040. ret = intel_pipe_set_base(crtc, x, y, fb);
  5041. return ret;
  5042. }
  5043. static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
  5044. struct intel_link_m_n *m_n)
  5045. {
  5046. struct drm_device *dev = crtc->base.dev;
  5047. struct drm_i915_private *dev_priv = dev->dev_private;
  5048. enum pipe pipe = crtc->pipe;
  5049. m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
  5050. m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
  5051. m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
  5052. & ~TU_SIZE_MASK;
  5053. m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
  5054. m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
  5055. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  5056. }
  5057. static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
  5058. enum transcoder transcoder,
  5059. struct intel_link_m_n *m_n)
  5060. {
  5061. struct drm_device *dev = crtc->base.dev;
  5062. struct drm_i915_private *dev_priv = dev->dev_private;
  5063. enum pipe pipe = crtc->pipe;
  5064. if (INTEL_INFO(dev)->gen >= 5) {
  5065. m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
  5066. m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
  5067. m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
  5068. & ~TU_SIZE_MASK;
  5069. m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
  5070. m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
  5071. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  5072. } else {
  5073. m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
  5074. m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
  5075. m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
  5076. & ~TU_SIZE_MASK;
  5077. m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
  5078. m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
  5079. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  5080. }
  5081. }
  5082. void intel_dp_get_m_n(struct intel_crtc *crtc,
  5083. struct intel_crtc_config *pipe_config)
  5084. {
  5085. if (crtc->config.has_pch_encoder)
  5086. intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
  5087. else
  5088. intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  5089. &pipe_config->dp_m_n);
  5090. }
  5091. static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
  5092. struct intel_crtc_config *pipe_config)
  5093. {
  5094. intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  5095. &pipe_config->fdi_m_n);
  5096. }
  5097. static void ironlake_get_pfit_config(struct intel_crtc *crtc,
  5098. struct intel_crtc_config *pipe_config)
  5099. {
  5100. struct drm_device *dev = crtc->base.dev;
  5101. struct drm_i915_private *dev_priv = dev->dev_private;
  5102. uint32_t tmp;
  5103. tmp = I915_READ(PF_CTL(crtc->pipe));
  5104. if (tmp & PF_ENABLE) {
  5105. pipe_config->pch_pfit.enabled = true;
  5106. pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
  5107. pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
  5108. /* We currently do not free assignements of panel fitters on
  5109. * ivb/hsw (since we don't use the higher upscaling modes which
  5110. * differentiates them) so just WARN about this case for now. */
  5111. if (IS_GEN7(dev)) {
  5112. WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
  5113. PF_PIPE_SEL_IVB(crtc->pipe));
  5114. }
  5115. }
  5116. }
  5117. static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
  5118. struct intel_crtc_config *pipe_config)
  5119. {
  5120. struct drm_device *dev = crtc->base.dev;
  5121. struct drm_i915_private *dev_priv = dev->dev_private;
  5122. uint32_t tmp;
  5123. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  5124. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  5125. tmp = I915_READ(PIPECONF(crtc->pipe));
  5126. if (!(tmp & PIPECONF_ENABLE))
  5127. return false;
  5128. switch (tmp & PIPECONF_BPC_MASK) {
  5129. case PIPECONF_6BPC:
  5130. pipe_config->pipe_bpp = 18;
  5131. break;
  5132. case PIPECONF_8BPC:
  5133. pipe_config->pipe_bpp = 24;
  5134. break;
  5135. case PIPECONF_10BPC:
  5136. pipe_config->pipe_bpp = 30;
  5137. break;
  5138. case PIPECONF_12BPC:
  5139. pipe_config->pipe_bpp = 36;
  5140. break;
  5141. default:
  5142. break;
  5143. }
  5144. if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
  5145. struct intel_shared_dpll *pll;
  5146. pipe_config->has_pch_encoder = true;
  5147. tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
  5148. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  5149. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  5150. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  5151. if (HAS_PCH_IBX(dev_priv->dev)) {
  5152. pipe_config->shared_dpll =
  5153. (enum intel_dpll_id) crtc->pipe;
  5154. } else {
  5155. tmp = I915_READ(PCH_DPLL_SEL);
  5156. if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
  5157. pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
  5158. else
  5159. pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
  5160. }
  5161. pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
  5162. WARN_ON(!pll->get_hw_state(dev_priv, pll,
  5163. &pipe_config->dpll_hw_state));
  5164. tmp = pipe_config->dpll_hw_state.dpll;
  5165. pipe_config->pixel_multiplier =
  5166. ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
  5167. >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
  5168. ironlake_pch_clock_get(crtc, pipe_config);
  5169. } else {
  5170. pipe_config->pixel_multiplier = 1;
  5171. }
  5172. intel_get_pipe_timings(crtc, pipe_config);
  5173. ironlake_get_pfit_config(crtc, pipe_config);
  5174. return true;
  5175. }
  5176. static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
  5177. {
  5178. struct drm_device *dev = dev_priv->dev;
  5179. struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
  5180. struct intel_crtc *crtc;
  5181. unsigned long irqflags;
  5182. uint32_t val;
  5183. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
  5184. WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
  5185. pipe_name(crtc->pipe));
  5186. WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
  5187. WARN(plls->spll_refcount, "SPLL enabled\n");
  5188. WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
  5189. WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
  5190. WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
  5191. WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
  5192. "CPU PWM1 enabled\n");
  5193. WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
  5194. "CPU PWM2 enabled\n");
  5195. WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
  5196. "PCH PWM1 enabled\n");
  5197. WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
  5198. "Utility pin enabled\n");
  5199. WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
  5200. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  5201. val = I915_READ(DEIMR);
  5202. WARN((val & ~DE_PCH_EVENT_IVB) != val,
  5203. "Unexpected DEIMR bits enabled: 0x%x\n", val);
  5204. val = I915_READ(SDEIMR);
  5205. WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
  5206. "Unexpected SDEIMR bits enabled: 0x%x\n", val);
  5207. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  5208. }
  5209. /*
  5210. * This function implements pieces of two sequences from BSpec:
  5211. * - Sequence for display software to disable LCPLL
  5212. * - Sequence for display software to allow package C8+
  5213. * The steps implemented here are just the steps that actually touch the LCPLL
  5214. * register. Callers should take care of disabling all the display engine
  5215. * functions, doing the mode unset, fixing interrupts, etc.
  5216. */
  5217. static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
  5218. bool switch_to_fclk, bool allow_power_down)
  5219. {
  5220. uint32_t val;
  5221. assert_can_disable_lcpll(dev_priv);
  5222. val = I915_READ(LCPLL_CTL);
  5223. if (switch_to_fclk) {
  5224. val |= LCPLL_CD_SOURCE_FCLK;
  5225. I915_WRITE(LCPLL_CTL, val);
  5226. if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
  5227. LCPLL_CD_SOURCE_FCLK_DONE, 1))
  5228. DRM_ERROR("Switching to FCLK failed\n");
  5229. val = I915_READ(LCPLL_CTL);
  5230. }
  5231. val |= LCPLL_PLL_DISABLE;
  5232. I915_WRITE(LCPLL_CTL, val);
  5233. POSTING_READ(LCPLL_CTL);
  5234. if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
  5235. DRM_ERROR("LCPLL still locked\n");
  5236. val = I915_READ(D_COMP);
  5237. val |= D_COMP_COMP_DISABLE;
  5238. mutex_lock(&dev_priv->rps.hw_lock);
  5239. if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
  5240. DRM_ERROR("Failed to disable D_COMP\n");
  5241. mutex_unlock(&dev_priv->rps.hw_lock);
  5242. POSTING_READ(D_COMP);
  5243. ndelay(100);
  5244. if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
  5245. DRM_ERROR("D_COMP RCOMP still in progress\n");
  5246. if (allow_power_down) {
  5247. val = I915_READ(LCPLL_CTL);
  5248. val |= LCPLL_POWER_DOWN_ALLOW;
  5249. I915_WRITE(LCPLL_CTL, val);
  5250. POSTING_READ(LCPLL_CTL);
  5251. }
  5252. }
  5253. /*
  5254. * Fully restores LCPLL, disallowing power down and switching back to LCPLL
  5255. * source.
  5256. */
  5257. static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
  5258. {
  5259. uint32_t val;
  5260. val = I915_READ(LCPLL_CTL);
  5261. if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
  5262. LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
  5263. return;
  5264. /* Make sure we're not on PC8 state before disabling PC8, otherwise
  5265. * we'll hang the machine! */
  5266. dev_priv->uncore.funcs.force_wake_get(dev_priv);
  5267. if (val & LCPLL_POWER_DOWN_ALLOW) {
  5268. val &= ~LCPLL_POWER_DOWN_ALLOW;
  5269. I915_WRITE(LCPLL_CTL, val);
  5270. POSTING_READ(LCPLL_CTL);
  5271. }
  5272. val = I915_READ(D_COMP);
  5273. val |= D_COMP_COMP_FORCE;
  5274. val &= ~D_COMP_COMP_DISABLE;
  5275. mutex_lock(&dev_priv->rps.hw_lock);
  5276. if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
  5277. DRM_ERROR("Failed to enable D_COMP\n");
  5278. mutex_unlock(&dev_priv->rps.hw_lock);
  5279. POSTING_READ(D_COMP);
  5280. val = I915_READ(LCPLL_CTL);
  5281. val &= ~LCPLL_PLL_DISABLE;
  5282. I915_WRITE(LCPLL_CTL, val);
  5283. if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
  5284. DRM_ERROR("LCPLL not locked yet\n");
  5285. if (val & LCPLL_CD_SOURCE_FCLK) {
  5286. val = I915_READ(LCPLL_CTL);
  5287. val &= ~LCPLL_CD_SOURCE_FCLK;
  5288. I915_WRITE(LCPLL_CTL, val);
  5289. if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
  5290. LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
  5291. DRM_ERROR("Switching back to LCPLL failed\n");
  5292. }
  5293. dev_priv->uncore.funcs.force_wake_put(dev_priv);
  5294. }
  5295. void hsw_enable_pc8_work(struct work_struct *__work)
  5296. {
  5297. struct drm_i915_private *dev_priv =
  5298. container_of(to_delayed_work(__work), struct drm_i915_private,
  5299. pc8.enable_work);
  5300. struct drm_device *dev = dev_priv->dev;
  5301. uint32_t val;
  5302. if (dev_priv->pc8.enabled)
  5303. return;
  5304. DRM_DEBUG_KMS("Enabling package C8+\n");
  5305. dev_priv->pc8.enabled = true;
  5306. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  5307. val = I915_READ(SOUTH_DSPCLK_GATE_D);
  5308. val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
  5309. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  5310. }
  5311. lpt_disable_clkout_dp(dev);
  5312. hsw_pc8_disable_interrupts(dev);
  5313. hsw_disable_lcpll(dev_priv, true, true);
  5314. }
  5315. static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
  5316. {
  5317. WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
  5318. WARN(dev_priv->pc8.disable_count < 1,
  5319. "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
  5320. dev_priv->pc8.disable_count--;
  5321. if (dev_priv->pc8.disable_count != 0)
  5322. return;
  5323. schedule_delayed_work(&dev_priv->pc8.enable_work,
  5324. msecs_to_jiffies(i915_pc8_timeout));
  5325. }
  5326. static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
  5327. {
  5328. struct drm_device *dev = dev_priv->dev;
  5329. uint32_t val;
  5330. WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
  5331. WARN(dev_priv->pc8.disable_count < 0,
  5332. "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
  5333. dev_priv->pc8.disable_count++;
  5334. if (dev_priv->pc8.disable_count != 1)
  5335. return;
  5336. cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
  5337. if (!dev_priv->pc8.enabled)
  5338. return;
  5339. DRM_DEBUG_KMS("Disabling package C8+\n");
  5340. hsw_restore_lcpll(dev_priv);
  5341. hsw_pc8_restore_interrupts(dev);
  5342. lpt_init_pch_refclk(dev);
  5343. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  5344. val = I915_READ(SOUTH_DSPCLK_GATE_D);
  5345. val |= PCH_LP_PARTITION_LEVEL_DISABLE;
  5346. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  5347. }
  5348. intel_prepare_ddi(dev);
  5349. i915_gem_init_swizzling(dev);
  5350. mutex_lock(&dev_priv->rps.hw_lock);
  5351. gen6_update_ring_freq(dev);
  5352. mutex_unlock(&dev_priv->rps.hw_lock);
  5353. dev_priv->pc8.enabled = false;
  5354. }
  5355. void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
  5356. {
  5357. mutex_lock(&dev_priv->pc8.lock);
  5358. __hsw_enable_package_c8(dev_priv);
  5359. mutex_unlock(&dev_priv->pc8.lock);
  5360. }
  5361. void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
  5362. {
  5363. mutex_lock(&dev_priv->pc8.lock);
  5364. __hsw_disable_package_c8(dev_priv);
  5365. mutex_unlock(&dev_priv->pc8.lock);
  5366. }
  5367. static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
  5368. {
  5369. struct drm_device *dev = dev_priv->dev;
  5370. struct intel_crtc *crtc;
  5371. uint32_t val;
  5372. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
  5373. if (crtc->base.enabled)
  5374. return false;
  5375. /* This case is still possible since we have the i915.disable_power_well
  5376. * parameter and also the KVMr or something else might be requesting the
  5377. * power well. */
  5378. val = I915_READ(HSW_PWR_WELL_DRIVER);
  5379. if (val != 0) {
  5380. DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
  5381. return false;
  5382. }
  5383. return true;
  5384. }
  5385. /* Since we're called from modeset_global_resources there's no way to
  5386. * symmetrically increase and decrease the refcount, so we use
  5387. * dev_priv->pc8.requirements_met to track whether we already have the refcount
  5388. * or not.
  5389. */
  5390. static void hsw_update_package_c8(struct drm_device *dev)
  5391. {
  5392. struct drm_i915_private *dev_priv = dev->dev_private;
  5393. bool allow;
  5394. if (!i915_enable_pc8)
  5395. return;
  5396. mutex_lock(&dev_priv->pc8.lock);
  5397. allow = hsw_can_enable_package_c8(dev_priv);
  5398. if (allow == dev_priv->pc8.requirements_met)
  5399. goto done;
  5400. dev_priv->pc8.requirements_met = allow;
  5401. if (allow)
  5402. __hsw_enable_package_c8(dev_priv);
  5403. else
  5404. __hsw_disable_package_c8(dev_priv);
  5405. done:
  5406. mutex_unlock(&dev_priv->pc8.lock);
  5407. }
  5408. static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
  5409. {
  5410. if (!dev_priv->pc8.gpu_idle) {
  5411. dev_priv->pc8.gpu_idle = true;
  5412. hsw_enable_package_c8(dev_priv);
  5413. }
  5414. }
  5415. static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
  5416. {
  5417. if (dev_priv->pc8.gpu_idle) {
  5418. dev_priv->pc8.gpu_idle = false;
  5419. hsw_disable_package_c8(dev_priv);
  5420. }
  5421. }
  5422. static void haswell_modeset_global_resources(struct drm_device *dev)
  5423. {
  5424. bool enable = false;
  5425. struct intel_crtc *crtc;
  5426. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  5427. if (!crtc->base.enabled)
  5428. continue;
  5429. if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
  5430. crtc->config.cpu_transcoder != TRANSCODER_EDP)
  5431. enable = true;
  5432. }
  5433. intel_set_power_well(dev, enable);
  5434. hsw_update_package_c8(dev);
  5435. }
  5436. static int haswell_crtc_mode_set(struct drm_crtc *crtc,
  5437. int x, int y,
  5438. struct drm_framebuffer *fb)
  5439. {
  5440. struct drm_device *dev = crtc->dev;
  5441. struct drm_i915_private *dev_priv = dev->dev_private;
  5442. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5443. int plane = intel_crtc->plane;
  5444. int ret;
  5445. if (!intel_ddi_pll_mode_set(crtc))
  5446. return -EINVAL;
  5447. if (intel_crtc->config.has_dp_encoder)
  5448. intel_dp_set_m_n(intel_crtc);
  5449. intel_crtc->lowfreq_avail = false;
  5450. intel_set_pipe_timings(intel_crtc);
  5451. if (intel_crtc->config.has_pch_encoder) {
  5452. intel_cpu_transcoder_set_m_n(intel_crtc,
  5453. &intel_crtc->config.fdi_m_n);
  5454. }
  5455. haswell_set_pipeconf(crtc);
  5456. intel_set_pipe_csc(crtc);
  5457. /* Set up the display plane register */
  5458. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
  5459. POSTING_READ(DSPCNTR(plane));
  5460. ret = intel_pipe_set_base(crtc, x, y, fb);
  5461. return ret;
  5462. }
  5463. static bool haswell_get_pipe_config(struct intel_crtc *crtc,
  5464. struct intel_crtc_config *pipe_config)
  5465. {
  5466. struct drm_device *dev = crtc->base.dev;
  5467. struct drm_i915_private *dev_priv = dev->dev_private;
  5468. enum intel_display_power_domain pfit_domain;
  5469. uint32_t tmp;
  5470. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  5471. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  5472. tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  5473. if (tmp & TRANS_DDI_FUNC_ENABLE) {
  5474. enum pipe trans_edp_pipe;
  5475. switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  5476. default:
  5477. WARN(1, "unknown pipe linked to edp transcoder\n");
  5478. case TRANS_DDI_EDP_INPUT_A_ONOFF:
  5479. case TRANS_DDI_EDP_INPUT_A_ON:
  5480. trans_edp_pipe = PIPE_A;
  5481. break;
  5482. case TRANS_DDI_EDP_INPUT_B_ONOFF:
  5483. trans_edp_pipe = PIPE_B;
  5484. break;
  5485. case TRANS_DDI_EDP_INPUT_C_ONOFF:
  5486. trans_edp_pipe = PIPE_C;
  5487. break;
  5488. }
  5489. if (trans_edp_pipe == crtc->pipe)
  5490. pipe_config->cpu_transcoder = TRANSCODER_EDP;
  5491. }
  5492. if (!intel_display_power_enabled(dev,
  5493. POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
  5494. return false;
  5495. tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
  5496. if (!(tmp & PIPECONF_ENABLE))
  5497. return false;
  5498. /*
  5499. * Haswell has only FDI/PCH transcoder A. It is which is connected to
  5500. * DDI E. So just check whether this pipe is wired to DDI E and whether
  5501. * the PCH transcoder is on.
  5502. */
  5503. tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
  5504. if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
  5505. I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
  5506. pipe_config->has_pch_encoder = true;
  5507. tmp = I915_READ(FDI_RX_CTL(PIPE_A));
  5508. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  5509. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  5510. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  5511. }
  5512. intel_get_pipe_timings(crtc, pipe_config);
  5513. pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
  5514. if (intel_display_power_enabled(dev, pfit_domain))
  5515. ironlake_get_pfit_config(crtc, pipe_config);
  5516. pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
  5517. (I915_READ(IPS_CTL) & IPS_ENABLE);
  5518. pipe_config->pixel_multiplier = 1;
  5519. return true;
  5520. }
  5521. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  5522. int x, int y,
  5523. struct drm_framebuffer *fb)
  5524. {
  5525. struct drm_device *dev = crtc->dev;
  5526. struct drm_i915_private *dev_priv = dev->dev_private;
  5527. struct intel_encoder *encoder;
  5528. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5529. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  5530. int pipe = intel_crtc->pipe;
  5531. int ret;
  5532. drm_vblank_pre_modeset(dev, pipe);
  5533. ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
  5534. drm_vblank_post_modeset(dev, pipe);
  5535. if (ret != 0)
  5536. return ret;
  5537. for_each_encoder_on_crtc(dev, crtc, encoder) {
  5538. DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
  5539. encoder->base.base.id,
  5540. drm_get_encoder_name(&encoder->base),
  5541. mode->base.id, mode->name);
  5542. encoder->mode_set(encoder);
  5543. }
  5544. return 0;
  5545. }
  5546. static bool intel_eld_uptodate(struct drm_connector *connector,
  5547. int reg_eldv, uint32_t bits_eldv,
  5548. int reg_elda, uint32_t bits_elda,
  5549. int reg_edid)
  5550. {
  5551. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5552. uint8_t *eld = connector->eld;
  5553. uint32_t i;
  5554. i = I915_READ(reg_eldv);
  5555. i &= bits_eldv;
  5556. if (!eld[0])
  5557. return !i;
  5558. if (!i)
  5559. return false;
  5560. i = I915_READ(reg_elda);
  5561. i &= ~bits_elda;
  5562. I915_WRITE(reg_elda, i);
  5563. for (i = 0; i < eld[2]; i++)
  5564. if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  5565. return false;
  5566. return true;
  5567. }
  5568. static void g4x_write_eld(struct drm_connector *connector,
  5569. struct drm_crtc *crtc)
  5570. {
  5571. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5572. uint8_t *eld = connector->eld;
  5573. uint32_t eldv;
  5574. uint32_t len;
  5575. uint32_t i;
  5576. i = I915_READ(G4X_AUD_VID_DID);
  5577. if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  5578. eldv = G4X_ELDV_DEVCL_DEVBLC;
  5579. else
  5580. eldv = G4X_ELDV_DEVCTG;
  5581. if (intel_eld_uptodate(connector,
  5582. G4X_AUD_CNTL_ST, eldv,
  5583. G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  5584. G4X_HDMIW_HDMIEDID))
  5585. return;
  5586. i = I915_READ(G4X_AUD_CNTL_ST);
  5587. i &= ~(eldv | G4X_ELD_ADDR);
  5588. len = (i >> 9) & 0x1f; /* ELD buffer size */
  5589. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5590. if (!eld[0])
  5591. return;
  5592. len = min_t(uint8_t, eld[2], len);
  5593. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5594. for (i = 0; i < len; i++)
  5595. I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  5596. i = I915_READ(G4X_AUD_CNTL_ST);
  5597. i |= eldv;
  5598. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5599. }
  5600. static void haswell_write_eld(struct drm_connector *connector,
  5601. struct drm_crtc *crtc)
  5602. {
  5603. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5604. uint8_t *eld = connector->eld;
  5605. struct drm_device *dev = crtc->dev;
  5606. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5607. uint32_t eldv;
  5608. uint32_t i;
  5609. int len;
  5610. int pipe = to_intel_crtc(crtc)->pipe;
  5611. int tmp;
  5612. int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
  5613. int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
  5614. int aud_config = HSW_AUD_CFG(pipe);
  5615. int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
  5616. DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
  5617. /* Audio output enable */
  5618. DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
  5619. tmp = I915_READ(aud_cntrl_st2);
  5620. tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
  5621. I915_WRITE(aud_cntrl_st2, tmp);
  5622. /* Wait for 1 vertical blank */
  5623. intel_wait_for_vblank(dev, pipe);
  5624. /* Set ELD valid state */
  5625. tmp = I915_READ(aud_cntrl_st2);
  5626. DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
  5627. tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
  5628. I915_WRITE(aud_cntrl_st2, tmp);
  5629. tmp = I915_READ(aud_cntrl_st2);
  5630. DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
  5631. /* Enable HDMI mode */
  5632. tmp = I915_READ(aud_config);
  5633. DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
  5634. /* clear N_programing_enable and N_value_index */
  5635. tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
  5636. I915_WRITE(aud_config, tmp);
  5637. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5638. eldv = AUDIO_ELD_VALID_A << (pipe * 4);
  5639. intel_crtc->eld_vld = true;
  5640. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5641. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5642. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5643. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5644. } else
  5645. I915_WRITE(aud_config, 0);
  5646. if (intel_eld_uptodate(connector,
  5647. aud_cntrl_st2, eldv,
  5648. aud_cntl_st, IBX_ELD_ADDRESS,
  5649. hdmiw_hdmiedid))
  5650. return;
  5651. i = I915_READ(aud_cntrl_st2);
  5652. i &= ~eldv;
  5653. I915_WRITE(aud_cntrl_st2, i);
  5654. if (!eld[0])
  5655. return;
  5656. i = I915_READ(aud_cntl_st);
  5657. i &= ~IBX_ELD_ADDRESS;
  5658. I915_WRITE(aud_cntl_st, i);
  5659. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5660. DRM_DEBUG_DRIVER("port num:%d\n", i);
  5661. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5662. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5663. for (i = 0; i < len; i++)
  5664. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5665. i = I915_READ(aud_cntrl_st2);
  5666. i |= eldv;
  5667. I915_WRITE(aud_cntrl_st2, i);
  5668. }
  5669. static void ironlake_write_eld(struct drm_connector *connector,
  5670. struct drm_crtc *crtc)
  5671. {
  5672. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5673. uint8_t *eld = connector->eld;
  5674. uint32_t eldv;
  5675. uint32_t i;
  5676. int len;
  5677. int hdmiw_hdmiedid;
  5678. int aud_config;
  5679. int aud_cntl_st;
  5680. int aud_cntrl_st2;
  5681. int pipe = to_intel_crtc(crtc)->pipe;
  5682. if (HAS_PCH_IBX(connector->dev)) {
  5683. hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
  5684. aud_config = IBX_AUD_CFG(pipe);
  5685. aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
  5686. aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  5687. } else {
  5688. hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
  5689. aud_config = CPT_AUD_CFG(pipe);
  5690. aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
  5691. aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  5692. }
  5693. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5694. i = I915_READ(aud_cntl_st);
  5695. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5696. if (!i) {
  5697. DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  5698. /* operate blindly on all ports */
  5699. eldv = IBX_ELD_VALIDB;
  5700. eldv |= IBX_ELD_VALIDB << 4;
  5701. eldv |= IBX_ELD_VALIDB << 8;
  5702. } else {
  5703. DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
  5704. eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  5705. }
  5706. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5707. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5708. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5709. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5710. } else
  5711. I915_WRITE(aud_config, 0);
  5712. if (intel_eld_uptodate(connector,
  5713. aud_cntrl_st2, eldv,
  5714. aud_cntl_st, IBX_ELD_ADDRESS,
  5715. hdmiw_hdmiedid))
  5716. return;
  5717. i = I915_READ(aud_cntrl_st2);
  5718. i &= ~eldv;
  5719. I915_WRITE(aud_cntrl_st2, i);
  5720. if (!eld[0])
  5721. return;
  5722. i = I915_READ(aud_cntl_st);
  5723. i &= ~IBX_ELD_ADDRESS;
  5724. I915_WRITE(aud_cntl_st, i);
  5725. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5726. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5727. for (i = 0; i < len; i++)
  5728. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5729. i = I915_READ(aud_cntrl_st2);
  5730. i |= eldv;
  5731. I915_WRITE(aud_cntrl_st2, i);
  5732. }
  5733. void intel_write_eld(struct drm_encoder *encoder,
  5734. struct drm_display_mode *mode)
  5735. {
  5736. struct drm_crtc *crtc = encoder->crtc;
  5737. struct drm_connector *connector;
  5738. struct drm_device *dev = encoder->dev;
  5739. struct drm_i915_private *dev_priv = dev->dev_private;
  5740. connector = drm_select_eld(encoder, mode);
  5741. if (!connector)
  5742. return;
  5743. DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5744. connector->base.id,
  5745. drm_get_connector_name(connector),
  5746. connector->encoder->base.id,
  5747. drm_get_encoder_name(connector->encoder));
  5748. connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  5749. if (dev_priv->display.write_eld)
  5750. dev_priv->display.write_eld(connector, crtc);
  5751. }
  5752. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  5753. {
  5754. struct drm_device *dev = crtc->dev;
  5755. struct drm_i915_private *dev_priv = dev->dev_private;
  5756. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5757. bool visible = base != 0;
  5758. u32 cntl;
  5759. if (intel_crtc->cursor_visible == visible)
  5760. return;
  5761. cntl = I915_READ(_CURACNTR);
  5762. if (visible) {
  5763. /* On these chipsets we can only modify the base whilst
  5764. * the cursor is disabled.
  5765. */
  5766. I915_WRITE(_CURABASE, base);
  5767. cntl &= ~(CURSOR_FORMAT_MASK);
  5768. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  5769. cntl |= CURSOR_ENABLE |
  5770. CURSOR_GAMMA_ENABLE |
  5771. CURSOR_FORMAT_ARGB;
  5772. } else
  5773. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  5774. I915_WRITE(_CURACNTR, cntl);
  5775. intel_crtc->cursor_visible = visible;
  5776. }
  5777. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  5778. {
  5779. struct drm_device *dev = crtc->dev;
  5780. struct drm_i915_private *dev_priv = dev->dev_private;
  5781. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5782. int pipe = intel_crtc->pipe;
  5783. bool visible = base != 0;
  5784. if (intel_crtc->cursor_visible != visible) {
  5785. uint32_t cntl = I915_READ(CURCNTR(pipe));
  5786. if (base) {
  5787. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  5788. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5789. cntl |= pipe << 28; /* Connect to correct pipe */
  5790. } else {
  5791. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5792. cntl |= CURSOR_MODE_DISABLE;
  5793. }
  5794. I915_WRITE(CURCNTR(pipe), cntl);
  5795. intel_crtc->cursor_visible = visible;
  5796. }
  5797. /* and commit changes on next vblank */
  5798. I915_WRITE(CURBASE(pipe), base);
  5799. }
  5800. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  5801. {
  5802. struct drm_device *dev = crtc->dev;
  5803. struct drm_i915_private *dev_priv = dev->dev_private;
  5804. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5805. int pipe = intel_crtc->pipe;
  5806. bool visible = base != 0;
  5807. if (intel_crtc->cursor_visible != visible) {
  5808. uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  5809. if (base) {
  5810. cntl &= ~CURSOR_MODE;
  5811. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5812. } else {
  5813. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5814. cntl |= CURSOR_MODE_DISABLE;
  5815. }
  5816. if (IS_HASWELL(dev)) {
  5817. cntl |= CURSOR_PIPE_CSC_ENABLE;
  5818. cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
  5819. }
  5820. I915_WRITE(CURCNTR_IVB(pipe), cntl);
  5821. intel_crtc->cursor_visible = visible;
  5822. }
  5823. /* and commit changes on next vblank */
  5824. I915_WRITE(CURBASE_IVB(pipe), base);
  5825. }
  5826. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  5827. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  5828. bool on)
  5829. {
  5830. struct drm_device *dev = crtc->dev;
  5831. struct drm_i915_private *dev_priv = dev->dev_private;
  5832. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5833. int pipe = intel_crtc->pipe;
  5834. int x = intel_crtc->cursor_x;
  5835. int y = intel_crtc->cursor_y;
  5836. u32 base = 0, pos = 0;
  5837. bool visible;
  5838. if (on)
  5839. base = intel_crtc->cursor_addr;
  5840. if (x >= intel_crtc->config.pipe_src_w)
  5841. base = 0;
  5842. if (y >= intel_crtc->config.pipe_src_h)
  5843. base = 0;
  5844. if (x < 0) {
  5845. if (x + intel_crtc->cursor_width <= 0)
  5846. base = 0;
  5847. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  5848. x = -x;
  5849. }
  5850. pos |= x << CURSOR_X_SHIFT;
  5851. if (y < 0) {
  5852. if (y + intel_crtc->cursor_height <= 0)
  5853. base = 0;
  5854. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  5855. y = -y;
  5856. }
  5857. pos |= y << CURSOR_Y_SHIFT;
  5858. visible = base != 0;
  5859. if (!visible && !intel_crtc->cursor_visible)
  5860. return;
  5861. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  5862. I915_WRITE(CURPOS_IVB(pipe), pos);
  5863. ivb_update_cursor(crtc, base);
  5864. } else {
  5865. I915_WRITE(CURPOS(pipe), pos);
  5866. if (IS_845G(dev) || IS_I865G(dev))
  5867. i845_update_cursor(crtc, base);
  5868. else
  5869. i9xx_update_cursor(crtc, base);
  5870. }
  5871. }
  5872. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  5873. struct drm_file *file,
  5874. uint32_t handle,
  5875. uint32_t width, uint32_t height)
  5876. {
  5877. struct drm_device *dev = crtc->dev;
  5878. struct drm_i915_private *dev_priv = dev->dev_private;
  5879. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5880. struct drm_i915_gem_object *obj;
  5881. uint32_t addr;
  5882. int ret;
  5883. /* if we want to turn off the cursor ignore width and height */
  5884. if (!handle) {
  5885. DRM_DEBUG_KMS("cursor off\n");
  5886. addr = 0;
  5887. obj = NULL;
  5888. mutex_lock(&dev->struct_mutex);
  5889. goto finish;
  5890. }
  5891. /* Currently we only support 64x64 cursors */
  5892. if (width != 64 || height != 64) {
  5893. DRM_ERROR("we currently only support 64x64 cursors\n");
  5894. return -EINVAL;
  5895. }
  5896. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  5897. if (&obj->base == NULL)
  5898. return -ENOENT;
  5899. if (obj->base.size < width * height * 4) {
  5900. DRM_ERROR("buffer is to small\n");
  5901. ret = -ENOMEM;
  5902. goto fail;
  5903. }
  5904. /* we only need to pin inside GTT if cursor is non-phy */
  5905. mutex_lock(&dev->struct_mutex);
  5906. if (!dev_priv->info->cursor_needs_physical) {
  5907. unsigned alignment;
  5908. if (obj->tiling_mode) {
  5909. DRM_ERROR("cursor cannot be tiled\n");
  5910. ret = -EINVAL;
  5911. goto fail_locked;
  5912. }
  5913. /* Note that the w/a also requires 2 PTE of padding following
  5914. * the bo. We currently fill all unused PTE with the shadow
  5915. * page and so we should always have valid PTE following the
  5916. * cursor preventing the VT-d warning.
  5917. */
  5918. alignment = 0;
  5919. if (need_vtd_wa(dev))
  5920. alignment = 64*1024;
  5921. ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
  5922. if (ret) {
  5923. DRM_ERROR("failed to move cursor bo into the GTT\n");
  5924. goto fail_locked;
  5925. }
  5926. ret = i915_gem_object_put_fence(obj);
  5927. if (ret) {
  5928. DRM_ERROR("failed to release fence for cursor");
  5929. goto fail_unpin;
  5930. }
  5931. addr = i915_gem_obj_ggtt_offset(obj);
  5932. } else {
  5933. int align = IS_I830(dev) ? 16 * 1024 : 256;
  5934. ret = i915_gem_attach_phys_object(dev, obj,
  5935. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  5936. align);
  5937. if (ret) {
  5938. DRM_ERROR("failed to attach phys object\n");
  5939. goto fail_locked;
  5940. }
  5941. addr = obj->phys_obj->handle->busaddr;
  5942. }
  5943. if (IS_GEN2(dev))
  5944. I915_WRITE(CURSIZE, (height << 12) | width);
  5945. finish:
  5946. if (intel_crtc->cursor_bo) {
  5947. if (dev_priv->info->cursor_needs_physical) {
  5948. if (intel_crtc->cursor_bo != obj)
  5949. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  5950. } else
  5951. i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
  5952. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  5953. }
  5954. mutex_unlock(&dev->struct_mutex);
  5955. intel_crtc->cursor_addr = addr;
  5956. intel_crtc->cursor_bo = obj;
  5957. intel_crtc->cursor_width = width;
  5958. intel_crtc->cursor_height = height;
  5959. if (intel_crtc->active)
  5960. intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  5961. return 0;
  5962. fail_unpin:
  5963. i915_gem_object_unpin_from_display_plane(obj);
  5964. fail_locked:
  5965. mutex_unlock(&dev->struct_mutex);
  5966. fail:
  5967. drm_gem_object_unreference_unlocked(&obj->base);
  5968. return ret;
  5969. }
  5970. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  5971. {
  5972. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5973. intel_crtc->cursor_x = x;
  5974. intel_crtc->cursor_y = y;
  5975. if (intel_crtc->active)
  5976. intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  5977. return 0;
  5978. }
  5979. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  5980. u16 *blue, uint32_t start, uint32_t size)
  5981. {
  5982. int end = (start + size > 256) ? 256 : start + size, i;
  5983. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5984. for (i = start; i < end; i++) {
  5985. intel_crtc->lut_r[i] = red[i] >> 8;
  5986. intel_crtc->lut_g[i] = green[i] >> 8;
  5987. intel_crtc->lut_b[i] = blue[i] >> 8;
  5988. }
  5989. intel_crtc_load_lut(crtc);
  5990. }
  5991. /* VESA 640x480x72Hz mode to set on the pipe */
  5992. static struct drm_display_mode load_detect_mode = {
  5993. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  5994. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  5995. };
  5996. static struct drm_framebuffer *
  5997. intel_framebuffer_create(struct drm_device *dev,
  5998. struct drm_mode_fb_cmd2 *mode_cmd,
  5999. struct drm_i915_gem_object *obj)
  6000. {
  6001. struct intel_framebuffer *intel_fb;
  6002. int ret;
  6003. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  6004. if (!intel_fb) {
  6005. drm_gem_object_unreference_unlocked(&obj->base);
  6006. return ERR_PTR(-ENOMEM);
  6007. }
  6008. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  6009. if (ret) {
  6010. drm_gem_object_unreference_unlocked(&obj->base);
  6011. kfree(intel_fb);
  6012. return ERR_PTR(ret);
  6013. }
  6014. return &intel_fb->base;
  6015. }
  6016. static u32
  6017. intel_framebuffer_pitch_for_width(int width, int bpp)
  6018. {
  6019. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  6020. return ALIGN(pitch, 64);
  6021. }
  6022. static u32
  6023. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  6024. {
  6025. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  6026. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  6027. }
  6028. static struct drm_framebuffer *
  6029. intel_framebuffer_create_for_mode(struct drm_device *dev,
  6030. struct drm_display_mode *mode,
  6031. int depth, int bpp)
  6032. {
  6033. struct drm_i915_gem_object *obj;
  6034. struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  6035. obj = i915_gem_alloc_object(dev,
  6036. intel_framebuffer_size_for_mode(mode, bpp));
  6037. if (obj == NULL)
  6038. return ERR_PTR(-ENOMEM);
  6039. mode_cmd.width = mode->hdisplay;
  6040. mode_cmd.height = mode->vdisplay;
  6041. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  6042. bpp);
  6043. mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  6044. return intel_framebuffer_create(dev, &mode_cmd, obj);
  6045. }
  6046. static struct drm_framebuffer *
  6047. mode_fits_in_fbdev(struct drm_device *dev,
  6048. struct drm_display_mode *mode)
  6049. {
  6050. struct drm_i915_private *dev_priv = dev->dev_private;
  6051. struct drm_i915_gem_object *obj;
  6052. struct drm_framebuffer *fb;
  6053. if (dev_priv->fbdev == NULL)
  6054. return NULL;
  6055. obj = dev_priv->fbdev->ifb.obj;
  6056. if (obj == NULL)
  6057. return NULL;
  6058. fb = &dev_priv->fbdev->ifb.base;
  6059. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  6060. fb->bits_per_pixel))
  6061. return NULL;
  6062. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  6063. return NULL;
  6064. return fb;
  6065. }
  6066. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  6067. struct drm_display_mode *mode,
  6068. struct intel_load_detect_pipe *old)
  6069. {
  6070. struct intel_crtc *intel_crtc;
  6071. struct intel_encoder *intel_encoder =
  6072. intel_attached_encoder(connector);
  6073. struct drm_crtc *possible_crtc;
  6074. struct drm_encoder *encoder = &intel_encoder->base;
  6075. struct drm_crtc *crtc = NULL;
  6076. struct drm_device *dev = encoder->dev;
  6077. struct drm_framebuffer *fb;
  6078. int i = -1;
  6079. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  6080. connector->base.id, drm_get_connector_name(connector),
  6081. encoder->base.id, drm_get_encoder_name(encoder));
  6082. /*
  6083. * Algorithm gets a little messy:
  6084. *
  6085. * - if the connector already has an assigned crtc, use it (but make
  6086. * sure it's on first)
  6087. *
  6088. * - try to find the first unused crtc that can drive this connector,
  6089. * and use that if we find one
  6090. */
  6091. /* See if we already have a CRTC for this connector */
  6092. if (encoder->crtc) {
  6093. crtc = encoder->crtc;
  6094. mutex_lock(&crtc->mutex);
  6095. old->dpms_mode = connector->dpms;
  6096. old->load_detect_temp = false;
  6097. /* Make sure the crtc and connector are running */
  6098. if (connector->dpms != DRM_MODE_DPMS_ON)
  6099. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  6100. return true;
  6101. }
  6102. /* Find an unused one (if possible) */
  6103. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  6104. i++;
  6105. if (!(encoder->possible_crtcs & (1 << i)))
  6106. continue;
  6107. if (!possible_crtc->enabled) {
  6108. crtc = possible_crtc;
  6109. break;
  6110. }
  6111. }
  6112. /*
  6113. * If we didn't find an unused CRTC, don't use any.
  6114. */
  6115. if (!crtc) {
  6116. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  6117. return false;
  6118. }
  6119. mutex_lock(&crtc->mutex);
  6120. intel_encoder->new_crtc = to_intel_crtc(crtc);
  6121. to_intel_connector(connector)->new_encoder = intel_encoder;
  6122. intel_crtc = to_intel_crtc(crtc);
  6123. old->dpms_mode = connector->dpms;
  6124. old->load_detect_temp = true;
  6125. old->release_fb = NULL;
  6126. if (!mode)
  6127. mode = &load_detect_mode;
  6128. /* We need a framebuffer large enough to accommodate all accesses
  6129. * that the plane may generate whilst we perform load detection.
  6130. * We can not rely on the fbcon either being present (we get called
  6131. * during its initialisation to detect all boot displays, or it may
  6132. * not even exist) or that it is large enough to satisfy the
  6133. * requested mode.
  6134. */
  6135. fb = mode_fits_in_fbdev(dev, mode);
  6136. if (fb == NULL) {
  6137. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  6138. fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  6139. old->release_fb = fb;
  6140. } else
  6141. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  6142. if (IS_ERR(fb)) {
  6143. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  6144. mutex_unlock(&crtc->mutex);
  6145. return false;
  6146. }
  6147. if (intel_set_mode(crtc, mode, 0, 0, fb)) {
  6148. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  6149. if (old->release_fb)
  6150. old->release_fb->funcs->destroy(old->release_fb);
  6151. mutex_unlock(&crtc->mutex);
  6152. return false;
  6153. }
  6154. /* let the connector get through one full cycle before testing */
  6155. intel_wait_for_vblank(dev, intel_crtc->pipe);
  6156. return true;
  6157. }
  6158. void intel_release_load_detect_pipe(struct drm_connector *connector,
  6159. struct intel_load_detect_pipe *old)
  6160. {
  6161. struct intel_encoder *intel_encoder =
  6162. intel_attached_encoder(connector);
  6163. struct drm_encoder *encoder = &intel_encoder->base;
  6164. struct drm_crtc *crtc = encoder->crtc;
  6165. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  6166. connector->base.id, drm_get_connector_name(connector),
  6167. encoder->base.id, drm_get_encoder_name(encoder));
  6168. if (old->load_detect_temp) {
  6169. to_intel_connector(connector)->new_encoder = NULL;
  6170. intel_encoder->new_crtc = NULL;
  6171. intel_set_mode(crtc, NULL, 0, 0, NULL);
  6172. if (old->release_fb) {
  6173. drm_framebuffer_unregister_private(old->release_fb);
  6174. drm_framebuffer_unreference(old->release_fb);
  6175. }
  6176. mutex_unlock(&crtc->mutex);
  6177. return;
  6178. }
  6179. /* Switch crtc and encoder back off if necessary */
  6180. if (old->dpms_mode != DRM_MODE_DPMS_ON)
  6181. connector->funcs->dpms(connector, old->dpms_mode);
  6182. mutex_unlock(&crtc->mutex);
  6183. }
  6184. static int i9xx_pll_refclk(struct drm_device *dev,
  6185. const struct intel_crtc_config *pipe_config)
  6186. {
  6187. struct drm_i915_private *dev_priv = dev->dev_private;
  6188. u32 dpll = pipe_config->dpll_hw_state.dpll;
  6189. if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
  6190. return dev_priv->vbt.lvds_ssc_freq * 1000;
  6191. else if (HAS_PCH_SPLIT(dev))
  6192. return 120000;
  6193. else if (!IS_GEN2(dev))
  6194. return 96000;
  6195. else
  6196. return 48000;
  6197. }
  6198. /* Returns the clock of the currently programmed mode of the given pipe. */
  6199. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  6200. struct intel_crtc_config *pipe_config)
  6201. {
  6202. struct drm_device *dev = crtc->base.dev;
  6203. struct drm_i915_private *dev_priv = dev->dev_private;
  6204. int pipe = pipe_config->cpu_transcoder;
  6205. u32 dpll = pipe_config->dpll_hw_state.dpll;
  6206. u32 fp;
  6207. intel_clock_t clock;
  6208. int refclk = i9xx_pll_refclk(dev, pipe_config);
  6209. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  6210. fp = pipe_config->dpll_hw_state.fp0;
  6211. else
  6212. fp = pipe_config->dpll_hw_state.fp1;
  6213. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  6214. if (IS_PINEVIEW(dev)) {
  6215. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  6216. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  6217. } else {
  6218. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  6219. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  6220. }
  6221. if (!IS_GEN2(dev)) {
  6222. if (IS_PINEVIEW(dev))
  6223. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  6224. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  6225. else
  6226. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  6227. DPLL_FPA01_P1_POST_DIV_SHIFT);
  6228. switch (dpll & DPLL_MODE_MASK) {
  6229. case DPLLB_MODE_DAC_SERIAL:
  6230. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  6231. 5 : 10;
  6232. break;
  6233. case DPLLB_MODE_LVDS:
  6234. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  6235. 7 : 14;
  6236. break;
  6237. default:
  6238. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  6239. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  6240. return;
  6241. }
  6242. if (IS_PINEVIEW(dev))
  6243. pineview_clock(refclk, &clock);
  6244. else
  6245. i9xx_clock(refclk, &clock);
  6246. } else {
  6247. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  6248. if (is_lvds) {
  6249. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  6250. DPLL_FPA01_P1_POST_DIV_SHIFT);
  6251. clock.p2 = 14;
  6252. } else {
  6253. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  6254. clock.p1 = 2;
  6255. else {
  6256. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  6257. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  6258. }
  6259. if (dpll & PLL_P2_DIVIDE_BY_4)
  6260. clock.p2 = 4;
  6261. else
  6262. clock.p2 = 2;
  6263. }
  6264. i9xx_clock(refclk, &clock);
  6265. }
  6266. /*
  6267. * This value includes pixel_multiplier. We will use
  6268. * port_clock to compute adjusted_mode.clock in the
  6269. * encoder's get_config() function.
  6270. */
  6271. pipe_config->port_clock = clock.dot;
  6272. }
  6273. int intel_dotclock_calculate(int link_freq,
  6274. const struct intel_link_m_n *m_n)
  6275. {
  6276. /*
  6277. * The calculation for the data clock is:
  6278. * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
  6279. * But we want to avoid losing precison if possible, so:
  6280. * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
  6281. *
  6282. * and the link clock is simpler:
  6283. * link_clock = (m * link_clock) / n
  6284. */
  6285. if (!m_n->link_n)
  6286. return 0;
  6287. return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
  6288. }
  6289. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  6290. struct intel_crtc_config *pipe_config)
  6291. {
  6292. struct drm_device *dev = crtc->base.dev;
  6293. /* read out port_clock from the DPLL */
  6294. i9xx_crtc_clock_get(crtc, pipe_config);
  6295. /*
  6296. * This value does not include pixel_multiplier.
  6297. * We will check that port_clock and adjusted_mode.clock
  6298. * agree once we know their relationship in the encoder's
  6299. * get_config() function.
  6300. */
  6301. pipe_config->adjusted_mode.clock =
  6302. intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
  6303. &pipe_config->fdi_m_n);
  6304. }
  6305. /** Returns the currently programmed mode of the given pipe. */
  6306. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  6307. struct drm_crtc *crtc)
  6308. {
  6309. struct drm_i915_private *dev_priv = dev->dev_private;
  6310. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6311. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  6312. struct drm_display_mode *mode;
  6313. struct intel_crtc_config pipe_config;
  6314. int htot = I915_READ(HTOTAL(cpu_transcoder));
  6315. int hsync = I915_READ(HSYNC(cpu_transcoder));
  6316. int vtot = I915_READ(VTOTAL(cpu_transcoder));
  6317. int vsync = I915_READ(VSYNC(cpu_transcoder));
  6318. enum pipe pipe = intel_crtc->pipe;
  6319. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  6320. if (!mode)
  6321. return NULL;
  6322. /*
  6323. * Construct a pipe_config sufficient for getting the clock info
  6324. * back out of crtc_clock_get.
  6325. *
  6326. * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
  6327. * to use a real value here instead.
  6328. */
  6329. pipe_config.cpu_transcoder = (enum transcoder) pipe;
  6330. pipe_config.pixel_multiplier = 1;
  6331. pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
  6332. pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
  6333. pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
  6334. i9xx_crtc_clock_get(intel_crtc, &pipe_config);
  6335. mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
  6336. mode->hdisplay = (htot & 0xffff) + 1;
  6337. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  6338. mode->hsync_start = (hsync & 0xffff) + 1;
  6339. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  6340. mode->vdisplay = (vtot & 0xffff) + 1;
  6341. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  6342. mode->vsync_start = (vsync & 0xffff) + 1;
  6343. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  6344. drm_mode_set_name(mode);
  6345. return mode;
  6346. }
  6347. static void intel_increase_pllclock(struct drm_crtc *crtc)
  6348. {
  6349. struct drm_device *dev = crtc->dev;
  6350. drm_i915_private_t *dev_priv = dev->dev_private;
  6351. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6352. int pipe = intel_crtc->pipe;
  6353. int dpll_reg = DPLL(pipe);
  6354. int dpll;
  6355. if (HAS_PCH_SPLIT(dev))
  6356. return;
  6357. if (!dev_priv->lvds_downclock_avail)
  6358. return;
  6359. dpll = I915_READ(dpll_reg);
  6360. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  6361. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  6362. assert_panel_unlocked(dev_priv, pipe);
  6363. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  6364. I915_WRITE(dpll_reg, dpll);
  6365. intel_wait_for_vblank(dev, pipe);
  6366. dpll = I915_READ(dpll_reg);
  6367. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  6368. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  6369. }
  6370. }
  6371. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  6372. {
  6373. struct drm_device *dev = crtc->dev;
  6374. drm_i915_private_t *dev_priv = dev->dev_private;
  6375. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6376. if (HAS_PCH_SPLIT(dev))
  6377. return;
  6378. if (!dev_priv->lvds_downclock_avail)
  6379. return;
  6380. /*
  6381. * Since this is called by a timer, we should never get here in
  6382. * the manual case.
  6383. */
  6384. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  6385. int pipe = intel_crtc->pipe;
  6386. int dpll_reg = DPLL(pipe);
  6387. int dpll;
  6388. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  6389. assert_panel_unlocked(dev_priv, pipe);
  6390. dpll = I915_READ(dpll_reg);
  6391. dpll |= DISPLAY_RATE_SELECT_FPA1;
  6392. I915_WRITE(dpll_reg, dpll);
  6393. intel_wait_for_vblank(dev, pipe);
  6394. dpll = I915_READ(dpll_reg);
  6395. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  6396. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  6397. }
  6398. }
  6399. void intel_mark_busy(struct drm_device *dev)
  6400. {
  6401. struct drm_i915_private *dev_priv = dev->dev_private;
  6402. hsw_package_c8_gpu_busy(dev_priv);
  6403. i915_update_gfx_val(dev_priv);
  6404. }
  6405. void intel_mark_idle(struct drm_device *dev)
  6406. {
  6407. struct drm_i915_private *dev_priv = dev->dev_private;
  6408. struct drm_crtc *crtc;
  6409. hsw_package_c8_gpu_idle(dev_priv);
  6410. if (!i915_powersave)
  6411. return;
  6412. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6413. if (!crtc->fb)
  6414. continue;
  6415. intel_decrease_pllclock(crtc);
  6416. }
  6417. }
  6418. void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
  6419. struct intel_ring_buffer *ring)
  6420. {
  6421. struct drm_device *dev = obj->base.dev;
  6422. struct drm_crtc *crtc;
  6423. if (!i915_powersave)
  6424. return;
  6425. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6426. if (!crtc->fb)
  6427. continue;
  6428. if (to_intel_framebuffer(crtc->fb)->obj != obj)
  6429. continue;
  6430. intel_increase_pllclock(crtc);
  6431. if (ring && intel_fbc_enabled(dev))
  6432. ring->fbc_dirty = true;
  6433. }
  6434. }
  6435. static void intel_crtc_destroy(struct drm_crtc *crtc)
  6436. {
  6437. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6438. struct drm_device *dev = crtc->dev;
  6439. struct intel_unpin_work *work;
  6440. unsigned long flags;
  6441. spin_lock_irqsave(&dev->event_lock, flags);
  6442. work = intel_crtc->unpin_work;
  6443. intel_crtc->unpin_work = NULL;
  6444. spin_unlock_irqrestore(&dev->event_lock, flags);
  6445. if (work) {
  6446. cancel_work_sync(&work->work);
  6447. kfree(work);
  6448. }
  6449. intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
  6450. drm_crtc_cleanup(crtc);
  6451. kfree(intel_crtc);
  6452. }
  6453. static void intel_unpin_work_fn(struct work_struct *__work)
  6454. {
  6455. struct intel_unpin_work *work =
  6456. container_of(__work, struct intel_unpin_work, work);
  6457. struct drm_device *dev = work->crtc->dev;
  6458. mutex_lock(&dev->struct_mutex);
  6459. intel_unpin_fb_obj(work->old_fb_obj);
  6460. drm_gem_object_unreference(&work->pending_flip_obj->base);
  6461. drm_gem_object_unreference(&work->old_fb_obj->base);
  6462. intel_update_fbc(dev);
  6463. mutex_unlock(&dev->struct_mutex);
  6464. BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
  6465. atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
  6466. kfree(work);
  6467. }
  6468. static void do_intel_finish_page_flip(struct drm_device *dev,
  6469. struct drm_crtc *crtc)
  6470. {
  6471. drm_i915_private_t *dev_priv = dev->dev_private;
  6472. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6473. struct intel_unpin_work *work;
  6474. unsigned long flags;
  6475. /* Ignore early vblank irqs */
  6476. if (intel_crtc == NULL)
  6477. return;
  6478. spin_lock_irqsave(&dev->event_lock, flags);
  6479. work = intel_crtc->unpin_work;
  6480. /* Ensure we don't miss a work->pending update ... */
  6481. smp_rmb();
  6482. if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  6483. spin_unlock_irqrestore(&dev->event_lock, flags);
  6484. return;
  6485. }
  6486. /* and that the unpin work is consistent wrt ->pending. */
  6487. smp_rmb();
  6488. intel_crtc->unpin_work = NULL;
  6489. if (work->event)
  6490. drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
  6491. drm_vblank_put(dev, intel_crtc->pipe);
  6492. spin_unlock_irqrestore(&dev->event_lock, flags);
  6493. wake_up_all(&dev_priv->pending_flip_queue);
  6494. queue_work(dev_priv->wq, &work->work);
  6495. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  6496. }
  6497. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  6498. {
  6499. drm_i915_private_t *dev_priv = dev->dev_private;
  6500. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  6501. do_intel_finish_page_flip(dev, crtc);
  6502. }
  6503. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  6504. {
  6505. drm_i915_private_t *dev_priv = dev->dev_private;
  6506. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  6507. do_intel_finish_page_flip(dev, crtc);
  6508. }
  6509. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  6510. {
  6511. drm_i915_private_t *dev_priv = dev->dev_private;
  6512. struct intel_crtc *intel_crtc =
  6513. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  6514. unsigned long flags;
  6515. /* NB: An MMIO update of the plane base pointer will also
  6516. * generate a page-flip completion irq, i.e. every modeset
  6517. * is also accompanied by a spurious intel_prepare_page_flip().
  6518. */
  6519. spin_lock_irqsave(&dev->event_lock, flags);
  6520. if (intel_crtc->unpin_work)
  6521. atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
  6522. spin_unlock_irqrestore(&dev->event_lock, flags);
  6523. }
  6524. inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
  6525. {
  6526. /* Ensure that the work item is consistent when activating it ... */
  6527. smp_wmb();
  6528. atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
  6529. /* and that it is marked active as soon as the irq could fire. */
  6530. smp_wmb();
  6531. }
  6532. static int intel_gen2_queue_flip(struct drm_device *dev,
  6533. struct drm_crtc *crtc,
  6534. struct drm_framebuffer *fb,
  6535. struct drm_i915_gem_object *obj,
  6536. uint32_t flags)
  6537. {
  6538. struct drm_i915_private *dev_priv = dev->dev_private;
  6539. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6540. u32 flip_mask;
  6541. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6542. int ret;
  6543. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6544. if (ret)
  6545. goto err;
  6546. ret = intel_ring_begin(ring, 6);
  6547. if (ret)
  6548. goto err_unpin;
  6549. /* Can't queue multiple flips, so wait for the previous
  6550. * one to finish before executing the next.
  6551. */
  6552. if (intel_crtc->plane)
  6553. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6554. else
  6555. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6556. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6557. intel_ring_emit(ring, MI_NOOP);
  6558. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6559. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6560. intel_ring_emit(ring, fb->pitches[0]);
  6561. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6562. intel_ring_emit(ring, 0); /* aux display base address, unused */
  6563. intel_mark_page_flip_active(intel_crtc);
  6564. __intel_ring_advance(ring);
  6565. return 0;
  6566. err_unpin:
  6567. intel_unpin_fb_obj(obj);
  6568. err:
  6569. return ret;
  6570. }
  6571. static int intel_gen3_queue_flip(struct drm_device *dev,
  6572. struct drm_crtc *crtc,
  6573. struct drm_framebuffer *fb,
  6574. struct drm_i915_gem_object *obj,
  6575. uint32_t flags)
  6576. {
  6577. struct drm_i915_private *dev_priv = dev->dev_private;
  6578. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6579. u32 flip_mask;
  6580. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6581. int ret;
  6582. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6583. if (ret)
  6584. goto err;
  6585. ret = intel_ring_begin(ring, 6);
  6586. if (ret)
  6587. goto err_unpin;
  6588. if (intel_crtc->plane)
  6589. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6590. else
  6591. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6592. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6593. intel_ring_emit(ring, MI_NOOP);
  6594. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  6595. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6596. intel_ring_emit(ring, fb->pitches[0]);
  6597. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6598. intel_ring_emit(ring, MI_NOOP);
  6599. intel_mark_page_flip_active(intel_crtc);
  6600. __intel_ring_advance(ring);
  6601. return 0;
  6602. err_unpin:
  6603. intel_unpin_fb_obj(obj);
  6604. err:
  6605. return ret;
  6606. }
  6607. static int intel_gen4_queue_flip(struct drm_device *dev,
  6608. struct drm_crtc *crtc,
  6609. struct drm_framebuffer *fb,
  6610. struct drm_i915_gem_object *obj,
  6611. uint32_t flags)
  6612. {
  6613. struct drm_i915_private *dev_priv = dev->dev_private;
  6614. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6615. uint32_t pf, pipesrc;
  6616. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6617. int ret;
  6618. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6619. if (ret)
  6620. goto err;
  6621. ret = intel_ring_begin(ring, 4);
  6622. if (ret)
  6623. goto err_unpin;
  6624. /* i965+ uses the linear or tiled offsets from the
  6625. * Display Registers (which do not change across a page-flip)
  6626. * so we need only reprogram the base address.
  6627. */
  6628. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6629. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6630. intel_ring_emit(ring, fb->pitches[0]);
  6631. intel_ring_emit(ring,
  6632. (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
  6633. obj->tiling_mode);
  6634. /* XXX Enabling the panel-fitter across page-flip is so far
  6635. * untested on non-native modes, so ignore it for now.
  6636. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  6637. */
  6638. pf = 0;
  6639. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6640. intel_ring_emit(ring, pf | pipesrc);
  6641. intel_mark_page_flip_active(intel_crtc);
  6642. __intel_ring_advance(ring);
  6643. return 0;
  6644. err_unpin:
  6645. intel_unpin_fb_obj(obj);
  6646. err:
  6647. return ret;
  6648. }
  6649. static int intel_gen6_queue_flip(struct drm_device *dev,
  6650. struct drm_crtc *crtc,
  6651. struct drm_framebuffer *fb,
  6652. struct drm_i915_gem_object *obj,
  6653. uint32_t flags)
  6654. {
  6655. struct drm_i915_private *dev_priv = dev->dev_private;
  6656. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6657. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6658. uint32_t pf, pipesrc;
  6659. int ret;
  6660. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6661. if (ret)
  6662. goto err;
  6663. ret = intel_ring_begin(ring, 4);
  6664. if (ret)
  6665. goto err_unpin;
  6666. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6667. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6668. intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  6669. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6670. /* Contrary to the suggestions in the documentation,
  6671. * "Enable Panel Fitter" does not seem to be required when page
  6672. * flipping with a non-native mode, and worse causes a normal
  6673. * modeset to fail.
  6674. * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  6675. */
  6676. pf = 0;
  6677. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6678. intel_ring_emit(ring, pf | pipesrc);
  6679. intel_mark_page_flip_active(intel_crtc);
  6680. __intel_ring_advance(ring);
  6681. return 0;
  6682. err_unpin:
  6683. intel_unpin_fb_obj(obj);
  6684. err:
  6685. return ret;
  6686. }
  6687. static int intel_gen7_queue_flip(struct drm_device *dev,
  6688. struct drm_crtc *crtc,
  6689. struct drm_framebuffer *fb,
  6690. struct drm_i915_gem_object *obj,
  6691. uint32_t flags)
  6692. {
  6693. struct drm_i915_private *dev_priv = dev->dev_private;
  6694. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6695. struct intel_ring_buffer *ring;
  6696. uint32_t plane_bit = 0;
  6697. int len, ret;
  6698. ring = obj->ring;
  6699. if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
  6700. ring = &dev_priv->ring[BCS];
  6701. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6702. if (ret)
  6703. goto err;
  6704. switch(intel_crtc->plane) {
  6705. case PLANE_A:
  6706. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  6707. break;
  6708. case PLANE_B:
  6709. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  6710. break;
  6711. case PLANE_C:
  6712. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  6713. break;
  6714. default:
  6715. WARN_ONCE(1, "unknown plane in flip command\n");
  6716. ret = -ENODEV;
  6717. goto err_unpin;
  6718. }
  6719. len = 4;
  6720. if (ring->id == RCS)
  6721. len += 6;
  6722. ret = intel_ring_begin(ring, len);
  6723. if (ret)
  6724. goto err_unpin;
  6725. /* Unmask the flip-done completion message. Note that the bspec says that
  6726. * we should do this for both the BCS and RCS, and that we must not unmask
  6727. * more than one flip event at any time (or ensure that one flip message
  6728. * can be sent by waiting for flip-done prior to queueing new flips).
  6729. * Experimentation says that BCS works despite DERRMR masking all
  6730. * flip-done completion events and that unmasking all planes at once
  6731. * for the RCS also doesn't appear to drop events. Setting the DERRMR
  6732. * to zero does lead to lockups within MI_DISPLAY_FLIP.
  6733. */
  6734. if (ring->id == RCS) {
  6735. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  6736. intel_ring_emit(ring, DERRMR);
  6737. intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
  6738. DERRMR_PIPEB_PRI_FLIP_DONE |
  6739. DERRMR_PIPEC_PRI_FLIP_DONE));
  6740. intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
  6741. intel_ring_emit(ring, DERRMR);
  6742. intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
  6743. }
  6744. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  6745. intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  6746. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6747. intel_ring_emit(ring, (MI_NOOP));
  6748. intel_mark_page_flip_active(intel_crtc);
  6749. __intel_ring_advance(ring);
  6750. return 0;
  6751. err_unpin:
  6752. intel_unpin_fb_obj(obj);
  6753. err:
  6754. return ret;
  6755. }
  6756. static int intel_default_queue_flip(struct drm_device *dev,
  6757. struct drm_crtc *crtc,
  6758. struct drm_framebuffer *fb,
  6759. struct drm_i915_gem_object *obj,
  6760. uint32_t flags)
  6761. {
  6762. return -ENODEV;
  6763. }
  6764. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  6765. struct drm_framebuffer *fb,
  6766. struct drm_pending_vblank_event *event,
  6767. uint32_t page_flip_flags)
  6768. {
  6769. struct drm_device *dev = crtc->dev;
  6770. struct drm_i915_private *dev_priv = dev->dev_private;
  6771. struct drm_framebuffer *old_fb = crtc->fb;
  6772. struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
  6773. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6774. struct intel_unpin_work *work;
  6775. unsigned long flags;
  6776. int ret;
  6777. /* Can't change pixel format via MI display flips. */
  6778. if (fb->pixel_format != crtc->fb->pixel_format)
  6779. return -EINVAL;
  6780. /*
  6781. * TILEOFF/LINOFF registers can't be changed via MI display flips.
  6782. * Note that pitch changes could also affect these register.
  6783. */
  6784. if (INTEL_INFO(dev)->gen > 3 &&
  6785. (fb->offsets[0] != crtc->fb->offsets[0] ||
  6786. fb->pitches[0] != crtc->fb->pitches[0]))
  6787. return -EINVAL;
  6788. work = kzalloc(sizeof(*work), GFP_KERNEL);
  6789. if (work == NULL)
  6790. return -ENOMEM;
  6791. work->event = event;
  6792. work->crtc = crtc;
  6793. work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
  6794. INIT_WORK(&work->work, intel_unpin_work_fn);
  6795. ret = drm_vblank_get(dev, intel_crtc->pipe);
  6796. if (ret)
  6797. goto free_work;
  6798. /* We borrow the event spin lock for protecting unpin_work */
  6799. spin_lock_irqsave(&dev->event_lock, flags);
  6800. if (intel_crtc->unpin_work) {
  6801. spin_unlock_irqrestore(&dev->event_lock, flags);
  6802. kfree(work);
  6803. drm_vblank_put(dev, intel_crtc->pipe);
  6804. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  6805. return -EBUSY;
  6806. }
  6807. intel_crtc->unpin_work = work;
  6808. spin_unlock_irqrestore(&dev->event_lock, flags);
  6809. if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
  6810. flush_workqueue(dev_priv->wq);
  6811. ret = i915_mutex_lock_interruptible(dev);
  6812. if (ret)
  6813. goto cleanup;
  6814. /* Reference the objects for the scheduled work. */
  6815. drm_gem_object_reference(&work->old_fb_obj->base);
  6816. drm_gem_object_reference(&obj->base);
  6817. crtc->fb = fb;
  6818. work->pending_flip_obj = obj;
  6819. work->enable_stall_check = true;
  6820. atomic_inc(&intel_crtc->unpin_work_count);
  6821. intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  6822. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
  6823. if (ret)
  6824. goto cleanup_pending;
  6825. intel_disable_fbc(dev);
  6826. intel_mark_fb_busy(obj, NULL);
  6827. mutex_unlock(&dev->struct_mutex);
  6828. trace_i915_flip_request(intel_crtc->plane, obj);
  6829. return 0;
  6830. cleanup_pending:
  6831. atomic_dec(&intel_crtc->unpin_work_count);
  6832. crtc->fb = old_fb;
  6833. drm_gem_object_unreference(&work->old_fb_obj->base);
  6834. drm_gem_object_unreference(&obj->base);
  6835. mutex_unlock(&dev->struct_mutex);
  6836. cleanup:
  6837. spin_lock_irqsave(&dev->event_lock, flags);
  6838. intel_crtc->unpin_work = NULL;
  6839. spin_unlock_irqrestore(&dev->event_lock, flags);
  6840. drm_vblank_put(dev, intel_crtc->pipe);
  6841. free_work:
  6842. kfree(work);
  6843. return ret;
  6844. }
  6845. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  6846. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  6847. .load_lut = intel_crtc_load_lut,
  6848. };
  6849. static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
  6850. struct drm_crtc *crtc)
  6851. {
  6852. struct drm_device *dev;
  6853. struct drm_crtc *tmp;
  6854. int crtc_mask = 1;
  6855. WARN(!crtc, "checking null crtc?\n");
  6856. dev = crtc->dev;
  6857. list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
  6858. if (tmp == crtc)
  6859. break;
  6860. crtc_mask <<= 1;
  6861. }
  6862. if (encoder->possible_crtcs & crtc_mask)
  6863. return true;
  6864. return false;
  6865. }
  6866. /**
  6867. * intel_modeset_update_staged_output_state
  6868. *
  6869. * Updates the staged output configuration state, e.g. after we've read out the
  6870. * current hw state.
  6871. */
  6872. static void intel_modeset_update_staged_output_state(struct drm_device *dev)
  6873. {
  6874. struct intel_encoder *encoder;
  6875. struct intel_connector *connector;
  6876. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6877. base.head) {
  6878. connector->new_encoder =
  6879. to_intel_encoder(connector->base.encoder);
  6880. }
  6881. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6882. base.head) {
  6883. encoder->new_crtc =
  6884. to_intel_crtc(encoder->base.crtc);
  6885. }
  6886. }
  6887. /**
  6888. * intel_modeset_commit_output_state
  6889. *
  6890. * This function copies the stage display pipe configuration to the real one.
  6891. */
  6892. static void intel_modeset_commit_output_state(struct drm_device *dev)
  6893. {
  6894. struct intel_encoder *encoder;
  6895. struct intel_connector *connector;
  6896. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6897. base.head) {
  6898. connector->base.encoder = &connector->new_encoder->base;
  6899. }
  6900. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6901. base.head) {
  6902. encoder->base.crtc = &encoder->new_crtc->base;
  6903. }
  6904. }
  6905. static void
  6906. connected_sink_compute_bpp(struct intel_connector * connector,
  6907. struct intel_crtc_config *pipe_config)
  6908. {
  6909. int bpp = pipe_config->pipe_bpp;
  6910. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
  6911. connector->base.base.id,
  6912. drm_get_connector_name(&connector->base));
  6913. /* Don't use an invalid EDID bpc value */
  6914. if (connector->base.display_info.bpc &&
  6915. connector->base.display_info.bpc * 3 < bpp) {
  6916. DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
  6917. bpp, connector->base.display_info.bpc*3);
  6918. pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
  6919. }
  6920. /* Clamp bpp to 8 on screens without EDID 1.4 */
  6921. if (connector->base.display_info.bpc == 0 && bpp > 24) {
  6922. DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
  6923. bpp);
  6924. pipe_config->pipe_bpp = 24;
  6925. }
  6926. }
  6927. static int
  6928. compute_baseline_pipe_bpp(struct intel_crtc *crtc,
  6929. struct drm_framebuffer *fb,
  6930. struct intel_crtc_config *pipe_config)
  6931. {
  6932. struct drm_device *dev = crtc->base.dev;
  6933. struct intel_connector *connector;
  6934. int bpp;
  6935. switch (fb->pixel_format) {
  6936. case DRM_FORMAT_C8:
  6937. bpp = 8*3; /* since we go through a colormap */
  6938. break;
  6939. case DRM_FORMAT_XRGB1555:
  6940. case DRM_FORMAT_ARGB1555:
  6941. /* checked in intel_framebuffer_init already */
  6942. if (WARN_ON(INTEL_INFO(dev)->gen > 3))
  6943. return -EINVAL;
  6944. case DRM_FORMAT_RGB565:
  6945. bpp = 6*3; /* min is 18bpp */
  6946. break;
  6947. case DRM_FORMAT_XBGR8888:
  6948. case DRM_FORMAT_ABGR8888:
  6949. /* checked in intel_framebuffer_init already */
  6950. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  6951. return -EINVAL;
  6952. case DRM_FORMAT_XRGB8888:
  6953. case DRM_FORMAT_ARGB8888:
  6954. bpp = 8*3;
  6955. break;
  6956. case DRM_FORMAT_XRGB2101010:
  6957. case DRM_FORMAT_ARGB2101010:
  6958. case DRM_FORMAT_XBGR2101010:
  6959. case DRM_FORMAT_ABGR2101010:
  6960. /* checked in intel_framebuffer_init already */
  6961. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  6962. return -EINVAL;
  6963. bpp = 10*3;
  6964. break;
  6965. /* TODO: gen4+ supports 16 bpc floating point, too. */
  6966. default:
  6967. DRM_DEBUG_KMS("unsupported depth\n");
  6968. return -EINVAL;
  6969. }
  6970. pipe_config->pipe_bpp = bpp;
  6971. /* Clamp display bpp to EDID value */
  6972. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6973. base.head) {
  6974. if (!connector->new_encoder ||
  6975. connector->new_encoder->new_crtc != crtc)
  6976. continue;
  6977. connected_sink_compute_bpp(connector, pipe_config);
  6978. }
  6979. return bpp;
  6980. }
  6981. static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
  6982. {
  6983. DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
  6984. "type: 0x%x flags: 0x%x\n",
  6985. mode->clock,
  6986. mode->crtc_hdisplay, mode->crtc_hsync_start,
  6987. mode->crtc_hsync_end, mode->crtc_htotal,
  6988. mode->crtc_vdisplay, mode->crtc_vsync_start,
  6989. mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
  6990. }
  6991. static void intel_dump_pipe_config(struct intel_crtc *crtc,
  6992. struct intel_crtc_config *pipe_config,
  6993. const char *context)
  6994. {
  6995. DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
  6996. context, pipe_name(crtc->pipe));
  6997. DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
  6998. DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
  6999. pipe_config->pipe_bpp, pipe_config->dither);
  7000. DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  7001. pipe_config->has_pch_encoder,
  7002. pipe_config->fdi_lanes,
  7003. pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
  7004. pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
  7005. pipe_config->fdi_m_n.tu);
  7006. DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  7007. pipe_config->has_dp_encoder,
  7008. pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
  7009. pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
  7010. pipe_config->dp_m_n.tu);
  7011. DRM_DEBUG_KMS("requested mode:\n");
  7012. drm_mode_debug_printmodeline(&pipe_config->requested_mode);
  7013. DRM_DEBUG_KMS("adjusted mode:\n");
  7014. drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
  7015. intel_dump_crtc_timings(&pipe_config->adjusted_mode);
  7016. DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
  7017. DRM_DEBUG_KMS("pipe src size: %dx%d\n",
  7018. pipe_config->pipe_src_w, pipe_config->pipe_src_h);
  7019. DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
  7020. pipe_config->gmch_pfit.control,
  7021. pipe_config->gmch_pfit.pgm_ratios,
  7022. pipe_config->gmch_pfit.lvds_border_bits);
  7023. DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
  7024. pipe_config->pch_pfit.pos,
  7025. pipe_config->pch_pfit.size,
  7026. pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
  7027. DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
  7028. DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
  7029. }
  7030. static bool check_encoder_cloning(struct drm_crtc *crtc)
  7031. {
  7032. int num_encoders = 0;
  7033. bool uncloneable_encoders = false;
  7034. struct intel_encoder *encoder;
  7035. list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
  7036. base.head) {
  7037. if (&encoder->new_crtc->base != crtc)
  7038. continue;
  7039. num_encoders++;
  7040. if (!encoder->cloneable)
  7041. uncloneable_encoders = true;
  7042. }
  7043. return !(num_encoders > 1 && uncloneable_encoders);
  7044. }
  7045. static struct intel_crtc_config *
  7046. intel_modeset_pipe_config(struct drm_crtc *crtc,
  7047. struct drm_framebuffer *fb,
  7048. struct drm_display_mode *mode)
  7049. {
  7050. struct drm_device *dev = crtc->dev;
  7051. struct intel_encoder *encoder;
  7052. struct intel_crtc_config *pipe_config;
  7053. int plane_bpp, ret = -EINVAL;
  7054. bool retry = true;
  7055. if (!check_encoder_cloning(crtc)) {
  7056. DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
  7057. return ERR_PTR(-EINVAL);
  7058. }
  7059. pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
  7060. if (!pipe_config)
  7061. return ERR_PTR(-ENOMEM);
  7062. drm_mode_copy(&pipe_config->adjusted_mode, mode);
  7063. drm_mode_copy(&pipe_config->requested_mode, mode);
  7064. pipe_config->pipe_src_w = mode->hdisplay;
  7065. pipe_config->pipe_src_h = mode->vdisplay;
  7066. pipe_config->cpu_transcoder =
  7067. (enum transcoder) to_intel_crtc(crtc)->pipe;
  7068. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  7069. /*
  7070. * Sanitize sync polarity flags based on requested ones. If neither
  7071. * positive or negative polarity is requested, treat this as meaning
  7072. * negative polarity.
  7073. */
  7074. if (!(pipe_config->adjusted_mode.flags &
  7075. (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
  7076. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
  7077. if (!(pipe_config->adjusted_mode.flags &
  7078. (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
  7079. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
  7080. /* Compute a starting value for pipe_config->pipe_bpp taking the source
  7081. * plane pixel format and any sink constraints into account. Returns the
  7082. * source plane bpp so that dithering can be selected on mismatches
  7083. * after encoders and crtc also have had their say. */
  7084. plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
  7085. fb, pipe_config);
  7086. if (plane_bpp < 0)
  7087. goto fail;
  7088. encoder_retry:
  7089. /* Ensure the port clock defaults are reset when retrying. */
  7090. pipe_config->port_clock = 0;
  7091. pipe_config->pixel_multiplier = 1;
  7092. /* Fill in default crtc timings, allow encoders to overwrite them. */
  7093. drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
  7094. /* Pass our mode to the connectors and the CRTC to give them a chance to
  7095. * adjust it according to limitations or connector properties, and also
  7096. * a chance to reject the mode entirely.
  7097. */
  7098. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7099. base.head) {
  7100. if (&encoder->new_crtc->base != crtc)
  7101. continue;
  7102. if (!(encoder->compute_config(encoder, pipe_config))) {
  7103. DRM_DEBUG_KMS("Encoder config failure\n");
  7104. goto fail;
  7105. }
  7106. }
  7107. /* Set default port clock if not overwritten by the encoder. Needs to be
  7108. * done afterwards in case the encoder adjusts the mode. */
  7109. if (!pipe_config->port_clock)
  7110. pipe_config->port_clock = pipe_config->adjusted_mode.clock *
  7111. pipe_config->pixel_multiplier;
  7112. ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
  7113. if (ret < 0) {
  7114. DRM_DEBUG_KMS("CRTC fixup failed\n");
  7115. goto fail;
  7116. }
  7117. if (ret == RETRY) {
  7118. if (WARN(!retry, "loop in pipe configuration computation\n")) {
  7119. ret = -EINVAL;
  7120. goto fail;
  7121. }
  7122. DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
  7123. retry = false;
  7124. goto encoder_retry;
  7125. }
  7126. pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
  7127. DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
  7128. plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
  7129. return pipe_config;
  7130. fail:
  7131. kfree(pipe_config);
  7132. return ERR_PTR(ret);
  7133. }
  7134. /* Computes which crtcs are affected and sets the relevant bits in the mask. For
  7135. * simplicity we use the crtc's pipe number (because it's easier to obtain). */
  7136. static void
  7137. intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
  7138. unsigned *prepare_pipes, unsigned *disable_pipes)
  7139. {
  7140. struct intel_crtc *intel_crtc;
  7141. struct drm_device *dev = crtc->dev;
  7142. struct intel_encoder *encoder;
  7143. struct intel_connector *connector;
  7144. struct drm_crtc *tmp_crtc;
  7145. *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
  7146. /* Check which crtcs have changed outputs connected to them, these need
  7147. * to be part of the prepare_pipes mask. We don't (yet) support global
  7148. * modeset across multiple crtcs, so modeset_pipes will only have one
  7149. * bit set at most. */
  7150. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7151. base.head) {
  7152. if (connector->base.encoder == &connector->new_encoder->base)
  7153. continue;
  7154. if (connector->base.encoder) {
  7155. tmp_crtc = connector->base.encoder->crtc;
  7156. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  7157. }
  7158. if (connector->new_encoder)
  7159. *prepare_pipes |=
  7160. 1 << connector->new_encoder->new_crtc->pipe;
  7161. }
  7162. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7163. base.head) {
  7164. if (encoder->base.crtc == &encoder->new_crtc->base)
  7165. continue;
  7166. if (encoder->base.crtc) {
  7167. tmp_crtc = encoder->base.crtc;
  7168. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  7169. }
  7170. if (encoder->new_crtc)
  7171. *prepare_pipes |= 1 << encoder->new_crtc->pipe;
  7172. }
  7173. /* Check for any pipes that will be fully disabled ... */
  7174. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  7175. base.head) {
  7176. bool used = false;
  7177. /* Don't try to disable disabled crtcs. */
  7178. if (!intel_crtc->base.enabled)
  7179. continue;
  7180. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7181. base.head) {
  7182. if (encoder->new_crtc == intel_crtc)
  7183. used = true;
  7184. }
  7185. if (!used)
  7186. *disable_pipes |= 1 << intel_crtc->pipe;
  7187. }
  7188. /* set_mode is also used to update properties on life display pipes. */
  7189. intel_crtc = to_intel_crtc(crtc);
  7190. if (crtc->enabled)
  7191. *prepare_pipes |= 1 << intel_crtc->pipe;
  7192. /*
  7193. * For simplicity do a full modeset on any pipe where the output routing
  7194. * changed. We could be more clever, but that would require us to be
  7195. * more careful with calling the relevant encoder->mode_set functions.
  7196. */
  7197. if (*prepare_pipes)
  7198. *modeset_pipes = *prepare_pipes;
  7199. /* ... and mask these out. */
  7200. *modeset_pipes &= ~(*disable_pipes);
  7201. *prepare_pipes &= ~(*disable_pipes);
  7202. /*
  7203. * HACK: We don't (yet) fully support global modesets. intel_set_config
  7204. * obies this rule, but the modeset restore mode of
  7205. * intel_modeset_setup_hw_state does not.
  7206. */
  7207. *modeset_pipes &= 1 << intel_crtc->pipe;
  7208. *prepare_pipes &= 1 << intel_crtc->pipe;
  7209. DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
  7210. *modeset_pipes, *prepare_pipes, *disable_pipes);
  7211. }
  7212. static bool intel_crtc_in_use(struct drm_crtc *crtc)
  7213. {
  7214. struct drm_encoder *encoder;
  7215. struct drm_device *dev = crtc->dev;
  7216. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
  7217. if (encoder->crtc == crtc)
  7218. return true;
  7219. return false;
  7220. }
  7221. static void
  7222. intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
  7223. {
  7224. struct intel_encoder *intel_encoder;
  7225. struct intel_crtc *intel_crtc;
  7226. struct drm_connector *connector;
  7227. list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
  7228. base.head) {
  7229. if (!intel_encoder->base.crtc)
  7230. continue;
  7231. intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
  7232. if (prepare_pipes & (1 << intel_crtc->pipe))
  7233. intel_encoder->connectors_active = false;
  7234. }
  7235. intel_modeset_commit_output_state(dev);
  7236. /* Update computed state. */
  7237. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  7238. base.head) {
  7239. intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
  7240. }
  7241. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  7242. if (!connector->encoder || !connector->encoder->crtc)
  7243. continue;
  7244. intel_crtc = to_intel_crtc(connector->encoder->crtc);
  7245. if (prepare_pipes & (1 << intel_crtc->pipe)) {
  7246. struct drm_property *dpms_property =
  7247. dev->mode_config.dpms_property;
  7248. connector->dpms = DRM_MODE_DPMS_ON;
  7249. drm_object_property_set_value(&connector->base,
  7250. dpms_property,
  7251. DRM_MODE_DPMS_ON);
  7252. intel_encoder = to_intel_encoder(connector->encoder);
  7253. intel_encoder->connectors_active = true;
  7254. }
  7255. }
  7256. }
  7257. static bool intel_fuzzy_clock_check(int clock1, int clock2)
  7258. {
  7259. int diff;
  7260. if (clock1 == clock2)
  7261. return true;
  7262. if (!clock1 || !clock2)
  7263. return false;
  7264. diff = abs(clock1 - clock2);
  7265. if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
  7266. return true;
  7267. return false;
  7268. }
  7269. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  7270. list_for_each_entry((intel_crtc), \
  7271. &(dev)->mode_config.crtc_list, \
  7272. base.head) \
  7273. if (mask & (1 <<(intel_crtc)->pipe))
  7274. static bool
  7275. intel_pipe_config_compare(struct drm_device *dev,
  7276. struct intel_crtc_config *current_config,
  7277. struct intel_crtc_config *pipe_config)
  7278. {
  7279. #define PIPE_CONF_CHECK_X(name) \
  7280. if (current_config->name != pipe_config->name) { \
  7281. DRM_ERROR("mismatch in " #name " " \
  7282. "(expected 0x%08x, found 0x%08x)\n", \
  7283. current_config->name, \
  7284. pipe_config->name); \
  7285. return false; \
  7286. }
  7287. #define PIPE_CONF_CHECK_I(name) \
  7288. if (current_config->name != pipe_config->name) { \
  7289. DRM_ERROR("mismatch in " #name " " \
  7290. "(expected %i, found %i)\n", \
  7291. current_config->name, \
  7292. pipe_config->name); \
  7293. return false; \
  7294. }
  7295. #define PIPE_CONF_CHECK_FLAGS(name, mask) \
  7296. if ((current_config->name ^ pipe_config->name) & (mask)) { \
  7297. DRM_ERROR("mismatch in " #name "(" #mask ") " \
  7298. "(expected %i, found %i)\n", \
  7299. current_config->name & (mask), \
  7300. pipe_config->name & (mask)); \
  7301. return false; \
  7302. }
  7303. #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
  7304. if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
  7305. DRM_ERROR("mismatch in " #name " " \
  7306. "(expected %i, found %i)\n", \
  7307. current_config->name, \
  7308. pipe_config->name); \
  7309. return false; \
  7310. }
  7311. #define PIPE_CONF_QUIRK(quirk) \
  7312. ((current_config->quirks | pipe_config->quirks) & (quirk))
  7313. PIPE_CONF_CHECK_I(cpu_transcoder);
  7314. PIPE_CONF_CHECK_I(has_pch_encoder);
  7315. PIPE_CONF_CHECK_I(fdi_lanes);
  7316. PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
  7317. PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
  7318. PIPE_CONF_CHECK_I(fdi_m_n.link_m);
  7319. PIPE_CONF_CHECK_I(fdi_m_n.link_n);
  7320. PIPE_CONF_CHECK_I(fdi_m_n.tu);
  7321. PIPE_CONF_CHECK_I(has_dp_encoder);
  7322. PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
  7323. PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
  7324. PIPE_CONF_CHECK_I(dp_m_n.link_m);
  7325. PIPE_CONF_CHECK_I(dp_m_n.link_n);
  7326. PIPE_CONF_CHECK_I(dp_m_n.tu);
  7327. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
  7328. PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
  7329. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
  7330. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
  7331. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
  7332. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
  7333. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
  7334. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
  7335. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
  7336. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
  7337. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
  7338. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
  7339. PIPE_CONF_CHECK_I(pixel_multiplier);
  7340. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7341. DRM_MODE_FLAG_INTERLACE);
  7342. if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
  7343. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7344. DRM_MODE_FLAG_PHSYNC);
  7345. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7346. DRM_MODE_FLAG_NHSYNC);
  7347. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7348. DRM_MODE_FLAG_PVSYNC);
  7349. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7350. DRM_MODE_FLAG_NVSYNC);
  7351. }
  7352. PIPE_CONF_CHECK_I(pipe_src_w);
  7353. PIPE_CONF_CHECK_I(pipe_src_h);
  7354. PIPE_CONF_CHECK_I(gmch_pfit.control);
  7355. /* pfit ratios are autocomputed by the hw on gen4+ */
  7356. if (INTEL_INFO(dev)->gen < 4)
  7357. PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
  7358. PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
  7359. PIPE_CONF_CHECK_I(pch_pfit.enabled);
  7360. if (current_config->pch_pfit.enabled) {
  7361. PIPE_CONF_CHECK_I(pch_pfit.pos);
  7362. PIPE_CONF_CHECK_I(pch_pfit.size);
  7363. }
  7364. PIPE_CONF_CHECK_I(ips_enabled);
  7365. PIPE_CONF_CHECK_I(double_wide);
  7366. PIPE_CONF_CHECK_I(shared_dpll);
  7367. PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
  7368. PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
  7369. PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
  7370. PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
  7371. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
  7372. PIPE_CONF_CHECK_I(pipe_bpp);
  7373. if (!IS_HASWELL(dev)) {
  7374. PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
  7375. PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
  7376. }
  7377. #undef PIPE_CONF_CHECK_X
  7378. #undef PIPE_CONF_CHECK_I
  7379. #undef PIPE_CONF_CHECK_FLAGS
  7380. #undef PIPE_CONF_CHECK_CLOCK_FUZZY
  7381. #undef PIPE_CONF_QUIRK
  7382. return true;
  7383. }
  7384. static void
  7385. check_connector_state(struct drm_device *dev)
  7386. {
  7387. struct intel_connector *connector;
  7388. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7389. base.head) {
  7390. /* This also checks the encoder/connector hw state with the
  7391. * ->get_hw_state callbacks. */
  7392. intel_connector_check_state(connector);
  7393. WARN(&connector->new_encoder->base != connector->base.encoder,
  7394. "connector's staged encoder doesn't match current encoder\n");
  7395. }
  7396. }
  7397. static void
  7398. check_encoder_state(struct drm_device *dev)
  7399. {
  7400. struct intel_encoder *encoder;
  7401. struct intel_connector *connector;
  7402. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7403. base.head) {
  7404. bool enabled = false;
  7405. bool active = false;
  7406. enum pipe pipe, tracked_pipe;
  7407. DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  7408. encoder->base.base.id,
  7409. drm_get_encoder_name(&encoder->base));
  7410. WARN(&encoder->new_crtc->base != encoder->base.crtc,
  7411. "encoder's stage crtc doesn't match current crtc\n");
  7412. WARN(encoder->connectors_active && !encoder->base.crtc,
  7413. "encoder's active_connectors set, but no crtc\n");
  7414. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7415. base.head) {
  7416. if (connector->base.encoder != &encoder->base)
  7417. continue;
  7418. enabled = true;
  7419. if (connector->base.dpms != DRM_MODE_DPMS_OFF)
  7420. active = true;
  7421. }
  7422. WARN(!!encoder->base.crtc != enabled,
  7423. "encoder's enabled state mismatch "
  7424. "(expected %i, found %i)\n",
  7425. !!encoder->base.crtc, enabled);
  7426. WARN(active && !encoder->base.crtc,
  7427. "active encoder with no crtc\n");
  7428. WARN(encoder->connectors_active != active,
  7429. "encoder's computed active state doesn't match tracked active state "
  7430. "(expected %i, found %i)\n", active, encoder->connectors_active);
  7431. active = encoder->get_hw_state(encoder, &pipe);
  7432. WARN(active != encoder->connectors_active,
  7433. "encoder's hw state doesn't match sw tracking "
  7434. "(expected %i, found %i)\n",
  7435. encoder->connectors_active, active);
  7436. if (!encoder->base.crtc)
  7437. continue;
  7438. tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  7439. WARN(active && pipe != tracked_pipe,
  7440. "active encoder's pipe doesn't match"
  7441. "(expected %i, found %i)\n",
  7442. tracked_pipe, pipe);
  7443. }
  7444. }
  7445. static void
  7446. check_crtc_state(struct drm_device *dev)
  7447. {
  7448. drm_i915_private_t *dev_priv = dev->dev_private;
  7449. struct intel_crtc *crtc;
  7450. struct intel_encoder *encoder;
  7451. struct intel_crtc_config pipe_config;
  7452. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  7453. base.head) {
  7454. bool enabled = false;
  7455. bool active = false;
  7456. memset(&pipe_config, 0, sizeof(pipe_config));
  7457. DRM_DEBUG_KMS("[CRTC:%d]\n",
  7458. crtc->base.base.id);
  7459. WARN(crtc->active && !crtc->base.enabled,
  7460. "active crtc, but not enabled in sw tracking\n");
  7461. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7462. base.head) {
  7463. if (encoder->base.crtc != &crtc->base)
  7464. continue;
  7465. enabled = true;
  7466. if (encoder->connectors_active)
  7467. active = true;
  7468. }
  7469. WARN(active != crtc->active,
  7470. "crtc's computed active state doesn't match tracked active state "
  7471. "(expected %i, found %i)\n", active, crtc->active);
  7472. WARN(enabled != crtc->base.enabled,
  7473. "crtc's computed enabled state doesn't match tracked enabled state "
  7474. "(expected %i, found %i)\n", enabled, crtc->base.enabled);
  7475. active = dev_priv->display.get_pipe_config(crtc,
  7476. &pipe_config);
  7477. /* hw state is inconsistent with the pipe A quirk */
  7478. if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  7479. active = crtc->active;
  7480. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7481. base.head) {
  7482. enum pipe pipe;
  7483. if (encoder->base.crtc != &crtc->base)
  7484. continue;
  7485. if (encoder->get_config &&
  7486. encoder->get_hw_state(encoder, &pipe))
  7487. encoder->get_config(encoder, &pipe_config);
  7488. }
  7489. WARN(crtc->active != active,
  7490. "crtc active state doesn't match with hw state "
  7491. "(expected %i, found %i)\n", crtc->active, active);
  7492. if (active &&
  7493. !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
  7494. WARN(1, "pipe state doesn't match!\n");
  7495. intel_dump_pipe_config(crtc, &pipe_config,
  7496. "[hw state]");
  7497. intel_dump_pipe_config(crtc, &crtc->config,
  7498. "[sw state]");
  7499. }
  7500. }
  7501. }
  7502. static void
  7503. check_shared_dpll_state(struct drm_device *dev)
  7504. {
  7505. drm_i915_private_t *dev_priv = dev->dev_private;
  7506. struct intel_crtc *crtc;
  7507. struct intel_dpll_hw_state dpll_hw_state;
  7508. int i;
  7509. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  7510. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  7511. int enabled_crtcs = 0, active_crtcs = 0;
  7512. bool active;
  7513. memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
  7514. DRM_DEBUG_KMS("%s\n", pll->name);
  7515. active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
  7516. WARN(pll->active > pll->refcount,
  7517. "more active pll users than references: %i vs %i\n",
  7518. pll->active, pll->refcount);
  7519. WARN(pll->active && !pll->on,
  7520. "pll in active use but not on in sw tracking\n");
  7521. WARN(pll->on && !pll->active,
  7522. "pll in on but not on in use in sw tracking\n");
  7523. WARN(pll->on != active,
  7524. "pll on state mismatch (expected %i, found %i)\n",
  7525. pll->on, active);
  7526. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  7527. base.head) {
  7528. if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
  7529. enabled_crtcs++;
  7530. if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  7531. active_crtcs++;
  7532. }
  7533. WARN(pll->active != active_crtcs,
  7534. "pll active crtcs mismatch (expected %i, found %i)\n",
  7535. pll->active, active_crtcs);
  7536. WARN(pll->refcount != enabled_crtcs,
  7537. "pll enabled crtcs mismatch (expected %i, found %i)\n",
  7538. pll->refcount, enabled_crtcs);
  7539. WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
  7540. sizeof(dpll_hw_state)),
  7541. "pll hw state mismatch\n");
  7542. }
  7543. }
  7544. void
  7545. intel_modeset_check_state(struct drm_device *dev)
  7546. {
  7547. check_connector_state(dev);
  7548. check_encoder_state(dev);
  7549. check_crtc_state(dev);
  7550. check_shared_dpll_state(dev);
  7551. }
  7552. void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
  7553. int dotclock)
  7554. {
  7555. /*
  7556. * FDI already provided one idea for the dotclock.
  7557. * Yell if the encoder disagrees.
  7558. */
  7559. WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
  7560. "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
  7561. pipe_config->adjusted_mode.clock, dotclock);
  7562. }
  7563. static int __intel_set_mode(struct drm_crtc *crtc,
  7564. struct drm_display_mode *mode,
  7565. int x, int y, struct drm_framebuffer *fb)
  7566. {
  7567. struct drm_device *dev = crtc->dev;
  7568. drm_i915_private_t *dev_priv = dev->dev_private;
  7569. struct drm_display_mode *saved_mode, *saved_hwmode;
  7570. struct intel_crtc_config *pipe_config = NULL;
  7571. struct intel_crtc *intel_crtc;
  7572. unsigned disable_pipes, prepare_pipes, modeset_pipes;
  7573. int ret = 0;
  7574. saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
  7575. if (!saved_mode)
  7576. return -ENOMEM;
  7577. saved_hwmode = saved_mode + 1;
  7578. intel_modeset_affected_pipes(crtc, &modeset_pipes,
  7579. &prepare_pipes, &disable_pipes);
  7580. *saved_hwmode = crtc->hwmode;
  7581. *saved_mode = crtc->mode;
  7582. /* Hack: Because we don't (yet) support global modeset on multiple
  7583. * crtcs, we don't keep track of the new mode for more than one crtc.
  7584. * Hence simply check whether any bit is set in modeset_pipes in all the
  7585. * pieces of code that are not yet converted to deal with mutliple crtcs
  7586. * changing their mode at the same time. */
  7587. if (modeset_pipes) {
  7588. pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
  7589. if (IS_ERR(pipe_config)) {
  7590. ret = PTR_ERR(pipe_config);
  7591. pipe_config = NULL;
  7592. goto out;
  7593. }
  7594. intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
  7595. "[modeset]");
  7596. }
  7597. for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
  7598. intel_crtc_disable(&intel_crtc->base);
  7599. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
  7600. if (intel_crtc->base.enabled)
  7601. dev_priv->display.crtc_disable(&intel_crtc->base);
  7602. }
  7603. /* crtc->mode is already used by the ->mode_set callbacks, hence we need
  7604. * to set it here already despite that we pass it down the callchain.
  7605. */
  7606. if (modeset_pipes) {
  7607. crtc->mode = *mode;
  7608. /* mode_set/enable/disable functions rely on a correct pipe
  7609. * config. */
  7610. to_intel_crtc(crtc)->config = *pipe_config;
  7611. }
  7612. /* Only after disabling all output pipelines that will be changed can we
  7613. * update the the output configuration. */
  7614. intel_modeset_update_state(dev, prepare_pipes);
  7615. if (dev_priv->display.modeset_global_resources)
  7616. dev_priv->display.modeset_global_resources(dev);
  7617. /* Set up the DPLL and any encoders state that needs to adjust or depend
  7618. * on the DPLL.
  7619. */
  7620. for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
  7621. ret = intel_crtc_mode_set(&intel_crtc->base,
  7622. x, y, fb);
  7623. if (ret)
  7624. goto done;
  7625. }
  7626. /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  7627. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
  7628. dev_priv->display.crtc_enable(&intel_crtc->base);
  7629. if (modeset_pipes) {
  7630. /* Store real post-adjustment hardware mode. */
  7631. crtc->hwmode = pipe_config->adjusted_mode;
  7632. /* Calculate and store various constants which
  7633. * are later needed by vblank and swap-completion
  7634. * timestamping. They are derived from true hwmode.
  7635. */
  7636. drm_calc_timestamping_constants(crtc);
  7637. }
  7638. /* FIXME: add subpixel order */
  7639. done:
  7640. if (ret && crtc->enabled) {
  7641. crtc->hwmode = *saved_hwmode;
  7642. crtc->mode = *saved_mode;
  7643. }
  7644. out:
  7645. kfree(pipe_config);
  7646. kfree(saved_mode);
  7647. return ret;
  7648. }
  7649. static int intel_set_mode(struct drm_crtc *crtc,
  7650. struct drm_display_mode *mode,
  7651. int x, int y, struct drm_framebuffer *fb)
  7652. {
  7653. int ret;
  7654. ret = __intel_set_mode(crtc, mode, x, y, fb);
  7655. if (ret == 0)
  7656. intel_modeset_check_state(crtc->dev);
  7657. return ret;
  7658. }
  7659. void intel_crtc_restore_mode(struct drm_crtc *crtc)
  7660. {
  7661. intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
  7662. }
  7663. #undef for_each_intel_crtc_masked
  7664. static void intel_set_config_free(struct intel_set_config *config)
  7665. {
  7666. if (!config)
  7667. return;
  7668. kfree(config->save_connector_encoders);
  7669. kfree(config->save_encoder_crtcs);
  7670. kfree(config);
  7671. }
  7672. static int intel_set_config_save_state(struct drm_device *dev,
  7673. struct intel_set_config *config)
  7674. {
  7675. struct drm_encoder *encoder;
  7676. struct drm_connector *connector;
  7677. int count;
  7678. config->save_encoder_crtcs =
  7679. kcalloc(dev->mode_config.num_encoder,
  7680. sizeof(struct drm_crtc *), GFP_KERNEL);
  7681. if (!config->save_encoder_crtcs)
  7682. return -ENOMEM;
  7683. config->save_connector_encoders =
  7684. kcalloc(dev->mode_config.num_connector,
  7685. sizeof(struct drm_encoder *), GFP_KERNEL);
  7686. if (!config->save_connector_encoders)
  7687. return -ENOMEM;
  7688. /* Copy data. Note that driver private data is not affected.
  7689. * Should anything bad happen only the expected state is
  7690. * restored, not the drivers personal bookkeeping.
  7691. */
  7692. count = 0;
  7693. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  7694. config->save_encoder_crtcs[count++] = encoder->crtc;
  7695. }
  7696. count = 0;
  7697. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  7698. config->save_connector_encoders[count++] = connector->encoder;
  7699. }
  7700. return 0;
  7701. }
  7702. static void intel_set_config_restore_state(struct drm_device *dev,
  7703. struct intel_set_config *config)
  7704. {
  7705. struct intel_encoder *encoder;
  7706. struct intel_connector *connector;
  7707. int count;
  7708. count = 0;
  7709. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  7710. encoder->new_crtc =
  7711. to_intel_crtc(config->save_encoder_crtcs[count++]);
  7712. }
  7713. count = 0;
  7714. list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
  7715. connector->new_encoder =
  7716. to_intel_encoder(config->save_connector_encoders[count++]);
  7717. }
  7718. }
  7719. static bool
  7720. is_crtc_connector_off(struct drm_mode_set *set)
  7721. {
  7722. int i;
  7723. if (set->num_connectors == 0)
  7724. return false;
  7725. if (WARN_ON(set->connectors == NULL))
  7726. return false;
  7727. for (i = 0; i < set->num_connectors; i++)
  7728. if (set->connectors[i]->encoder &&
  7729. set->connectors[i]->encoder->crtc == set->crtc &&
  7730. set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
  7731. return true;
  7732. return false;
  7733. }
  7734. static void
  7735. intel_set_config_compute_mode_changes(struct drm_mode_set *set,
  7736. struct intel_set_config *config)
  7737. {
  7738. /* We should be able to check here if the fb has the same properties
  7739. * and then just flip_or_move it */
  7740. if (is_crtc_connector_off(set)) {
  7741. config->mode_changed = true;
  7742. } else if (set->crtc->fb != set->fb) {
  7743. /* If we have no fb then treat it as a full mode set */
  7744. if (set->crtc->fb == NULL) {
  7745. struct intel_crtc *intel_crtc =
  7746. to_intel_crtc(set->crtc);
  7747. if (intel_crtc->active && i915_fastboot) {
  7748. DRM_DEBUG_KMS("crtc has no fb, will flip\n");
  7749. config->fb_changed = true;
  7750. } else {
  7751. DRM_DEBUG_KMS("inactive crtc, full mode set\n");
  7752. config->mode_changed = true;
  7753. }
  7754. } else if (set->fb == NULL) {
  7755. config->mode_changed = true;
  7756. } else if (set->fb->pixel_format !=
  7757. set->crtc->fb->pixel_format) {
  7758. config->mode_changed = true;
  7759. } else {
  7760. config->fb_changed = true;
  7761. }
  7762. }
  7763. if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
  7764. config->fb_changed = true;
  7765. if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
  7766. DRM_DEBUG_KMS("modes are different, full mode set\n");
  7767. drm_mode_debug_printmodeline(&set->crtc->mode);
  7768. drm_mode_debug_printmodeline(set->mode);
  7769. config->mode_changed = true;
  7770. }
  7771. DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
  7772. set->crtc->base.id, config->mode_changed, config->fb_changed);
  7773. }
  7774. static int
  7775. intel_modeset_stage_output_state(struct drm_device *dev,
  7776. struct drm_mode_set *set,
  7777. struct intel_set_config *config)
  7778. {
  7779. struct drm_crtc *new_crtc;
  7780. struct intel_connector *connector;
  7781. struct intel_encoder *encoder;
  7782. int ro;
  7783. /* The upper layers ensure that we either disable a crtc or have a list
  7784. * of connectors. For paranoia, double-check this. */
  7785. WARN_ON(!set->fb && (set->num_connectors != 0));
  7786. WARN_ON(set->fb && (set->num_connectors == 0));
  7787. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7788. base.head) {
  7789. /* Otherwise traverse passed in connector list and get encoders
  7790. * for them. */
  7791. for (ro = 0; ro < set->num_connectors; ro++) {
  7792. if (set->connectors[ro] == &connector->base) {
  7793. connector->new_encoder = connector->encoder;
  7794. break;
  7795. }
  7796. }
  7797. /* If we disable the crtc, disable all its connectors. Also, if
  7798. * the connector is on the changing crtc but not on the new
  7799. * connector list, disable it. */
  7800. if ((!set->fb || ro == set->num_connectors) &&
  7801. connector->base.encoder &&
  7802. connector->base.encoder->crtc == set->crtc) {
  7803. connector->new_encoder = NULL;
  7804. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
  7805. connector->base.base.id,
  7806. drm_get_connector_name(&connector->base));
  7807. }
  7808. if (&connector->new_encoder->base != connector->base.encoder) {
  7809. DRM_DEBUG_KMS("encoder changed, full mode switch\n");
  7810. config->mode_changed = true;
  7811. }
  7812. }
  7813. /* connector->new_encoder is now updated for all connectors. */
  7814. /* Update crtc of enabled connectors. */
  7815. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7816. base.head) {
  7817. if (!connector->new_encoder)
  7818. continue;
  7819. new_crtc = connector->new_encoder->base.crtc;
  7820. for (ro = 0; ro < set->num_connectors; ro++) {
  7821. if (set->connectors[ro] == &connector->base)
  7822. new_crtc = set->crtc;
  7823. }
  7824. /* Make sure the new CRTC will work with the encoder */
  7825. if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
  7826. new_crtc)) {
  7827. return -EINVAL;
  7828. }
  7829. connector->encoder->new_crtc = to_intel_crtc(new_crtc);
  7830. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
  7831. connector->base.base.id,
  7832. drm_get_connector_name(&connector->base),
  7833. new_crtc->base.id);
  7834. }
  7835. /* Check for any encoders that needs to be disabled. */
  7836. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7837. base.head) {
  7838. list_for_each_entry(connector,
  7839. &dev->mode_config.connector_list,
  7840. base.head) {
  7841. if (connector->new_encoder == encoder) {
  7842. WARN_ON(!connector->new_encoder->new_crtc);
  7843. goto next_encoder;
  7844. }
  7845. }
  7846. encoder->new_crtc = NULL;
  7847. next_encoder:
  7848. /* Only now check for crtc changes so we don't miss encoders
  7849. * that will be disabled. */
  7850. if (&encoder->new_crtc->base != encoder->base.crtc) {
  7851. DRM_DEBUG_KMS("crtc changed, full mode switch\n");
  7852. config->mode_changed = true;
  7853. }
  7854. }
  7855. /* Now we've also updated encoder->new_crtc for all encoders. */
  7856. return 0;
  7857. }
  7858. static int intel_crtc_set_config(struct drm_mode_set *set)
  7859. {
  7860. struct drm_device *dev;
  7861. struct drm_mode_set save_set;
  7862. struct intel_set_config *config;
  7863. int ret;
  7864. BUG_ON(!set);
  7865. BUG_ON(!set->crtc);
  7866. BUG_ON(!set->crtc->helper_private);
  7867. /* Enforce sane interface api - has been abused by the fb helper. */
  7868. BUG_ON(!set->mode && set->fb);
  7869. BUG_ON(set->fb && set->num_connectors == 0);
  7870. if (set->fb) {
  7871. DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
  7872. set->crtc->base.id, set->fb->base.id,
  7873. (int)set->num_connectors, set->x, set->y);
  7874. } else {
  7875. DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
  7876. }
  7877. dev = set->crtc->dev;
  7878. ret = -ENOMEM;
  7879. config = kzalloc(sizeof(*config), GFP_KERNEL);
  7880. if (!config)
  7881. goto out_config;
  7882. ret = intel_set_config_save_state(dev, config);
  7883. if (ret)
  7884. goto out_config;
  7885. save_set.crtc = set->crtc;
  7886. save_set.mode = &set->crtc->mode;
  7887. save_set.x = set->crtc->x;
  7888. save_set.y = set->crtc->y;
  7889. save_set.fb = set->crtc->fb;
  7890. /* Compute whether we need a full modeset, only an fb base update or no
  7891. * change at all. In the future we might also check whether only the
  7892. * mode changed, e.g. for LVDS where we only change the panel fitter in
  7893. * such cases. */
  7894. intel_set_config_compute_mode_changes(set, config);
  7895. ret = intel_modeset_stage_output_state(dev, set, config);
  7896. if (ret)
  7897. goto fail;
  7898. if (config->mode_changed) {
  7899. ret = intel_set_mode(set->crtc, set->mode,
  7900. set->x, set->y, set->fb);
  7901. } else if (config->fb_changed) {
  7902. intel_crtc_wait_for_pending_flips(set->crtc);
  7903. ret = intel_pipe_set_base(set->crtc,
  7904. set->x, set->y, set->fb);
  7905. }
  7906. if (ret) {
  7907. DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
  7908. set->crtc->base.id, ret);
  7909. fail:
  7910. intel_set_config_restore_state(dev, config);
  7911. /* Try to restore the config */
  7912. if (config->mode_changed &&
  7913. intel_set_mode(save_set.crtc, save_set.mode,
  7914. save_set.x, save_set.y, save_set.fb))
  7915. DRM_ERROR("failed to restore config after modeset failure\n");
  7916. }
  7917. out_config:
  7918. intel_set_config_free(config);
  7919. return ret;
  7920. }
  7921. static const struct drm_crtc_funcs intel_crtc_funcs = {
  7922. .cursor_set = intel_crtc_cursor_set,
  7923. .cursor_move = intel_crtc_cursor_move,
  7924. .gamma_set = intel_crtc_gamma_set,
  7925. .set_config = intel_crtc_set_config,
  7926. .destroy = intel_crtc_destroy,
  7927. .page_flip = intel_crtc_page_flip,
  7928. };
  7929. static void intel_cpu_pll_init(struct drm_device *dev)
  7930. {
  7931. if (HAS_DDI(dev))
  7932. intel_ddi_pll_init(dev);
  7933. }
  7934. static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
  7935. struct intel_shared_dpll *pll,
  7936. struct intel_dpll_hw_state *hw_state)
  7937. {
  7938. uint32_t val;
  7939. val = I915_READ(PCH_DPLL(pll->id));
  7940. hw_state->dpll = val;
  7941. hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
  7942. hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
  7943. return val & DPLL_VCO_ENABLE;
  7944. }
  7945. static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
  7946. struct intel_shared_dpll *pll)
  7947. {
  7948. I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
  7949. I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
  7950. }
  7951. static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
  7952. struct intel_shared_dpll *pll)
  7953. {
  7954. /* PCH refclock must be enabled first */
  7955. assert_pch_refclk_enabled(dev_priv);
  7956. I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  7957. /* Wait for the clocks to stabilize. */
  7958. POSTING_READ(PCH_DPLL(pll->id));
  7959. udelay(150);
  7960. /* The pixel multiplier can only be updated once the
  7961. * DPLL is enabled and the clocks are stable.
  7962. *
  7963. * So write it again.
  7964. */
  7965. I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  7966. POSTING_READ(PCH_DPLL(pll->id));
  7967. udelay(200);
  7968. }
  7969. static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
  7970. struct intel_shared_dpll *pll)
  7971. {
  7972. struct drm_device *dev = dev_priv->dev;
  7973. struct intel_crtc *crtc;
  7974. /* Make sure no transcoder isn't still depending on us. */
  7975. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  7976. if (intel_crtc_to_shared_dpll(crtc) == pll)
  7977. assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
  7978. }
  7979. I915_WRITE(PCH_DPLL(pll->id), 0);
  7980. POSTING_READ(PCH_DPLL(pll->id));
  7981. udelay(200);
  7982. }
  7983. static char *ibx_pch_dpll_names[] = {
  7984. "PCH DPLL A",
  7985. "PCH DPLL B",
  7986. };
  7987. static void ibx_pch_dpll_init(struct drm_device *dev)
  7988. {
  7989. struct drm_i915_private *dev_priv = dev->dev_private;
  7990. int i;
  7991. dev_priv->num_shared_dpll = 2;
  7992. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  7993. dev_priv->shared_dplls[i].id = i;
  7994. dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
  7995. dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
  7996. dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
  7997. dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
  7998. dev_priv->shared_dplls[i].get_hw_state =
  7999. ibx_pch_dpll_get_hw_state;
  8000. }
  8001. }
  8002. static void intel_shared_dpll_init(struct drm_device *dev)
  8003. {
  8004. struct drm_i915_private *dev_priv = dev->dev_private;
  8005. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  8006. ibx_pch_dpll_init(dev);
  8007. else
  8008. dev_priv->num_shared_dpll = 0;
  8009. BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
  8010. DRM_DEBUG_KMS("%i shared PLLs initialized\n",
  8011. dev_priv->num_shared_dpll);
  8012. }
  8013. static void intel_crtc_init(struct drm_device *dev, int pipe)
  8014. {
  8015. drm_i915_private_t *dev_priv = dev->dev_private;
  8016. struct intel_crtc *intel_crtc;
  8017. int i;
  8018. intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
  8019. if (intel_crtc == NULL)
  8020. return;
  8021. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  8022. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  8023. for (i = 0; i < 256; i++) {
  8024. intel_crtc->lut_r[i] = i;
  8025. intel_crtc->lut_g[i] = i;
  8026. intel_crtc->lut_b[i] = i;
  8027. }
  8028. /* Swap pipes & planes for FBC on pre-965 */
  8029. intel_crtc->pipe = pipe;
  8030. intel_crtc->plane = pipe;
  8031. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  8032. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  8033. intel_crtc->plane = !pipe;
  8034. }
  8035. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  8036. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  8037. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  8038. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  8039. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  8040. }
  8041. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  8042. struct drm_file *file)
  8043. {
  8044. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  8045. struct drm_mode_object *drmmode_obj;
  8046. struct intel_crtc *crtc;
  8047. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  8048. return -ENODEV;
  8049. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  8050. DRM_MODE_OBJECT_CRTC);
  8051. if (!drmmode_obj) {
  8052. DRM_ERROR("no such CRTC id\n");
  8053. return -EINVAL;
  8054. }
  8055. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  8056. pipe_from_crtc_id->pipe = crtc->pipe;
  8057. return 0;
  8058. }
  8059. static int intel_encoder_clones(struct intel_encoder *encoder)
  8060. {
  8061. struct drm_device *dev = encoder->base.dev;
  8062. struct intel_encoder *source_encoder;
  8063. int index_mask = 0;
  8064. int entry = 0;
  8065. list_for_each_entry(source_encoder,
  8066. &dev->mode_config.encoder_list, base.head) {
  8067. if (encoder == source_encoder)
  8068. index_mask |= (1 << entry);
  8069. /* Intel hw has only one MUX where enocoders could be cloned. */
  8070. if (encoder->cloneable && source_encoder->cloneable)
  8071. index_mask |= (1 << entry);
  8072. entry++;
  8073. }
  8074. return index_mask;
  8075. }
  8076. static bool has_edp_a(struct drm_device *dev)
  8077. {
  8078. struct drm_i915_private *dev_priv = dev->dev_private;
  8079. if (!IS_MOBILE(dev))
  8080. return false;
  8081. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  8082. return false;
  8083. if (IS_GEN5(dev) &&
  8084. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  8085. return false;
  8086. return true;
  8087. }
  8088. static void intel_setup_outputs(struct drm_device *dev)
  8089. {
  8090. struct drm_i915_private *dev_priv = dev->dev_private;
  8091. struct intel_encoder *encoder;
  8092. bool dpd_is_edp = false;
  8093. intel_lvds_init(dev);
  8094. if (!IS_ULT(dev))
  8095. intel_crt_init(dev);
  8096. if (HAS_DDI(dev)) {
  8097. int found;
  8098. /* Haswell uses DDI functions to detect digital outputs */
  8099. found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
  8100. /* DDI A only supports eDP */
  8101. if (found)
  8102. intel_ddi_init(dev, PORT_A);
  8103. /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  8104. * register */
  8105. found = I915_READ(SFUSE_STRAP);
  8106. if (found & SFUSE_STRAP_DDIB_DETECTED)
  8107. intel_ddi_init(dev, PORT_B);
  8108. if (found & SFUSE_STRAP_DDIC_DETECTED)
  8109. intel_ddi_init(dev, PORT_C);
  8110. if (found & SFUSE_STRAP_DDID_DETECTED)
  8111. intel_ddi_init(dev, PORT_D);
  8112. } else if (HAS_PCH_SPLIT(dev)) {
  8113. int found;
  8114. dpd_is_edp = intel_dpd_is_edp(dev);
  8115. if (has_edp_a(dev))
  8116. intel_dp_init(dev, DP_A, PORT_A);
  8117. if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
  8118. /* PCH SDVOB multiplex with HDMIB */
  8119. found = intel_sdvo_init(dev, PCH_SDVOB, true);
  8120. if (!found)
  8121. intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
  8122. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  8123. intel_dp_init(dev, PCH_DP_B, PORT_B);
  8124. }
  8125. if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
  8126. intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
  8127. if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
  8128. intel_hdmi_init(dev, PCH_HDMID, PORT_D);
  8129. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  8130. intel_dp_init(dev, PCH_DP_C, PORT_C);
  8131. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  8132. intel_dp_init(dev, PCH_DP_D, PORT_D);
  8133. } else if (IS_VALLEYVIEW(dev)) {
  8134. /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
  8135. if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
  8136. intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
  8137. PORT_C);
  8138. if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
  8139. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
  8140. PORT_C);
  8141. }
  8142. if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
  8143. intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
  8144. PORT_B);
  8145. if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
  8146. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
  8147. }
  8148. intel_dsi_init(dev);
  8149. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  8150. bool found = false;
  8151. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  8152. DRM_DEBUG_KMS("probing SDVOB\n");
  8153. found = intel_sdvo_init(dev, GEN3_SDVOB, true);
  8154. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  8155. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  8156. intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
  8157. }
  8158. if (!found && SUPPORTS_INTEGRATED_DP(dev))
  8159. intel_dp_init(dev, DP_B, PORT_B);
  8160. }
  8161. /* Before G4X SDVOC doesn't have its own detect register */
  8162. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  8163. DRM_DEBUG_KMS("probing SDVOC\n");
  8164. found = intel_sdvo_init(dev, GEN3_SDVOC, false);
  8165. }
  8166. if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
  8167. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  8168. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  8169. intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
  8170. }
  8171. if (SUPPORTS_INTEGRATED_DP(dev))
  8172. intel_dp_init(dev, DP_C, PORT_C);
  8173. }
  8174. if (SUPPORTS_INTEGRATED_DP(dev) &&
  8175. (I915_READ(DP_D) & DP_DETECTED))
  8176. intel_dp_init(dev, DP_D, PORT_D);
  8177. } else if (IS_GEN2(dev))
  8178. intel_dvo_init(dev);
  8179. if (SUPPORTS_TV(dev))
  8180. intel_tv_init(dev);
  8181. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  8182. encoder->base.possible_crtcs = encoder->crtc_mask;
  8183. encoder->base.possible_clones =
  8184. intel_encoder_clones(encoder);
  8185. }
  8186. intel_init_pch_refclk(dev);
  8187. drm_helper_move_panel_connectors_to_head(dev);
  8188. }
  8189. void intel_framebuffer_fini(struct intel_framebuffer *fb)
  8190. {
  8191. drm_framebuffer_cleanup(&fb->base);
  8192. drm_gem_object_unreference_unlocked(&fb->obj->base);
  8193. }
  8194. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  8195. {
  8196. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  8197. intel_framebuffer_fini(intel_fb);
  8198. kfree(intel_fb);
  8199. }
  8200. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  8201. struct drm_file *file,
  8202. unsigned int *handle)
  8203. {
  8204. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  8205. struct drm_i915_gem_object *obj = intel_fb->obj;
  8206. return drm_gem_handle_create(file, &obj->base, handle);
  8207. }
  8208. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  8209. .destroy = intel_user_framebuffer_destroy,
  8210. .create_handle = intel_user_framebuffer_create_handle,
  8211. };
  8212. int intel_framebuffer_init(struct drm_device *dev,
  8213. struct intel_framebuffer *intel_fb,
  8214. struct drm_mode_fb_cmd2 *mode_cmd,
  8215. struct drm_i915_gem_object *obj)
  8216. {
  8217. int pitch_limit;
  8218. int ret;
  8219. if (obj->tiling_mode == I915_TILING_Y) {
  8220. DRM_DEBUG("hardware does not support tiling Y\n");
  8221. return -EINVAL;
  8222. }
  8223. if (mode_cmd->pitches[0] & 63) {
  8224. DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
  8225. mode_cmd->pitches[0]);
  8226. return -EINVAL;
  8227. }
  8228. if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
  8229. pitch_limit = 32*1024;
  8230. } else if (INTEL_INFO(dev)->gen >= 4) {
  8231. if (obj->tiling_mode)
  8232. pitch_limit = 16*1024;
  8233. else
  8234. pitch_limit = 32*1024;
  8235. } else if (INTEL_INFO(dev)->gen >= 3) {
  8236. if (obj->tiling_mode)
  8237. pitch_limit = 8*1024;
  8238. else
  8239. pitch_limit = 16*1024;
  8240. } else
  8241. /* XXX DSPC is limited to 4k tiled */
  8242. pitch_limit = 8*1024;
  8243. if (mode_cmd->pitches[0] > pitch_limit) {
  8244. DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
  8245. obj->tiling_mode ? "tiled" : "linear",
  8246. mode_cmd->pitches[0], pitch_limit);
  8247. return -EINVAL;
  8248. }
  8249. if (obj->tiling_mode != I915_TILING_NONE &&
  8250. mode_cmd->pitches[0] != obj->stride) {
  8251. DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
  8252. mode_cmd->pitches[0], obj->stride);
  8253. return -EINVAL;
  8254. }
  8255. /* Reject formats not supported by any plane early. */
  8256. switch (mode_cmd->pixel_format) {
  8257. case DRM_FORMAT_C8:
  8258. case DRM_FORMAT_RGB565:
  8259. case DRM_FORMAT_XRGB8888:
  8260. case DRM_FORMAT_ARGB8888:
  8261. break;
  8262. case DRM_FORMAT_XRGB1555:
  8263. case DRM_FORMAT_ARGB1555:
  8264. if (INTEL_INFO(dev)->gen > 3) {
  8265. DRM_DEBUG("unsupported pixel format: %s\n",
  8266. drm_get_format_name(mode_cmd->pixel_format));
  8267. return -EINVAL;
  8268. }
  8269. break;
  8270. case DRM_FORMAT_XBGR8888:
  8271. case DRM_FORMAT_ABGR8888:
  8272. case DRM_FORMAT_XRGB2101010:
  8273. case DRM_FORMAT_ARGB2101010:
  8274. case DRM_FORMAT_XBGR2101010:
  8275. case DRM_FORMAT_ABGR2101010:
  8276. if (INTEL_INFO(dev)->gen < 4) {
  8277. DRM_DEBUG("unsupported pixel format: %s\n",
  8278. drm_get_format_name(mode_cmd->pixel_format));
  8279. return -EINVAL;
  8280. }
  8281. break;
  8282. case DRM_FORMAT_YUYV:
  8283. case DRM_FORMAT_UYVY:
  8284. case DRM_FORMAT_YVYU:
  8285. case DRM_FORMAT_VYUY:
  8286. if (INTEL_INFO(dev)->gen < 5) {
  8287. DRM_DEBUG("unsupported pixel format: %s\n",
  8288. drm_get_format_name(mode_cmd->pixel_format));
  8289. return -EINVAL;
  8290. }
  8291. break;
  8292. default:
  8293. DRM_DEBUG("unsupported pixel format: %s\n",
  8294. drm_get_format_name(mode_cmd->pixel_format));
  8295. return -EINVAL;
  8296. }
  8297. /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
  8298. if (mode_cmd->offsets[0] != 0)
  8299. return -EINVAL;
  8300. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  8301. intel_fb->obj = obj;
  8302. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  8303. if (ret) {
  8304. DRM_ERROR("framebuffer init failed %d\n", ret);
  8305. return ret;
  8306. }
  8307. return 0;
  8308. }
  8309. static struct drm_framebuffer *
  8310. intel_user_framebuffer_create(struct drm_device *dev,
  8311. struct drm_file *filp,
  8312. struct drm_mode_fb_cmd2 *mode_cmd)
  8313. {
  8314. struct drm_i915_gem_object *obj;
  8315. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  8316. mode_cmd->handles[0]));
  8317. if (&obj->base == NULL)
  8318. return ERR_PTR(-ENOENT);
  8319. return intel_framebuffer_create(dev, mode_cmd, obj);
  8320. }
  8321. static const struct drm_mode_config_funcs intel_mode_funcs = {
  8322. .fb_create = intel_user_framebuffer_create,
  8323. .output_poll_changed = intel_fb_output_poll_changed,
  8324. };
  8325. /* Set up chip specific display functions */
  8326. static void intel_init_display(struct drm_device *dev)
  8327. {
  8328. struct drm_i915_private *dev_priv = dev->dev_private;
  8329. if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
  8330. dev_priv->display.find_dpll = g4x_find_best_dpll;
  8331. else if (IS_VALLEYVIEW(dev))
  8332. dev_priv->display.find_dpll = vlv_find_best_dpll;
  8333. else if (IS_PINEVIEW(dev))
  8334. dev_priv->display.find_dpll = pnv_find_best_dpll;
  8335. else
  8336. dev_priv->display.find_dpll = i9xx_find_best_dpll;
  8337. if (HAS_DDI(dev)) {
  8338. dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  8339. dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
  8340. dev_priv->display.crtc_enable = haswell_crtc_enable;
  8341. dev_priv->display.crtc_disable = haswell_crtc_disable;
  8342. dev_priv->display.off = haswell_crtc_off;
  8343. dev_priv->display.update_plane = ironlake_update_plane;
  8344. } else if (HAS_PCH_SPLIT(dev)) {
  8345. dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
  8346. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  8347. dev_priv->display.crtc_enable = ironlake_crtc_enable;
  8348. dev_priv->display.crtc_disable = ironlake_crtc_disable;
  8349. dev_priv->display.off = ironlake_crtc_off;
  8350. dev_priv->display.update_plane = ironlake_update_plane;
  8351. } else if (IS_VALLEYVIEW(dev)) {
  8352. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  8353. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  8354. dev_priv->display.crtc_enable = valleyview_crtc_enable;
  8355. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  8356. dev_priv->display.off = i9xx_crtc_off;
  8357. dev_priv->display.update_plane = i9xx_update_plane;
  8358. } else {
  8359. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  8360. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  8361. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  8362. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  8363. dev_priv->display.off = i9xx_crtc_off;
  8364. dev_priv->display.update_plane = i9xx_update_plane;
  8365. }
  8366. /* Returns the core display clock speed */
  8367. if (IS_VALLEYVIEW(dev))
  8368. dev_priv->display.get_display_clock_speed =
  8369. valleyview_get_display_clock_speed;
  8370. else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  8371. dev_priv->display.get_display_clock_speed =
  8372. i945_get_display_clock_speed;
  8373. else if (IS_I915G(dev))
  8374. dev_priv->display.get_display_clock_speed =
  8375. i915_get_display_clock_speed;
  8376. else if (IS_I945GM(dev) || IS_845G(dev))
  8377. dev_priv->display.get_display_clock_speed =
  8378. i9xx_misc_get_display_clock_speed;
  8379. else if (IS_PINEVIEW(dev))
  8380. dev_priv->display.get_display_clock_speed =
  8381. pnv_get_display_clock_speed;
  8382. else if (IS_I915GM(dev))
  8383. dev_priv->display.get_display_clock_speed =
  8384. i915gm_get_display_clock_speed;
  8385. else if (IS_I865G(dev))
  8386. dev_priv->display.get_display_clock_speed =
  8387. i865_get_display_clock_speed;
  8388. else if (IS_I85X(dev))
  8389. dev_priv->display.get_display_clock_speed =
  8390. i855_get_display_clock_speed;
  8391. else /* 852, 830 */
  8392. dev_priv->display.get_display_clock_speed =
  8393. i830_get_display_clock_speed;
  8394. if (HAS_PCH_SPLIT(dev)) {
  8395. if (IS_GEN5(dev)) {
  8396. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  8397. dev_priv->display.write_eld = ironlake_write_eld;
  8398. } else if (IS_GEN6(dev)) {
  8399. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  8400. dev_priv->display.write_eld = ironlake_write_eld;
  8401. } else if (IS_IVYBRIDGE(dev)) {
  8402. /* FIXME: detect B0+ stepping and use auto training */
  8403. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  8404. dev_priv->display.write_eld = ironlake_write_eld;
  8405. dev_priv->display.modeset_global_resources =
  8406. ivb_modeset_global_resources;
  8407. } else if (IS_HASWELL(dev)) {
  8408. dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  8409. dev_priv->display.write_eld = haswell_write_eld;
  8410. dev_priv->display.modeset_global_resources =
  8411. haswell_modeset_global_resources;
  8412. }
  8413. } else if (IS_G4X(dev)) {
  8414. dev_priv->display.write_eld = g4x_write_eld;
  8415. }
  8416. /* Default just returns -ENODEV to indicate unsupported */
  8417. dev_priv->display.queue_flip = intel_default_queue_flip;
  8418. switch (INTEL_INFO(dev)->gen) {
  8419. case 2:
  8420. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  8421. break;
  8422. case 3:
  8423. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  8424. break;
  8425. case 4:
  8426. case 5:
  8427. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  8428. break;
  8429. case 6:
  8430. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  8431. break;
  8432. case 7:
  8433. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  8434. break;
  8435. }
  8436. }
  8437. /*
  8438. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  8439. * resume, or other times. This quirk makes sure that's the case for
  8440. * affected systems.
  8441. */
  8442. static void quirk_pipea_force(struct drm_device *dev)
  8443. {
  8444. struct drm_i915_private *dev_priv = dev->dev_private;
  8445. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  8446. DRM_INFO("applying pipe a force quirk\n");
  8447. }
  8448. /*
  8449. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  8450. */
  8451. static void quirk_ssc_force_disable(struct drm_device *dev)
  8452. {
  8453. struct drm_i915_private *dev_priv = dev->dev_private;
  8454. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  8455. DRM_INFO("applying lvds SSC disable quirk\n");
  8456. }
  8457. /*
  8458. * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  8459. * brightness value
  8460. */
  8461. static void quirk_invert_brightness(struct drm_device *dev)
  8462. {
  8463. struct drm_i915_private *dev_priv = dev->dev_private;
  8464. dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  8465. DRM_INFO("applying inverted panel brightness quirk\n");
  8466. }
  8467. /*
  8468. * Some machines (Dell XPS13) suffer broken backlight controls if
  8469. * BLM_PCH_PWM_ENABLE is set.
  8470. */
  8471. static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
  8472. {
  8473. struct drm_i915_private *dev_priv = dev->dev_private;
  8474. dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
  8475. DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
  8476. }
  8477. struct intel_quirk {
  8478. int device;
  8479. int subsystem_vendor;
  8480. int subsystem_device;
  8481. void (*hook)(struct drm_device *dev);
  8482. };
  8483. /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
  8484. struct intel_dmi_quirk {
  8485. void (*hook)(struct drm_device *dev);
  8486. const struct dmi_system_id (*dmi_id_list)[];
  8487. };
  8488. static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
  8489. {
  8490. DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
  8491. return 1;
  8492. }
  8493. static const struct intel_dmi_quirk intel_dmi_quirks[] = {
  8494. {
  8495. .dmi_id_list = &(const struct dmi_system_id[]) {
  8496. {
  8497. .callback = intel_dmi_reverse_brightness,
  8498. .ident = "NCR Corporation",
  8499. .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
  8500. DMI_MATCH(DMI_PRODUCT_NAME, ""),
  8501. },
  8502. },
  8503. { } /* terminating entry */
  8504. },
  8505. .hook = quirk_invert_brightness,
  8506. },
  8507. };
  8508. static struct intel_quirk intel_quirks[] = {
  8509. /* HP Mini needs pipe A force quirk (LP: #322104) */
  8510. { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  8511. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  8512. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  8513. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  8514. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  8515. /* 830/845 need to leave pipe A & dpll A up */
  8516. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  8517. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  8518. /* Lenovo U160 cannot use SSC on LVDS */
  8519. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  8520. /* Sony Vaio Y cannot use SSC on LVDS */
  8521. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  8522. /*
  8523. * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
  8524. * seem to use inverted backlight PWM.
  8525. */
  8526. { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
  8527. /* Dell XPS13 HD Sandy Bridge */
  8528. { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
  8529. /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
  8530. { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
  8531. };
  8532. static void intel_init_quirks(struct drm_device *dev)
  8533. {
  8534. struct pci_dev *d = dev->pdev;
  8535. int i;
  8536. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  8537. struct intel_quirk *q = &intel_quirks[i];
  8538. if (d->device == q->device &&
  8539. (d->subsystem_vendor == q->subsystem_vendor ||
  8540. q->subsystem_vendor == PCI_ANY_ID) &&
  8541. (d->subsystem_device == q->subsystem_device ||
  8542. q->subsystem_device == PCI_ANY_ID))
  8543. q->hook(dev);
  8544. }
  8545. for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
  8546. if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
  8547. intel_dmi_quirks[i].hook(dev);
  8548. }
  8549. }
  8550. /* Disable the VGA plane that we never use */
  8551. static void i915_disable_vga(struct drm_device *dev)
  8552. {
  8553. struct drm_i915_private *dev_priv = dev->dev_private;
  8554. u8 sr1;
  8555. u32 vga_reg = i915_vgacntrl_reg(dev);
  8556. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  8557. outb(SR01, VGA_SR_INDEX);
  8558. sr1 = inb(VGA_SR_DATA);
  8559. outb(sr1 | 1<<5, VGA_SR_DATA);
  8560. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  8561. udelay(300);
  8562. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  8563. POSTING_READ(vga_reg);
  8564. }
  8565. static void i915_enable_vga_mem(struct drm_device *dev)
  8566. {
  8567. /* Enable VGA memory on Intel HD */
  8568. if (HAS_PCH_SPLIT(dev)) {
  8569. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  8570. outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
  8571. vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
  8572. VGA_RSRC_LEGACY_MEM |
  8573. VGA_RSRC_NORMAL_IO |
  8574. VGA_RSRC_NORMAL_MEM);
  8575. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  8576. }
  8577. }
  8578. void i915_disable_vga_mem(struct drm_device *dev)
  8579. {
  8580. /* Disable VGA memory on Intel HD */
  8581. if (HAS_PCH_SPLIT(dev)) {
  8582. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  8583. outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
  8584. vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
  8585. VGA_RSRC_NORMAL_IO |
  8586. VGA_RSRC_NORMAL_MEM);
  8587. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  8588. }
  8589. }
  8590. void intel_modeset_init_hw(struct drm_device *dev)
  8591. {
  8592. intel_prepare_ddi(dev);
  8593. intel_init_clock_gating(dev);
  8594. mutex_lock(&dev->struct_mutex);
  8595. intel_enable_gt_powersave(dev);
  8596. mutex_unlock(&dev->struct_mutex);
  8597. }
  8598. void intel_modeset_suspend_hw(struct drm_device *dev)
  8599. {
  8600. intel_suspend_hw(dev);
  8601. }
  8602. void intel_modeset_init(struct drm_device *dev)
  8603. {
  8604. struct drm_i915_private *dev_priv = dev->dev_private;
  8605. int i, j, ret;
  8606. drm_mode_config_init(dev);
  8607. dev->mode_config.min_width = 0;
  8608. dev->mode_config.min_height = 0;
  8609. dev->mode_config.preferred_depth = 24;
  8610. dev->mode_config.prefer_shadow = 1;
  8611. dev->mode_config.funcs = &intel_mode_funcs;
  8612. intel_init_quirks(dev);
  8613. intel_init_pm(dev);
  8614. if (INTEL_INFO(dev)->num_pipes == 0)
  8615. return;
  8616. intel_init_display(dev);
  8617. if (IS_GEN2(dev)) {
  8618. dev->mode_config.max_width = 2048;
  8619. dev->mode_config.max_height = 2048;
  8620. } else if (IS_GEN3(dev)) {
  8621. dev->mode_config.max_width = 4096;
  8622. dev->mode_config.max_height = 4096;
  8623. } else {
  8624. dev->mode_config.max_width = 8192;
  8625. dev->mode_config.max_height = 8192;
  8626. }
  8627. dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
  8628. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  8629. INTEL_INFO(dev)->num_pipes,
  8630. INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
  8631. for_each_pipe(i) {
  8632. intel_crtc_init(dev, i);
  8633. for (j = 0; j < dev_priv->num_plane; j++) {
  8634. ret = intel_plane_init(dev, i, j);
  8635. if (ret)
  8636. DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
  8637. pipe_name(i), sprite_name(i, j), ret);
  8638. }
  8639. }
  8640. intel_cpu_pll_init(dev);
  8641. intel_shared_dpll_init(dev);
  8642. /* Just disable it once at startup */
  8643. i915_disable_vga(dev);
  8644. intel_setup_outputs(dev);
  8645. /* Just in case the BIOS is doing something questionable. */
  8646. intel_disable_fbc(dev);
  8647. }
  8648. static void
  8649. intel_connector_break_all_links(struct intel_connector *connector)
  8650. {
  8651. connector->base.dpms = DRM_MODE_DPMS_OFF;
  8652. connector->base.encoder = NULL;
  8653. connector->encoder->connectors_active = false;
  8654. connector->encoder->base.crtc = NULL;
  8655. }
  8656. static void intel_enable_pipe_a(struct drm_device *dev)
  8657. {
  8658. struct intel_connector *connector;
  8659. struct drm_connector *crt = NULL;
  8660. struct intel_load_detect_pipe load_detect_temp;
  8661. /* We can't just switch on the pipe A, we need to set things up with a
  8662. * proper mode and output configuration. As a gross hack, enable pipe A
  8663. * by enabling the load detect pipe once. */
  8664. list_for_each_entry(connector,
  8665. &dev->mode_config.connector_list,
  8666. base.head) {
  8667. if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  8668. crt = &connector->base;
  8669. break;
  8670. }
  8671. }
  8672. if (!crt)
  8673. return;
  8674. if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
  8675. intel_release_load_detect_pipe(crt, &load_detect_temp);
  8676. }
  8677. static bool
  8678. intel_check_plane_mapping(struct intel_crtc *crtc)
  8679. {
  8680. struct drm_device *dev = crtc->base.dev;
  8681. struct drm_i915_private *dev_priv = dev->dev_private;
  8682. u32 reg, val;
  8683. if (INTEL_INFO(dev)->num_pipes == 1)
  8684. return true;
  8685. reg = DSPCNTR(!crtc->plane);
  8686. val = I915_READ(reg);
  8687. if ((val & DISPLAY_PLANE_ENABLE) &&
  8688. (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  8689. return false;
  8690. return true;
  8691. }
  8692. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  8693. {
  8694. struct drm_device *dev = crtc->base.dev;
  8695. struct drm_i915_private *dev_priv = dev->dev_private;
  8696. u32 reg;
  8697. /* Clear any frame start delays used for debugging left by the BIOS */
  8698. reg = PIPECONF(crtc->config.cpu_transcoder);
  8699. I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  8700. /* We need to sanitize the plane -> pipe mapping first because this will
  8701. * disable the crtc (and hence change the state) if it is wrong. Note
  8702. * that gen4+ has a fixed plane -> pipe mapping. */
  8703. if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
  8704. struct intel_connector *connector;
  8705. bool plane;
  8706. DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  8707. crtc->base.base.id);
  8708. /* Pipe has the wrong plane attached and the plane is active.
  8709. * Temporarily change the plane mapping and disable everything
  8710. * ... */
  8711. plane = crtc->plane;
  8712. crtc->plane = !plane;
  8713. dev_priv->display.crtc_disable(&crtc->base);
  8714. crtc->plane = plane;
  8715. /* ... and break all links. */
  8716. list_for_each_entry(connector, &dev->mode_config.connector_list,
  8717. base.head) {
  8718. if (connector->encoder->base.crtc != &crtc->base)
  8719. continue;
  8720. intel_connector_break_all_links(connector);
  8721. }
  8722. WARN_ON(crtc->active);
  8723. crtc->base.enabled = false;
  8724. }
  8725. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  8726. crtc->pipe == PIPE_A && !crtc->active) {
  8727. /* BIOS forgot to enable pipe A, this mostly happens after
  8728. * resume. Force-enable the pipe to fix this, the update_dpms
  8729. * call below we restore the pipe to the right state, but leave
  8730. * the required bits on. */
  8731. intel_enable_pipe_a(dev);
  8732. }
  8733. /* Adjust the state of the output pipe according to whether we
  8734. * have active connectors/encoders. */
  8735. intel_crtc_update_dpms(&crtc->base);
  8736. if (crtc->active != crtc->base.enabled) {
  8737. struct intel_encoder *encoder;
  8738. /* This can happen either due to bugs in the get_hw_state
  8739. * functions or because the pipe is force-enabled due to the
  8740. * pipe A quirk. */
  8741. DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
  8742. crtc->base.base.id,
  8743. crtc->base.enabled ? "enabled" : "disabled",
  8744. crtc->active ? "enabled" : "disabled");
  8745. crtc->base.enabled = crtc->active;
  8746. /* Because we only establish the connector -> encoder ->
  8747. * crtc links if something is active, this means the
  8748. * crtc is now deactivated. Break the links. connector
  8749. * -> encoder links are only establish when things are
  8750. * actually up, hence no need to break them. */
  8751. WARN_ON(crtc->active);
  8752. for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
  8753. WARN_ON(encoder->connectors_active);
  8754. encoder->base.crtc = NULL;
  8755. }
  8756. }
  8757. }
  8758. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  8759. {
  8760. struct intel_connector *connector;
  8761. struct drm_device *dev = encoder->base.dev;
  8762. /* We need to check both for a crtc link (meaning that the
  8763. * encoder is active and trying to read from a pipe) and the
  8764. * pipe itself being active. */
  8765. bool has_active_crtc = encoder->base.crtc &&
  8766. to_intel_crtc(encoder->base.crtc)->active;
  8767. if (encoder->connectors_active && !has_active_crtc) {
  8768. DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  8769. encoder->base.base.id,
  8770. drm_get_encoder_name(&encoder->base));
  8771. /* Connector is active, but has no active pipe. This is
  8772. * fallout from our resume register restoring. Disable
  8773. * the encoder manually again. */
  8774. if (encoder->base.crtc) {
  8775. DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  8776. encoder->base.base.id,
  8777. drm_get_encoder_name(&encoder->base));
  8778. encoder->disable(encoder);
  8779. }
  8780. /* Inconsistent output/port/pipe state happens presumably due to
  8781. * a bug in one of the get_hw_state functions. Or someplace else
  8782. * in our code, like the register restore mess on resume. Clamp
  8783. * things to off as a safer default. */
  8784. list_for_each_entry(connector,
  8785. &dev->mode_config.connector_list,
  8786. base.head) {
  8787. if (connector->encoder != encoder)
  8788. continue;
  8789. intel_connector_break_all_links(connector);
  8790. }
  8791. }
  8792. /* Enabled encoders without active connectors will be fixed in
  8793. * the crtc fixup. */
  8794. }
  8795. void i915_redisable_vga(struct drm_device *dev)
  8796. {
  8797. struct drm_i915_private *dev_priv = dev->dev_private;
  8798. u32 vga_reg = i915_vgacntrl_reg(dev);
  8799. /* This function can be called both from intel_modeset_setup_hw_state or
  8800. * at a very early point in our resume sequence, where the power well
  8801. * structures are not yet restored. Since this function is at a very
  8802. * paranoid "someone might have enabled VGA while we were not looking"
  8803. * level, just check if the power well is enabled instead of trying to
  8804. * follow the "don't touch the power well if we don't need it" policy
  8805. * the rest of the driver uses. */
  8806. if (HAS_POWER_WELL(dev) &&
  8807. (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
  8808. return;
  8809. if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
  8810. DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
  8811. i915_disable_vga(dev);
  8812. i915_disable_vga_mem(dev);
  8813. }
  8814. }
  8815. static void intel_modeset_readout_hw_state(struct drm_device *dev)
  8816. {
  8817. struct drm_i915_private *dev_priv = dev->dev_private;
  8818. enum pipe pipe;
  8819. struct intel_crtc *crtc;
  8820. struct intel_encoder *encoder;
  8821. struct intel_connector *connector;
  8822. int i;
  8823. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8824. base.head) {
  8825. memset(&crtc->config, 0, sizeof(crtc->config));
  8826. crtc->active = dev_priv->display.get_pipe_config(crtc,
  8827. &crtc->config);
  8828. crtc->base.enabled = crtc->active;
  8829. DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  8830. crtc->base.base.id,
  8831. crtc->active ? "enabled" : "disabled");
  8832. }
  8833. /* FIXME: Smash this into the new shared dpll infrastructure. */
  8834. if (HAS_DDI(dev))
  8835. intel_ddi_setup_hw_pll_state(dev);
  8836. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  8837. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  8838. pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
  8839. pll->active = 0;
  8840. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8841. base.head) {
  8842. if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  8843. pll->active++;
  8844. }
  8845. pll->refcount = pll->active;
  8846. DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
  8847. pll->name, pll->refcount, pll->on);
  8848. }
  8849. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8850. base.head) {
  8851. pipe = 0;
  8852. if (encoder->get_hw_state(encoder, &pipe)) {
  8853. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  8854. encoder->base.crtc = &crtc->base;
  8855. if (encoder->get_config)
  8856. encoder->get_config(encoder, &crtc->config);
  8857. } else {
  8858. encoder->base.crtc = NULL;
  8859. }
  8860. encoder->connectors_active = false;
  8861. DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
  8862. encoder->base.base.id,
  8863. drm_get_encoder_name(&encoder->base),
  8864. encoder->base.crtc ? "enabled" : "disabled",
  8865. pipe);
  8866. }
  8867. list_for_each_entry(connector, &dev->mode_config.connector_list,
  8868. base.head) {
  8869. if (connector->get_hw_state(connector)) {
  8870. connector->base.dpms = DRM_MODE_DPMS_ON;
  8871. connector->encoder->connectors_active = true;
  8872. connector->base.encoder = &connector->encoder->base;
  8873. } else {
  8874. connector->base.dpms = DRM_MODE_DPMS_OFF;
  8875. connector->base.encoder = NULL;
  8876. }
  8877. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  8878. connector->base.base.id,
  8879. drm_get_connector_name(&connector->base),
  8880. connector->base.encoder ? "enabled" : "disabled");
  8881. }
  8882. }
  8883. /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  8884. * and i915 state tracking structures. */
  8885. void intel_modeset_setup_hw_state(struct drm_device *dev,
  8886. bool force_restore)
  8887. {
  8888. struct drm_i915_private *dev_priv = dev->dev_private;
  8889. enum pipe pipe;
  8890. struct intel_crtc *crtc;
  8891. struct intel_encoder *encoder;
  8892. int i;
  8893. intel_modeset_readout_hw_state(dev);
  8894. /*
  8895. * Now that we have the config, copy it to each CRTC struct
  8896. * Note that this could go away if we move to using crtc_config
  8897. * checking everywhere.
  8898. */
  8899. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8900. base.head) {
  8901. if (crtc->active && i915_fastboot) {
  8902. intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
  8903. DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
  8904. crtc->base.base.id);
  8905. drm_mode_debug_printmodeline(&crtc->base.mode);
  8906. }
  8907. }
  8908. /* HW state is read out, now we need to sanitize this mess. */
  8909. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8910. base.head) {
  8911. intel_sanitize_encoder(encoder);
  8912. }
  8913. for_each_pipe(pipe) {
  8914. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  8915. intel_sanitize_crtc(crtc);
  8916. intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
  8917. }
  8918. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  8919. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  8920. if (!pll->on || pll->active)
  8921. continue;
  8922. DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
  8923. pll->disable(dev_priv, pll);
  8924. pll->on = false;
  8925. }
  8926. if (force_restore) {
  8927. i915_redisable_vga(dev);
  8928. /*
  8929. * We need to use raw interfaces for restoring state to avoid
  8930. * checking (bogus) intermediate states.
  8931. */
  8932. for_each_pipe(pipe) {
  8933. struct drm_crtc *crtc =
  8934. dev_priv->pipe_to_crtc_mapping[pipe];
  8935. __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
  8936. crtc->fb);
  8937. }
  8938. } else {
  8939. intel_modeset_update_staged_output_state(dev);
  8940. }
  8941. intel_modeset_check_state(dev);
  8942. drm_mode_config_reset(dev);
  8943. }
  8944. void intel_modeset_gem_init(struct drm_device *dev)
  8945. {
  8946. intel_modeset_init_hw(dev);
  8947. intel_setup_overlay(dev);
  8948. intel_modeset_setup_hw_state(dev, false);
  8949. }
  8950. void intel_modeset_cleanup(struct drm_device *dev)
  8951. {
  8952. struct drm_i915_private *dev_priv = dev->dev_private;
  8953. struct drm_crtc *crtc;
  8954. /*
  8955. * Interrupts and polling as the first thing to avoid creating havoc.
  8956. * Too much stuff here (turning of rps, connectors, ...) would
  8957. * experience fancy races otherwise.
  8958. */
  8959. drm_irq_uninstall(dev);
  8960. cancel_work_sync(&dev_priv->hotplug_work);
  8961. /*
  8962. * Due to the hpd irq storm handling the hotplug work can re-arm the
  8963. * poll handlers. Hence disable polling after hpd handling is shut down.
  8964. */
  8965. drm_kms_helper_poll_fini(dev);
  8966. mutex_lock(&dev->struct_mutex);
  8967. intel_unregister_dsm_handler();
  8968. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  8969. /* Skip inactive CRTCs */
  8970. if (!crtc->fb)
  8971. continue;
  8972. intel_increase_pllclock(crtc);
  8973. }
  8974. intel_disable_fbc(dev);
  8975. i915_enable_vga_mem(dev);
  8976. intel_disable_gt_powersave(dev);
  8977. ironlake_teardown_rc6(dev);
  8978. mutex_unlock(&dev->struct_mutex);
  8979. /* flush any delayed tasks or pending work */
  8980. flush_scheduled_work();
  8981. /* destroy backlight, if any, before the connectors */
  8982. intel_panel_destroy_backlight(dev);
  8983. drm_mode_config_cleanup(dev);
  8984. intel_cleanup_overlay(dev);
  8985. }
  8986. /*
  8987. * Return which encoder is currently attached for connector.
  8988. */
  8989. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  8990. {
  8991. return &intel_attached_encoder(connector)->base;
  8992. }
  8993. void intel_connector_attach_encoder(struct intel_connector *connector,
  8994. struct intel_encoder *encoder)
  8995. {
  8996. connector->encoder = encoder;
  8997. drm_mode_connector_attach_encoder(&connector->base,
  8998. &encoder->base);
  8999. }
  9000. /*
  9001. * set vga decode state - true == enable VGA decode
  9002. */
  9003. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  9004. {
  9005. struct drm_i915_private *dev_priv = dev->dev_private;
  9006. u16 gmch_ctrl;
  9007. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  9008. if (state)
  9009. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  9010. else
  9011. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  9012. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  9013. return 0;
  9014. }
  9015. struct intel_display_error_state {
  9016. u32 power_well_driver;
  9017. int num_transcoders;
  9018. struct intel_cursor_error_state {
  9019. u32 control;
  9020. u32 position;
  9021. u32 base;
  9022. u32 size;
  9023. } cursor[I915_MAX_PIPES];
  9024. struct intel_pipe_error_state {
  9025. u32 source;
  9026. } pipe[I915_MAX_PIPES];
  9027. struct intel_plane_error_state {
  9028. u32 control;
  9029. u32 stride;
  9030. u32 size;
  9031. u32 pos;
  9032. u32 addr;
  9033. u32 surface;
  9034. u32 tile_offset;
  9035. } plane[I915_MAX_PIPES];
  9036. struct intel_transcoder_error_state {
  9037. enum transcoder cpu_transcoder;
  9038. u32 conf;
  9039. u32 htotal;
  9040. u32 hblank;
  9041. u32 hsync;
  9042. u32 vtotal;
  9043. u32 vblank;
  9044. u32 vsync;
  9045. } transcoder[4];
  9046. };
  9047. struct intel_display_error_state *
  9048. intel_display_capture_error_state(struct drm_device *dev)
  9049. {
  9050. drm_i915_private_t *dev_priv = dev->dev_private;
  9051. struct intel_display_error_state *error;
  9052. int transcoders[] = {
  9053. TRANSCODER_A,
  9054. TRANSCODER_B,
  9055. TRANSCODER_C,
  9056. TRANSCODER_EDP,
  9057. };
  9058. int i;
  9059. if (INTEL_INFO(dev)->num_pipes == 0)
  9060. return NULL;
  9061. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  9062. if (error == NULL)
  9063. return NULL;
  9064. if (HAS_POWER_WELL(dev))
  9065. error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
  9066. for_each_pipe(i) {
  9067. if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
  9068. error->cursor[i].control = I915_READ(CURCNTR(i));
  9069. error->cursor[i].position = I915_READ(CURPOS(i));
  9070. error->cursor[i].base = I915_READ(CURBASE(i));
  9071. } else {
  9072. error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
  9073. error->cursor[i].position = I915_READ(CURPOS_IVB(i));
  9074. error->cursor[i].base = I915_READ(CURBASE_IVB(i));
  9075. }
  9076. error->plane[i].control = I915_READ(DSPCNTR(i));
  9077. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  9078. if (INTEL_INFO(dev)->gen <= 3) {
  9079. error->plane[i].size = I915_READ(DSPSIZE(i));
  9080. error->plane[i].pos = I915_READ(DSPPOS(i));
  9081. }
  9082. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  9083. error->plane[i].addr = I915_READ(DSPADDR(i));
  9084. if (INTEL_INFO(dev)->gen >= 4) {
  9085. error->plane[i].surface = I915_READ(DSPSURF(i));
  9086. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  9087. }
  9088. error->pipe[i].source = I915_READ(PIPESRC(i));
  9089. }
  9090. error->num_transcoders = INTEL_INFO(dev)->num_pipes;
  9091. if (HAS_DDI(dev_priv->dev))
  9092. error->num_transcoders++; /* Account for eDP. */
  9093. for (i = 0; i < error->num_transcoders; i++) {
  9094. enum transcoder cpu_transcoder = transcoders[i];
  9095. error->transcoder[i].cpu_transcoder = cpu_transcoder;
  9096. error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
  9097. error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
  9098. error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
  9099. error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
  9100. error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
  9101. error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
  9102. error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
  9103. }
  9104. /* In the code above we read the registers without checking if the power
  9105. * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
  9106. * prevent the next I915_WRITE from detecting it and printing an error
  9107. * message. */
  9108. intel_uncore_clear_errors(dev);
  9109. return error;
  9110. }
  9111. #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
  9112. void
  9113. intel_display_print_error_state(struct drm_i915_error_state_buf *m,
  9114. struct drm_device *dev,
  9115. struct intel_display_error_state *error)
  9116. {
  9117. int i;
  9118. if (!error)
  9119. return;
  9120. err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
  9121. if (HAS_POWER_WELL(dev))
  9122. err_printf(m, "PWR_WELL_CTL2: %08x\n",
  9123. error->power_well_driver);
  9124. for_each_pipe(i) {
  9125. err_printf(m, "Pipe [%d]:\n", i);
  9126. err_printf(m, " SRC: %08x\n", error->pipe[i].source);
  9127. err_printf(m, "Plane [%d]:\n", i);
  9128. err_printf(m, " CNTR: %08x\n", error->plane[i].control);
  9129. err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  9130. if (INTEL_INFO(dev)->gen <= 3) {
  9131. err_printf(m, " SIZE: %08x\n", error->plane[i].size);
  9132. err_printf(m, " POS: %08x\n", error->plane[i].pos);
  9133. }
  9134. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  9135. err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  9136. if (INTEL_INFO(dev)->gen >= 4) {
  9137. err_printf(m, " SURF: %08x\n", error->plane[i].surface);
  9138. err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  9139. }
  9140. err_printf(m, "Cursor [%d]:\n", i);
  9141. err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  9142. err_printf(m, " POS: %08x\n", error->cursor[i].position);
  9143. err_printf(m, " BASE: %08x\n", error->cursor[i].base);
  9144. }
  9145. for (i = 0; i < error->num_transcoders; i++) {
  9146. err_printf(m, " CPU transcoder: %c\n",
  9147. transcoder_name(error->transcoder[i].cpu_transcoder));
  9148. err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
  9149. err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
  9150. err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
  9151. err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
  9152. err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
  9153. err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
  9154. err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
  9155. }
  9156. }