twl4030.c 37 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x93, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /*
  117. * read twl4030 register cache
  118. */
  119. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  120. unsigned int reg)
  121. {
  122. u8 *cache = codec->reg_cache;
  123. if (reg >= TWL4030_CACHEREGNUM)
  124. return -EIO;
  125. return cache[reg];
  126. }
  127. /*
  128. * write twl4030 register cache
  129. */
  130. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  131. u8 reg, u8 value)
  132. {
  133. u8 *cache = codec->reg_cache;
  134. if (reg >= TWL4030_CACHEREGNUM)
  135. return;
  136. cache[reg] = value;
  137. }
  138. /*
  139. * write to the twl4030 register space
  140. */
  141. static int twl4030_write(struct snd_soc_codec *codec,
  142. unsigned int reg, unsigned int value)
  143. {
  144. twl4030_write_reg_cache(codec, reg, value);
  145. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  146. }
  147. static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
  148. {
  149. u8 mode;
  150. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  151. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  152. mode & ~TWL4030_CODECPDZ);
  153. /* REVISIT: this delay is present in TI sample drivers */
  154. /* but there seems to be no TRM requirement for it */
  155. udelay(10);
  156. }
  157. static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
  158. {
  159. u8 mode;
  160. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  161. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  162. mode | TWL4030_CODECPDZ);
  163. /* REVISIT: this delay is present in TI sample drivers */
  164. /* but there seems to be no TRM requirement for it */
  165. udelay(10);
  166. }
  167. static void twl4030_init_chip(struct snd_soc_codec *codec)
  168. {
  169. int i;
  170. /* clear CODECPDZ prior to setting register defaults */
  171. twl4030_clear_codecpdz(codec);
  172. /* set all audio section registers to reasonable defaults */
  173. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  174. twl4030_write(codec, i, twl4030_reg[i]);
  175. }
  176. /* Earpiece */
  177. static const char *twl4030_earpiece_texts[] =
  178. {"Off", "DACL1", "DACL2", "DACR1"};
  179. static const unsigned int twl4030_earpiece_values[] =
  180. {0x0, 0x1, 0x2, 0x4};
  181. static const struct soc_enum twl4030_earpiece_enum =
  182. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
  183. ARRAY_SIZE(twl4030_earpiece_texts),
  184. twl4030_earpiece_texts,
  185. twl4030_earpiece_values);
  186. static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
  187. SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
  188. /* PreDrive Left */
  189. static const char *twl4030_predrivel_texts[] =
  190. {"Off", "DACL1", "DACL2", "DACR2"};
  191. static const unsigned int twl4030_predrivel_values[] =
  192. {0x0, 0x1, 0x2, 0x4};
  193. static const struct soc_enum twl4030_predrivel_enum =
  194. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
  195. ARRAY_SIZE(twl4030_predrivel_texts),
  196. twl4030_predrivel_texts,
  197. twl4030_predrivel_values);
  198. static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
  199. SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
  200. /* PreDrive Right */
  201. static const char *twl4030_predriver_texts[] =
  202. {"Off", "DACR1", "DACR2", "DACL2"};
  203. static const unsigned int twl4030_predriver_values[] =
  204. {0x0, 0x1, 0x2, 0x4};
  205. static const struct soc_enum twl4030_predriver_enum =
  206. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
  207. ARRAY_SIZE(twl4030_predriver_texts),
  208. twl4030_predriver_texts,
  209. twl4030_predriver_values);
  210. static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
  211. SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
  212. /* Headset Left */
  213. static const char *twl4030_hsol_texts[] =
  214. {"Off", "DACL1", "DACL2"};
  215. static const struct soc_enum twl4030_hsol_enum =
  216. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
  217. ARRAY_SIZE(twl4030_hsol_texts),
  218. twl4030_hsol_texts);
  219. static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
  220. SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
  221. /* Headset Right */
  222. static const char *twl4030_hsor_texts[] =
  223. {"Off", "DACR1", "DACR2"};
  224. static const struct soc_enum twl4030_hsor_enum =
  225. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
  226. ARRAY_SIZE(twl4030_hsor_texts),
  227. twl4030_hsor_texts);
  228. static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
  229. SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
  230. /* Carkit Left */
  231. static const char *twl4030_carkitl_texts[] =
  232. {"Off", "DACL1", "DACL2"};
  233. static const struct soc_enum twl4030_carkitl_enum =
  234. SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
  235. ARRAY_SIZE(twl4030_carkitl_texts),
  236. twl4030_carkitl_texts);
  237. static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
  238. SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
  239. /* Carkit Right */
  240. static const char *twl4030_carkitr_texts[] =
  241. {"Off", "DACR1", "DACR2"};
  242. static const struct soc_enum twl4030_carkitr_enum =
  243. SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
  244. ARRAY_SIZE(twl4030_carkitr_texts),
  245. twl4030_carkitr_texts);
  246. static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
  247. SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
  248. /* Handsfree Left */
  249. static const char *twl4030_handsfreel_texts[] =
  250. {"Voice", "DACL1", "DACL2", "DACR2"};
  251. static const struct soc_enum twl4030_handsfreel_enum =
  252. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  253. ARRAY_SIZE(twl4030_handsfreel_texts),
  254. twl4030_handsfreel_texts);
  255. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  256. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  257. /* Handsfree Right */
  258. static const char *twl4030_handsfreer_texts[] =
  259. {"Voice", "DACR1", "DACR2", "DACL2"};
  260. static const struct soc_enum twl4030_handsfreer_enum =
  261. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  262. ARRAY_SIZE(twl4030_handsfreer_texts),
  263. twl4030_handsfreer_texts);
  264. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  265. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  266. /* Left analog microphone selection */
  267. static const char *twl4030_analoglmic_texts[] =
  268. {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
  269. static const unsigned int twl4030_analoglmic_values[] =
  270. {0x0, 0x1, 0x2, 0x4, 0x8};
  271. static const struct soc_enum twl4030_analoglmic_enum =
  272. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
  273. ARRAY_SIZE(twl4030_analoglmic_texts),
  274. twl4030_analoglmic_texts,
  275. twl4030_analoglmic_values);
  276. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
  277. SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
  278. /* Right analog microphone selection */
  279. static const char *twl4030_analogrmic_texts[] =
  280. {"Off", "Sub mic", "AUXR"};
  281. static const unsigned int twl4030_analogrmic_values[] =
  282. {0x0, 0x1, 0x4};
  283. static const struct soc_enum twl4030_analogrmic_enum =
  284. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
  285. ARRAY_SIZE(twl4030_analogrmic_texts),
  286. twl4030_analogrmic_texts,
  287. twl4030_analogrmic_values);
  288. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
  289. SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
  290. /* TX1 L/R Analog/Digital microphone selection */
  291. static const char *twl4030_micpathtx1_texts[] =
  292. {"Analog", "Digimic0"};
  293. static const struct soc_enum twl4030_micpathtx1_enum =
  294. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  295. ARRAY_SIZE(twl4030_micpathtx1_texts),
  296. twl4030_micpathtx1_texts);
  297. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  298. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  299. /* TX2 L/R Analog/Digital microphone selection */
  300. static const char *twl4030_micpathtx2_texts[] =
  301. {"Analog", "Digimic1"};
  302. static const struct soc_enum twl4030_micpathtx2_enum =
  303. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  304. ARRAY_SIZE(twl4030_micpathtx2_texts),
  305. twl4030_micpathtx2_texts);
  306. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  307. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  308. static int micpath_event(struct snd_soc_dapm_widget *w,
  309. struct snd_kcontrol *kcontrol, int event)
  310. {
  311. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  312. unsigned char adcmicsel, micbias_ctl;
  313. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  314. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  315. /* Prepare the bits for the given TX path:
  316. * shift_l == 0: TX1 microphone path
  317. * shift_l == 2: TX2 microphone path */
  318. if (e->shift_l) {
  319. /* TX2 microphone path */
  320. if (adcmicsel & TWL4030_TX2IN_SEL)
  321. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  322. else
  323. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  324. } else {
  325. /* TX1 microphone path */
  326. if (adcmicsel & TWL4030_TX1IN_SEL)
  327. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  328. else
  329. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  330. }
  331. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  332. return 0;
  333. }
  334. static int handsfree_event(struct snd_soc_dapm_widget *w,
  335. struct snd_kcontrol *kcontrol, int event)
  336. {
  337. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  338. unsigned char hs_ctl;
  339. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  340. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  341. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  342. twl4030_write(w->codec, e->reg, hs_ctl);
  343. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  344. twl4030_write(w->codec, e->reg, hs_ctl);
  345. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  346. twl4030_write(w->codec, e->reg, hs_ctl);
  347. } else {
  348. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  349. | TWL4030_HF_CTL_HB_EN);
  350. twl4030_write(w->codec, e->reg, hs_ctl);
  351. }
  352. return 0;
  353. }
  354. /*
  355. * Some of the gain controls in TWL (mostly those which are associated with
  356. * the outputs) are implemented in an interesting way:
  357. * 0x0 : Power down (mute)
  358. * 0x1 : 6dB
  359. * 0x2 : 0 dB
  360. * 0x3 : -6 dB
  361. * Inverting not going to help with these.
  362. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  363. */
  364. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  365. xinvert, tlv_array) \
  366. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  367. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  368. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  369. .tlv.p = (tlv_array), \
  370. .info = snd_soc_info_volsw, \
  371. .get = snd_soc_get_volsw_twl4030, \
  372. .put = snd_soc_put_volsw_twl4030, \
  373. .private_value = (unsigned long)&(struct soc_mixer_control) \
  374. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  375. .max = xmax, .invert = xinvert} }
  376. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  377. xinvert, tlv_array) \
  378. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  379. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  380. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  381. .tlv.p = (tlv_array), \
  382. .info = snd_soc_info_volsw_2r, \
  383. .get = snd_soc_get_volsw_r2_twl4030,\
  384. .put = snd_soc_put_volsw_r2_twl4030, \
  385. .private_value = (unsigned long)&(struct soc_mixer_control) \
  386. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  387. .rshift = xshift, .max = xmax, .invert = xinvert} }
  388. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  389. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  390. xinvert, tlv_array)
  391. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  392. struct snd_ctl_elem_value *ucontrol)
  393. {
  394. struct soc_mixer_control *mc =
  395. (struct soc_mixer_control *)kcontrol->private_value;
  396. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  397. unsigned int reg = mc->reg;
  398. unsigned int shift = mc->shift;
  399. unsigned int rshift = mc->rshift;
  400. int max = mc->max;
  401. int mask = (1 << fls(max)) - 1;
  402. ucontrol->value.integer.value[0] =
  403. (snd_soc_read(codec, reg) >> shift) & mask;
  404. if (ucontrol->value.integer.value[0])
  405. ucontrol->value.integer.value[0] =
  406. max + 1 - ucontrol->value.integer.value[0];
  407. if (shift != rshift) {
  408. ucontrol->value.integer.value[1] =
  409. (snd_soc_read(codec, reg) >> rshift) & mask;
  410. if (ucontrol->value.integer.value[1])
  411. ucontrol->value.integer.value[1] =
  412. max + 1 - ucontrol->value.integer.value[1];
  413. }
  414. return 0;
  415. }
  416. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  417. struct snd_ctl_elem_value *ucontrol)
  418. {
  419. struct soc_mixer_control *mc =
  420. (struct soc_mixer_control *)kcontrol->private_value;
  421. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  422. unsigned int reg = mc->reg;
  423. unsigned int shift = mc->shift;
  424. unsigned int rshift = mc->rshift;
  425. int max = mc->max;
  426. int mask = (1 << fls(max)) - 1;
  427. unsigned short val, val2, val_mask;
  428. val = (ucontrol->value.integer.value[0] & mask);
  429. val_mask = mask << shift;
  430. if (val)
  431. val = max + 1 - val;
  432. val = val << shift;
  433. if (shift != rshift) {
  434. val2 = (ucontrol->value.integer.value[1] & mask);
  435. val_mask |= mask << rshift;
  436. if (val2)
  437. val2 = max + 1 - val2;
  438. val |= val2 << rshift;
  439. }
  440. return snd_soc_update_bits(codec, reg, val_mask, val);
  441. }
  442. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  443. struct snd_ctl_elem_value *ucontrol)
  444. {
  445. struct soc_mixer_control *mc =
  446. (struct soc_mixer_control *)kcontrol->private_value;
  447. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  448. unsigned int reg = mc->reg;
  449. unsigned int reg2 = mc->rreg;
  450. unsigned int shift = mc->shift;
  451. int max = mc->max;
  452. int mask = (1<<fls(max))-1;
  453. ucontrol->value.integer.value[0] =
  454. (snd_soc_read(codec, reg) >> shift) & mask;
  455. ucontrol->value.integer.value[1] =
  456. (snd_soc_read(codec, reg2) >> shift) & mask;
  457. if (ucontrol->value.integer.value[0])
  458. ucontrol->value.integer.value[0] =
  459. max + 1 - ucontrol->value.integer.value[0];
  460. if (ucontrol->value.integer.value[1])
  461. ucontrol->value.integer.value[1] =
  462. max + 1 - ucontrol->value.integer.value[1];
  463. return 0;
  464. }
  465. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  466. struct snd_ctl_elem_value *ucontrol)
  467. {
  468. struct soc_mixer_control *mc =
  469. (struct soc_mixer_control *)kcontrol->private_value;
  470. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  471. unsigned int reg = mc->reg;
  472. unsigned int reg2 = mc->rreg;
  473. unsigned int shift = mc->shift;
  474. int max = mc->max;
  475. int mask = (1 << fls(max)) - 1;
  476. int err;
  477. unsigned short val, val2, val_mask;
  478. val_mask = mask << shift;
  479. val = (ucontrol->value.integer.value[0] & mask);
  480. val2 = (ucontrol->value.integer.value[1] & mask);
  481. if (val)
  482. val = max + 1 - val;
  483. if (val2)
  484. val2 = max + 1 - val2;
  485. val = val << shift;
  486. val2 = val2 << shift;
  487. err = snd_soc_update_bits(codec, reg, val_mask, val);
  488. if (err < 0)
  489. return err;
  490. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  491. return err;
  492. }
  493. /*
  494. * FGAIN volume control:
  495. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  496. */
  497. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  498. /*
  499. * CGAIN volume control:
  500. * 0 dB to 12 dB in 6 dB steps
  501. * value 2 and 3 means 12 dB
  502. */
  503. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  504. /*
  505. * Analog playback gain
  506. * -24 dB to 12 dB in 2 dB steps
  507. */
  508. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  509. /*
  510. * Gain controls tied to outputs
  511. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  512. */
  513. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  514. /*
  515. * Capture gain after the ADCs
  516. * from 0 dB to 31 dB in 1 dB steps
  517. */
  518. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  519. /*
  520. * Gain control for input amplifiers
  521. * 0 dB to 30 dB in 6 dB steps
  522. */
  523. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  524. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  525. /* Common playback gain controls */
  526. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  527. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  528. 0, 0x3f, 0, digital_fine_tlv),
  529. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  530. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  531. 0, 0x3f, 0, digital_fine_tlv),
  532. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  533. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  534. 6, 0x2, 0, digital_coarse_tlv),
  535. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  536. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  537. 6, 0x2, 0, digital_coarse_tlv),
  538. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  539. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  540. 3, 0x12, 1, analog_tlv),
  541. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  542. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  543. 3, 0x12, 1, analog_tlv),
  544. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  545. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  546. 1, 1, 0),
  547. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  548. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  549. 1, 1, 0),
  550. /* Separate output gain controls */
  551. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  552. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  553. 4, 3, 0, output_tvl),
  554. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  555. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  556. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  557. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  558. 4, 3, 0, output_tvl),
  559. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  560. TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
  561. /* Common capture gain controls */
  562. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  563. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  564. 0, 0x1f, 0, digital_capture_tlv),
  565. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  566. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  567. 0, 0x1f, 0, digital_capture_tlv),
  568. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  569. 0, 3, 5, 0, input_gain_tlv),
  570. };
  571. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  572. /* Left channel inputs */
  573. SND_SOC_DAPM_INPUT("MAINMIC"),
  574. SND_SOC_DAPM_INPUT("HSMIC"),
  575. SND_SOC_DAPM_INPUT("AUXL"),
  576. SND_SOC_DAPM_INPUT("CARKITMIC"),
  577. /* Right channel inputs */
  578. SND_SOC_DAPM_INPUT("SUBMIC"),
  579. SND_SOC_DAPM_INPUT("AUXR"),
  580. /* Digital microphones (Stereo) */
  581. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  582. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  583. /* Outputs */
  584. SND_SOC_DAPM_OUTPUT("OUTL"),
  585. SND_SOC_DAPM_OUTPUT("OUTR"),
  586. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  587. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  588. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  589. SND_SOC_DAPM_OUTPUT("HSOL"),
  590. SND_SOC_DAPM_OUTPUT("HSOR"),
  591. SND_SOC_DAPM_OUTPUT("CARKITL"),
  592. SND_SOC_DAPM_OUTPUT("CARKITR"),
  593. SND_SOC_DAPM_OUTPUT("HFL"),
  594. SND_SOC_DAPM_OUTPUT("HFR"),
  595. /* DACs */
  596. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  597. TWL4030_REG_AVDAC_CTL, 0, 0),
  598. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  599. TWL4030_REG_AVDAC_CTL, 1, 0),
  600. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  601. TWL4030_REG_AVDAC_CTL, 2, 0),
  602. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  603. TWL4030_REG_AVDAC_CTL, 3, 0),
  604. /* Analog PGAs */
  605. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  606. 0, 0, NULL, 0),
  607. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  608. 0, 0, NULL, 0),
  609. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  610. 0, 0, NULL, 0),
  611. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  612. 0, 0, NULL, 0),
  613. /* Output MUX controls */
  614. /* Earpiece */
  615. SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
  616. &twl4030_dapm_earpiece_control),
  617. /* PreDrivL/R */
  618. SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
  619. &twl4030_dapm_predrivel_control),
  620. SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
  621. &twl4030_dapm_predriver_control),
  622. /* HeadsetL/R */
  623. SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
  624. &twl4030_dapm_hsol_control),
  625. SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
  626. &twl4030_dapm_hsor_control),
  627. /* CarkitL/R */
  628. SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
  629. &twl4030_dapm_carkitl_control),
  630. SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
  631. &twl4030_dapm_carkitr_control),
  632. /* HandsfreeL/R */
  633. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  634. &twl4030_dapm_handsfreel_control, handsfree_event,
  635. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  636. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  637. &twl4030_dapm_handsfreer_control, handsfree_event,
  638. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  639. /* Introducing four virtual ADC, since TWL4030 have four channel for
  640. capture */
  641. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  642. SND_SOC_NOPM, 0, 0),
  643. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  644. SND_SOC_NOPM, 0, 0),
  645. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  646. SND_SOC_NOPM, 0, 0),
  647. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  648. SND_SOC_NOPM, 0, 0),
  649. /* Analog/Digital mic path selection.
  650. TX1 Left/Right: either analog Left/Right or Digimic0
  651. TX2 Left/Right: either analog Left/Right or Digimic1 */
  652. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  653. &twl4030_dapm_micpathtx1_control, micpath_event,
  654. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  655. SND_SOC_DAPM_POST_REG),
  656. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  657. &twl4030_dapm_micpathtx2_control, micpath_event,
  658. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  659. SND_SOC_DAPM_POST_REG),
  660. /* Analog input muxes with power switch for the physical ADCL/R */
  661. SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
  662. TWL4030_REG_AVADC_CTL, 3, 0, &twl4030_dapm_analoglmic_control),
  663. SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
  664. TWL4030_REG_AVADC_CTL, 1, 0, &twl4030_dapm_analogrmic_control),
  665. SND_SOC_DAPM_PGA("Analog Left Amplifier",
  666. TWL4030_REG_ANAMICL, 4, 0, NULL, 0),
  667. SND_SOC_DAPM_PGA("Analog Right Amplifier",
  668. TWL4030_REG_ANAMICR, 4, 0, NULL, 0),
  669. SND_SOC_DAPM_PGA("Digimic0 Enable",
  670. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  671. SND_SOC_DAPM_PGA("Digimic1 Enable",
  672. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  673. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  674. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  675. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  676. };
  677. static const struct snd_soc_dapm_route intercon[] = {
  678. {"ARXL1_APGA", NULL, "DAC Left1"},
  679. {"ARXR1_APGA", NULL, "DAC Right1"},
  680. {"ARXL2_APGA", NULL, "DAC Left2"},
  681. {"ARXR2_APGA", NULL, "DAC Right2"},
  682. /* Internal playback routings */
  683. /* Earpiece */
  684. {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
  685. {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
  686. {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
  687. /* PreDrivL */
  688. {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
  689. {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
  690. {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
  691. /* PreDrivR */
  692. {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
  693. {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
  694. {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
  695. /* HeadsetL */
  696. {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
  697. {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
  698. /* HeadsetR */
  699. {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
  700. {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
  701. /* CarkitL */
  702. {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
  703. {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
  704. /* CarkitR */
  705. {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
  706. {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
  707. /* HandsfreeL */
  708. {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
  709. {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
  710. {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
  711. /* HandsfreeR */
  712. {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
  713. {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
  714. {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
  715. /* outputs */
  716. {"OUTL", NULL, "ARXL2_APGA"},
  717. {"OUTR", NULL, "ARXR2_APGA"},
  718. {"EARPIECE", NULL, "Earpiece Mux"},
  719. {"PREDRIVEL", NULL, "PredriveL Mux"},
  720. {"PREDRIVER", NULL, "PredriveR Mux"},
  721. {"HSOL", NULL, "HeadsetL Mux"},
  722. {"HSOR", NULL, "HeadsetR Mux"},
  723. {"CARKITL", NULL, "CarkitL Mux"},
  724. {"CARKITR", NULL, "CarkitR Mux"},
  725. {"HFL", NULL, "HandsfreeL Mux"},
  726. {"HFR", NULL, "HandsfreeR Mux"},
  727. /* Capture path */
  728. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  729. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  730. {"Analog Left Capture Route", "AUXL", "AUXL"},
  731. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  732. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  733. {"Analog Right Capture Route", "AUXR", "AUXR"},
  734. {"Analog Left Amplifier", NULL, "Analog Left Capture Route"},
  735. {"Analog Right Amplifier", NULL, "Analog Right Capture Route"},
  736. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  737. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  738. /* TX1 Left capture path */
  739. {"TX1 Capture Route", "Analog", "Analog Left Amplifier"},
  740. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  741. /* TX1 Right capture path */
  742. {"TX1 Capture Route", "Analog", "Analog Right Amplifier"},
  743. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  744. /* TX2 Left capture path */
  745. {"TX2 Capture Route", "Analog", "Analog Left Amplifier"},
  746. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  747. /* TX2 Right capture path */
  748. {"TX2 Capture Route", "Analog", "Analog Right Amplifier"},
  749. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  750. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  751. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  752. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  753. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  754. };
  755. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  756. {
  757. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  758. ARRAY_SIZE(twl4030_dapm_widgets));
  759. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  760. snd_soc_dapm_new_widgets(codec);
  761. return 0;
  762. }
  763. static void twl4030_power_up(struct snd_soc_codec *codec)
  764. {
  765. u8 anamicl, regmisc1, byte, popn;
  766. int i = 0;
  767. /* set CODECPDZ to turn on codec */
  768. twl4030_set_codecpdz(codec);
  769. /* initiate offset cancellation */
  770. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  771. twl4030_write(codec, TWL4030_REG_ANAMICL,
  772. anamicl | TWL4030_CNCL_OFFSET_START);
  773. /* wait for offset cancellation to complete */
  774. do {
  775. /* this takes a little while, so don't slam i2c */
  776. udelay(2000);
  777. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  778. TWL4030_REG_ANAMICL);
  779. } while ((i++ < 100) &&
  780. ((byte & TWL4030_CNCL_OFFSET_START) ==
  781. TWL4030_CNCL_OFFSET_START));
  782. /* anti-pop when changing analog gain */
  783. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  784. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  785. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  786. /* toggle CODECPDZ as per TRM */
  787. twl4030_clear_codecpdz(codec);
  788. twl4030_set_codecpdz(codec);
  789. /* program anti-pop with bias ramp delay */
  790. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  791. popn &= TWL4030_RAMP_DELAY;
  792. popn |= TWL4030_RAMP_DELAY_645MS;
  793. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  794. popn |= TWL4030_VMID_EN;
  795. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  796. /* enable anti-pop ramp */
  797. popn |= TWL4030_RAMP_EN;
  798. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  799. }
  800. static void twl4030_power_down(struct snd_soc_codec *codec)
  801. {
  802. u8 popn;
  803. /* disable anti-pop ramp */
  804. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  805. popn &= ~TWL4030_RAMP_EN;
  806. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  807. /* disable bias out */
  808. popn &= ~TWL4030_VMID_EN;
  809. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  810. /* power down */
  811. twl4030_clear_codecpdz(codec);
  812. }
  813. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  814. enum snd_soc_bias_level level)
  815. {
  816. switch (level) {
  817. case SND_SOC_BIAS_ON:
  818. twl4030_power_up(codec);
  819. break;
  820. case SND_SOC_BIAS_PREPARE:
  821. /* TODO: develop a twl4030_prepare function */
  822. break;
  823. case SND_SOC_BIAS_STANDBY:
  824. /* TODO: develop a twl4030_standby function */
  825. twl4030_power_down(codec);
  826. break;
  827. case SND_SOC_BIAS_OFF:
  828. twl4030_power_down(codec);
  829. break;
  830. }
  831. codec->bias_level = level;
  832. return 0;
  833. }
  834. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  835. struct snd_pcm_hw_params *params,
  836. struct snd_soc_dai *dai)
  837. {
  838. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  839. struct snd_soc_device *socdev = rtd->socdev;
  840. struct snd_soc_codec *codec = socdev->card->codec;
  841. u8 mode, old_mode, format, old_format;
  842. /* bit rate */
  843. old_mode = twl4030_read_reg_cache(codec,
  844. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  845. mode = old_mode & ~TWL4030_APLL_RATE;
  846. switch (params_rate(params)) {
  847. case 8000:
  848. mode |= TWL4030_APLL_RATE_8000;
  849. break;
  850. case 11025:
  851. mode |= TWL4030_APLL_RATE_11025;
  852. break;
  853. case 12000:
  854. mode |= TWL4030_APLL_RATE_12000;
  855. break;
  856. case 16000:
  857. mode |= TWL4030_APLL_RATE_16000;
  858. break;
  859. case 22050:
  860. mode |= TWL4030_APLL_RATE_22050;
  861. break;
  862. case 24000:
  863. mode |= TWL4030_APLL_RATE_24000;
  864. break;
  865. case 32000:
  866. mode |= TWL4030_APLL_RATE_32000;
  867. break;
  868. case 44100:
  869. mode |= TWL4030_APLL_RATE_44100;
  870. break;
  871. case 48000:
  872. mode |= TWL4030_APLL_RATE_48000;
  873. break;
  874. default:
  875. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  876. params_rate(params));
  877. return -EINVAL;
  878. }
  879. if (mode != old_mode) {
  880. /* change rate and set CODECPDZ */
  881. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  882. twl4030_set_codecpdz(codec);
  883. }
  884. /* sample size */
  885. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  886. format = old_format;
  887. format &= ~TWL4030_DATA_WIDTH;
  888. switch (params_format(params)) {
  889. case SNDRV_PCM_FORMAT_S16_LE:
  890. format |= TWL4030_DATA_WIDTH_16S_16W;
  891. break;
  892. case SNDRV_PCM_FORMAT_S24_LE:
  893. format |= TWL4030_DATA_WIDTH_32S_24W;
  894. break;
  895. default:
  896. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  897. params_format(params));
  898. return -EINVAL;
  899. }
  900. if (format != old_format) {
  901. /* clear CODECPDZ before changing format (codec requirement) */
  902. twl4030_clear_codecpdz(codec);
  903. /* change format */
  904. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  905. /* set CODECPDZ afterwards */
  906. twl4030_set_codecpdz(codec);
  907. }
  908. return 0;
  909. }
  910. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  911. int clk_id, unsigned int freq, int dir)
  912. {
  913. struct snd_soc_codec *codec = codec_dai->codec;
  914. u8 infreq;
  915. switch (freq) {
  916. case 19200000:
  917. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  918. break;
  919. case 26000000:
  920. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  921. break;
  922. case 38400000:
  923. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  924. break;
  925. default:
  926. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  927. freq);
  928. return -EINVAL;
  929. }
  930. infreq |= TWL4030_APLL_EN;
  931. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  932. return 0;
  933. }
  934. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  935. unsigned int fmt)
  936. {
  937. struct snd_soc_codec *codec = codec_dai->codec;
  938. u8 old_format, format;
  939. /* get format */
  940. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  941. format = old_format;
  942. /* set master/slave audio interface */
  943. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  944. case SND_SOC_DAIFMT_CBM_CFM:
  945. format &= ~(TWL4030_AIF_SLAVE_EN);
  946. format &= ~(TWL4030_CLK256FS_EN);
  947. break;
  948. case SND_SOC_DAIFMT_CBS_CFS:
  949. format |= TWL4030_AIF_SLAVE_EN;
  950. format |= TWL4030_CLK256FS_EN;
  951. break;
  952. default:
  953. return -EINVAL;
  954. }
  955. /* interface format */
  956. format &= ~TWL4030_AIF_FORMAT;
  957. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  958. case SND_SOC_DAIFMT_I2S:
  959. format |= TWL4030_AIF_FORMAT_CODEC;
  960. break;
  961. default:
  962. return -EINVAL;
  963. }
  964. if (format != old_format) {
  965. /* clear CODECPDZ before changing format (codec requirement) */
  966. twl4030_clear_codecpdz(codec);
  967. /* change format */
  968. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  969. /* set CODECPDZ afterwards */
  970. twl4030_set_codecpdz(codec);
  971. }
  972. return 0;
  973. }
  974. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  975. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  976. struct snd_soc_dai twl4030_dai = {
  977. .name = "twl4030",
  978. .playback = {
  979. .stream_name = "Playback",
  980. .channels_min = 2,
  981. .channels_max = 2,
  982. .rates = TWL4030_RATES,
  983. .formats = TWL4030_FORMATS,},
  984. .capture = {
  985. .stream_name = "Capture",
  986. .channels_min = 2,
  987. .channels_max = 2,
  988. .rates = TWL4030_RATES,
  989. .formats = TWL4030_FORMATS,},
  990. .ops = {
  991. .hw_params = twl4030_hw_params,
  992. .set_sysclk = twl4030_set_dai_sysclk,
  993. .set_fmt = twl4030_set_dai_fmt,
  994. }
  995. };
  996. EXPORT_SYMBOL_GPL(twl4030_dai);
  997. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  998. {
  999. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1000. struct snd_soc_codec *codec = socdev->card->codec;
  1001. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1002. return 0;
  1003. }
  1004. static int twl4030_resume(struct platform_device *pdev)
  1005. {
  1006. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1007. struct snd_soc_codec *codec = socdev->card->codec;
  1008. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1009. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1010. return 0;
  1011. }
  1012. /*
  1013. * initialize the driver
  1014. * register the mixer and dsp interfaces with the kernel
  1015. */
  1016. static int twl4030_init(struct snd_soc_device *socdev)
  1017. {
  1018. struct snd_soc_codec *codec = socdev->card->codec;
  1019. int ret = 0;
  1020. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1021. codec->name = "twl4030";
  1022. codec->owner = THIS_MODULE;
  1023. codec->read = twl4030_read_reg_cache;
  1024. codec->write = twl4030_write;
  1025. codec->set_bias_level = twl4030_set_bias_level;
  1026. codec->dai = &twl4030_dai;
  1027. codec->num_dai = 1;
  1028. codec->reg_cache_size = sizeof(twl4030_reg);
  1029. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1030. GFP_KERNEL);
  1031. if (codec->reg_cache == NULL)
  1032. return -ENOMEM;
  1033. /* register pcms */
  1034. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1035. if (ret < 0) {
  1036. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1037. goto pcm_err;
  1038. }
  1039. twl4030_init_chip(codec);
  1040. /* power on device */
  1041. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1042. snd_soc_add_controls(codec, twl4030_snd_controls,
  1043. ARRAY_SIZE(twl4030_snd_controls));
  1044. twl4030_add_widgets(codec);
  1045. ret = snd_soc_init_card(socdev);
  1046. if (ret < 0) {
  1047. printk(KERN_ERR "twl4030: failed to register card\n");
  1048. goto card_err;
  1049. }
  1050. return ret;
  1051. card_err:
  1052. snd_soc_free_pcms(socdev);
  1053. snd_soc_dapm_free(socdev);
  1054. pcm_err:
  1055. kfree(codec->reg_cache);
  1056. return ret;
  1057. }
  1058. static struct snd_soc_device *twl4030_socdev;
  1059. static int twl4030_probe(struct platform_device *pdev)
  1060. {
  1061. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1062. struct snd_soc_codec *codec;
  1063. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1064. if (codec == NULL)
  1065. return -ENOMEM;
  1066. socdev->card->codec = codec;
  1067. mutex_init(&codec->mutex);
  1068. INIT_LIST_HEAD(&codec->dapm_widgets);
  1069. INIT_LIST_HEAD(&codec->dapm_paths);
  1070. twl4030_socdev = socdev;
  1071. twl4030_init(socdev);
  1072. return 0;
  1073. }
  1074. static int twl4030_remove(struct platform_device *pdev)
  1075. {
  1076. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1077. struct snd_soc_codec *codec = socdev->card->codec;
  1078. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1079. snd_soc_free_pcms(socdev);
  1080. snd_soc_dapm_free(socdev);
  1081. kfree(codec);
  1082. return 0;
  1083. }
  1084. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1085. .probe = twl4030_probe,
  1086. .remove = twl4030_remove,
  1087. .suspend = twl4030_suspend,
  1088. .resume = twl4030_resume,
  1089. };
  1090. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1091. static int __init twl4030_modinit(void)
  1092. {
  1093. return snd_soc_register_dai(&twl4030_dai);
  1094. }
  1095. module_init(twl4030_modinit);
  1096. static void __exit twl4030_exit(void)
  1097. {
  1098. snd_soc_unregister_dai(&twl4030_dai);
  1099. }
  1100. module_exit(twl4030_exit);
  1101. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1102. MODULE_AUTHOR("Steve Sakoman");
  1103. MODULE_LICENSE("GPL");