prom.c 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124
  1. /*
  2. * linux/arch/mips/tx4938/common/prom.c
  3. *
  4. * common tx4938 memory interface
  5. * Copyright (C) 2000-2001 Toshiba Corporation
  6. *
  7. * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
  8. * terms of the GNU General Public License version 2. This program is
  9. * licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. *
  12. * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  13. */
  14. #include <linux/init.h>
  15. #include <linux/types.h>
  16. #include <linux/io.h>
  17. static unsigned int __init
  18. tx4938_process_sdccr(u64 * addr)
  19. {
  20. u64 val;
  21. unsigned int sdccr_ce;
  22. unsigned int sdccr_rs;
  23. unsigned int sdccr_cs;
  24. unsigned int sdccr_mw;
  25. unsigned int rs = 0;
  26. unsigned int cs = 0;
  27. unsigned int mw = 0;
  28. unsigned int bc = 4;
  29. unsigned int msize = 0;
  30. val = ____raw_readq((void __iomem *)addr);
  31. /* MVMCP -- need #defs for these bits masks */
  32. sdccr_ce = ((val & (1 << 10)) >> 10);
  33. sdccr_rs = ((val & (3 << 5)) >> 5);
  34. sdccr_cs = ((val & (7 << 2)) >> 2);
  35. sdccr_mw = ((val & (1 << 0)) >> 0);
  36. if (sdccr_ce) {
  37. switch (sdccr_rs) {
  38. case 0:{
  39. rs = 2048;
  40. break;
  41. }
  42. case 1:{
  43. rs = 4096;
  44. break;
  45. }
  46. case 2:{
  47. rs = 8192;
  48. break;
  49. }
  50. default:{
  51. rs = 0;
  52. break;
  53. }
  54. }
  55. switch (sdccr_cs) {
  56. case 0:{
  57. cs = 256;
  58. break;
  59. }
  60. case 1:{
  61. cs = 512;
  62. break;
  63. }
  64. case 2:{
  65. cs = 1024;
  66. break;
  67. }
  68. case 3:{
  69. cs = 2048;
  70. break;
  71. }
  72. case 4:{
  73. cs = 4096;
  74. break;
  75. }
  76. default:{
  77. cs = 0;
  78. break;
  79. }
  80. }
  81. switch (sdccr_mw) {
  82. case 0:{
  83. mw = 8;
  84. break;
  85. } /* 8 bytes = 64 bits */
  86. case 1:{
  87. mw = 4;
  88. break;
  89. } /* 4 bytes = 32 bits */
  90. }
  91. }
  92. /* bytes per chip MB per chip bank count */
  93. msize = (((rs * cs * mw) / (1024 * 1024)) * (bc));
  94. /* MVMCP -- bc hard coded to 4 from table 9.3.1 */
  95. /* boad supports bc=2 but no way to detect */
  96. return (msize);
  97. }
  98. unsigned int __init
  99. tx4938_get_mem_size(void)
  100. {
  101. unsigned int c0;
  102. unsigned int c1;
  103. unsigned int c2;
  104. unsigned int c3;
  105. unsigned int total;
  106. /* MVMCP -- need #defs for these registers */
  107. c0 = tx4938_process_sdccr((u64 *) 0xff1f8000);
  108. c1 = tx4938_process_sdccr((u64 *) 0xff1f8008);
  109. c2 = tx4938_process_sdccr((u64 *) 0xff1f8010);
  110. c3 = tx4938_process_sdccr((u64 *) 0xff1f8018);
  111. total = c0 + c1 + c2 + c3;
  112. return (total);
  113. }