radeon_atombios.c 42 KB

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  1. /*
  2. * Copyright 2007-8 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice shall be included in
  13. * all copies or substantial portions of the Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21. * OTHER DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors: Dave Airlie
  24. * Alex Deucher
  25. */
  26. #include "drmP.h"
  27. #include "radeon_drm.h"
  28. #include "radeon.h"
  29. #include "atom.h"
  30. #include "atom-bits.h"
  31. /* from radeon_encoder.c */
  32. extern uint32_t
  33. radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  34. uint8_t dac);
  35. extern void radeon_link_encoder_connector(struct drm_device *dev);
  36. extern void
  37. radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  38. uint32_t supported_device);
  39. /* from radeon_connector.c */
  40. extern void
  41. radeon_add_atom_connector(struct drm_device *dev,
  42. uint32_t connector_id,
  43. uint32_t supported_device,
  44. int connector_type,
  45. struct radeon_i2c_bus_rec *i2c_bus,
  46. bool linkb, uint32_t igp_lane_info);
  47. /* from radeon_legacy_encoder.c */
  48. extern void
  49. radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  50. uint32_t supported_device);
  51. union atom_supported_devices {
  52. struct _ATOM_SUPPORTED_DEVICES_INFO info;
  53. struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  54. struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  55. };
  56. static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
  57. *dev, uint8_t id)
  58. {
  59. struct radeon_device *rdev = dev->dev_private;
  60. struct atom_context *ctx = rdev->mode_info.atom_context;
  61. ATOM_GPIO_I2C_ASSIGMENT gpio;
  62. struct radeon_i2c_bus_rec i2c;
  63. int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  64. struct _ATOM_GPIO_I2C_INFO *i2c_info;
  65. uint16_t data_offset;
  66. memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  67. i2c.valid = false;
  68. atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  69. i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  70. gpio = i2c_info->asGPIO_Info[id];
  71. i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
  72. i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
  73. i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
  74. i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
  75. i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
  76. i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
  77. i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
  78. i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
  79. i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
  80. i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
  81. i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
  82. i2c.put_data_mask = (1 << gpio.ucDataEnShift);
  83. i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
  84. i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
  85. i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
  86. i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
  87. i2c.valid = true;
  88. return i2c;
  89. }
  90. static bool radeon_atom_apply_quirks(struct drm_device *dev,
  91. uint32_t supported_device,
  92. int *connector_type,
  93. struct radeon_i2c_bus_rec *i2c_bus,
  94. uint16_t *line_mux)
  95. {
  96. /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
  97. if ((dev->pdev->device == 0x791e) &&
  98. (dev->pdev->subsystem_vendor == 0x1043) &&
  99. (dev->pdev->subsystem_device == 0x826d)) {
  100. if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
  101. (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
  102. *connector_type = DRM_MODE_CONNECTOR_DVID;
  103. }
  104. /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
  105. if ((dev->pdev->device == 0x7941) &&
  106. (dev->pdev->subsystem_vendor == 0x147b) &&
  107. (dev->pdev->subsystem_device == 0x2412)) {
  108. if (*connector_type == DRM_MODE_CONNECTOR_DVII)
  109. return false;
  110. }
  111. /* Falcon NW laptop lists vga ddc line for LVDS */
  112. if ((dev->pdev->device == 0x5653) &&
  113. (dev->pdev->subsystem_vendor == 0x1462) &&
  114. (dev->pdev->subsystem_device == 0x0291)) {
  115. if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
  116. i2c_bus->valid = false;
  117. *line_mux = 53;
  118. }
  119. }
  120. /* Funky macbooks */
  121. if ((dev->pdev->device == 0x71C5) &&
  122. (dev->pdev->subsystem_vendor == 0x106b) &&
  123. (dev->pdev->subsystem_device == 0x0080)) {
  124. if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
  125. (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
  126. return false;
  127. }
  128. /* ASUS HD 3600 XT board lists the DVI port as HDMI */
  129. if ((dev->pdev->device == 0x9598) &&
  130. (dev->pdev->subsystem_vendor == 0x1043) &&
  131. (dev->pdev->subsystem_device == 0x01da)) {
  132. if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
  133. *connector_type = DRM_MODE_CONNECTOR_DVII;
  134. }
  135. }
  136. /* ASUS HD 3450 board lists the DVI port as HDMI */
  137. if ((dev->pdev->device == 0x95C5) &&
  138. (dev->pdev->subsystem_vendor == 0x1043) &&
  139. (dev->pdev->subsystem_device == 0x01e2)) {
  140. if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
  141. *connector_type = DRM_MODE_CONNECTOR_DVII;
  142. }
  143. }
  144. /* some BIOSes seem to report DAC on HDMI - usually this is a board with
  145. * HDMI + VGA reporting as HDMI
  146. */
  147. if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
  148. if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
  149. *connector_type = DRM_MODE_CONNECTOR_VGA;
  150. *line_mux = 0;
  151. }
  152. }
  153. return true;
  154. }
  155. const int supported_devices_connector_convert[] = {
  156. DRM_MODE_CONNECTOR_Unknown,
  157. DRM_MODE_CONNECTOR_VGA,
  158. DRM_MODE_CONNECTOR_DVII,
  159. DRM_MODE_CONNECTOR_DVID,
  160. DRM_MODE_CONNECTOR_DVIA,
  161. DRM_MODE_CONNECTOR_SVIDEO,
  162. DRM_MODE_CONNECTOR_Composite,
  163. DRM_MODE_CONNECTOR_LVDS,
  164. DRM_MODE_CONNECTOR_Unknown,
  165. DRM_MODE_CONNECTOR_Unknown,
  166. DRM_MODE_CONNECTOR_HDMIA,
  167. DRM_MODE_CONNECTOR_HDMIB,
  168. DRM_MODE_CONNECTOR_Unknown,
  169. DRM_MODE_CONNECTOR_Unknown,
  170. DRM_MODE_CONNECTOR_9PinDIN,
  171. DRM_MODE_CONNECTOR_DisplayPort
  172. };
  173. const int object_connector_convert[] = {
  174. DRM_MODE_CONNECTOR_Unknown,
  175. DRM_MODE_CONNECTOR_DVII,
  176. DRM_MODE_CONNECTOR_DVII,
  177. DRM_MODE_CONNECTOR_DVID,
  178. DRM_MODE_CONNECTOR_DVID,
  179. DRM_MODE_CONNECTOR_VGA,
  180. DRM_MODE_CONNECTOR_Composite,
  181. DRM_MODE_CONNECTOR_SVIDEO,
  182. DRM_MODE_CONNECTOR_Unknown,
  183. DRM_MODE_CONNECTOR_Unknown,
  184. DRM_MODE_CONNECTOR_9PinDIN,
  185. DRM_MODE_CONNECTOR_Unknown,
  186. DRM_MODE_CONNECTOR_HDMIA,
  187. DRM_MODE_CONNECTOR_HDMIB,
  188. DRM_MODE_CONNECTOR_LVDS,
  189. DRM_MODE_CONNECTOR_9PinDIN,
  190. DRM_MODE_CONNECTOR_Unknown,
  191. DRM_MODE_CONNECTOR_Unknown,
  192. DRM_MODE_CONNECTOR_Unknown,
  193. DRM_MODE_CONNECTOR_DisplayPort
  194. };
  195. bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
  196. {
  197. struct radeon_device *rdev = dev->dev_private;
  198. struct radeon_mode_info *mode_info = &rdev->mode_info;
  199. struct atom_context *ctx = mode_info->atom_context;
  200. int index = GetIndexIntoMasterTable(DATA, Object_Header);
  201. uint16_t size, data_offset;
  202. uint8_t frev, crev, line_mux = 0;
  203. ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
  204. ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
  205. ATOM_OBJECT_HEADER *obj_header;
  206. int i, j, path_size, device_support;
  207. int connector_type;
  208. uint16_t igp_lane_info, conn_id;
  209. bool linkb;
  210. struct radeon_i2c_bus_rec ddc_bus;
  211. atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
  212. if (data_offset == 0)
  213. return false;
  214. if (crev < 2)
  215. return false;
  216. obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
  217. path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
  218. (ctx->bios + data_offset +
  219. le16_to_cpu(obj_header->usDisplayPathTableOffset));
  220. con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
  221. (ctx->bios + data_offset +
  222. le16_to_cpu(obj_header->usConnectorObjectTableOffset));
  223. device_support = le16_to_cpu(obj_header->usDeviceSupport);
  224. path_size = 0;
  225. for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
  226. uint8_t *addr = (uint8_t *) path_obj->asDispPath;
  227. ATOM_DISPLAY_OBJECT_PATH *path;
  228. addr += path_size;
  229. path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
  230. path_size += le16_to_cpu(path->usSize);
  231. linkb = false;
  232. if (device_support & le16_to_cpu(path->usDeviceTag)) {
  233. uint8_t con_obj_id, con_obj_num, con_obj_type;
  234. con_obj_id =
  235. (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
  236. >> OBJECT_ID_SHIFT;
  237. con_obj_num =
  238. (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
  239. >> ENUM_ID_SHIFT;
  240. con_obj_type =
  241. (le16_to_cpu(path->usConnObjectId) &
  242. OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
  243. if ((le16_to_cpu(path->usDeviceTag) ==
  244. ATOM_DEVICE_TV1_SUPPORT)
  245. || (le16_to_cpu(path->usDeviceTag) ==
  246. ATOM_DEVICE_TV2_SUPPORT)
  247. || (le16_to_cpu(path->usDeviceTag) ==
  248. ATOM_DEVICE_CV_SUPPORT))
  249. continue;
  250. if ((rdev->family == CHIP_RS780) &&
  251. (con_obj_id ==
  252. CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
  253. uint16_t igp_offset = 0;
  254. ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
  255. index =
  256. GetIndexIntoMasterTable(DATA,
  257. IntegratedSystemInfo);
  258. atom_parse_data_header(ctx, index, &size, &frev,
  259. &crev, &igp_offset);
  260. if (crev >= 2) {
  261. igp_obj =
  262. (ATOM_INTEGRATED_SYSTEM_INFO_V2
  263. *) (ctx->bios + igp_offset);
  264. if (igp_obj) {
  265. uint32_t slot_config, ct;
  266. if (con_obj_num == 1)
  267. slot_config =
  268. igp_obj->
  269. ulDDISlot1Config;
  270. else
  271. slot_config =
  272. igp_obj->
  273. ulDDISlot2Config;
  274. ct = (slot_config >> 16) & 0xff;
  275. connector_type =
  276. object_connector_convert
  277. [ct];
  278. igp_lane_info =
  279. slot_config & 0xffff;
  280. } else
  281. continue;
  282. } else
  283. continue;
  284. } else {
  285. igp_lane_info = 0;
  286. connector_type =
  287. object_connector_convert[con_obj_id];
  288. }
  289. if (connector_type == DRM_MODE_CONNECTOR_Unknown)
  290. continue;
  291. for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
  292. j++) {
  293. uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
  294. enc_obj_id =
  295. (le16_to_cpu(path->usGraphicObjIds[j]) &
  296. OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
  297. enc_obj_num =
  298. (le16_to_cpu(path->usGraphicObjIds[j]) &
  299. ENUM_ID_MASK) >> ENUM_ID_SHIFT;
  300. enc_obj_type =
  301. (le16_to_cpu(path->usGraphicObjIds[j]) &
  302. OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
  303. /* FIXME: add support for router objects */
  304. if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
  305. if (enc_obj_num == 2)
  306. linkb = true;
  307. else
  308. linkb = false;
  309. radeon_add_atom_encoder(dev,
  310. enc_obj_id,
  311. le16_to_cpu
  312. (path->
  313. usDeviceTag));
  314. }
  315. }
  316. /* look up gpio for ddc */
  317. if ((le16_to_cpu(path->usDeviceTag) &
  318. (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
  319. == 0) {
  320. for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
  321. if (le16_to_cpu(path->usConnObjectId) ==
  322. le16_to_cpu(con_obj->asObjects[j].
  323. usObjectID)) {
  324. ATOM_COMMON_RECORD_HEADER
  325. *record =
  326. (ATOM_COMMON_RECORD_HEADER
  327. *)
  328. (ctx->bios + data_offset +
  329. le16_to_cpu(con_obj->
  330. asObjects[j].
  331. usRecordOffset));
  332. ATOM_I2C_RECORD *i2c_record;
  333. while (record->ucRecordType > 0
  334. && record->
  335. ucRecordType <=
  336. ATOM_MAX_OBJECT_RECORD_NUMBER) {
  337. switch (record->
  338. ucRecordType) {
  339. case ATOM_I2C_RECORD_TYPE:
  340. i2c_record =
  341. (ATOM_I2C_RECORD
  342. *) record;
  343. line_mux =
  344. i2c_record->
  345. sucI2cId.
  346. bfI2C_LineMux;
  347. break;
  348. }
  349. record =
  350. (ATOM_COMMON_RECORD_HEADER
  351. *) ((char *)record
  352. +
  353. record->
  354. ucRecordSize);
  355. }
  356. break;
  357. }
  358. }
  359. } else
  360. line_mux = 0;
  361. if ((le16_to_cpu(path->usDeviceTag) ==
  362. ATOM_DEVICE_TV1_SUPPORT)
  363. || (le16_to_cpu(path->usDeviceTag) ==
  364. ATOM_DEVICE_TV2_SUPPORT)
  365. || (le16_to_cpu(path->usDeviceTag) ==
  366. ATOM_DEVICE_CV_SUPPORT))
  367. ddc_bus.valid = false;
  368. else
  369. ddc_bus = radeon_lookup_gpio(dev, line_mux);
  370. conn_id = le16_to_cpu(path->usConnObjectId);
  371. if (!radeon_atom_apply_quirks
  372. (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
  373. &ddc_bus, &conn_id))
  374. continue;
  375. radeon_add_atom_connector(dev,
  376. conn_id,
  377. le16_to_cpu(path->
  378. usDeviceTag),
  379. connector_type, &ddc_bus,
  380. linkb, igp_lane_info);
  381. }
  382. }
  383. radeon_link_encoder_connector(dev);
  384. return true;
  385. }
  386. struct bios_connector {
  387. bool valid;
  388. uint16_t line_mux;
  389. uint16_t devices;
  390. int connector_type;
  391. struct radeon_i2c_bus_rec ddc_bus;
  392. };
  393. bool radeon_get_atom_connector_info_from_supported_devices_table(struct
  394. drm_device
  395. *dev)
  396. {
  397. struct radeon_device *rdev = dev->dev_private;
  398. struct radeon_mode_info *mode_info = &rdev->mode_info;
  399. struct atom_context *ctx = mode_info->atom_context;
  400. int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
  401. uint16_t size, data_offset;
  402. uint8_t frev, crev;
  403. uint16_t device_support;
  404. uint8_t dac;
  405. union atom_supported_devices *supported_devices;
  406. int i, j;
  407. struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
  408. atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
  409. supported_devices =
  410. (union atom_supported_devices *)(ctx->bios + data_offset);
  411. device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
  412. for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
  413. ATOM_CONNECTOR_INFO_I2C ci =
  414. supported_devices->info.asConnInfo[i];
  415. bios_connectors[i].valid = false;
  416. if (!(device_support & (1 << i))) {
  417. continue;
  418. }
  419. if (i == ATOM_DEVICE_CV_INDEX) {
  420. DRM_DEBUG("Skipping Component Video\n");
  421. continue;
  422. }
  423. bios_connectors[i].connector_type =
  424. supported_devices_connector_convert[ci.sucConnectorInfo.
  425. sbfAccess.
  426. bfConnectorType];
  427. if (bios_connectors[i].connector_type ==
  428. DRM_MODE_CONNECTOR_Unknown)
  429. continue;
  430. dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
  431. if ((rdev->family == CHIP_RS690) ||
  432. (rdev->family == CHIP_RS740)) {
  433. if ((i == ATOM_DEVICE_DFP2_INDEX)
  434. && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
  435. bios_connectors[i].line_mux =
  436. ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
  437. else if ((i == ATOM_DEVICE_DFP3_INDEX)
  438. && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
  439. bios_connectors[i].line_mux =
  440. ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
  441. else
  442. bios_connectors[i].line_mux =
  443. ci.sucI2cId.sbfAccess.bfI2C_LineMux;
  444. } else
  445. bios_connectors[i].line_mux =
  446. ci.sucI2cId.sbfAccess.bfI2C_LineMux;
  447. /* give tv unique connector ids */
  448. if (i == ATOM_DEVICE_TV1_INDEX) {
  449. bios_connectors[i].ddc_bus.valid = false;
  450. bios_connectors[i].line_mux = 50;
  451. } else if (i == ATOM_DEVICE_TV2_INDEX) {
  452. bios_connectors[i].ddc_bus.valid = false;
  453. bios_connectors[i].line_mux = 51;
  454. } else if (i == ATOM_DEVICE_CV_INDEX) {
  455. bios_connectors[i].ddc_bus.valid = false;
  456. bios_connectors[i].line_mux = 52;
  457. } else
  458. bios_connectors[i].ddc_bus =
  459. radeon_lookup_gpio(dev,
  460. bios_connectors[i].line_mux);
  461. /* Always set the connector type to VGA for CRT1/CRT2. if they are
  462. * shared with a DVI port, we'll pick up the DVI connector when we
  463. * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
  464. */
  465. if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
  466. bios_connectors[i].connector_type =
  467. DRM_MODE_CONNECTOR_VGA;
  468. if (!radeon_atom_apply_quirks
  469. (dev, (1 << i), &bios_connectors[i].connector_type,
  470. &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
  471. continue;
  472. bios_connectors[i].valid = true;
  473. bios_connectors[i].devices = (1 << i);
  474. if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
  475. radeon_add_atom_encoder(dev,
  476. radeon_get_encoder_id(dev,
  477. (1 << i),
  478. dac),
  479. (1 << i));
  480. else
  481. radeon_add_legacy_encoder(dev,
  482. radeon_get_encoder_id(dev,
  483. (1 <<
  484. i),
  485. dac),
  486. (1 << i));
  487. }
  488. /* combine shared connectors */
  489. for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
  490. if (bios_connectors[i].valid) {
  491. for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
  492. if (bios_connectors[j].valid && (i != j)) {
  493. if (bios_connectors[i].line_mux ==
  494. bios_connectors[j].line_mux) {
  495. if (((bios_connectors[i].
  496. devices &
  497. (ATOM_DEVICE_DFP_SUPPORT))
  498. && (bios_connectors[j].
  499. devices &
  500. (ATOM_DEVICE_CRT_SUPPORT)))
  501. ||
  502. ((bios_connectors[j].
  503. devices &
  504. (ATOM_DEVICE_DFP_SUPPORT))
  505. && (bios_connectors[i].
  506. devices &
  507. (ATOM_DEVICE_CRT_SUPPORT)))) {
  508. bios_connectors[i].
  509. devices |=
  510. bios_connectors[j].
  511. devices;
  512. bios_connectors[i].
  513. connector_type =
  514. DRM_MODE_CONNECTOR_DVII;
  515. bios_connectors[j].
  516. valid = false;
  517. }
  518. }
  519. }
  520. }
  521. }
  522. }
  523. /* add the connectors */
  524. for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
  525. if (bios_connectors[i].valid)
  526. radeon_add_atom_connector(dev,
  527. bios_connectors[i].line_mux,
  528. bios_connectors[i].devices,
  529. bios_connectors[i].
  530. connector_type,
  531. &bios_connectors[i].ddc_bus,
  532. false, 0);
  533. }
  534. radeon_link_encoder_connector(dev);
  535. return true;
  536. }
  537. union firmware_info {
  538. ATOM_FIRMWARE_INFO info;
  539. ATOM_FIRMWARE_INFO_V1_2 info_12;
  540. ATOM_FIRMWARE_INFO_V1_3 info_13;
  541. ATOM_FIRMWARE_INFO_V1_4 info_14;
  542. };
  543. bool radeon_atom_get_clock_info(struct drm_device *dev)
  544. {
  545. struct radeon_device *rdev = dev->dev_private;
  546. struct radeon_mode_info *mode_info = &rdev->mode_info;
  547. int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
  548. union firmware_info *firmware_info;
  549. uint8_t frev, crev;
  550. struct radeon_pll *p1pll = &rdev->clock.p1pll;
  551. struct radeon_pll *p2pll = &rdev->clock.p2pll;
  552. struct radeon_pll *spll = &rdev->clock.spll;
  553. struct radeon_pll *mpll = &rdev->clock.mpll;
  554. uint16_t data_offset;
  555. atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
  556. &crev, &data_offset);
  557. firmware_info =
  558. (union firmware_info *)(mode_info->atom_context->bios +
  559. data_offset);
  560. if (firmware_info) {
  561. /* pixel clocks */
  562. p1pll->reference_freq =
  563. le16_to_cpu(firmware_info->info.usReferenceClock);
  564. p1pll->reference_div = 0;
  565. p1pll->pll_out_min =
  566. le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
  567. p1pll->pll_out_max =
  568. le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
  569. if (p1pll->pll_out_min == 0) {
  570. if (ASIC_IS_AVIVO(rdev))
  571. p1pll->pll_out_min = 64800;
  572. else
  573. p1pll->pll_out_min = 20000;
  574. }
  575. p1pll->pll_in_min =
  576. le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
  577. p1pll->pll_in_max =
  578. le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
  579. *p2pll = *p1pll;
  580. /* system clock */
  581. spll->reference_freq =
  582. le16_to_cpu(firmware_info->info.usReferenceClock);
  583. spll->reference_div = 0;
  584. spll->pll_out_min =
  585. le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
  586. spll->pll_out_max =
  587. le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
  588. /* ??? */
  589. if (spll->pll_out_min == 0) {
  590. if (ASIC_IS_AVIVO(rdev))
  591. spll->pll_out_min = 64800;
  592. else
  593. spll->pll_out_min = 20000;
  594. }
  595. spll->pll_in_min =
  596. le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
  597. spll->pll_in_max =
  598. le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
  599. /* memory clock */
  600. mpll->reference_freq =
  601. le16_to_cpu(firmware_info->info.usReferenceClock);
  602. mpll->reference_div = 0;
  603. mpll->pll_out_min =
  604. le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
  605. mpll->pll_out_max =
  606. le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
  607. /* ??? */
  608. if (mpll->pll_out_min == 0) {
  609. if (ASIC_IS_AVIVO(rdev))
  610. mpll->pll_out_min = 64800;
  611. else
  612. mpll->pll_out_min = 20000;
  613. }
  614. mpll->pll_in_min =
  615. le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
  616. mpll->pll_in_max =
  617. le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
  618. rdev->clock.default_sclk =
  619. le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
  620. rdev->clock.default_mclk =
  621. le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
  622. return true;
  623. }
  624. return false;
  625. }
  626. struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
  627. radeon_encoder
  628. *encoder)
  629. {
  630. struct drm_device *dev = encoder->base.dev;
  631. struct radeon_device *rdev = dev->dev_private;
  632. struct radeon_mode_info *mode_info = &rdev->mode_info;
  633. int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
  634. uint16_t data_offset;
  635. struct _ATOM_TMDS_INFO *tmds_info;
  636. uint8_t frev, crev;
  637. uint16_t maxfreq;
  638. int i;
  639. struct radeon_encoder_int_tmds *tmds = NULL;
  640. atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
  641. &crev, &data_offset);
  642. tmds_info =
  643. (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
  644. data_offset);
  645. if (tmds_info) {
  646. tmds =
  647. kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
  648. if (!tmds)
  649. return NULL;
  650. maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
  651. for (i = 0; i < 4; i++) {
  652. tmds->tmds_pll[i].freq =
  653. le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
  654. tmds->tmds_pll[i].value =
  655. tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
  656. tmds->tmds_pll[i].value |=
  657. (tmds_info->asMiscInfo[i].
  658. ucPLL_VCO_Gain & 0x3f) << 6;
  659. tmds->tmds_pll[i].value |=
  660. (tmds_info->asMiscInfo[i].
  661. ucPLL_DutyCycle & 0xf) << 12;
  662. tmds->tmds_pll[i].value |=
  663. (tmds_info->asMiscInfo[i].
  664. ucPLL_VoltageSwing & 0xf) << 16;
  665. DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
  666. tmds->tmds_pll[i].freq,
  667. tmds->tmds_pll[i].value);
  668. if (maxfreq == tmds->tmds_pll[i].freq) {
  669. tmds->tmds_pll[i].freq = 0xffffffff;
  670. break;
  671. }
  672. }
  673. }
  674. return tmds;
  675. }
  676. union lvds_info {
  677. struct _ATOM_LVDS_INFO info;
  678. struct _ATOM_LVDS_INFO_V12 info_12;
  679. };
  680. struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
  681. radeon_encoder
  682. *encoder)
  683. {
  684. struct drm_device *dev = encoder->base.dev;
  685. struct radeon_device *rdev = dev->dev_private;
  686. struct radeon_mode_info *mode_info = &rdev->mode_info;
  687. int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
  688. uint16_t data_offset;
  689. union lvds_info *lvds_info;
  690. uint8_t frev, crev;
  691. struct radeon_encoder_atom_dig *lvds = NULL;
  692. atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
  693. &crev, &data_offset);
  694. lvds_info =
  695. (union lvds_info *)(mode_info->atom_context->bios + data_offset);
  696. if (lvds_info) {
  697. lvds =
  698. kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
  699. if (!lvds)
  700. return NULL;
  701. lvds->native_mode.dotclock =
  702. le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
  703. lvds->native_mode.panel_xres =
  704. le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
  705. lvds->native_mode.panel_yres =
  706. le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
  707. lvds->native_mode.hblank =
  708. le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
  709. lvds->native_mode.hoverplus =
  710. le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
  711. lvds->native_mode.hsync_width =
  712. le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
  713. lvds->native_mode.vblank =
  714. le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
  715. lvds->native_mode.voverplus =
  716. le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
  717. lvds->native_mode.vsync_width =
  718. le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
  719. lvds->panel_pwr_delay =
  720. le16_to_cpu(lvds_info->info.usOffDelayInMs);
  721. lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
  722. encoder->native_mode = lvds->native_mode;
  723. }
  724. return lvds;
  725. }
  726. struct radeon_encoder_primary_dac *
  727. radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
  728. {
  729. struct drm_device *dev = encoder->base.dev;
  730. struct radeon_device *rdev = dev->dev_private;
  731. struct radeon_mode_info *mode_info = &rdev->mode_info;
  732. int index = GetIndexIntoMasterTable(DATA, CompassionateData);
  733. uint16_t data_offset;
  734. struct _COMPASSIONATE_DATA *dac_info;
  735. uint8_t frev, crev;
  736. uint8_t bg, dac;
  737. struct radeon_encoder_primary_dac *p_dac = NULL;
  738. atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
  739. dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
  740. if (dac_info) {
  741. p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
  742. if (!p_dac)
  743. return NULL;
  744. bg = dac_info->ucDAC1_BG_Adjustment;
  745. dac = dac_info->ucDAC1_DAC_Adjustment;
  746. p_dac->ps2_pdac_adj = (bg << 8) | (dac);
  747. }
  748. return p_dac;
  749. }
  750. bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  751. SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
  752. int32_t *pixel_clock)
  753. {
  754. struct radeon_mode_info *mode_info = &rdev->mode_info;
  755. ATOM_ANALOG_TV_INFO *tv_info;
  756. ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
  757. ATOM_DTD_FORMAT *dtd_timings;
  758. int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
  759. u8 frev, crev;
  760. uint16_t data_offset;
  761. atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
  762. switch (crev) {
  763. case 1:
  764. tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
  765. if (index > MAX_SUPPORTED_TV_TIMING)
  766. return false;
  767. crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
  768. crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
  769. crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
  770. crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
  771. crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
  772. crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
  773. crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
  774. crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
  775. crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
  776. crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
  777. crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
  778. crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
  779. crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
  780. *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
  781. if (index == 1) {
  782. /* PAL timings appear to have wrong values for totals */
  783. crtc_timing->usH_Total -= 1;
  784. crtc_timing->usV_Total -= 1;
  785. }
  786. break;
  787. case 2:
  788. tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
  789. if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
  790. return false;
  791. dtd_timings = &tv_info_v1_2->aModeTimings[index];
  792. crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
  793. crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
  794. crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
  795. crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
  796. crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
  797. crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
  798. crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
  799. crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
  800. crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
  801. *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
  802. break;
  803. }
  804. return true;
  805. }
  806. struct radeon_encoder_tv_dac *
  807. radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
  808. {
  809. struct drm_device *dev = encoder->base.dev;
  810. struct radeon_device *rdev = dev->dev_private;
  811. struct radeon_mode_info *mode_info = &rdev->mode_info;
  812. int index = GetIndexIntoMasterTable(DATA, CompassionateData);
  813. uint16_t data_offset;
  814. struct _COMPASSIONATE_DATA *dac_info;
  815. uint8_t frev, crev;
  816. uint8_t bg, dac;
  817. struct radeon_encoder_tv_dac *tv_dac = NULL;
  818. atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
  819. dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
  820. if (dac_info) {
  821. tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
  822. if (!tv_dac)
  823. return NULL;
  824. bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
  825. dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
  826. tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
  827. bg = dac_info->ucDAC2_PAL_BG_Adjustment;
  828. dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
  829. tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
  830. bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
  831. dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
  832. tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
  833. }
  834. return tv_dac;
  835. }
  836. void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
  837. {
  838. DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
  839. int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
  840. args.ucEnable = enable;
  841. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  842. }
  843. void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
  844. {
  845. ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
  846. int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
  847. args.ucEnable = enable;
  848. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  849. }
  850. void radeon_atom_set_engine_clock(struct radeon_device *rdev,
  851. uint32_t eng_clock)
  852. {
  853. SET_ENGINE_CLOCK_PS_ALLOCATION args;
  854. int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
  855. args.ulTargetEngineClock = eng_clock; /* 10 khz */
  856. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  857. }
  858. void radeon_atom_set_memory_clock(struct radeon_device *rdev,
  859. uint32_t mem_clock)
  860. {
  861. SET_MEMORY_CLOCK_PS_ALLOCATION args;
  862. int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
  863. if (rdev->flags & RADEON_IS_IGP)
  864. return;
  865. args.ulTargetMemoryClock = mem_clock; /* 10 khz */
  866. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  867. }
  868. void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
  869. {
  870. struct radeon_device *rdev = dev->dev_private;
  871. uint32_t bios_2_scratch, bios_6_scratch;
  872. if (rdev->family >= CHIP_R600) {
  873. bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  874. bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
  875. } else {
  876. bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  877. bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
  878. }
  879. /* let the bios control the backlight */
  880. bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
  881. /* tell the bios not to handle mode switching */
  882. bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
  883. if (rdev->family >= CHIP_R600) {
  884. WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  885. WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
  886. } else {
  887. WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  888. WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
  889. }
  890. }
  891. void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
  892. {
  893. uint32_t scratch_reg;
  894. int i;
  895. if (rdev->family >= CHIP_R600)
  896. scratch_reg = R600_BIOS_0_SCRATCH;
  897. else
  898. scratch_reg = RADEON_BIOS_0_SCRATCH;
  899. for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
  900. rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
  901. }
  902. void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
  903. {
  904. uint32_t scratch_reg;
  905. int i;
  906. if (rdev->family >= CHIP_R600)
  907. scratch_reg = R600_BIOS_0_SCRATCH;
  908. else
  909. scratch_reg = RADEON_BIOS_0_SCRATCH;
  910. for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
  911. WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
  912. }
  913. void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
  914. {
  915. struct drm_device *dev = encoder->dev;
  916. struct radeon_device *rdev = dev->dev_private;
  917. uint32_t bios_6_scratch;
  918. if (rdev->family >= CHIP_R600)
  919. bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
  920. else
  921. bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
  922. if (lock)
  923. bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
  924. else
  925. bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
  926. if (rdev->family >= CHIP_R600)
  927. WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
  928. else
  929. WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
  930. }
  931. /* at some point we may want to break this out into individual functions */
  932. void
  933. radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
  934. struct drm_encoder *encoder,
  935. bool connected)
  936. {
  937. struct drm_device *dev = connector->dev;
  938. struct radeon_device *rdev = dev->dev_private;
  939. struct radeon_connector *radeon_connector =
  940. to_radeon_connector(connector);
  941. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  942. uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
  943. if (rdev->family >= CHIP_R600) {
  944. bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
  945. bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
  946. bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
  947. } else {
  948. bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
  949. bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
  950. bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
  951. }
  952. if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
  953. (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
  954. if (connected) {
  955. DRM_DEBUG("TV1 connected\n");
  956. bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
  957. bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
  958. } else {
  959. DRM_DEBUG("TV1 disconnected\n");
  960. bios_0_scratch &= ~ATOM_S0_TV1_MASK;
  961. bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
  962. bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
  963. }
  964. }
  965. if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
  966. (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
  967. if (connected) {
  968. DRM_DEBUG("CV connected\n");
  969. bios_3_scratch |= ATOM_S3_CV_ACTIVE;
  970. bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
  971. } else {
  972. DRM_DEBUG("CV disconnected\n");
  973. bios_0_scratch &= ~ATOM_S0_CV_MASK;
  974. bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
  975. bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
  976. }
  977. }
  978. if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
  979. (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
  980. if (connected) {
  981. DRM_DEBUG("LCD1 connected\n");
  982. bios_0_scratch |= ATOM_S0_LCD1;
  983. bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
  984. bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
  985. } else {
  986. DRM_DEBUG("LCD1 disconnected\n");
  987. bios_0_scratch &= ~ATOM_S0_LCD1;
  988. bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
  989. bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
  990. }
  991. }
  992. if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
  993. (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
  994. if (connected) {
  995. DRM_DEBUG("CRT1 connected\n");
  996. bios_0_scratch |= ATOM_S0_CRT1_COLOR;
  997. bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
  998. bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
  999. } else {
  1000. DRM_DEBUG("CRT1 disconnected\n");
  1001. bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
  1002. bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
  1003. bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
  1004. }
  1005. }
  1006. if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
  1007. (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
  1008. if (connected) {
  1009. DRM_DEBUG("CRT2 connected\n");
  1010. bios_0_scratch |= ATOM_S0_CRT2_COLOR;
  1011. bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
  1012. bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
  1013. } else {
  1014. DRM_DEBUG("CRT2 disconnected\n");
  1015. bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
  1016. bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
  1017. bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
  1018. }
  1019. }
  1020. if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
  1021. (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
  1022. if (connected) {
  1023. DRM_DEBUG("DFP1 connected\n");
  1024. bios_0_scratch |= ATOM_S0_DFP1;
  1025. bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
  1026. bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
  1027. } else {
  1028. DRM_DEBUG("DFP1 disconnected\n");
  1029. bios_0_scratch &= ~ATOM_S0_DFP1;
  1030. bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
  1031. bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
  1032. }
  1033. }
  1034. if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
  1035. (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
  1036. if (connected) {
  1037. DRM_DEBUG("DFP2 connected\n");
  1038. bios_0_scratch |= ATOM_S0_DFP2;
  1039. bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
  1040. bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
  1041. } else {
  1042. DRM_DEBUG("DFP2 disconnected\n");
  1043. bios_0_scratch &= ~ATOM_S0_DFP2;
  1044. bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
  1045. bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
  1046. }
  1047. }
  1048. if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
  1049. (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
  1050. if (connected) {
  1051. DRM_DEBUG("DFP3 connected\n");
  1052. bios_0_scratch |= ATOM_S0_DFP3;
  1053. bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
  1054. bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
  1055. } else {
  1056. DRM_DEBUG("DFP3 disconnected\n");
  1057. bios_0_scratch &= ~ATOM_S0_DFP3;
  1058. bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
  1059. bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
  1060. }
  1061. }
  1062. if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
  1063. (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
  1064. if (connected) {
  1065. DRM_DEBUG("DFP4 connected\n");
  1066. bios_0_scratch |= ATOM_S0_DFP4;
  1067. bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
  1068. bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
  1069. } else {
  1070. DRM_DEBUG("DFP4 disconnected\n");
  1071. bios_0_scratch &= ~ATOM_S0_DFP4;
  1072. bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
  1073. bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
  1074. }
  1075. }
  1076. if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
  1077. (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
  1078. if (connected) {
  1079. DRM_DEBUG("DFP5 connected\n");
  1080. bios_0_scratch |= ATOM_S0_DFP5;
  1081. bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
  1082. bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
  1083. } else {
  1084. DRM_DEBUG("DFP5 disconnected\n");
  1085. bios_0_scratch &= ~ATOM_S0_DFP5;
  1086. bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
  1087. bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
  1088. }
  1089. }
  1090. if (rdev->family >= CHIP_R600) {
  1091. WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
  1092. WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
  1093. WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
  1094. } else {
  1095. WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
  1096. WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
  1097. WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
  1098. }
  1099. }
  1100. void
  1101. radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
  1102. {
  1103. struct drm_device *dev = encoder->dev;
  1104. struct radeon_device *rdev = dev->dev_private;
  1105. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1106. uint32_t bios_3_scratch;
  1107. if (rdev->family >= CHIP_R600)
  1108. bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
  1109. else
  1110. bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
  1111. if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
  1112. bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
  1113. bios_3_scratch |= (crtc << 18);
  1114. }
  1115. if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
  1116. bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
  1117. bios_3_scratch |= (crtc << 24);
  1118. }
  1119. if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
  1120. bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
  1121. bios_3_scratch |= (crtc << 16);
  1122. }
  1123. if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
  1124. bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
  1125. bios_3_scratch |= (crtc << 20);
  1126. }
  1127. if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
  1128. bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
  1129. bios_3_scratch |= (crtc << 17);
  1130. }
  1131. if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
  1132. bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
  1133. bios_3_scratch |= (crtc << 19);
  1134. }
  1135. if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
  1136. bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
  1137. bios_3_scratch |= (crtc << 23);
  1138. }
  1139. if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
  1140. bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
  1141. bios_3_scratch |= (crtc << 25);
  1142. }
  1143. if (rdev->family >= CHIP_R600)
  1144. WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
  1145. else
  1146. WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
  1147. }
  1148. void
  1149. radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
  1150. {
  1151. struct drm_device *dev = encoder->dev;
  1152. struct radeon_device *rdev = dev->dev_private;
  1153. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1154. uint32_t bios_2_scratch;
  1155. if (rdev->family >= CHIP_R600)
  1156. bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  1157. else
  1158. bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  1159. if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
  1160. if (on)
  1161. bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
  1162. else
  1163. bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
  1164. }
  1165. if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
  1166. if (on)
  1167. bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
  1168. else
  1169. bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
  1170. }
  1171. if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
  1172. if (on)
  1173. bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
  1174. else
  1175. bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
  1176. }
  1177. if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
  1178. if (on)
  1179. bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
  1180. else
  1181. bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
  1182. }
  1183. if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
  1184. if (on)
  1185. bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
  1186. else
  1187. bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
  1188. }
  1189. if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
  1190. if (on)
  1191. bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
  1192. else
  1193. bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
  1194. }
  1195. if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
  1196. if (on)
  1197. bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
  1198. else
  1199. bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
  1200. }
  1201. if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
  1202. if (on)
  1203. bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
  1204. else
  1205. bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
  1206. }
  1207. if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
  1208. if (on)
  1209. bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
  1210. else
  1211. bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
  1212. }
  1213. if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
  1214. if (on)
  1215. bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
  1216. else
  1217. bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
  1218. }
  1219. if (rdev->family >= CHIP_R600)
  1220. WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  1221. else
  1222. WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  1223. }