irq.c 5.0 KB

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  1. /* linux/arch/arm/mach-s3c2412/irq.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/ioport.h>
  25. #include <linux/sysdev.h>
  26. #include <asm/hardware.h>
  27. #include <asm/irq.h>
  28. #include <asm/io.h>
  29. #include <asm/mach/irq.h>
  30. #include <asm/arch/regs-irq.h>
  31. #include <asm/arch/regs-gpio.h>
  32. #include <asm/plat-s3c24xx/cpu.h>
  33. #include <asm/plat-s3c24xx/irq.h>
  34. #include <asm/plat-s3c24xx/pm.h>
  35. #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
  36. #define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
  37. /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
  38. * having them turn up in both the INT* and the EINT* registers. Whilst
  39. * both show the status, they both now need to be acked when the IRQs
  40. * go off.
  41. */
  42. static void
  43. s3c2412_irq_mask(unsigned int irqno)
  44. {
  45. unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
  46. unsigned long mask;
  47. mask = __raw_readl(S3C2410_INTMSK);
  48. __raw_writel(mask | bitval, S3C2410_INTMSK);
  49. mask = __raw_readl(S3C2412_EINTMASK);
  50. __raw_writel(mask | bitval, S3C2412_EINTMASK);
  51. }
  52. static inline void
  53. s3c2412_irq_ack(unsigned int irqno)
  54. {
  55. unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
  56. __raw_writel(bitval, S3C2412_EINTPEND);
  57. __raw_writel(bitval, S3C2410_SRCPND);
  58. __raw_writel(bitval, S3C2410_INTPND);
  59. }
  60. static inline void
  61. s3c2412_irq_maskack(unsigned int irqno)
  62. {
  63. unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
  64. unsigned long mask;
  65. mask = __raw_readl(S3C2410_INTMSK);
  66. __raw_writel(mask|bitval, S3C2410_INTMSK);
  67. mask = __raw_readl(S3C2412_EINTMASK);
  68. __raw_writel(mask | bitval, S3C2412_EINTMASK);
  69. __raw_writel(bitval, S3C2412_EINTPEND);
  70. __raw_writel(bitval, S3C2410_SRCPND);
  71. __raw_writel(bitval, S3C2410_INTPND);
  72. }
  73. static void
  74. s3c2412_irq_unmask(unsigned int irqno)
  75. {
  76. unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
  77. unsigned long mask;
  78. mask = __raw_readl(S3C2412_EINTMASK);
  79. __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
  80. mask = __raw_readl(S3C2410_INTMSK);
  81. __raw_writel(mask & ~bitval, S3C2410_INTMSK);
  82. }
  83. static struct irq_chip s3c2412_irq_eint0t4 = {
  84. .ack = s3c2412_irq_ack,
  85. .mask = s3c2412_irq_mask,
  86. .unmask = s3c2412_irq_unmask,
  87. .set_wake = s3c_irq_wake,
  88. .set_type = s3c_irqext_type,
  89. };
  90. #define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
  91. /* CF and SDI sub interrupts */
  92. static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
  93. {
  94. unsigned int subsrc, submsk;
  95. subsrc = __raw_readl(S3C2410_SUBSRCPND);
  96. submsk = __raw_readl(S3C2410_INTSUBMSK);
  97. subsrc &= ~submsk;
  98. if (subsrc & INTBIT(IRQ_S3C2412_SDI))
  99. desc_handle_irq(IRQ_S3C2412_SDI, irq_desc + IRQ_S3C2412_SDI);
  100. if (subsrc & INTBIT(IRQ_S3C2412_CF))
  101. desc_handle_irq(IRQ_S3C2412_CF, irq_desc + IRQ_S3C2412_CF);
  102. }
  103. #define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
  104. #define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
  105. static void s3c2412_irq_cfsdi_mask(unsigned int irqno)
  106. {
  107. s3c_irqsub_mask(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
  108. }
  109. static void s3c2412_irq_cfsdi_unmask(unsigned int irqno)
  110. {
  111. s3c_irqsub_unmask(irqno, INTMSK_CFSDI);
  112. }
  113. static void s3c2412_irq_cfsdi_ack(unsigned int irqno)
  114. {
  115. s3c_irqsub_maskack(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
  116. }
  117. static struct irq_chip s3c2412_irq_cfsdi = {
  118. .name = "s3c2412-cfsdi",
  119. .ack = s3c2412_irq_cfsdi_ack,
  120. .mask = s3c2412_irq_cfsdi_mask,
  121. .unmask = s3c2412_irq_cfsdi_unmask,
  122. };
  123. static int s3c2412_irq_add(struct sys_device *sysdev)
  124. {
  125. unsigned int irqno;
  126. for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
  127. set_irq_chip(irqno, &s3c2412_irq_eint0t4);
  128. set_irq_handler(irqno, handle_edge_irq);
  129. set_irq_flags(irqno, IRQF_VALID);
  130. }
  131. /* add demux support for CF/SDI */
  132. set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
  133. for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
  134. set_irq_chip(irqno, &s3c2412_irq_cfsdi);
  135. set_irq_handler(irqno, handle_level_irq);
  136. set_irq_flags(irqno, IRQF_VALID);
  137. }
  138. return 0;
  139. }
  140. static struct sysdev_driver s3c2412_irq_driver = {
  141. .add = s3c2412_irq_add,
  142. .suspend = s3c24xx_irq_suspend,
  143. .resume = s3c24xx_irq_resume,
  144. };
  145. static int s3c2412_irq_init(void)
  146. {
  147. return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver);
  148. }
  149. arch_initcall(s3c2412_irq_init);