mwl8k.c 96 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108
  1. /*
  2. * drivers/net/wireless/mwl8k.c
  3. * Driver for Marvell TOPDOG 802.11 Wireless cards
  4. *
  5. * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/sched.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/list.h>
  17. #include <linux/pci.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <linux/etherdevice.h>
  21. #include <net/mac80211.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/firmware.h>
  24. #include <linux/workqueue.h>
  25. #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
  26. #define MWL8K_NAME KBUILD_MODNAME
  27. #define MWL8K_VERSION "0.11"
  28. /* Register definitions */
  29. #define MWL8K_HIU_GEN_PTR 0x00000c10
  30. #define MWL8K_MODE_STA 0x0000005a
  31. #define MWL8K_MODE_AP 0x000000a5
  32. #define MWL8K_HIU_INT_CODE 0x00000c14
  33. #define MWL8K_FWSTA_READY 0xf0f1f2f4
  34. #define MWL8K_FWAP_READY 0xf1f2f4a5
  35. #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
  36. #define MWL8K_HIU_SCRATCH 0x00000c40
  37. /* Host->device communications */
  38. #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
  39. #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
  40. #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
  41. #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
  42. #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
  43. #define MWL8K_H2A_INT_DUMMY (1 << 20)
  44. #define MWL8K_H2A_INT_RESET (1 << 15)
  45. #define MWL8K_H2A_INT_DOORBELL (1 << 1)
  46. #define MWL8K_H2A_INT_PPA_READY (1 << 0)
  47. /* Device->host communications */
  48. #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
  49. #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
  50. #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
  51. #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
  52. #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
  53. #define MWL8K_A2H_INT_DUMMY (1 << 20)
  54. #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
  55. #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
  56. #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
  57. #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
  58. #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
  59. #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
  60. #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
  61. #define MWL8K_A2H_INT_RX_READY (1 << 1)
  62. #define MWL8K_A2H_INT_TX_DONE (1 << 0)
  63. #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
  64. MWL8K_A2H_INT_CHNL_SWITCHED | \
  65. MWL8K_A2H_INT_QUEUE_EMPTY | \
  66. MWL8K_A2H_INT_RADAR_DETECT | \
  67. MWL8K_A2H_INT_RADIO_ON | \
  68. MWL8K_A2H_INT_RADIO_OFF | \
  69. MWL8K_A2H_INT_MAC_EVENT | \
  70. MWL8K_A2H_INT_OPC_DONE | \
  71. MWL8K_A2H_INT_RX_READY | \
  72. MWL8K_A2H_INT_TX_DONE)
  73. #define MWL8K_RX_QUEUES 1
  74. #define MWL8K_TX_QUEUES 4
  75. struct rxd_ops {
  76. int rxd_size;
  77. void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
  78. void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
  79. int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
  80. __le16 *qos);
  81. };
  82. struct mwl8k_device_info {
  83. char *part_name;
  84. char *helper_image;
  85. char *fw_image;
  86. struct rxd_ops *ap_rxd_ops;
  87. };
  88. struct mwl8k_rx_queue {
  89. int rxd_count;
  90. /* hw receives here */
  91. int head;
  92. /* refill descs here */
  93. int tail;
  94. void *rxd;
  95. dma_addr_t rxd_dma;
  96. struct {
  97. struct sk_buff *skb;
  98. DECLARE_PCI_UNMAP_ADDR(dma)
  99. } *buf;
  100. };
  101. struct mwl8k_tx_queue {
  102. /* hw transmits here */
  103. int head;
  104. /* sw appends here */
  105. int tail;
  106. struct ieee80211_tx_queue_stats stats;
  107. struct mwl8k_tx_desc *txd;
  108. dma_addr_t txd_dma;
  109. struct sk_buff **skb;
  110. };
  111. struct mwl8k_priv {
  112. struct ieee80211_hw *hw;
  113. struct pci_dev *pdev;
  114. struct mwl8k_device_info *device_info;
  115. void __iomem *sram;
  116. void __iomem *regs;
  117. /* firmware */
  118. struct firmware *fw_helper;
  119. struct firmware *fw_ucode;
  120. /* hardware/firmware parameters */
  121. bool ap_fw;
  122. struct rxd_ops *rxd_ops;
  123. /* firmware access */
  124. struct mutex fw_mutex;
  125. struct task_struct *fw_mutex_owner;
  126. int fw_mutex_depth;
  127. struct completion *hostcmd_wait;
  128. /* lock held over TX and TX reap */
  129. spinlock_t tx_lock;
  130. /* TX quiesce completion, protected by fw_mutex and tx_lock */
  131. struct completion *tx_wait;
  132. struct ieee80211_vif *vif;
  133. /* power management status cookie from firmware */
  134. u32 *cookie;
  135. dma_addr_t cookie_dma;
  136. u16 num_mcaddrs;
  137. u8 hw_rev;
  138. u32 fw_rev;
  139. /*
  140. * Running count of TX packets in flight, to avoid
  141. * iterating over the transmit rings each time.
  142. */
  143. int pending_tx_pkts;
  144. struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
  145. struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
  146. /* PHY parameters */
  147. struct ieee80211_supported_band band;
  148. struct ieee80211_channel channels[14];
  149. struct ieee80211_rate rates[14];
  150. bool radio_on;
  151. bool radio_short_preamble;
  152. bool sniffer_enabled;
  153. bool wmm_enabled;
  154. struct work_struct sta_notify_worker;
  155. spinlock_t sta_notify_list_lock;
  156. struct list_head sta_notify_list;
  157. /* XXX need to convert this to handle multiple interfaces */
  158. bool capture_beacon;
  159. u8 capture_bssid[ETH_ALEN];
  160. struct sk_buff *beacon_skb;
  161. /*
  162. * This FJ worker has to be global as it is scheduled from the
  163. * RX handler. At this point we don't know which interface it
  164. * belongs to until the list of bssids waiting to complete join
  165. * is checked.
  166. */
  167. struct work_struct finalize_join_worker;
  168. /* Tasklet to perform TX reclaim. */
  169. struct tasklet_struct poll_tx_task;
  170. /* Tasklet to perform RX. */
  171. struct tasklet_struct poll_rx_task;
  172. };
  173. /* Per interface specific private data */
  174. struct mwl8k_vif {
  175. /* Non AMPDU sequence number assigned by driver. */
  176. u16 seqno;
  177. };
  178. #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
  179. struct mwl8k_sta {
  180. /* Index into station database. Returned by UPDATE_STADB. */
  181. u8 peer_id;
  182. };
  183. #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
  184. static const struct ieee80211_channel mwl8k_channels[] = {
  185. { .center_freq = 2412, .hw_value = 1, },
  186. { .center_freq = 2417, .hw_value = 2, },
  187. { .center_freq = 2422, .hw_value = 3, },
  188. { .center_freq = 2427, .hw_value = 4, },
  189. { .center_freq = 2432, .hw_value = 5, },
  190. { .center_freq = 2437, .hw_value = 6, },
  191. { .center_freq = 2442, .hw_value = 7, },
  192. { .center_freq = 2447, .hw_value = 8, },
  193. { .center_freq = 2452, .hw_value = 9, },
  194. { .center_freq = 2457, .hw_value = 10, },
  195. { .center_freq = 2462, .hw_value = 11, },
  196. { .center_freq = 2467, .hw_value = 12, },
  197. { .center_freq = 2472, .hw_value = 13, },
  198. { .center_freq = 2484, .hw_value = 14, },
  199. };
  200. static const struct ieee80211_rate mwl8k_rates[] = {
  201. { .bitrate = 10, .hw_value = 2, },
  202. { .bitrate = 20, .hw_value = 4, },
  203. { .bitrate = 55, .hw_value = 11, },
  204. { .bitrate = 110, .hw_value = 22, },
  205. { .bitrate = 220, .hw_value = 44, },
  206. { .bitrate = 60, .hw_value = 12, },
  207. { .bitrate = 90, .hw_value = 18, },
  208. { .bitrate = 120, .hw_value = 24, },
  209. { .bitrate = 180, .hw_value = 36, },
  210. { .bitrate = 240, .hw_value = 48, },
  211. { .bitrate = 360, .hw_value = 72, },
  212. { .bitrate = 480, .hw_value = 96, },
  213. { .bitrate = 540, .hw_value = 108, },
  214. { .bitrate = 720, .hw_value = 144, },
  215. };
  216. /* Set or get info from Firmware */
  217. #define MWL8K_CMD_SET 0x0001
  218. #define MWL8K_CMD_GET 0x0000
  219. /* Firmware command codes */
  220. #define MWL8K_CMD_CODE_DNLD 0x0001
  221. #define MWL8K_CMD_GET_HW_SPEC 0x0003
  222. #define MWL8K_CMD_SET_HW_SPEC 0x0004
  223. #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
  224. #define MWL8K_CMD_GET_STAT 0x0014
  225. #define MWL8K_CMD_RADIO_CONTROL 0x001c
  226. #define MWL8K_CMD_RF_TX_POWER 0x001e
  227. #define MWL8K_CMD_RF_ANTENNA 0x0020
  228. #define MWL8K_CMD_SET_BEACON 0x0100
  229. #define MWL8K_CMD_SET_PRE_SCAN 0x0107
  230. #define MWL8K_CMD_SET_POST_SCAN 0x0108
  231. #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
  232. #define MWL8K_CMD_SET_AID 0x010d
  233. #define MWL8K_CMD_SET_RATE 0x0110
  234. #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
  235. #define MWL8K_CMD_RTS_THRESHOLD 0x0113
  236. #define MWL8K_CMD_SET_SLOT 0x0114
  237. #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
  238. #define MWL8K_CMD_SET_WMM_MODE 0x0123
  239. #define MWL8K_CMD_MIMO_CONFIG 0x0125
  240. #define MWL8K_CMD_USE_FIXED_RATE 0x0126
  241. #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
  242. #define MWL8K_CMD_SET_MAC_ADDR 0x0202
  243. #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
  244. #define MWL8K_CMD_BSS_START 0x1100
  245. #define MWL8K_CMD_SET_NEW_STN 0x1111
  246. #define MWL8K_CMD_UPDATE_STADB 0x1123
  247. static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
  248. {
  249. #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
  250. snprintf(buf, bufsize, "%s", #x);\
  251. return buf;\
  252. } while (0)
  253. switch (cmd & ~0x8000) {
  254. MWL8K_CMDNAME(CODE_DNLD);
  255. MWL8K_CMDNAME(GET_HW_SPEC);
  256. MWL8K_CMDNAME(SET_HW_SPEC);
  257. MWL8K_CMDNAME(MAC_MULTICAST_ADR);
  258. MWL8K_CMDNAME(GET_STAT);
  259. MWL8K_CMDNAME(RADIO_CONTROL);
  260. MWL8K_CMDNAME(RF_TX_POWER);
  261. MWL8K_CMDNAME(RF_ANTENNA);
  262. MWL8K_CMDNAME(SET_BEACON);
  263. MWL8K_CMDNAME(SET_PRE_SCAN);
  264. MWL8K_CMDNAME(SET_POST_SCAN);
  265. MWL8K_CMDNAME(SET_RF_CHANNEL);
  266. MWL8K_CMDNAME(SET_AID);
  267. MWL8K_CMDNAME(SET_RATE);
  268. MWL8K_CMDNAME(SET_FINALIZE_JOIN);
  269. MWL8K_CMDNAME(RTS_THRESHOLD);
  270. MWL8K_CMDNAME(SET_SLOT);
  271. MWL8K_CMDNAME(SET_EDCA_PARAMS);
  272. MWL8K_CMDNAME(SET_WMM_MODE);
  273. MWL8K_CMDNAME(MIMO_CONFIG);
  274. MWL8K_CMDNAME(USE_FIXED_RATE);
  275. MWL8K_CMDNAME(ENABLE_SNIFFER);
  276. MWL8K_CMDNAME(SET_MAC_ADDR);
  277. MWL8K_CMDNAME(SET_RATEADAPT_MODE);
  278. MWL8K_CMDNAME(BSS_START);
  279. MWL8K_CMDNAME(SET_NEW_STN);
  280. MWL8K_CMDNAME(UPDATE_STADB);
  281. default:
  282. snprintf(buf, bufsize, "0x%x", cmd);
  283. }
  284. #undef MWL8K_CMDNAME
  285. return buf;
  286. }
  287. /* Hardware and firmware reset */
  288. static void mwl8k_hw_reset(struct mwl8k_priv *priv)
  289. {
  290. iowrite32(MWL8K_H2A_INT_RESET,
  291. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  292. iowrite32(MWL8K_H2A_INT_RESET,
  293. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  294. msleep(20);
  295. }
  296. /* Release fw image */
  297. static void mwl8k_release_fw(struct firmware **fw)
  298. {
  299. if (*fw == NULL)
  300. return;
  301. release_firmware(*fw);
  302. *fw = NULL;
  303. }
  304. static void mwl8k_release_firmware(struct mwl8k_priv *priv)
  305. {
  306. mwl8k_release_fw(&priv->fw_ucode);
  307. mwl8k_release_fw(&priv->fw_helper);
  308. }
  309. /* Request fw image */
  310. static int mwl8k_request_fw(struct mwl8k_priv *priv,
  311. const char *fname, struct firmware **fw)
  312. {
  313. /* release current image */
  314. if (*fw != NULL)
  315. mwl8k_release_fw(fw);
  316. return request_firmware((const struct firmware **)fw,
  317. fname, &priv->pdev->dev);
  318. }
  319. static int mwl8k_request_firmware(struct mwl8k_priv *priv)
  320. {
  321. struct mwl8k_device_info *di = priv->device_info;
  322. int rc;
  323. if (di->helper_image != NULL) {
  324. rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
  325. if (rc) {
  326. printk(KERN_ERR "%s: Error requesting helper "
  327. "firmware file %s\n", pci_name(priv->pdev),
  328. di->helper_image);
  329. return rc;
  330. }
  331. }
  332. rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
  333. if (rc) {
  334. printk(KERN_ERR "%s: Error requesting firmware file %s\n",
  335. pci_name(priv->pdev), di->fw_image);
  336. mwl8k_release_fw(&priv->fw_helper);
  337. return rc;
  338. }
  339. return 0;
  340. }
  341. struct mwl8k_cmd_pkt {
  342. __le16 code;
  343. __le16 length;
  344. __le16 seq_num;
  345. __le16 result;
  346. char payload[0];
  347. } __attribute__((packed));
  348. /*
  349. * Firmware loading.
  350. */
  351. static int
  352. mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
  353. {
  354. void __iomem *regs = priv->regs;
  355. dma_addr_t dma_addr;
  356. int loops;
  357. dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
  358. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  359. return -ENOMEM;
  360. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  361. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  362. iowrite32(MWL8K_H2A_INT_DOORBELL,
  363. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  364. iowrite32(MWL8K_H2A_INT_DUMMY,
  365. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  366. loops = 1000;
  367. do {
  368. u32 int_code;
  369. int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
  370. if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
  371. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  372. break;
  373. }
  374. cond_resched();
  375. udelay(1);
  376. } while (--loops);
  377. pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
  378. return loops ? 0 : -ETIMEDOUT;
  379. }
  380. static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
  381. const u8 *data, size_t length)
  382. {
  383. struct mwl8k_cmd_pkt *cmd;
  384. int done;
  385. int rc = 0;
  386. cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
  387. if (cmd == NULL)
  388. return -ENOMEM;
  389. cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
  390. cmd->seq_num = 0;
  391. cmd->result = 0;
  392. done = 0;
  393. while (length) {
  394. int block_size = length > 256 ? 256 : length;
  395. memcpy(cmd->payload, data + done, block_size);
  396. cmd->length = cpu_to_le16(block_size);
  397. rc = mwl8k_send_fw_load_cmd(priv, cmd,
  398. sizeof(*cmd) + block_size);
  399. if (rc)
  400. break;
  401. done += block_size;
  402. length -= block_size;
  403. }
  404. if (!rc) {
  405. cmd->length = 0;
  406. rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
  407. }
  408. kfree(cmd);
  409. return rc;
  410. }
  411. static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
  412. const u8 *data, size_t length)
  413. {
  414. unsigned char *buffer;
  415. int may_continue, rc = 0;
  416. u32 done, prev_block_size;
  417. buffer = kmalloc(1024, GFP_KERNEL);
  418. if (buffer == NULL)
  419. return -ENOMEM;
  420. done = 0;
  421. prev_block_size = 0;
  422. may_continue = 1000;
  423. while (may_continue > 0) {
  424. u32 block_size;
  425. block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
  426. if (block_size & 1) {
  427. block_size &= ~1;
  428. may_continue--;
  429. } else {
  430. done += prev_block_size;
  431. length -= prev_block_size;
  432. }
  433. if (block_size > 1024 || block_size > length) {
  434. rc = -EOVERFLOW;
  435. break;
  436. }
  437. if (length == 0) {
  438. rc = 0;
  439. break;
  440. }
  441. if (block_size == 0) {
  442. rc = -EPROTO;
  443. may_continue--;
  444. udelay(1);
  445. continue;
  446. }
  447. prev_block_size = block_size;
  448. memcpy(buffer, data + done, block_size);
  449. rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
  450. if (rc)
  451. break;
  452. }
  453. if (!rc && length != 0)
  454. rc = -EREMOTEIO;
  455. kfree(buffer);
  456. return rc;
  457. }
  458. static int mwl8k_load_firmware(struct ieee80211_hw *hw)
  459. {
  460. struct mwl8k_priv *priv = hw->priv;
  461. struct firmware *fw = priv->fw_ucode;
  462. int rc;
  463. int loops;
  464. if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
  465. struct firmware *helper = priv->fw_helper;
  466. if (helper == NULL) {
  467. printk(KERN_ERR "%s: helper image needed but none "
  468. "given\n", pci_name(priv->pdev));
  469. return -EINVAL;
  470. }
  471. rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
  472. if (rc) {
  473. printk(KERN_ERR "%s: unable to load firmware "
  474. "helper image\n", pci_name(priv->pdev));
  475. return rc;
  476. }
  477. msleep(5);
  478. rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
  479. } else {
  480. rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
  481. }
  482. if (rc) {
  483. printk(KERN_ERR "%s: unable to load firmware image\n",
  484. pci_name(priv->pdev));
  485. return rc;
  486. }
  487. iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
  488. loops = 500000;
  489. do {
  490. u32 ready_code;
  491. ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  492. if (ready_code == MWL8K_FWAP_READY) {
  493. priv->ap_fw = 1;
  494. break;
  495. } else if (ready_code == MWL8K_FWSTA_READY) {
  496. priv->ap_fw = 0;
  497. break;
  498. }
  499. cond_resched();
  500. udelay(1);
  501. } while (--loops);
  502. return loops ? 0 : -ETIMEDOUT;
  503. }
  504. /* DMA header used by firmware and hardware. */
  505. struct mwl8k_dma_data {
  506. __le16 fwlen;
  507. struct ieee80211_hdr wh;
  508. char data[0];
  509. } __attribute__((packed));
  510. /* Routines to add/remove DMA header from skb. */
  511. static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
  512. {
  513. struct mwl8k_dma_data *tr;
  514. int hdrlen;
  515. tr = (struct mwl8k_dma_data *)skb->data;
  516. hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
  517. if (hdrlen != sizeof(tr->wh)) {
  518. if (ieee80211_is_data_qos(tr->wh.frame_control)) {
  519. memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
  520. *((__le16 *)(tr->data - 2)) = qos;
  521. } else {
  522. memmove(tr->data - hdrlen, &tr->wh, hdrlen);
  523. }
  524. }
  525. if (hdrlen != sizeof(*tr))
  526. skb_pull(skb, sizeof(*tr) - hdrlen);
  527. }
  528. static inline void mwl8k_add_dma_header(struct sk_buff *skb)
  529. {
  530. struct ieee80211_hdr *wh;
  531. int hdrlen;
  532. struct mwl8k_dma_data *tr;
  533. /*
  534. * Add a firmware DMA header; the firmware requires that we
  535. * present a 2-byte payload length followed by a 4-address
  536. * header (without QoS field), followed (optionally) by any
  537. * WEP/ExtIV header (but only filled in for CCMP).
  538. */
  539. wh = (struct ieee80211_hdr *)skb->data;
  540. hdrlen = ieee80211_hdrlen(wh->frame_control);
  541. if (hdrlen != sizeof(*tr))
  542. skb_push(skb, sizeof(*tr) - hdrlen);
  543. if (ieee80211_is_data_qos(wh->frame_control))
  544. hdrlen -= 2;
  545. tr = (struct mwl8k_dma_data *)skb->data;
  546. if (wh != &tr->wh)
  547. memmove(&tr->wh, wh, hdrlen);
  548. if (hdrlen != sizeof(tr->wh))
  549. memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
  550. /*
  551. * Firmware length is the length of the fully formed "802.11
  552. * payload". That is, everything except for the 802.11 header.
  553. * This includes all crypto material including the MIC.
  554. */
  555. tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
  556. }
  557. /*
  558. * Packet reception for 88w8366 AP firmware.
  559. */
  560. struct mwl8k_rxd_8366_ap {
  561. __le16 pkt_len;
  562. __u8 sq2;
  563. __u8 rate;
  564. __le32 pkt_phys_addr;
  565. __le32 next_rxd_phys_addr;
  566. __le16 qos_control;
  567. __le16 htsig2;
  568. __le32 hw_rssi_info;
  569. __le32 hw_noise_floor_info;
  570. __u8 noise_floor;
  571. __u8 pad0[3];
  572. __u8 rssi;
  573. __u8 rx_status;
  574. __u8 channel;
  575. __u8 rx_ctrl;
  576. } __attribute__((packed));
  577. #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
  578. #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
  579. #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
  580. #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
  581. static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
  582. {
  583. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  584. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  585. rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
  586. }
  587. static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
  588. {
  589. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  590. rxd->pkt_len = cpu_to_le16(len);
  591. rxd->pkt_phys_addr = cpu_to_le32(addr);
  592. wmb();
  593. rxd->rx_ctrl = 0;
  594. }
  595. static int
  596. mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
  597. __le16 *qos)
  598. {
  599. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  600. if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
  601. return -1;
  602. rmb();
  603. memset(status, 0, sizeof(*status));
  604. status->signal = -rxd->rssi;
  605. status->noise = -rxd->noise_floor;
  606. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
  607. status->flag |= RX_FLAG_HT;
  608. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
  609. status->flag |= RX_FLAG_40MHZ;
  610. status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
  611. } else {
  612. int i;
  613. for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
  614. if (mwl8k_rates[i].hw_value == rxd->rate) {
  615. status->rate_idx = i;
  616. break;
  617. }
  618. }
  619. }
  620. status->band = IEEE80211_BAND_2GHZ;
  621. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  622. *qos = rxd->qos_control;
  623. return le16_to_cpu(rxd->pkt_len);
  624. }
  625. static struct rxd_ops rxd_8366_ap_ops = {
  626. .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
  627. .rxd_init = mwl8k_rxd_8366_ap_init,
  628. .rxd_refill = mwl8k_rxd_8366_ap_refill,
  629. .rxd_process = mwl8k_rxd_8366_ap_process,
  630. };
  631. /*
  632. * Packet reception for STA firmware.
  633. */
  634. struct mwl8k_rxd_sta {
  635. __le16 pkt_len;
  636. __u8 link_quality;
  637. __u8 noise_level;
  638. __le32 pkt_phys_addr;
  639. __le32 next_rxd_phys_addr;
  640. __le16 qos_control;
  641. __le16 rate_info;
  642. __le32 pad0[4];
  643. __u8 rssi;
  644. __u8 channel;
  645. __le16 pad1;
  646. __u8 rx_ctrl;
  647. __u8 rx_status;
  648. __u8 pad2[2];
  649. } __attribute__((packed));
  650. #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
  651. #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
  652. #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
  653. #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
  654. #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
  655. #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
  656. #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
  657. static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
  658. {
  659. struct mwl8k_rxd_sta *rxd = _rxd;
  660. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  661. rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
  662. }
  663. static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
  664. {
  665. struct mwl8k_rxd_sta *rxd = _rxd;
  666. rxd->pkt_len = cpu_to_le16(len);
  667. rxd->pkt_phys_addr = cpu_to_le32(addr);
  668. wmb();
  669. rxd->rx_ctrl = 0;
  670. }
  671. static int
  672. mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
  673. __le16 *qos)
  674. {
  675. struct mwl8k_rxd_sta *rxd = _rxd;
  676. u16 rate_info;
  677. if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
  678. return -1;
  679. rmb();
  680. rate_info = le16_to_cpu(rxd->rate_info);
  681. memset(status, 0, sizeof(*status));
  682. status->signal = -rxd->rssi;
  683. status->noise = -rxd->noise_level;
  684. status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
  685. status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
  686. if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
  687. status->flag |= RX_FLAG_SHORTPRE;
  688. if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
  689. status->flag |= RX_FLAG_40MHZ;
  690. if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
  691. status->flag |= RX_FLAG_SHORT_GI;
  692. if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
  693. status->flag |= RX_FLAG_HT;
  694. status->band = IEEE80211_BAND_2GHZ;
  695. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  696. *qos = rxd->qos_control;
  697. return le16_to_cpu(rxd->pkt_len);
  698. }
  699. static struct rxd_ops rxd_sta_ops = {
  700. .rxd_size = sizeof(struct mwl8k_rxd_sta),
  701. .rxd_init = mwl8k_rxd_sta_init,
  702. .rxd_refill = mwl8k_rxd_sta_refill,
  703. .rxd_process = mwl8k_rxd_sta_process,
  704. };
  705. #define MWL8K_RX_DESCS 256
  706. #define MWL8K_RX_MAXSZ 3800
  707. static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
  708. {
  709. struct mwl8k_priv *priv = hw->priv;
  710. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  711. int size;
  712. int i;
  713. rxq->rxd_count = 0;
  714. rxq->head = 0;
  715. rxq->tail = 0;
  716. size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
  717. rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
  718. if (rxq->rxd == NULL) {
  719. printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
  720. wiphy_name(hw->wiphy));
  721. return -ENOMEM;
  722. }
  723. memset(rxq->rxd, 0, size);
  724. rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
  725. if (rxq->buf == NULL) {
  726. printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
  727. wiphy_name(hw->wiphy));
  728. pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
  729. return -ENOMEM;
  730. }
  731. memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
  732. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  733. int desc_size;
  734. void *rxd;
  735. int nexti;
  736. dma_addr_t next_dma_addr;
  737. desc_size = priv->rxd_ops->rxd_size;
  738. rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
  739. nexti = i + 1;
  740. if (nexti == MWL8K_RX_DESCS)
  741. nexti = 0;
  742. next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
  743. priv->rxd_ops->rxd_init(rxd, next_dma_addr);
  744. }
  745. return 0;
  746. }
  747. static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
  748. {
  749. struct mwl8k_priv *priv = hw->priv;
  750. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  751. int refilled;
  752. refilled = 0;
  753. while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
  754. struct sk_buff *skb;
  755. dma_addr_t addr;
  756. int rx;
  757. void *rxd;
  758. skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
  759. if (skb == NULL)
  760. break;
  761. addr = pci_map_single(priv->pdev, skb->data,
  762. MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
  763. rxq->rxd_count++;
  764. rx = rxq->tail++;
  765. if (rxq->tail == MWL8K_RX_DESCS)
  766. rxq->tail = 0;
  767. rxq->buf[rx].skb = skb;
  768. pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
  769. rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
  770. priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
  771. refilled++;
  772. }
  773. return refilled;
  774. }
  775. /* Must be called only when the card's reception is completely halted */
  776. static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
  777. {
  778. struct mwl8k_priv *priv = hw->priv;
  779. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  780. int i;
  781. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  782. if (rxq->buf[i].skb != NULL) {
  783. pci_unmap_single(priv->pdev,
  784. pci_unmap_addr(&rxq->buf[i], dma),
  785. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  786. pci_unmap_addr_set(&rxq->buf[i], dma, 0);
  787. kfree_skb(rxq->buf[i].skb);
  788. rxq->buf[i].skb = NULL;
  789. }
  790. }
  791. kfree(rxq->buf);
  792. rxq->buf = NULL;
  793. pci_free_consistent(priv->pdev,
  794. MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
  795. rxq->rxd, rxq->rxd_dma);
  796. rxq->rxd = NULL;
  797. }
  798. /*
  799. * Scan a list of BSSIDs to process for finalize join.
  800. * Allows for extension to process multiple BSSIDs.
  801. */
  802. static inline int
  803. mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
  804. {
  805. return priv->capture_beacon &&
  806. ieee80211_is_beacon(wh->frame_control) &&
  807. !compare_ether_addr(wh->addr3, priv->capture_bssid);
  808. }
  809. static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
  810. struct sk_buff *skb)
  811. {
  812. struct mwl8k_priv *priv = hw->priv;
  813. priv->capture_beacon = false;
  814. memset(priv->capture_bssid, 0, ETH_ALEN);
  815. /*
  816. * Use GFP_ATOMIC as rxq_process is called from
  817. * the primary interrupt handler, memory allocation call
  818. * must not sleep.
  819. */
  820. priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
  821. if (priv->beacon_skb != NULL)
  822. ieee80211_queue_work(hw, &priv->finalize_join_worker);
  823. }
  824. static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
  825. {
  826. struct mwl8k_priv *priv = hw->priv;
  827. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  828. int processed;
  829. processed = 0;
  830. while (rxq->rxd_count && limit--) {
  831. struct sk_buff *skb;
  832. void *rxd;
  833. int pkt_len;
  834. struct ieee80211_rx_status status;
  835. __le16 qos;
  836. skb = rxq->buf[rxq->head].skb;
  837. if (skb == NULL)
  838. break;
  839. rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
  840. pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
  841. if (pkt_len < 0)
  842. break;
  843. rxq->buf[rxq->head].skb = NULL;
  844. pci_unmap_single(priv->pdev,
  845. pci_unmap_addr(&rxq->buf[rxq->head], dma),
  846. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  847. pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
  848. rxq->head++;
  849. if (rxq->head == MWL8K_RX_DESCS)
  850. rxq->head = 0;
  851. rxq->rxd_count--;
  852. skb_put(skb, pkt_len);
  853. mwl8k_remove_dma_header(skb, qos);
  854. /*
  855. * Check for a pending join operation. Save a
  856. * copy of the beacon and schedule a tasklet to
  857. * send a FINALIZE_JOIN command to the firmware.
  858. */
  859. if (mwl8k_capture_bssid(priv, (void *)skb->data))
  860. mwl8k_save_beacon(hw, skb);
  861. memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
  862. ieee80211_rx_irqsafe(hw, skb);
  863. processed++;
  864. }
  865. return processed;
  866. }
  867. /*
  868. * Packet transmission.
  869. */
  870. #define MWL8K_TXD_STATUS_OK 0x00000001
  871. #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
  872. #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
  873. #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
  874. #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
  875. #define MWL8K_QOS_QLEN_UNSPEC 0xff00
  876. #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
  877. #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
  878. #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
  879. #define MWL8K_QOS_EOSP 0x0010
  880. struct mwl8k_tx_desc {
  881. __le32 status;
  882. __u8 data_rate;
  883. __u8 tx_priority;
  884. __le16 qos_control;
  885. __le32 pkt_phys_addr;
  886. __le16 pkt_len;
  887. __u8 dest_MAC_addr[ETH_ALEN];
  888. __le32 next_txd_phys_addr;
  889. __le32 reserved;
  890. __le16 rate_info;
  891. __u8 peer_id;
  892. __u8 tx_frag_cnt;
  893. } __attribute__((packed));
  894. #define MWL8K_TX_DESCS 128
  895. static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
  896. {
  897. struct mwl8k_priv *priv = hw->priv;
  898. struct mwl8k_tx_queue *txq = priv->txq + index;
  899. int size;
  900. int i;
  901. memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
  902. txq->stats.limit = MWL8K_TX_DESCS;
  903. txq->head = 0;
  904. txq->tail = 0;
  905. size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
  906. txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
  907. if (txq->txd == NULL) {
  908. printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
  909. wiphy_name(hw->wiphy));
  910. return -ENOMEM;
  911. }
  912. memset(txq->txd, 0, size);
  913. txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
  914. if (txq->skb == NULL) {
  915. printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
  916. wiphy_name(hw->wiphy));
  917. pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
  918. return -ENOMEM;
  919. }
  920. memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
  921. for (i = 0; i < MWL8K_TX_DESCS; i++) {
  922. struct mwl8k_tx_desc *tx_desc;
  923. int nexti;
  924. tx_desc = txq->txd + i;
  925. nexti = (i + 1) % MWL8K_TX_DESCS;
  926. tx_desc->status = 0;
  927. tx_desc->next_txd_phys_addr =
  928. cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
  929. }
  930. return 0;
  931. }
  932. static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
  933. {
  934. iowrite32(MWL8K_H2A_INT_PPA_READY,
  935. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  936. iowrite32(MWL8K_H2A_INT_DUMMY,
  937. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  938. ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  939. }
  940. static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
  941. {
  942. struct mwl8k_priv *priv = hw->priv;
  943. int i;
  944. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  945. struct mwl8k_tx_queue *txq = priv->txq + i;
  946. int fw_owned = 0;
  947. int drv_owned = 0;
  948. int unused = 0;
  949. int desc;
  950. for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
  951. struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
  952. u32 status;
  953. status = le32_to_cpu(tx_desc->status);
  954. if (status & MWL8K_TXD_STATUS_FW_OWNED)
  955. fw_owned++;
  956. else
  957. drv_owned++;
  958. if (tx_desc->pkt_len == 0)
  959. unused++;
  960. }
  961. printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
  962. "fw_owned=%d drv_owned=%d unused=%d\n",
  963. wiphy_name(hw->wiphy), i,
  964. txq->stats.len, txq->head, txq->tail,
  965. fw_owned, drv_owned, unused);
  966. }
  967. }
  968. /*
  969. * Must be called with priv->fw_mutex held and tx queues stopped.
  970. */
  971. #define MWL8K_TX_WAIT_TIMEOUT_MS 5000
  972. static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
  973. {
  974. struct mwl8k_priv *priv = hw->priv;
  975. DECLARE_COMPLETION_ONSTACK(tx_wait);
  976. int retry;
  977. int rc;
  978. might_sleep();
  979. /*
  980. * The TX queues are stopped at this point, so this test
  981. * doesn't need to take ->tx_lock.
  982. */
  983. if (!priv->pending_tx_pkts)
  984. return 0;
  985. retry = 0;
  986. rc = 0;
  987. spin_lock_bh(&priv->tx_lock);
  988. priv->tx_wait = &tx_wait;
  989. while (!rc) {
  990. int oldcount;
  991. unsigned long timeout;
  992. oldcount = priv->pending_tx_pkts;
  993. spin_unlock_bh(&priv->tx_lock);
  994. timeout = wait_for_completion_timeout(&tx_wait,
  995. msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
  996. spin_lock_bh(&priv->tx_lock);
  997. if (timeout) {
  998. WARN_ON(priv->pending_tx_pkts);
  999. if (retry) {
  1000. printk(KERN_NOTICE "%s: tx rings drained\n",
  1001. wiphy_name(hw->wiphy));
  1002. }
  1003. break;
  1004. }
  1005. if (priv->pending_tx_pkts < oldcount) {
  1006. printk(KERN_NOTICE "%s: waiting for tx rings "
  1007. "to drain (%d -> %d pkts)\n",
  1008. wiphy_name(hw->wiphy), oldcount,
  1009. priv->pending_tx_pkts);
  1010. retry = 1;
  1011. continue;
  1012. }
  1013. priv->tx_wait = NULL;
  1014. printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
  1015. wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
  1016. mwl8k_dump_tx_rings(hw);
  1017. rc = -ETIMEDOUT;
  1018. }
  1019. spin_unlock_bh(&priv->tx_lock);
  1020. return rc;
  1021. }
  1022. #define MWL8K_TXD_SUCCESS(status) \
  1023. ((status) & (MWL8K_TXD_STATUS_OK | \
  1024. MWL8K_TXD_STATUS_OK_RETRY | \
  1025. MWL8K_TXD_STATUS_OK_MORE_RETRY))
  1026. static int
  1027. mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
  1028. {
  1029. struct mwl8k_priv *priv = hw->priv;
  1030. struct mwl8k_tx_queue *txq = priv->txq + index;
  1031. int processed;
  1032. processed = 0;
  1033. while (txq->stats.len > 0 && limit--) {
  1034. int tx;
  1035. struct mwl8k_tx_desc *tx_desc;
  1036. unsigned long addr;
  1037. int size;
  1038. struct sk_buff *skb;
  1039. struct ieee80211_tx_info *info;
  1040. u32 status;
  1041. tx = txq->head;
  1042. tx_desc = txq->txd + tx;
  1043. status = le32_to_cpu(tx_desc->status);
  1044. if (status & MWL8K_TXD_STATUS_FW_OWNED) {
  1045. if (!force)
  1046. break;
  1047. tx_desc->status &=
  1048. ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
  1049. }
  1050. txq->head = (tx + 1) % MWL8K_TX_DESCS;
  1051. BUG_ON(txq->stats.len == 0);
  1052. txq->stats.len--;
  1053. priv->pending_tx_pkts--;
  1054. addr = le32_to_cpu(tx_desc->pkt_phys_addr);
  1055. size = le16_to_cpu(tx_desc->pkt_len);
  1056. skb = txq->skb[tx];
  1057. txq->skb[tx] = NULL;
  1058. BUG_ON(skb == NULL);
  1059. pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
  1060. mwl8k_remove_dma_header(skb, tx_desc->qos_control);
  1061. /* Mark descriptor as unused */
  1062. tx_desc->pkt_phys_addr = 0;
  1063. tx_desc->pkt_len = 0;
  1064. info = IEEE80211_SKB_CB(skb);
  1065. ieee80211_tx_info_clear_status(info);
  1066. if (MWL8K_TXD_SUCCESS(status))
  1067. info->flags |= IEEE80211_TX_STAT_ACK;
  1068. ieee80211_tx_status_irqsafe(hw, skb);
  1069. processed++;
  1070. }
  1071. if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
  1072. ieee80211_wake_queue(hw, index);
  1073. return processed;
  1074. }
  1075. /* must be called only when the card's transmit is completely halted */
  1076. static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
  1077. {
  1078. struct mwl8k_priv *priv = hw->priv;
  1079. struct mwl8k_tx_queue *txq = priv->txq + index;
  1080. mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
  1081. kfree(txq->skb);
  1082. txq->skb = NULL;
  1083. pci_free_consistent(priv->pdev,
  1084. MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
  1085. txq->txd, txq->txd_dma);
  1086. txq->txd = NULL;
  1087. }
  1088. static int
  1089. mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
  1090. {
  1091. struct mwl8k_priv *priv = hw->priv;
  1092. struct ieee80211_tx_info *tx_info;
  1093. struct mwl8k_vif *mwl8k_vif;
  1094. struct ieee80211_hdr *wh;
  1095. struct mwl8k_tx_queue *txq;
  1096. struct mwl8k_tx_desc *tx;
  1097. dma_addr_t dma;
  1098. u32 txstatus;
  1099. u8 txdatarate;
  1100. u16 qos;
  1101. wh = (struct ieee80211_hdr *)skb->data;
  1102. if (ieee80211_is_data_qos(wh->frame_control))
  1103. qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
  1104. else
  1105. qos = 0;
  1106. mwl8k_add_dma_header(skb);
  1107. wh = &((struct mwl8k_dma_data *)skb->data)->wh;
  1108. tx_info = IEEE80211_SKB_CB(skb);
  1109. mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
  1110. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1111. wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1112. wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
  1113. mwl8k_vif->seqno += 0x10;
  1114. }
  1115. /* Setup firmware control bit fields for each frame type. */
  1116. txstatus = 0;
  1117. txdatarate = 0;
  1118. if (ieee80211_is_mgmt(wh->frame_control) ||
  1119. ieee80211_is_ctl(wh->frame_control)) {
  1120. txdatarate = 0;
  1121. qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
  1122. } else if (ieee80211_is_data(wh->frame_control)) {
  1123. txdatarate = 1;
  1124. if (is_multicast_ether_addr(wh->addr1))
  1125. txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
  1126. qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
  1127. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
  1128. qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
  1129. else
  1130. qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
  1131. }
  1132. dma = pci_map_single(priv->pdev, skb->data,
  1133. skb->len, PCI_DMA_TODEVICE);
  1134. if (pci_dma_mapping_error(priv->pdev, dma)) {
  1135. printk(KERN_DEBUG "%s: failed to dma map skb, "
  1136. "dropping TX frame.\n", wiphy_name(hw->wiphy));
  1137. dev_kfree_skb(skb);
  1138. return NETDEV_TX_OK;
  1139. }
  1140. spin_lock_bh(&priv->tx_lock);
  1141. txq = priv->txq + index;
  1142. BUG_ON(txq->skb[txq->tail] != NULL);
  1143. txq->skb[txq->tail] = skb;
  1144. tx = txq->txd + txq->tail;
  1145. tx->data_rate = txdatarate;
  1146. tx->tx_priority = index;
  1147. tx->qos_control = cpu_to_le16(qos);
  1148. tx->pkt_phys_addr = cpu_to_le32(dma);
  1149. tx->pkt_len = cpu_to_le16(skb->len);
  1150. tx->rate_info = 0;
  1151. if (!priv->ap_fw && tx_info->control.sta != NULL)
  1152. tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
  1153. else
  1154. tx->peer_id = 0;
  1155. wmb();
  1156. tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
  1157. txq->stats.count++;
  1158. txq->stats.len++;
  1159. priv->pending_tx_pkts++;
  1160. txq->tail++;
  1161. if (txq->tail == MWL8K_TX_DESCS)
  1162. txq->tail = 0;
  1163. if (txq->head == txq->tail)
  1164. ieee80211_stop_queue(hw, index);
  1165. mwl8k_tx_start(priv);
  1166. spin_unlock_bh(&priv->tx_lock);
  1167. return NETDEV_TX_OK;
  1168. }
  1169. /*
  1170. * Firmware access.
  1171. *
  1172. * We have the following requirements for issuing firmware commands:
  1173. * - Some commands require that the packet transmit path is idle when
  1174. * the command is issued. (For simplicity, we'll just quiesce the
  1175. * transmit path for every command.)
  1176. * - There are certain sequences of commands that need to be issued to
  1177. * the hardware sequentially, with no other intervening commands.
  1178. *
  1179. * This leads to an implementation of a "firmware lock" as a mutex that
  1180. * can be taken recursively, and which is taken by both the low-level
  1181. * command submission function (mwl8k_post_cmd) as well as any users of
  1182. * that function that require issuing of an atomic sequence of commands,
  1183. * and quiesces the transmit path whenever it's taken.
  1184. */
  1185. static int mwl8k_fw_lock(struct ieee80211_hw *hw)
  1186. {
  1187. struct mwl8k_priv *priv = hw->priv;
  1188. if (priv->fw_mutex_owner != current) {
  1189. int rc;
  1190. mutex_lock(&priv->fw_mutex);
  1191. ieee80211_stop_queues(hw);
  1192. rc = mwl8k_tx_wait_empty(hw);
  1193. if (rc) {
  1194. ieee80211_wake_queues(hw);
  1195. mutex_unlock(&priv->fw_mutex);
  1196. return rc;
  1197. }
  1198. priv->fw_mutex_owner = current;
  1199. }
  1200. priv->fw_mutex_depth++;
  1201. return 0;
  1202. }
  1203. static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
  1204. {
  1205. struct mwl8k_priv *priv = hw->priv;
  1206. if (!--priv->fw_mutex_depth) {
  1207. ieee80211_wake_queues(hw);
  1208. priv->fw_mutex_owner = NULL;
  1209. mutex_unlock(&priv->fw_mutex);
  1210. }
  1211. }
  1212. /*
  1213. * Command processing.
  1214. */
  1215. /* Timeout firmware commands after 10s */
  1216. #define MWL8K_CMD_TIMEOUT_MS 10000
  1217. static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
  1218. {
  1219. DECLARE_COMPLETION_ONSTACK(cmd_wait);
  1220. struct mwl8k_priv *priv = hw->priv;
  1221. void __iomem *regs = priv->regs;
  1222. dma_addr_t dma_addr;
  1223. unsigned int dma_size;
  1224. int rc;
  1225. unsigned long timeout = 0;
  1226. u8 buf[32];
  1227. cmd->result = 0xffff;
  1228. dma_size = le16_to_cpu(cmd->length);
  1229. dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
  1230. PCI_DMA_BIDIRECTIONAL);
  1231. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  1232. return -ENOMEM;
  1233. rc = mwl8k_fw_lock(hw);
  1234. if (rc) {
  1235. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1236. PCI_DMA_BIDIRECTIONAL);
  1237. return rc;
  1238. }
  1239. priv->hostcmd_wait = &cmd_wait;
  1240. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  1241. iowrite32(MWL8K_H2A_INT_DOORBELL,
  1242. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1243. iowrite32(MWL8K_H2A_INT_DUMMY,
  1244. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1245. timeout = wait_for_completion_timeout(&cmd_wait,
  1246. msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
  1247. priv->hostcmd_wait = NULL;
  1248. mwl8k_fw_unlock(hw);
  1249. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1250. PCI_DMA_BIDIRECTIONAL);
  1251. if (!timeout) {
  1252. printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
  1253. wiphy_name(hw->wiphy),
  1254. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1255. MWL8K_CMD_TIMEOUT_MS);
  1256. rc = -ETIMEDOUT;
  1257. } else {
  1258. int ms;
  1259. ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
  1260. rc = cmd->result ? -EINVAL : 0;
  1261. if (rc)
  1262. printk(KERN_ERR "%s: Command %s error 0x%x\n",
  1263. wiphy_name(hw->wiphy),
  1264. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1265. le16_to_cpu(cmd->result));
  1266. else if (ms > 2000)
  1267. printk(KERN_NOTICE "%s: Command %s took %d ms\n",
  1268. wiphy_name(hw->wiphy),
  1269. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1270. ms);
  1271. }
  1272. return rc;
  1273. }
  1274. /*
  1275. * CMD_GET_HW_SPEC (STA version).
  1276. */
  1277. struct mwl8k_cmd_get_hw_spec_sta {
  1278. struct mwl8k_cmd_pkt header;
  1279. __u8 hw_rev;
  1280. __u8 host_interface;
  1281. __le16 num_mcaddrs;
  1282. __u8 perm_addr[ETH_ALEN];
  1283. __le16 region_code;
  1284. __le32 fw_rev;
  1285. __le32 ps_cookie;
  1286. __le32 caps;
  1287. __u8 mcs_bitmap[16];
  1288. __le32 rx_queue_ptr;
  1289. __le32 num_tx_queues;
  1290. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1291. __le32 caps2;
  1292. __le32 num_tx_desc_per_queue;
  1293. __le32 total_rxd;
  1294. } __attribute__((packed));
  1295. #define MWL8K_CAP_MAX_AMSDU 0x20000000
  1296. #define MWL8K_CAP_GREENFIELD 0x08000000
  1297. #define MWL8K_CAP_AMPDU 0x04000000
  1298. #define MWL8K_CAP_RX_STBC 0x01000000
  1299. #define MWL8K_CAP_TX_STBC 0x00800000
  1300. #define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
  1301. #define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
  1302. #define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
  1303. #define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
  1304. #define MWL8K_CAP_DELAY_BA 0x00003000
  1305. #define MWL8K_CAP_MIMO 0x00000200
  1306. #define MWL8K_CAP_40MHZ 0x00000100
  1307. static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
  1308. {
  1309. struct mwl8k_priv *priv = hw->priv;
  1310. int rx_streams;
  1311. int tx_streams;
  1312. priv->band.ht_cap.ht_supported = 1;
  1313. if (cap & MWL8K_CAP_MAX_AMSDU)
  1314. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  1315. if (cap & MWL8K_CAP_GREENFIELD)
  1316. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
  1317. if (cap & MWL8K_CAP_AMPDU) {
  1318. hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
  1319. priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  1320. priv->band.ht_cap.ampdu_density =
  1321. IEEE80211_HT_MPDU_DENSITY_NONE;
  1322. }
  1323. if (cap & MWL8K_CAP_RX_STBC)
  1324. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
  1325. if (cap & MWL8K_CAP_TX_STBC)
  1326. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
  1327. if (cap & MWL8K_CAP_SHORTGI_40MHZ)
  1328. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
  1329. if (cap & MWL8K_CAP_SHORTGI_20MHZ)
  1330. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
  1331. if (cap & MWL8K_CAP_DELAY_BA)
  1332. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
  1333. if (cap & MWL8K_CAP_40MHZ)
  1334. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  1335. rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
  1336. tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
  1337. priv->band.ht_cap.mcs.rx_mask[0] = 0xff;
  1338. if (rx_streams >= 2)
  1339. priv->band.ht_cap.mcs.rx_mask[1] = 0xff;
  1340. if (rx_streams >= 3)
  1341. priv->band.ht_cap.mcs.rx_mask[2] = 0xff;
  1342. priv->band.ht_cap.mcs.rx_mask[4] = 0x01;
  1343. priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  1344. if (rx_streams != tx_streams) {
  1345. priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  1346. priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) <<
  1347. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1348. }
  1349. }
  1350. static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
  1351. {
  1352. struct mwl8k_priv *priv = hw->priv;
  1353. struct mwl8k_cmd_get_hw_spec_sta *cmd;
  1354. int rc;
  1355. int i;
  1356. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1357. if (cmd == NULL)
  1358. return -ENOMEM;
  1359. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1360. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1361. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1362. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1363. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1364. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1365. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1366. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1367. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1368. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1369. rc = mwl8k_post_cmd(hw, &cmd->header);
  1370. if (!rc) {
  1371. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1372. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1373. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1374. priv->hw_rev = cmd->hw_rev;
  1375. if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
  1376. mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
  1377. }
  1378. kfree(cmd);
  1379. return rc;
  1380. }
  1381. /*
  1382. * CMD_GET_HW_SPEC (AP version).
  1383. */
  1384. struct mwl8k_cmd_get_hw_spec_ap {
  1385. struct mwl8k_cmd_pkt header;
  1386. __u8 hw_rev;
  1387. __u8 host_interface;
  1388. __le16 num_wcb;
  1389. __le16 num_mcaddrs;
  1390. __u8 perm_addr[ETH_ALEN];
  1391. __le16 region_code;
  1392. __le16 num_antenna;
  1393. __le32 fw_rev;
  1394. __le32 wcbbase0;
  1395. __le32 rxwrptr;
  1396. __le32 rxrdptr;
  1397. __le32 ps_cookie;
  1398. __le32 wcbbase1;
  1399. __le32 wcbbase2;
  1400. __le32 wcbbase3;
  1401. } __attribute__((packed));
  1402. static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
  1403. {
  1404. struct mwl8k_priv *priv = hw->priv;
  1405. struct mwl8k_cmd_get_hw_spec_ap *cmd;
  1406. int rc;
  1407. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1408. if (cmd == NULL)
  1409. return -ENOMEM;
  1410. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1411. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1412. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1413. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1414. rc = mwl8k_post_cmd(hw, &cmd->header);
  1415. if (!rc) {
  1416. int off;
  1417. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1418. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1419. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1420. priv->hw_rev = cmd->hw_rev;
  1421. off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
  1422. iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
  1423. off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
  1424. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1425. off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
  1426. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1427. off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
  1428. iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
  1429. off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
  1430. iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
  1431. off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
  1432. iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
  1433. }
  1434. kfree(cmd);
  1435. return rc;
  1436. }
  1437. /*
  1438. * CMD_SET_HW_SPEC.
  1439. */
  1440. struct mwl8k_cmd_set_hw_spec {
  1441. struct mwl8k_cmd_pkt header;
  1442. __u8 hw_rev;
  1443. __u8 host_interface;
  1444. __le16 num_mcaddrs;
  1445. __u8 perm_addr[ETH_ALEN];
  1446. __le16 region_code;
  1447. __le32 fw_rev;
  1448. __le32 ps_cookie;
  1449. __le32 caps;
  1450. __le32 rx_queue_ptr;
  1451. __le32 num_tx_queues;
  1452. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1453. __le32 flags;
  1454. __le32 num_tx_desc_per_queue;
  1455. __le32 total_rxd;
  1456. } __attribute__((packed));
  1457. #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
  1458. #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
  1459. #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
  1460. static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
  1461. {
  1462. struct mwl8k_priv *priv = hw->priv;
  1463. struct mwl8k_cmd_set_hw_spec *cmd;
  1464. int rc;
  1465. int i;
  1466. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1467. if (cmd == NULL)
  1468. return -ENOMEM;
  1469. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
  1470. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1471. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1472. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1473. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1474. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1475. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1476. cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
  1477. MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
  1478. MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
  1479. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1480. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1481. rc = mwl8k_post_cmd(hw, &cmd->header);
  1482. kfree(cmd);
  1483. return rc;
  1484. }
  1485. /*
  1486. * CMD_MAC_MULTICAST_ADR.
  1487. */
  1488. struct mwl8k_cmd_mac_multicast_adr {
  1489. struct mwl8k_cmd_pkt header;
  1490. __le16 action;
  1491. __le16 numaddr;
  1492. __u8 addr[0][ETH_ALEN];
  1493. };
  1494. #define MWL8K_ENABLE_RX_DIRECTED 0x0001
  1495. #define MWL8K_ENABLE_RX_MULTICAST 0x0002
  1496. #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
  1497. #define MWL8K_ENABLE_RX_BROADCAST 0x0008
  1498. static struct mwl8k_cmd_pkt *
  1499. __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
  1500. int mc_count, struct dev_addr_list *mclist)
  1501. {
  1502. struct mwl8k_priv *priv = hw->priv;
  1503. struct mwl8k_cmd_mac_multicast_adr *cmd;
  1504. int size;
  1505. if (allmulti || mc_count > priv->num_mcaddrs) {
  1506. allmulti = 1;
  1507. mc_count = 0;
  1508. }
  1509. size = sizeof(*cmd) + mc_count * ETH_ALEN;
  1510. cmd = kzalloc(size, GFP_ATOMIC);
  1511. if (cmd == NULL)
  1512. return NULL;
  1513. cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
  1514. cmd->header.length = cpu_to_le16(size);
  1515. cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
  1516. MWL8K_ENABLE_RX_BROADCAST);
  1517. if (allmulti) {
  1518. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
  1519. } else if (mc_count) {
  1520. int i;
  1521. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
  1522. cmd->numaddr = cpu_to_le16(mc_count);
  1523. for (i = 0; i < mc_count && mclist; i++) {
  1524. if (mclist->da_addrlen != ETH_ALEN) {
  1525. kfree(cmd);
  1526. return NULL;
  1527. }
  1528. memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
  1529. mclist = mclist->next;
  1530. }
  1531. }
  1532. return &cmd->header;
  1533. }
  1534. /*
  1535. * CMD_GET_STAT.
  1536. */
  1537. struct mwl8k_cmd_get_stat {
  1538. struct mwl8k_cmd_pkt header;
  1539. __le32 stats[64];
  1540. } __attribute__((packed));
  1541. #define MWL8K_STAT_ACK_FAILURE 9
  1542. #define MWL8K_STAT_RTS_FAILURE 12
  1543. #define MWL8K_STAT_FCS_ERROR 24
  1544. #define MWL8K_STAT_RTS_SUCCESS 11
  1545. static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
  1546. struct ieee80211_low_level_stats *stats)
  1547. {
  1548. struct mwl8k_cmd_get_stat *cmd;
  1549. int rc;
  1550. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1551. if (cmd == NULL)
  1552. return -ENOMEM;
  1553. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
  1554. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1555. rc = mwl8k_post_cmd(hw, &cmd->header);
  1556. if (!rc) {
  1557. stats->dot11ACKFailureCount =
  1558. le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
  1559. stats->dot11RTSFailureCount =
  1560. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
  1561. stats->dot11FCSErrorCount =
  1562. le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
  1563. stats->dot11RTSSuccessCount =
  1564. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
  1565. }
  1566. kfree(cmd);
  1567. return rc;
  1568. }
  1569. /*
  1570. * CMD_RADIO_CONTROL.
  1571. */
  1572. struct mwl8k_cmd_radio_control {
  1573. struct mwl8k_cmd_pkt header;
  1574. __le16 action;
  1575. __le16 control;
  1576. __le16 radio_on;
  1577. } __attribute__((packed));
  1578. static int
  1579. mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
  1580. {
  1581. struct mwl8k_priv *priv = hw->priv;
  1582. struct mwl8k_cmd_radio_control *cmd;
  1583. int rc;
  1584. if (enable == priv->radio_on && !force)
  1585. return 0;
  1586. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1587. if (cmd == NULL)
  1588. return -ENOMEM;
  1589. cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
  1590. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1591. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1592. cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
  1593. cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
  1594. rc = mwl8k_post_cmd(hw, &cmd->header);
  1595. kfree(cmd);
  1596. if (!rc)
  1597. priv->radio_on = enable;
  1598. return rc;
  1599. }
  1600. static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
  1601. {
  1602. return mwl8k_cmd_radio_control(hw, 0, 0);
  1603. }
  1604. static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
  1605. {
  1606. return mwl8k_cmd_radio_control(hw, 1, 0);
  1607. }
  1608. static int
  1609. mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
  1610. {
  1611. struct mwl8k_priv *priv = hw->priv;
  1612. priv->radio_short_preamble = short_preamble;
  1613. return mwl8k_cmd_radio_control(hw, 1, 1);
  1614. }
  1615. /*
  1616. * CMD_RF_TX_POWER.
  1617. */
  1618. #define MWL8K_TX_POWER_LEVEL_TOTAL 8
  1619. struct mwl8k_cmd_rf_tx_power {
  1620. struct mwl8k_cmd_pkt header;
  1621. __le16 action;
  1622. __le16 support_level;
  1623. __le16 current_level;
  1624. __le16 reserved;
  1625. __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
  1626. } __attribute__((packed));
  1627. static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
  1628. {
  1629. struct mwl8k_cmd_rf_tx_power *cmd;
  1630. int rc;
  1631. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1632. if (cmd == NULL)
  1633. return -ENOMEM;
  1634. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
  1635. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1636. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1637. cmd->support_level = cpu_to_le16(dBm);
  1638. rc = mwl8k_post_cmd(hw, &cmd->header);
  1639. kfree(cmd);
  1640. return rc;
  1641. }
  1642. /*
  1643. * CMD_RF_ANTENNA.
  1644. */
  1645. struct mwl8k_cmd_rf_antenna {
  1646. struct mwl8k_cmd_pkt header;
  1647. __le16 antenna;
  1648. __le16 mode;
  1649. } __attribute__((packed));
  1650. #define MWL8K_RF_ANTENNA_RX 1
  1651. #define MWL8K_RF_ANTENNA_TX 2
  1652. static int
  1653. mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
  1654. {
  1655. struct mwl8k_cmd_rf_antenna *cmd;
  1656. int rc;
  1657. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1658. if (cmd == NULL)
  1659. return -ENOMEM;
  1660. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
  1661. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1662. cmd->antenna = cpu_to_le16(antenna);
  1663. cmd->mode = cpu_to_le16(mask);
  1664. rc = mwl8k_post_cmd(hw, &cmd->header);
  1665. kfree(cmd);
  1666. return rc;
  1667. }
  1668. /*
  1669. * CMD_SET_BEACON.
  1670. */
  1671. struct mwl8k_cmd_set_beacon {
  1672. struct mwl8k_cmd_pkt header;
  1673. __le16 beacon_len;
  1674. __u8 beacon[0];
  1675. };
  1676. static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
  1677. {
  1678. struct mwl8k_cmd_set_beacon *cmd;
  1679. int rc;
  1680. cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
  1681. if (cmd == NULL)
  1682. return -ENOMEM;
  1683. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
  1684. cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
  1685. cmd->beacon_len = cpu_to_le16(len);
  1686. memcpy(cmd->beacon, beacon, len);
  1687. rc = mwl8k_post_cmd(hw, &cmd->header);
  1688. kfree(cmd);
  1689. return rc;
  1690. }
  1691. /*
  1692. * CMD_SET_PRE_SCAN.
  1693. */
  1694. struct mwl8k_cmd_set_pre_scan {
  1695. struct mwl8k_cmd_pkt header;
  1696. } __attribute__((packed));
  1697. static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
  1698. {
  1699. struct mwl8k_cmd_set_pre_scan *cmd;
  1700. int rc;
  1701. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1702. if (cmd == NULL)
  1703. return -ENOMEM;
  1704. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
  1705. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1706. rc = mwl8k_post_cmd(hw, &cmd->header);
  1707. kfree(cmd);
  1708. return rc;
  1709. }
  1710. /*
  1711. * CMD_SET_POST_SCAN.
  1712. */
  1713. struct mwl8k_cmd_set_post_scan {
  1714. struct mwl8k_cmd_pkt header;
  1715. __le32 isibss;
  1716. __u8 bssid[ETH_ALEN];
  1717. } __attribute__((packed));
  1718. static int
  1719. mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
  1720. {
  1721. struct mwl8k_cmd_set_post_scan *cmd;
  1722. int rc;
  1723. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1724. if (cmd == NULL)
  1725. return -ENOMEM;
  1726. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
  1727. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1728. cmd->isibss = 0;
  1729. memcpy(cmd->bssid, mac, ETH_ALEN);
  1730. rc = mwl8k_post_cmd(hw, &cmd->header);
  1731. kfree(cmd);
  1732. return rc;
  1733. }
  1734. /*
  1735. * CMD_SET_RF_CHANNEL.
  1736. */
  1737. struct mwl8k_cmd_set_rf_channel {
  1738. struct mwl8k_cmd_pkt header;
  1739. __le16 action;
  1740. __u8 current_channel;
  1741. __le32 channel_flags;
  1742. } __attribute__((packed));
  1743. static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
  1744. struct ieee80211_conf *conf)
  1745. {
  1746. struct ieee80211_channel *channel = conf->channel;
  1747. struct mwl8k_cmd_set_rf_channel *cmd;
  1748. int rc;
  1749. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1750. if (cmd == NULL)
  1751. return -ENOMEM;
  1752. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
  1753. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1754. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1755. cmd->current_channel = channel->hw_value;
  1756. if (channel->band == IEEE80211_BAND_2GHZ)
  1757. cmd->channel_flags |= cpu_to_le32(0x00000001);
  1758. if (conf->channel_type == NL80211_CHAN_NO_HT ||
  1759. conf->channel_type == NL80211_CHAN_HT20)
  1760. cmd->channel_flags |= cpu_to_le32(0x00000080);
  1761. else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
  1762. cmd->channel_flags |= cpu_to_le32(0x000001900);
  1763. else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
  1764. cmd->channel_flags |= cpu_to_le32(0x000000900);
  1765. rc = mwl8k_post_cmd(hw, &cmd->header);
  1766. kfree(cmd);
  1767. return rc;
  1768. }
  1769. /*
  1770. * CMD_SET_AID.
  1771. */
  1772. #define MWL8K_FRAME_PROT_DISABLED 0x00
  1773. #define MWL8K_FRAME_PROT_11G 0x07
  1774. #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
  1775. #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
  1776. struct mwl8k_cmd_update_set_aid {
  1777. struct mwl8k_cmd_pkt header;
  1778. __le16 aid;
  1779. /* AP's MAC address (BSSID) */
  1780. __u8 bssid[ETH_ALEN];
  1781. __le16 protection_mode;
  1782. __u8 supp_rates[14];
  1783. } __attribute__((packed));
  1784. static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
  1785. {
  1786. int i;
  1787. int j;
  1788. /*
  1789. * Clear nonstandard rates 4 and 13.
  1790. */
  1791. mask &= 0x1fef;
  1792. for (i = 0, j = 0; i < 14; i++) {
  1793. if (mask & (1 << i))
  1794. rates[j++] = mwl8k_rates[i].hw_value;
  1795. }
  1796. }
  1797. static int
  1798. mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
  1799. struct ieee80211_vif *vif, u32 legacy_rate_mask)
  1800. {
  1801. struct mwl8k_cmd_update_set_aid *cmd;
  1802. u16 prot_mode;
  1803. int rc;
  1804. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1805. if (cmd == NULL)
  1806. return -ENOMEM;
  1807. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
  1808. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1809. cmd->aid = cpu_to_le16(vif->bss_conf.aid);
  1810. memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
  1811. if (vif->bss_conf.use_cts_prot) {
  1812. prot_mode = MWL8K_FRAME_PROT_11G;
  1813. } else {
  1814. switch (vif->bss_conf.ht_operation_mode &
  1815. IEEE80211_HT_OP_MODE_PROTECTION) {
  1816. case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
  1817. prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
  1818. break;
  1819. case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
  1820. prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
  1821. break;
  1822. default:
  1823. prot_mode = MWL8K_FRAME_PROT_DISABLED;
  1824. break;
  1825. }
  1826. }
  1827. cmd->protection_mode = cpu_to_le16(prot_mode);
  1828. legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
  1829. rc = mwl8k_post_cmd(hw, &cmd->header);
  1830. kfree(cmd);
  1831. return rc;
  1832. }
  1833. /*
  1834. * CMD_SET_RATE.
  1835. */
  1836. struct mwl8k_cmd_set_rate {
  1837. struct mwl8k_cmd_pkt header;
  1838. __u8 legacy_rates[14];
  1839. /* Bitmap for supported MCS codes. */
  1840. __u8 mcs_set[16];
  1841. __u8 reserved[16];
  1842. } __attribute__((packed));
  1843. static int
  1844. mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1845. u32 legacy_rate_mask, u8 *mcs_rates)
  1846. {
  1847. struct mwl8k_cmd_set_rate *cmd;
  1848. int rc;
  1849. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1850. if (cmd == NULL)
  1851. return -ENOMEM;
  1852. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
  1853. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1854. legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
  1855. memcpy(cmd->mcs_set, mcs_rates, 16);
  1856. rc = mwl8k_post_cmd(hw, &cmd->header);
  1857. kfree(cmd);
  1858. return rc;
  1859. }
  1860. /*
  1861. * CMD_FINALIZE_JOIN.
  1862. */
  1863. #define MWL8K_FJ_BEACON_MAXLEN 128
  1864. struct mwl8k_cmd_finalize_join {
  1865. struct mwl8k_cmd_pkt header;
  1866. __le32 sleep_interval; /* Number of beacon periods to sleep */
  1867. __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
  1868. } __attribute__((packed));
  1869. static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
  1870. int framelen, int dtim)
  1871. {
  1872. struct mwl8k_cmd_finalize_join *cmd;
  1873. struct ieee80211_mgmt *payload = frame;
  1874. int payload_len;
  1875. int rc;
  1876. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1877. if (cmd == NULL)
  1878. return -ENOMEM;
  1879. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
  1880. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1881. cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
  1882. payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
  1883. if (payload_len < 0)
  1884. payload_len = 0;
  1885. else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
  1886. payload_len = MWL8K_FJ_BEACON_MAXLEN;
  1887. memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
  1888. rc = mwl8k_post_cmd(hw, &cmd->header);
  1889. kfree(cmd);
  1890. return rc;
  1891. }
  1892. /*
  1893. * CMD_SET_RTS_THRESHOLD.
  1894. */
  1895. struct mwl8k_cmd_set_rts_threshold {
  1896. struct mwl8k_cmd_pkt header;
  1897. __le16 action;
  1898. __le16 threshold;
  1899. } __attribute__((packed));
  1900. static int
  1901. mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
  1902. {
  1903. struct mwl8k_cmd_set_rts_threshold *cmd;
  1904. int rc;
  1905. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1906. if (cmd == NULL)
  1907. return -ENOMEM;
  1908. cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
  1909. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1910. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1911. cmd->threshold = cpu_to_le16(rts_thresh);
  1912. rc = mwl8k_post_cmd(hw, &cmd->header);
  1913. kfree(cmd);
  1914. return rc;
  1915. }
  1916. /*
  1917. * CMD_SET_SLOT.
  1918. */
  1919. struct mwl8k_cmd_set_slot {
  1920. struct mwl8k_cmd_pkt header;
  1921. __le16 action;
  1922. __u8 short_slot;
  1923. } __attribute__((packed));
  1924. static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
  1925. {
  1926. struct mwl8k_cmd_set_slot *cmd;
  1927. int rc;
  1928. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1929. if (cmd == NULL)
  1930. return -ENOMEM;
  1931. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
  1932. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1933. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1934. cmd->short_slot = short_slot_time;
  1935. rc = mwl8k_post_cmd(hw, &cmd->header);
  1936. kfree(cmd);
  1937. return rc;
  1938. }
  1939. /*
  1940. * CMD_SET_EDCA_PARAMS.
  1941. */
  1942. struct mwl8k_cmd_set_edca_params {
  1943. struct mwl8k_cmd_pkt header;
  1944. /* See MWL8K_SET_EDCA_XXX below */
  1945. __le16 action;
  1946. /* TX opportunity in units of 32 us */
  1947. __le16 txop;
  1948. union {
  1949. struct {
  1950. /* Log exponent of max contention period: 0...15 */
  1951. __le32 log_cw_max;
  1952. /* Log exponent of min contention period: 0...15 */
  1953. __le32 log_cw_min;
  1954. /* Adaptive interframe spacing in units of 32us */
  1955. __u8 aifs;
  1956. /* TX queue to configure */
  1957. __u8 txq;
  1958. } ap;
  1959. struct {
  1960. /* Log exponent of max contention period: 0...15 */
  1961. __u8 log_cw_max;
  1962. /* Log exponent of min contention period: 0...15 */
  1963. __u8 log_cw_min;
  1964. /* Adaptive interframe spacing in units of 32us */
  1965. __u8 aifs;
  1966. /* TX queue to configure */
  1967. __u8 txq;
  1968. } sta;
  1969. };
  1970. } __attribute__((packed));
  1971. #define MWL8K_SET_EDCA_CW 0x01
  1972. #define MWL8K_SET_EDCA_TXOP 0x02
  1973. #define MWL8K_SET_EDCA_AIFS 0x04
  1974. #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
  1975. MWL8K_SET_EDCA_TXOP | \
  1976. MWL8K_SET_EDCA_AIFS)
  1977. static int
  1978. mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
  1979. __u16 cw_min, __u16 cw_max,
  1980. __u8 aifs, __u16 txop)
  1981. {
  1982. struct mwl8k_priv *priv = hw->priv;
  1983. struct mwl8k_cmd_set_edca_params *cmd;
  1984. int rc;
  1985. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1986. if (cmd == NULL)
  1987. return -ENOMEM;
  1988. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
  1989. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1990. cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
  1991. cmd->txop = cpu_to_le16(txop);
  1992. if (priv->ap_fw) {
  1993. cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
  1994. cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
  1995. cmd->ap.aifs = aifs;
  1996. cmd->ap.txq = qnum;
  1997. } else {
  1998. cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
  1999. cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
  2000. cmd->sta.aifs = aifs;
  2001. cmd->sta.txq = qnum;
  2002. }
  2003. rc = mwl8k_post_cmd(hw, &cmd->header);
  2004. kfree(cmd);
  2005. return rc;
  2006. }
  2007. /*
  2008. * CMD_SET_WMM_MODE.
  2009. */
  2010. struct mwl8k_cmd_set_wmm_mode {
  2011. struct mwl8k_cmd_pkt header;
  2012. __le16 action;
  2013. } __attribute__((packed));
  2014. static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
  2015. {
  2016. struct mwl8k_priv *priv = hw->priv;
  2017. struct mwl8k_cmd_set_wmm_mode *cmd;
  2018. int rc;
  2019. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2020. if (cmd == NULL)
  2021. return -ENOMEM;
  2022. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
  2023. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2024. cmd->action = cpu_to_le16(!!enable);
  2025. rc = mwl8k_post_cmd(hw, &cmd->header);
  2026. kfree(cmd);
  2027. if (!rc)
  2028. priv->wmm_enabled = enable;
  2029. return rc;
  2030. }
  2031. /*
  2032. * CMD_MIMO_CONFIG.
  2033. */
  2034. struct mwl8k_cmd_mimo_config {
  2035. struct mwl8k_cmd_pkt header;
  2036. __le32 action;
  2037. __u8 rx_antenna_map;
  2038. __u8 tx_antenna_map;
  2039. } __attribute__((packed));
  2040. static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
  2041. {
  2042. struct mwl8k_cmd_mimo_config *cmd;
  2043. int rc;
  2044. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2045. if (cmd == NULL)
  2046. return -ENOMEM;
  2047. cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
  2048. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2049. cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
  2050. cmd->rx_antenna_map = rx;
  2051. cmd->tx_antenna_map = tx;
  2052. rc = mwl8k_post_cmd(hw, &cmd->header);
  2053. kfree(cmd);
  2054. return rc;
  2055. }
  2056. /*
  2057. * CMD_USE_FIXED_RATE (STA version).
  2058. */
  2059. struct mwl8k_cmd_use_fixed_rate_sta {
  2060. struct mwl8k_cmd_pkt header;
  2061. __le32 action;
  2062. __le32 allow_rate_drop;
  2063. __le32 num_rates;
  2064. struct {
  2065. __le32 is_ht_rate;
  2066. __le32 enable_retry;
  2067. __le32 rate;
  2068. __le32 retry_count;
  2069. } rate_entry[8];
  2070. __le32 rate_type;
  2071. __le32 reserved1;
  2072. __le32 reserved2;
  2073. } __attribute__((packed));
  2074. #define MWL8K_USE_AUTO_RATE 0x0002
  2075. #define MWL8K_UCAST_RATE 0
  2076. static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
  2077. {
  2078. struct mwl8k_cmd_use_fixed_rate_sta *cmd;
  2079. int rc;
  2080. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2081. if (cmd == NULL)
  2082. return -ENOMEM;
  2083. cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
  2084. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2085. cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
  2086. cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
  2087. rc = mwl8k_post_cmd(hw, &cmd->header);
  2088. kfree(cmd);
  2089. return rc;
  2090. }
  2091. /*
  2092. * CMD_USE_FIXED_RATE (AP version).
  2093. */
  2094. struct mwl8k_cmd_use_fixed_rate_ap {
  2095. struct mwl8k_cmd_pkt header;
  2096. __le32 action;
  2097. __le32 allow_rate_drop;
  2098. __le32 num_rates;
  2099. struct mwl8k_rate_entry_ap {
  2100. __le32 is_ht_rate;
  2101. __le32 enable_retry;
  2102. __le32 rate;
  2103. __le32 retry_count;
  2104. } rate_entry[4];
  2105. u8 multicast_rate;
  2106. u8 multicast_rate_type;
  2107. u8 management_rate;
  2108. } __attribute__((packed));
  2109. static int
  2110. mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
  2111. {
  2112. struct mwl8k_cmd_use_fixed_rate_ap *cmd;
  2113. int rc;
  2114. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2115. if (cmd == NULL)
  2116. return -ENOMEM;
  2117. cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
  2118. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2119. cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
  2120. cmd->multicast_rate = mcast;
  2121. cmd->management_rate = mgmt;
  2122. rc = mwl8k_post_cmd(hw, &cmd->header);
  2123. kfree(cmd);
  2124. return rc;
  2125. }
  2126. /*
  2127. * CMD_ENABLE_SNIFFER.
  2128. */
  2129. struct mwl8k_cmd_enable_sniffer {
  2130. struct mwl8k_cmd_pkt header;
  2131. __le32 action;
  2132. } __attribute__((packed));
  2133. static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
  2134. {
  2135. struct mwl8k_cmd_enable_sniffer *cmd;
  2136. int rc;
  2137. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2138. if (cmd == NULL)
  2139. return -ENOMEM;
  2140. cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
  2141. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2142. cmd->action = cpu_to_le32(!!enable);
  2143. rc = mwl8k_post_cmd(hw, &cmd->header);
  2144. kfree(cmd);
  2145. return rc;
  2146. }
  2147. /*
  2148. * CMD_SET_MAC_ADDR.
  2149. */
  2150. struct mwl8k_cmd_set_mac_addr {
  2151. struct mwl8k_cmd_pkt header;
  2152. union {
  2153. struct {
  2154. __le16 mac_type;
  2155. __u8 mac_addr[ETH_ALEN];
  2156. } mbss;
  2157. __u8 mac_addr[ETH_ALEN];
  2158. };
  2159. } __attribute__((packed));
  2160. #define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
  2161. #define MWL8K_MAC_TYPE_PRIMARY_AP 2
  2162. static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
  2163. {
  2164. struct mwl8k_priv *priv = hw->priv;
  2165. struct mwl8k_cmd_set_mac_addr *cmd;
  2166. int rc;
  2167. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2168. if (cmd == NULL)
  2169. return -ENOMEM;
  2170. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
  2171. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2172. if (priv->ap_fw) {
  2173. cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
  2174. memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
  2175. } else {
  2176. memcpy(cmd->mac_addr, mac, ETH_ALEN);
  2177. }
  2178. rc = mwl8k_post_cmd(hw, &cmd->header);
  2179. kfree(cmd);
  2180. return rc;
  2181. }
  2182. /*
  2183. * CMD_SET_RATEADAPT_MODE.
  2184. */
  2185. struct mwl8k_cmd_set_rate_adapt_mode {
  2186. struct mwl8k_cmd_pkt header;
  2187. __le16 action;
  2188. __le16 mode;
  2189. } __attribute__((packed));
  2190. static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
  2191. {
  2192. struct mwl8k_cmd_set_rate_adapt_mode *cmd;
  2193. int rc;
  2194. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2195. if (cmd == NULL)
  2196. return -ENOMEM;
  2197. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
  2198. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2199. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  2200. cmd->mode = cpu_to_le16(mode);
  2201. rc = mwl8k_post_cmd(hw, &cmd->header);
  2202. kfree(cmd);
  2203. return rc;
  2204. }
  2205. /*
  2206. * CMD_BSS_START.
  2207. */
  2208. struct mwl8k_cmd_bss_start {
  2209. struct mwl8k_cmd_pkt header;
  2210. __le32 enable;
  2211. } __attribute__((packed));
  2212. static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
  2213. {
  2214. struct mwl8k_cmd_bss_start *cmd;
  2215. int rc;
  2216. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2217. if (cmd == NULL)
  2218. return -ENOMEM;
  2219. cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
  2220. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2221. cmd->enable = cpu_to_le32(enable);
  2222. rc = mwl8k_post_cmd(hw, &cmd->header);
  2223. kfree(cmd);
  2224. return rc;
  2225. }
  2226. /*
  2227. * CMD_SET_NEW_STN.
  2228. */
  2229. struct mwl8k_cmd_set_new_stn {
  2230. struct mwl8k_cmd_pkt header;
  2231. __le16 aid;
  2232. __u8 mac_addr[6];
  2233. __le16 stn_id;
  2234. __le16 action;
  2235. __le16 rsvd;
  2236. __le32 legacy_rates;
  2237. __u8 ht_rates[4];
  2238. __le16 cap_info;
  2239. __le16 ht_capabilities_info;
  2240. __u8 mac_ht_param_info;
  2241. __u8 rev;
  2242. __u8 control_channel;
  2243. __u8 add_channel;
  2244. __le16 op_mode;
  2245. __le16 stbc;
  2246. __u8 add_qos_info;
  2247. __u8 is_qos_sta;
  2248. __le32 fw_sta_ptr;
  2249. } __attribute__((packed));
  2250. #define MWL8K_STA_ACTION_ADD 0
  2251. #define MWL8K_STA_ACTION_REMOVE 2
  2252. static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
  2253. struct ieee80211_vif *vif,
  2254. struct ieee80211_sta *sta)
  2255. {
  2256. struct mwl8k_cmd_set_new_stn *cmd;
  2257. int rc;
  2258. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2259. if (cmd == NULL)
  2260. return -ENOMEM;
  2261. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
  2262. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2263. cmd->aid = cpu_to_le16(sta->aid);
  2264. memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
  2265. cmd->stn_id = cpu_to_le16(sta->aid);
  2266. cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
  2267. cmd->legacy_rates = cpu_to_le32(sta->supp_rates[IEEE80211_BAND_2GHZ]);
  2268. if (sta->ht_cap.ht_supported) {
  2269. cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
  2270. cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
  2271. cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
  2272. cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
  2273. cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
  2274. cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
  2275. ((sta->ht_cap.ampdu_density & 7) << 2);
  2276. cmd->is_qos_sta = 1;
  2277. }
  2278. rc = mwl8k_post_cmd(hw, &cmd->header);
  2279. kfree(cmd);
  2280. return rc;
  2281. }
  2282. static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
  2283. struct ieee80211_vif *vif)
  2284. {
  2285. struct mwl8k_cmd_set_new_stn *cmd;
  2286. int rc;
  2287. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2288. if (cmd == NULL)
  2289. return -ENOMEM;
  2290. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
  2291. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2292. memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
  2293. rc = mwl8k_post_cmd(hw, &cmd->header);
  2294. kfree(cmd);
  2295. return rc;
  2296. }
  2297. static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
  2298. struct ieee80211_vif *vif, u8 *addr)
  2299. {
  2300. struct mwl8k_cmd_set_new_stn *cmd;
  2301. int rc;
  2302. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2303. if (cmd == NULL)
  2304. return -ENOMEM;
  2305. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
  2306. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2307. memcpy(cmd->mac_addr, addr, ETH_ALEN);
  2308. cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
  2309. rc = mwl8k_post_cmd(hw, &cmd->header);
  2310. kfree(cmd);
  2311. return rc;
  2312. }
  2313. /*
  2314. * CMD_UPDATE_STADB.
  2315. */
  2316. struct ewc_ht_info {
  2317. __le16 control1;
  2318. __le16 control2;
  2319. __le16 control3;
  2320. } __attribute__((packed));
  2321. struct peer_capability_info {
  2322. /* Peer type - AP vs. STA. */
  2323. __u8 peer_type;
  2324. /* Basic 802.11 capabilities from assoc resp. */
  2325. __le16 basic_caps;
  2326. /* Set if peer supports 802.11n high throughput (HT). */
  2327. __u8 ht_support;
  2328. /* Valid if HT is supported. */
  2329. __le16 ht_caps;
  2330. __u8 extended_ht_caps;
  2331. struct ewc_ht_info ewc_info;
  2332. /* Legacy rate table. Intersection of our rates and peer rates. */
  2333. __u8 legacy_rates[12];
  2334. /* HT rate table. Intersection of our rates and peer rates. */
  2335. __u8 ht_rates[16];
  2336. __u8 pad[16];
  2337. /* If set, interoperability mode, no proprietary extensions. */
  2338. __u8 interop;
  2339. __u8 pad2;
  2340. __u8 station_id;
  2341. __le16 amsdu_enabled;
  2342. } __attribute__((packed));
  2343. struct mwl8k_cmd_update_stadb {
  2344. struct mwl8k_cmd_pkt header;
  2345. /* See STADB_ACTION_TYPE */
  2346. __le32 action;
  2347. /* Peer MAC address */
  2348. __u8 peer_addr[ETH_ALEN];
  2349. __le32 reserved;
  2350. /* Peer info - valid during add/update. */
  2351. struct peer_capability_info peer_info;
  2352. } __attribute__((packed));
  2353. #define MWL8K_STA_DB_MODIFY_ENTRY 1
  2354. #define MWL8K_STA_DB_DEL_ENTRY 2
  2355. /* Peer Entry flags - used to define the type of the peer node */
  2356. #define MWL8K_PEER_TYPE_ACCESSPOINT 2
  2357. static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
  2358. struct ieee80211_vif *vif,
  2359. struct ieee80211_sta *sta)
  2360. {
  2361. struct mwl8k_cmd_update_stadb *cmd;
  2362. struct peer_capability_info *p;
  2363. int rc;
  2364. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2365. if (cmd == NULL)
  2366. return -ENOMEM;
  2367. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2368. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2369. cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
  2370. memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
  2371. p = &cmd->peer_info;
  2372. p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
  2373. p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
  2374. p->ht_support = sta->ht_cap.ht_supported;
  2375. p->ht_caps = sta->ht_cap.cap;
  2376. p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
  2377. ((sta->ht_cap.ampdu_density & 7) << 2);
  2378. legacy_rate_mask_to_array(p->legacy_rates,
  2379. sta->supp_rates[IEEE80211_BAND_2GHZ]);
  2380. memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
  2381. p->interop = 1;
  2382. p->amsdu_enabled = 0;
  2383. rc = mwl8k_post_cmd(hw, &cmd->header);
  2384. kfree(cmd);
  2385. return rc ? rc : p->station_id;
  2386. }
  2387. static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
  2388. struct ieee80211_vif *vif, u8 *addr)
  2389. {
  2390. struct mwl8k_cmd_update_stadb *cmd;
  2391. int rc;
  2392. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2393. if (cmd == NULL)
  2394. return -ENOMEM;
  2395. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2396. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2397. cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
  2398. memcpy(cmd->peer_addr, addr, ETH_ALEN);
  2399. rc = mwl8k_post_cmd(hw, &cmd->header);
  2400. kfree(cmd);
  2401. return rc;
  2402. }
  2403. /*
  2404. * Interrupt handling.
  2405. */
  2406. static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
  2407. {
  2408. struct ieee80211_hw *hw = dev_id;
  2409. struct mwl8k_priv *priv = hw->priv;
  2410. u32 status;
  2411. status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2412. if (!status)
  2413. return IRQ_NONE;
  2414. if (status & MWL8K_A2H_INT_TX_DONE) {
  2415. status &= ~MWL8K_A2H_INT_TX_DONE;
  2416. tasklet_schedule(&priv->poll_tx_task);
  2417. }
  2418. if (status & MWL8K_A2H_INT_RX_READY) {
  2419. status &= ~MWL8K_A2H_INT_RX_READY;
  2420. tasklet_schedule(&priv->poll_rx_task);
  2421. }
  2422. if (status)
  2423. iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2424. if (status & MWL8K_A2H_INT_OPC_DONE) {
  2425. if (priv->hostcmd_wait != NULL)
  2426. complete(priv->hostcmd_wait);
  2427. }
  2428. if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
  2429. if (!mutex_is_locked(&priv->fw_mutex) &&
  2430. priv->radio_on && priv->pending_tx_pkts)
  2431. mwl8k_tx_start(priv);
  2432. }
  2433. return IRQ_HANDLED;
  2434. }
  2435. static void mwl8k_tx_poll(unsigned long data)
  2436. {
  2437. struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
  2438. struct mwl8k_priv *priv = hw->priv;
  2439. int limit;
  2440. int i;
  2441. limit = 32;
  2442. spin_lock_bh(&priv->tx_lock);
  2443. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2444. limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
  2445. if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
  2446. complete(priv->tx_wait);
  2447. priv->tx_wait = NULL;
  2448. }
  2449. spin_unlock_bh(&priv->tx_lock);
  2450. if (limit) {
  2451. writel(~MWL8K_A2H_INT_TX_DONE,
  2452. priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2453. } else {
  2454. tasklet_schedule(&priv->poll_tx_task);
  2455. }
  2456. }
  2457. static void mwl8k_rx_poll(unsigned long data)
  2458. {
  2459. struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
  2460. struct mwl8k_priv *priv = hw->priv;
  2461. int limit;
  2462. limit = 32;
  2463. limit -= rxq_process(hw, 0, limit);
  2464. limit -= rxq_refill(hw, 0, limit);
  2465. if (limit) {
  2466. writel(~MWL8K_A2H_INT_RX_READY,
  2467. priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2468. } else {
  2469. tasklet_schedule(&priv->poll_rx_task);
  2470. }
  2471. }
  2472. /*
  2473. * Core driver operations.
  2474. */
  2475. static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2476. {
  2477. struct mwl8k_priv *priv = hw->priv;
  2478. int index = skb_get_queue_mapping(skb);
  2479. int rc;
  2480. if (!priv->radio_on) {
  2481. printk(KERN_DEBUG "%s: dropped TX frame since radio "
  2482. "disabled\n", wiphy_name(hw->wiphy));
  2483. dev_kfree_skb(skb);
  2484. return NETDEV_TX_OK;
  2485. }
  2486. rc = mwl8k_txq_xmit(hw, index, skb);
  2487. return rc;
  2488. }
  2489. static int mwl8k_start(struct ieee80211_hw *hw)
  2490. {
  2491. struct mwl8k_priv *priv = hw->priv;
  2492. int rc;
  2493. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  2494. IRQF_SHARED, MWL8K_NAME, hw);
  2495. if (rc) {
  2496. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  2497. wiphy_name(hw->wiphy));
  2498. return -EIO;
  2499. }
  2500. /* Enable TX reclaim and RX tasklets. */
  2501. tasklet_enable(&priv->poll_tx_task);
  2502. tasklet_enable(&priv->poll_rx_task);
  2503. /* Enable interrupts */
  2504. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2505. rc = mwl8k_fw_lock(hw);
  2506. if (!rc) {
  2507. rc = mwl8k_cmd_radio_enable(hw);
  2508. if (!priv->ap_fw) {
  2509. if (!rc)
  2510. rc = mwl8k_cmd_enable_sniffer(hw, 0);
  2511. if (!rc)
  2512. rc = mwl8k_cmd_set_pre_scan(hw);
  2513. if (!rc)
  2514. rc = mwl8k_cmd_set_post_scan(hw,
  2515. "\x00\x00\x00\x00\x00\x00");
  2516. }
  2517. if (!rc)
  2518. rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
  2519. if (!rc)
  2520. rc = mwl8k_cmd_set_wmm_mode(hw, 0);
  2521. mwl8k_fw_unlock(hw);
  2522. }
  2523. if (rc) {
  2524. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2525. free_irq(priv->pdev->irq, hw);
  2526. tasklet_disable(&priv->poll_tx_task);
  2527. tasklet_disable(&priv->poll_rx_task);
  2528. }
  2529. return rc;
  2530. }
  2531. static void mwl8k_stop(struct ieee80211_hw *hw)
  2532. {
  2533. struct mwl8k_priv *priv = hw->priv;
  2534. int i;
  2535. mwl8k_cmd_radio_disable(hw);
  2536. ieee80211_stop_queues(hw);
  2537. /* Disable interrupts */
  2538. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2539. free_irq(priv->pdev->irq, hw);
  2540. /* Stop finalize join worker */
  2541. cancel_work_sync(&priv->finalize_join_worker);
  2542. if (priv->beacon_skb != NULL)
  2543. dev_kfree_skb(priv->beacon_skb);
  2544. /* Stop TX reclaim and RX tasklets. */
  2545. tasklet_disable(&priv->poll_tx_task);
  2546. tasklet_disable(&priv->poll_rx_task);
  2547. /* Return all skbs to mac80211 */
  2548. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2549. mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
  2550. }
  2551. static int mwl8k_add_interface(struct ieee80211_hw *hw,
  2552. struct ieee80211_vif *vif)
  2553. {
  2554. struct mwl8k_priv *priv = hw->priv;
  2555. struct mwl8k_vif *mwl8k_vif;
  2556. /*
  2557. * We only support one active interface at a time.
  2558. */
  2559. if (priv->vif != NULL)
  2560. return -EBUSY;
  2561. /*
  2562. * Reject interface creation if sniffer mode is active, as
  2563. * STA operation is mutually exclusive with hardware sniffer
  2564. * mode. (Sniffer mode is only used on STA firmware.)
  2565. */
  2566. if (priv->sniffer_enabled) {
  2567. printk(KERN_INFO "%s: unable to create STA "
  2568. "interface due to sniffer mode being enabled\n",
  2569. wiphy_name(hw->wiphy));
  2570. return -EINVAL;
  2571. }
  2572. /* Set the mac address. */
  2573. mwl8k_cmd_set_mac_addr(hw, vif->addr);
  2574. if (priv->ap_fw)
  2575. mwl8k_cmd_set_new_stn_add_self(hw, vif);
  2576. /* Clean out driver private area */
  2577. mwl8k_vif = MWL8K_VIF(vif);
  2578. memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
  2579. /* Set Initial sequence number to zero */
  2580. mwl8k_vif->seqno = 0;
  2581. priv->vif = vif;
  2582. return 0;
  2583. }
  2584. static void mwl8k_remove_interface(struct ieee80211_hw *hw,
  2585. struct ieee80211_vif *vif)
  2586. {
  2587. struct mwl8k_priv *priv = hw->priv;
  2588. if (priv->ap_fw)
  2589. mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
  2590. mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  2591. priv->vif = NULL;
  2592. }
  2593. static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
  2594. {
  2595. struct ieee80211_conf *conf = &hw->conf;
  2596. struct mwl8k_priv *priv = hw->priv;
  2597. int rc;
  2598. if (conf->flags & IEEE80211_CONF_IDLE) {
  2599. mwl8k_cmd_radio_disable(hw);
  2600. return 0;
  2601. }
  2602. rc = mwl8k_fw_lock(hw);
  2603. if (rc)
  2604. return rc;
  2605. rc = mwl8k_cmd_radio_enable(hw);
  2606. if (rc)
  2607. goto out;
  2608. rc = mwl8k_cmd_set_rf_channel(hw, conf);
  2609. if (rc)
  2610. goto out;
  2611. if (conf->power_level > 18)
  2612. conf->power_level = 18;
  2613. rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
  2614. if (rc)
  2615. goto out;
  2616. if (priv->ap_fw) {
  2617. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
  2618. if (!rc)
  2619. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
  2620. } else {
  2621. rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
  2622. }
  2623. out:
  2624. mwl8k_fw_unlock(hw);
  2625. return rc;
  2626. }
  2627. static void
  2628. mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2629. struct ieee80211_bss_conf *info, u32 changed)
  2630. {
  2631. struct mwl8k_priv *priv = hw->priv;
  2632. u32 ap_legacy_rates;
  2633. u8 ap_mcs_rates[16];
  2634. int rc;
  2635. if (mwl8k_fw_lock(hw))
  2636. return;
  2637. /*
  2638. * No need to capture a beacon if we're no longer associated.
  2639. */
  2640. if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
  2641. priv->capture_beacon = false;
  2642. /*
  2643. * Get the AP's legacy and MCS rates.
  2644. */
  2645. if (vif->bss_conf.assoc) {
  2646. struct ieee80211_sta *ap;
  2647. rcu_read_lock();
  2648. ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
  2649. if (ap == NULL) {
  2650. rcu_read_unlock();
  2651. goto out;
  2652. }
  2653. ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
  2654. memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
  2655. rcu_read_unlock();
  2656. }
  2657. if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
  2658. rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
  2659. if (rc)
  2660. goto out;
  2661. rc = mwl8k_cmd_use_fixed_rate_sta(hw);
  2662. if (rc)
  2663. goto out;
  2664. }
  2665. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  2666. rc = mwl8k_set_radio_preamble(hw,
  2667. vif->bss_conf.use_short_preamble);
  2668. if (rc)
  2669. goto out;
  2670. }
  2671. if (changed & BSS_CHANGED_ERP_SLOT) {
  2672. rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
  2673. if (rc)
  2674. goto out;
  2675. }
  2676. if (vif->bss_conf.assoc &&
  2677. (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
  2678. BSS_CHANGED_HT))) {
  2679. rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
  2680. if (rc)
  2681. goto out;
  2682. }
  2683. if (vif->bss_conf.assoc &&
  2684. (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
  2685. /*
  2686. * Finalize the join. Tell rx handler to process
  2687. * next beacon from our BSSID.
  2688. */
  2689. memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
  2690. priv->capture_beacon = true;
  2691. }
  2692. out:
  2693. mwl8k_fw_unlock(hw);
  2694. }
  2695. static void
  2696. mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2697. struct ieee80211_bss_conf *info, u32 changed)
  2698. {
  2699. int rc;
  2700. if (mwl8k_fw_lock(hw))
  2701. return;
  2702. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  2703. rc = mwl8k_set_radio_preamble(hw,
  2704. vif->bss_conf.use_short_preamble);
  2705. if (rc)
  2706. goto out;
  2707. }
  2708. if (changed & BSS_CHANGED_BASIC_RATES) {
  2709. int idx;
  2710. int rate;
  2711. /*
  2712. * Use lowest supported basic rate for multicasts
  2713. * and management frames (such as probe responses --
  2714. * beacons will always go out at 1 Mb/s).
  2715. */
  2716. idx = ffs(vif->bss_conf.basic_rates);
  2717. rate = idx ? mwl8k_rates[idx - 1].hw_value : 2;
  2718. mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
  2719. }
  2720. if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
  2721. struct sk_buff *skb;
  2722. skb = ieee80211_beacon_get(hw, vif);
  2723. if (skb != NULL) {
  2724. mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
  2725. kfree_skb(skb);
  2726. }
  2727. }
  2728. if (changed & BSS_CHANGED_BEACON_ENABLED)
  2729. mwl8k_cmd_bss_start(hw, info->enable_beacon);
  2730. out:
  2731. mwl8k_fw_unlock(hw);
  2732. }
  2733. static void
  2734. mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2735. struct ieee80211_bss_conf *info, u32 changed)
  2736. {
  2737. struct mwl8k_priv *priv = hw->priv;
  2738. if (!priv->ap_fw)
  2739. mwl8k_bss_info_changed_sta(hw, vif, info, changed);
  2740. else
  2741. mwl8k_bss_info_changed_ap(hw, vif, info, changed);
  2742. }
  2743. static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
  2744. int mc_count, struct dev_addr_list *mclist)
  2745. {
  2746. struct mwl8k_cmd_pkt *cmd;
  2747. /*
  2748. * Synthesize and return a command packet that programs the
  2749. * hardware multicast address filter. At this point we don't
  2750. * know whether FIF_ALLMULTI is being requested, but if it is,
  2751. * we'll end up throwing this packet away and creating a new
  2752. * one in mwl8k_configure_filter().
  2753. */
  2754. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
  2755. return (unsigned long)cmd;
  2756. }
  2757. static int
  2758. mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
  2759. unsigned int changed_flags,
  2760. unsigned int *total_flags)
  2761. {
  2762. struct mwl8k_priv *priv = hw->priv;
  2763. /*
  2764. * Hardware sniffer mode is mutually exclusive with STA
  2765. * operation, so refuse to enable sniffer mode if a STA
  2766. * interface is active.
  2767. */
  2768. if (priv->vif != NULL) {
  2769. if (net_ratelimit())
  2770. printk(KERN_INFO "%s: not enabling sniffer "
  2771. "mode because STA interface is active\n",
  2772. wiphy_name(hw->wiphy));
  2773. return 0;
  2774. }
  2775. if (!priv->sniffer_enabled) {
  2776. if (mwl8k_cmd_enable_sniffer(hw, 1))
  2777. return 0;
  2778. priv->sniffer_enabled = true;
  2779. }
  2780. *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
  2781. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
  2782. FIF_OTHER_BSS;
  2783. return 1;
  2784. }
  2785. static void mwl8k_configure_filter(struct ieee80211_hw *hw,
  2786. unsigned int changed_flags,
  2787. unsigned int *total_flags,
  2788. u64 multicast)
  2789. {
  2790. struct mwl8k_priv *priv = hw->priv;
  2791. struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
  2792. /*
  2793. * AP firmware doesn't allow fine-grained control over
  2794. * the receive filter.
  2795. */
  2796. if (priv->ap_fw) {
  2797. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2798. kfree(cmd);
  2799. return;
  2800. }
  2801. /*
  2802. * Enable hardware sniffer mode if FIF_CONTROL or
  2803. * FIF_OTHER_BSS is requested.
  2804. */
  2805. if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
  2806. mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
  2807. kfree(cmd);
  2808. return;
  2809. }
  2810. /* Clear unsupported feature flags */
  2811. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2812. if (mwl8k_fw_lock(hw)) {
  2813. kfree(cmd);
  2814. return;
  2815. }
  2816. if (priv->sniffer_enabled) {
  2817. mwl8k_cmd_enable_sniffer(hw, 0);
  2818. priv->sniffer_enabled = false;
  2819. }
  2820. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  2821. if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
  2822. /*
  2823. * Disable the BSS filter.
  2824. */
  2825. mwl8k_cmd_set_pre_scan(hw);
  2826. } else {
  2827. const u8 *bssid;
  2828. /*
  2829. * Enable the BSS filter.
  2830. *
  2831. * If there is an active STA interface, use that
  2832. * interface's BSSID, otherwise use a dummy one
  2833. * (where the OUI part needs to be nonzero for
  2834. * the BSSID to be accepted by POST_SCAN).
  2835. */
  2836. bssid = "\x01\x00\x00\x00\x00\x00";
  2837. if (priv->vif != NULL)
  2838. bssid = priv->vif->bss_conf.bssid;
  2839. mwl8k_cmd_set_post_scan(hw, bssid);
  2840. }
  2841. }
  2842. /*
  2843. * If FIF_ALLMULTI is being requested, throw away the command
  2844. * packet that ->prepare_multicast() built and replace it with
  2845. * a command packet that enables reception of all multicast
  2846. * packets.
  2847. */
  2848. if (*total_flags & FIF_ALLMULTI) {
  2849. kfree(cmd);
  2850. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
  2851. }
  2852. if (cmd != NULL) {
  2853. mwl8k_post_cmd(hw, cmd);
  2854. kfree(cmd);
  2855. }
  2856. mwl8k_fw_unlock(hw);
  2857. }
  2858. static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
  2859. {
  2860. return mwl8k_cmd_set_rts_threshold(hw, value);
  2861. }
  2862. struct mwl8k_sta_notify_item
  2863. {
  2864. struct list_head list;
  2865. struct ieee80211_vif *vif;
  2866. enum sta_notify_cmd cmd;
  2867. struct ieee80211_sta sta;
  2868. };
  2869. static void
  2870. mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
  2871. {
  2872. struct mwl8k_priv *priv = hw->priv;
  2873. /*
  2874. * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
  2875. */
  2876. if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
  2877. int rc;
  2878. rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
  2879. if (rc >= 0) {
  2880. struct ieee80211_sta *sta;
  2881. rcu_read_lock();
  2882. sta = ieee80211_find_sta(s->vif, s->sta.addr);
  2883. if (sta != NULL)
  2884. MWL8K_STA(sta)->peer_id = rc;
  2885. rcu_read_unlock();
  2886. }
  2887. } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
  2888. mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
  2889. } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
  2890. mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
  2891. } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
  2892. mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
  2893. }
  2894. }
  2895. static void mwl8k_sta_notify_worker(struct work_struct *work)
  2896. {
  2897. struct mwl8k_priv *priv =
  2898. container_of(work, struct mwl8k_priv, sta_notify_worker);
  2899. struct ieee80211_hw *hw = priv->hw;
  2900. spin_lock_bh(&priv->sta_notify_list_lock);
  2901. while (!list_empty(&priv->sta_notify_list)) {
  2902. struct mwl8k_sta_notify_item *s;
  2903. s = list_entry(priv->sta_notify_list.next,
  2904. struct mwl8k_sta_notify_item, list);
  2905. list_del(&s->list);
  2906. spin_unlock_bh(&priv->sta_notify_list_lock);
  2907. mwl8k_do_sta_notify(hw, s);
  2908. kfree(s);
  2909. spin_lock_bh(&priv->sta_notify_list_lock);
  2910. }
  2911. spin_unlock_bh(&priv->sta_notify_list_lock);
  2912. }
  2913. static void
  2914. mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2915. enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
  2916. {
  2917. struct mwl8k_priv *priv = hw->priv;
  2918. struct mwl8k_sta_notify_item *s;
  2919. if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
  2920. return;
  2921. s = kmalloc(sizeof(*s), GFP_ATOMIC);
  2922. if (s != NULL) {
  2923. s->vif = vif;
  2924. s->cmd = cmd;
  2925. s->sta = *sta;
  2926. spin_lock(&priv->sta_notify_list_lock);
  2927. list_add_tail(&s->list, &priv->sta_notify_list);
  2928. spin_unlock(&priv->sta_notify_list_lock);
  2929. ieee80211_queue_work(hw, &priv->sta_notify_worker);
  2930. }
  2931. }
  2932. static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  2933. const struct ieee80211_tx_queue_params *params)
  2934. {
  2935. struct mwl8k_priv *priv = hw->priv;
  2936. int rc;
  2937. rc = mwl8k_fw_lock(hw);
  2938. if (!rc) {
  2939. if (!priv->wmm_enabled)
  2940. rc = mwl8k_cmd_set_wmm_mode(hw, 1);
  2941. if (!rc)
  2942. rc = mwl8k_cmd_set_edca_params(hw, queue,
  2943. params->cw_min,
  2944. params->cw_max,
  2945. params->aifs,
  2946. params->txop);
  2947. mwl8k_fw_unlock(hw);
  2948. }
  2949. return rc;
  2950. }
  2951. static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
  2952. struct ieee80211_tx_queue_stats *stats)
  2953. {
  2954. struct mwl8k_priv *priv = hw->priv;
  2955. struct mwl8k_tx_queue *txq;
  2956. int index;
  2957. spin_lock_bh(&priv->tx_lock);
  2958. for (index = 0; index < MWL8K_TX_QUEUES; index++) {
  2959. txq = priv->txq + index;
  2960. memcpy(&stats[index], &txq->stats,
  2961. sizeof(struct ieee80211_tx_queue_stats));
  2962. }
  2963. spin_unlock_bh(&priv->tx_lock);
  2964. return 0;
  2965. }
  2966. static int mwl8k_get_stats(struct ieee80211_hw *hw,
  2967. struct ieee80211_low_level_stats *stats)
  2968. {
  2969. return mwl8k_cmd_get_stat(hw, stats);
  2970. }
  2971. static int
  2972. mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2973. enum ieee80211_ampdu_mlme_action action,
  2974. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2975. {
  2976. switch (action) {
  2977. case IEEE80211_AMPDU_RX_START:
  2978. case IEEE80211_AMPDU_RX_STOP:
  2979. if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
  2980. return -ENOTSUPP;
  2981. return 0;
  2982. default:
  2983. return -ENOTSUPP;
  2984. }
  2985. }
  2986. static const struct ieee80211_ops mwl8k_ops = {
  2987. .tx = mwl8k_tx,
  2988. .start = mwl8k_start,
  2989. .stop = mwl8k_stop,
  2990. .add_interface = mwl8k_add_interface,
  2991. .remove_interface = mwl8k_remove_interface,
  2992. .config = mwl8k_config,
  2993. .bss_info_changed = mwl8k_bss_info_changed,
  2994. .prepare_multicast = mwl8k_prepare_multicast,
  2995. .configure_filter = mwl8k_configure_filter,
  2996. .set_rts_threshold = mwl8k_set_rts_threshold,
  2997. .sta_notify = mwl8k_sta_notify,
  2998. .conf_tx = mwl8k_conf_tx,
  2999. .get_tx_stats = mwl8k_get_tx_stats,
  3000. .get_stats = mwl8k_get_stats,
  3001. .ampdu_action = mwl8k_ampdu_action,
  3002. };
  3003. static void mwl8k_finalize_join_worker(struct work_struct *work)
  3004. {
  3005. struct mwl8k_priv *priv =
  3006. container_of(work, struct mwl8k_priv, finalize_join_worker);
  3007. struct sk_buff *skb = priv->beacon_skb;
  3008. mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
  3009. priv->vif->bss_conf.dtim_period);
  3010. dev_kfree_skb(skb);
  3011. priv->beacon_skb = NULL;
  3012. }
  3013. enum {
  3014. MWL8363 = 0,
  3015. MWL8687,
  3016. MWL8366,
  3017. };
  3018. static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
  3019. [MWL8363] = {
  3020. .part_name = "88w8363",
  3021. .helper_image = "mwl8k/helper_8363.fw",
  3022. .fw_image = "mwl8k/fmimage_8363.fw",
  3023. },
  3024. [MWL8687] = {
  3025. .part_name = "88w8687",
  3026. .helper_image = "mwl8k/helper_8687.fw",
  3027. .fw_image = "mwl8k/fmimage_8687.fw",
  3028. },
  3029. [MWL8366] = {
  3030. .part_name = "88w8366",
  3031. .helper_image = "mwl8k/helper_8366.fw",
  3032. .fw_image = "mwl8k/fmimage_8366.fw",
  3033. .ap_rxd_ops = &rxd_8366_ap_ops,
  3034. },
  3035. };
  3036. MODULE_FIRMWARE("mwl8k/helper_8363.fw");
  3037. MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
  3038. MODULE_FIRMWARE("mwl8k/helper_8687.fw");
  3039. MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
  3040. MODULE_FIRMWARE("mwl8k/helper_8366.fw");
  3041. MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
  3042. static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
  3043. { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
  3044. { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
  3045. { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
  3046. { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
  3047. { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
  3048. { },
  3049. };
  3050. MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
  3051. static int __devinit mwl8k_probe(struct pci_dev *pdev,
  3052. const struct pci_device_id *id)
  3053. {
  3054. static int printed_version = 0;
  3055. struct ieee80211_hw *hw;
  3056. struct mwl8k_priv *priv;
  3057. int rc;
  3058. int i;
  3059. if (!printed_version) {
  3060. printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
  3061. printed_version = 1;
  3062. }
  3063. rc = pci_enable_device(pdev);
  3064. if (rc) {
  3065. printk(KERN_ERR "%s: Cannot enable new PCI device\n",
  3066. MWL8K_NAME);
  3067. return rc;
  3068. }
  3069. rc = pci_request_regions(pdev, MWL8K_NAME);
  3070. if (rc) {
  3071. printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
  3072. MWL8K_NAME);
  3073. goto err_disable_device;
  3074. }
  3075. pci_set_master(pdev);
  3076. hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
  3077. if (hw == NULL) {
  3078. printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
  3079. rc = -ENOMEM;
  3080. goto err_free_reg;
  3081. }
  3082. SET_IEEE80211_DEV(hw, &pdev->dev);
  3083. pci_set_drvdata(pdev, hw);
  3084. priv = hw->priv;
  3085. priv->hw = hw;
  3086. priv->pdev = pdev;
  3087. priv->device_info = &mwl8k_info_tbl[id->driver_data];
  3088. priv->sram = pci_iomap(pdev, 0, 0x10000);
  3089. if (priv->sram == NULL) {
  3090. printk(KERN_ERR "%s: Cannot map device SRAM\n",
  3091. wiphy_name(hw->wiphy));
  3092. goto err_iounmap;
  3093. }
  3094. /*
  3095. * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
  3096. * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
  3097. */
  3098. priv->regs = pci_iomap(pdev, 1, 0x10000);
  3099. if (priv->regs == NULL) {
  3100. priv->regs = pci_iomap(pdev, 2, 0x10000);
  3101. if (priv->regs == NULL) {
  3102. printk(KERN_ERR "%s: Cannot map device registers\n",
  3103. wiphy_name(hw->wiphy));
  3104. goto err_iounmap;
  3105. }
  3106. }
  3107. /* Reset firmware and hardware */
  3108. mwl8k_hw_reset(priv);
  3109. /* Ask userland hotplug daemon for the device firmware */
  3110. rc = mwl8k_request_firmware(priv);
  3111. if (rc) {
  3112. printk(KERN_ERR "%s: Firmware files not found\n",
  3113. wiphy_name(hw->wiphy));
  3114. goto err_stop_firmware;
  3115. }
  3116. /* Load firmware into hardware */
  3117. rc = mwl8k_load_firmware(hw);
  3118. if (rc) {
  3119. printk(KERN_ERR "%s: Cannot start firmware\n",
  3120. wiphy_name(hw->wiphy));
  3121. goto err_stop_firmware;
  3122. }
  3123. /* Reclaim memory once firmware is successfully loaded */
  3124. mwl8k_release_firmware(priv);
  3125. if (priv->ap_fw) {
  3126. priv->rxd_ops = priv->device_info->ap_rxd_ops;
  3127. if (priv->rxd_ops == NULL) {
  3128. printk(KERN_ERR "%s: Driver does not have AP "
  3129. "firmware image support for this hardware\n",
  3130. wiphy_name(hw->wiphy));
  3131. goto err_stop_firmware;
  3132. }
  3133. } else {
  3134. priv->rxd_ops = &rxd_sta_ops;
  3135. }
  3136. priv->sniffer_enabled = false;
  3137. priv->wmm_enabled = false;
  3138. priv->pending_tx_pkts = 0;
  3139. memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
  3140. priv->band.band = IEEE80211_BAND_2GHZ;
  3141. priv->band.channels = priv->channels;
  3142. priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
  3143. priv->band.bitrates = priv->rates;
  3144. priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
  3145. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
  3146. BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
  3147. memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
  3148. /*
  3149. * Extra headroom is the size of the required DMA header
  3150. * minus the size of the smallest 802.11 frame (CTS frame).
  3151. */
  3152. hw->extra_tx_headroom =
  3153. sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
  3154. hw->channel_change_time = 10;
  3155. hw->queues = MWL8K_TX_QUEUES;
  3156. /* Set rssi and noise values to dBm */
  3157. hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
  3158. hw->vif_data_size = sizeof(struct mwl8k_vif);
  3159. hw->sta_data_size = sizeof(struct mwl8k_sta);
  3160. priv->vif = NULL;
  3161. /* Set default radio state and preamble */
  3162. priv->radio_on = 0;
  3163. priv->radio_short_preamble = 0;
  3164. /* Station database handling */
  3165. INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
  3166. spin_lock_init(&priv->sta_notify_list_lock);
  3167. INIT_LIST_HEAD(&priv->sta_notify_list);
  3168. /* Finalize join worker */
  3169. INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
  3170. /* TX reclaim and RX tasklets. */
  3171. tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
  3172. tasklet_disable(&priv->poll_tx_task);
  3173. tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
  3174. tasklet_disable(&priv->poll_rx_task);
  3175. /* Power management cookie */
  3176. priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
  3177. if (priv->cookie == NULL)
  3178. goto err_stop_firmware;
  3179. rc = mwl8k_rxq_init(hw, 0);
  3180. if (rc)
  3181. goto err_free_cookie;
  3182. rxq_refill(hw, 0, INT_MAX);
  3183. mutex_init(&priv->fw_mutex);
  3184. priv->fw_mutex_owner = NULL;
  3185. priv->fw_mutex_depth = 0;
  3186. priv->hostcmd_wait = NULL;
  3187. spin_lock_init(&priv->tx_lock);
  3188. priv->tx_wait = NULL;
  3189. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  3190. rc = mwl8k_txq_init(hw, i);
  3191. if (rc)
  3192. goto err_free_queues;
  3193. }
  3194. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  3195. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3196. iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
  3197. priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
  3198. iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
  3199. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  3200. IRQF_SHARED, MWL8K_NAME, hw);
  3201. if (rc) {
  3202. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  3203. wiphy_name(hw->wiphy));
  3204. goto err_free_queues;
  3205. }
  3206. /*
  3207. * Temporarily enable interrupts. Initial firmware host
  3208. * commands use interrupts and avoid polling. Disable
  3209. * interrupts when done.
  3210. */
  3211. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3212. /* Get config data, mac addrs etc */
  3213. if (priv->ap_fw) {
  3214. rc = mwl8k_cmd_get_hw_spec_ap(hw);
  3215. if (!rc)
  3216. rc = mwl8k_cmd_set_hw_spec(hw);
  3217. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
  3218. } else {
  3219. rc = mwl8k_cmd_get_hw_spec_sta(hw);
  3220. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
  3221. }
  3222. if (rc) {
  3223. printk(KERN_ERR "%s: Cannot initialise firmware\n",
  3224. wiphy_name(hw->wiphy));
  3225. goto err_free_irq;
  3226. }
  3227. /* Turn radio off */
  3228. rc = mwl8k_cmd_radio_disable(hw);
  3229. if (rc) {
  3230. printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
  3231. goto err_free_irq;
  3232. }
  3233. /* Clear MAC address */
  3234. rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  3235. if (rc) {
  3236. printk(KERN_ERR "%s: Cannot clear MAC address\n",
  3237. wiphy_name(hw->wiphy));
  3238. goto err_free_irq;
  3239. }
  3240. /* Disable interrupts */
  3241. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3242. free_irq(priv->pdev->irq, hw);
  3243. rc = ieee80211_register_hw(hw);
  3244. if (rc) {
  3245. printk(KERN_ERR "%s: Cannot register device\n",
  3246. wiphy_name(hw->wiphy));
  3247. goto err_free_queues;
  3248. }
  3249. printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
  3250. wiphy_name(hw->wiphy), priv->device_info->part_name,
  3251. priv->hw_rev, hw->wiphy->perm_addr,
  3252. priv->ap_fw ? "AP" : "STA",
  3253. (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
  3254. (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
  3255. return 0;
  3256. err_free_irq:
  3257. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3258. free_irq(priv->pdev->irq, hw);
  3259. err_free_queues:
  3260. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3261. mwl8k_txq_deinit(hw, i);
  3262. mwl8k_rxq_deinit(hw, 0);
  3263. err_free_cookie:
  3264. if (priv->cookie != NULL)
  3265. pci_free_consistent(priv->pdev, 4,
  3266. priv->cookie, priv->cookie_dma);
  3267. err_stop_firmware:
  3268. mwl8k_hw_reset(priv);
  3269. mwl8k_release_firmware(priv);
  3270. err_iounmap:
  3271. if (priv->regs != NULL)
  3272. pci_iounmap(pdev, priv->regs);
  3273. if (priv->sram != NULL)
  3274. pci_iounmap(pdev, priv->sram);
  3275. pci_set_drvdata(pdev, NULL);
  3276. ieee80211_free_hw(hw);
  3277. err_free_reg:
  3278. pci_release_regions(pdev);
  3279. err_disable_device:
  3280. pci_disable_device(pdev);
  3281. return rc;
  3282. }
  3283. static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
  3284. {
  3285. printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
  3286. }
  3287. static void __devexit mwl8k_remove(struct pci_dev *pdev)
  3288. {
  3289. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  3290. struct mwl8k_priv *priv;
  3291. int i;
  3292. if (hw == NULL)
  3293. return;
  3294. priv = hw->priv;
  3295. ieee80211_stop_queues(hw);
  3296. ieee80211_unregister_hw(hw);
  3297. /* Remove TX reclaim and RX tasklets. */
  3298. tasklet_kill(&priv->poll_tx_task);
  3299. tasklet_kill(&priv->poll_rx_task);
  3300. /* Stop hardware */
  3301. mwl8k_hw_reset(priv);
  3302. /* Return all skbs to mac80211 */
  3303. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3304. mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
  3305. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3306. mwl8k_txq_deinit(hw, i);
  3307. mwl8k_rxq_deinit(hw, 0);
  3308. pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
  3309. pci_iounmap(pdev, priv->regs);
  3310. pci_iounmap(pdev, priv->sram);
  3311. pci_set_drvdata(pdev, NULL);
  3312. ieee80211_free_hw(hw);
  3313. pci_release_regions(pdev);
  3314. pci_disable_device(pdev);
  3315. }
  3316. static struct pci_driver mwl8k_driver = {
  3317. .name = MWL8K_NAME,
  3318. .id_table = mwl8k_pci_id_table,
  3319. .probe = mwl8k_probe,
  3320. .remove = __devexit_p(mwl8k_remove),
  3321. .shutdown = __devexit_p(mwl8k_shutdown),
  3322. };
  3323. static int __init mwl8k_init(void)
  3324. {
  3325. return pci_register_driver(&mwl8k_driver);
  3326. }
  3327. static void __exit mwl8k_exit(void)
  3328. {
  3329. pci_unregister_driver(&mwl8k_driver);
  3330. }
  3331. module_init(mwl8k_init);
  3332. module_exit(mwl8k_exit);
  3333. MODULE_DESCRIPTION(MWL8K_DESC);
  3334. MODULE_VERSION(MWL8K_VERSION);
  3335. MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
  3336. MODULE_LICENSE("GPL");