cs4231.c 56 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130
  1. /*
  2. * Driver for CS4231 sound chips found on Sparcs.
  3. * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
  4. *
  5. * Based entirely upon drivers/sbus/audio/cs4231.c which is:
  6. * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
  7. * and also sound/isa/cs423x/cs4231_lib.c which is:
  8. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/slab.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/irq.h>
  18. #include <linux/io.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/info.h>
  24. #include <sound/control.h>
  25. #include <sound/timer.h>
  26. #include <sound/initval.h>
  27. #include <sound/pcm_params.h>
  28. #ifdef CONFIG_SBUS
  29. #define SBUS_SUPPORT
  30. #endif
  31. #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
  32. #define EBUS_SUPPORT
  33. #include <linux/pci.h>
  34. #include <asm/ebus_dma.h>
  35. #endif
  36. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  37. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  38. /* Enable this card */
  39. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  40. module_param_array(index, int, NULL, 0444);
  41. MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
  42. module_param_array(id, charp, NULL, 0444);
  43. MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
  44. module_param_array(enable, bool, NULL, 0444);
  45. MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
  46. MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
  47. MODULE_DESCRIPTION("Sun CS4231");
  48. MODULE_LICENSE("GPL");
  49. MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
  50. #ifdef SBUS_SUPPORT
  51. struct sbus_dma_info {
  52. spinlock_t lock; /* DMA access lock */
  53. int dir;
  54. void __iomem *regs;
  55. };
  56. #endif
  57. struct snd_cs4231;
  58. struct cs4231_dma_control {
  59. void (*prepare)(struct cs4231_dma_control *dma_cont,
  60. int dir);
  61. void (*enable)(struct cs4231_dma_control *dma_cont, int on);
  62. int (*request)(struct cs4231_dma_control *dma_cont,
  63. dma_addr_t bus_addr, size_t len);
  64. unsigned int (*address)(struct cs4231_dma_control *dma_cont);
  65. #ifdef EBUS_SUPPORT
  66. struct ebus_dma_info ebus_info;
  67. #endif
  68. #ifdef SBUS_SUPPORT
  69. struct sbus_dma_info sbus_info;
  70. #endif
  71. };
  72. struct snd_cs4231 {
  73. spinlock_t lock; /* registers access lock */
  74. void __iomem *port;
  75. struct cs4231_dma_control p_dma;
  76. struct cs4231_dma_control c_dma;
  77. u32 flags;
  78. #define CS4231_FLAG_EBUS 0x00000001
  79. #define CS4231_FLAG_PLAYBACK 0x00000002
  80. #define CS4231_FLAG_CAPTURE 0x00000004
  81. struct snd_card *card;
  82. struct snd_pcm *pcm;
  83. struct snd_pcm_substream *playback_substream;
  84. unsigned int p_periods_sent;
  85. struct snd_pcm_substream *capture_substream;
  86. unsigned int c_periods_sent;
  87. struct snd_timer *timer;
  88. unsigned short mode;
  89. #define CS4231_MODE_NONE 0x0000
  90. #define CS4231_MODE_PLAY 0x0001
  91. #define CS4231_MODE_RECORD 0x0002
  92. #define CS4231_MODE_TIMER 0x0004
  93. #define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \
  94. CS4231_MODE_TIMER)
  95. unsigned char image[32]; /* registers image */
  96. int mce_bit;
  97. int calibrate_mute;
  98. struct mutex mce_mutex; /* mutex for mce register */
  99. struct mutex open_mutex; /* mutex for ALSA open/close */
  100. struct of_device *op;
  101. unsigned int irq[2];
  102. unsigned int regs_size;
  103. struct snd_cs4231 *next;
  104. };
  105. /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
  106. * now.... -DaveM
  107. */
  108. /* IO ports */
  109. #include <sound/cs4231-regs.h>
  110. /* XXX offsets are different than PC ISA chips... */
  111. #define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
  112. /* SBUS DMA register defines. */
  113. #define APCCSR 0x10UL /* APC DMA CSR */
  114. #define APCCVA 0x20UL /* APC Capture DMA Address */
  115. #define APCCC 0x24UL /* APC Capture Count */
  116. #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
  117. #define APCCNC 0x2cUL /* APC Capture Next Count */
  118. #define APCPVA 0x30UL /* APC Play DMA Address */
  119. #define APCPC 0x34UL /* APC Play Count */
  120. #define APCPNVA 0x38UL /* APC Play DMA Next Address */
  121. #define APCPNC 0x3cUL /* APC Play Next Count */
  122. /* Defines for SBUS DMA-routines */
  123. #define APCVA 0x0UL /* APC DMA Address */
  124. #define APCC 0x4UL /* APC Count */
  125. #define APCNVA 0x8UL /* APC DMA Next Address */
  126. #define APCNC 0xcUL /* APC Next Count */
  127. #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
  128. #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
  129. /* APCCSR bits */
  130. #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
  131. #define APC_PLAY_INT 0x400000 /* Playback interrupt */
  132. #define APC_CAPT_INT 0x200000 /* Capture interrupt */
  133. #define APC_GENL_INT 0x100000 /* General interrupt */
  134. #define APC_XINT_ENA 0x80000 /* General ext int. enable */
  135. #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
  136. #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
  137. #define APC_XINT_GENL 0x10000 /* Error ext intr */
  138. #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
  139. #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
  140. #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
  141. #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
  142. #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
  143. #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
  144. #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
  145. #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
  146. #define APC_PPAUSE 0x80 /* Pause the play DMA */
  147. #define APC_CPAUSE 0x40 /* Pause the capture DMA */
  148. #define APC_CDC_RESET 0x20 /* CODEC RESET */
  149. #define APC_PDMA_READY 0x08 /* Play DMA Go */
  150. #define APC_CDMA_READY 0x04 /* Capture DMA Go */
  151. #define APC_CHIP_RESET 0x01 /* Reset the chip */
  152. /* EBUS DMA register offsets */
  153. #define EBDMA_CSR 0x00UL /* Control/Status */
  154. #define EBDMA_ADDR 0x04UL /* DMA Address */
  155. #define EBDMA_COUNT 0x08UL /* DMA Count */
  156. /*
  157. * Some variables
  158. */
  159. static unsigned char freq_bits[14] = {
  160. /* 5510 */ 0x00 | CS4231_XTAL2,
  161. /* 6620 */ 0x0E | CS4231_XTAL2,
  162. /* 8000 */ 0x00 | CS4231_XTAL1,
  163. /* 9600 */ 0x0E | CS4231_XTAL1,
  164. /* 11025 */ 0x02 | CS4231_XTAL2,
  165. /* 16000 */ 0x02 | CS4231_XTAL1,
  166. /* 18900 */ 0x04 | CS4231_XTAL2,
  167. /* 22050 */ 0x06 | CS4231_XTAL2,
  168. /* 27042 */ 0x04 | CS4231_XTAL1,
  169. /* 32000 */ 0x06 | CS4231_XTAL1,
  170. /* 33075 */ 0x0C | CS4231_XTAL2,
  171. /* 37800 */ 0x08 | CS4231_XTAL2,
  172. /* 44100 */ 0x0A | CS4231_XTAL2,
  173. /* 48000 */ 0x0C | CS4231_XTAL1
  174. };
  175. static unsigned int rates[14] = {
  176. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  177. 27042, 32000, 33075, 37800, 44100, 48000
  178. };
  179. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  180. .count = ARRAY_SIZE(rates),
  181. .list = rates,
  182. };
  183. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  184. {
  185. return snd_pcm_hw_constraint_list(runtime, 0,
  186. SNDRV_PCM_HW_PARAM_RATE,
  187. &hw_constraints_rates);
  188. }
  189. static unsigned char snd_cs4231_original_image[32] =
  190. {
  191. 0x00, /* 00/00 - lic */
  192. 0x00, /* 01/01 - ric */
  193. 0x9f, /* 02/02 - la1ic */
  194. 0x9f, /* 03/03 - ra1ic */
  195. 0x9f, /* 04/04 - la2ic */
  196. 0x9f, /* 05/05 - ra2ic */
  197. 0xbf, /* 06/06 - loc */
  198. 0xbf, /* 07/07 - roc */
  199. 0x20, /* 08/08 - pdfr */
  200. CS4231_AUTOCALIB, /* 09/09 - ic */
  201. 0x00, /* 0a/10 - pc */
  202. 0x00, /* 0b/11 - ti */
  203. CS4231_MODE2, /* 0c/12 - mi */
  204. 0x00, /* 0d/13 - lbc */
  205. 0x00, /* 0e/14 - pbru */
  206. 0x00, /* 0f/15 - pbrl */
  207. 0x80, /* 10/16 - afei */
  208. 0x01, /* 11/17 - afeii */
  209. 0x9f, /* 12/18 - llic */
  210. 0x9f, /* 13/19 - rlic */
  211. 0x00, /* 14/20 - tlb */
  212. 0x00, /* 15/21 - thb */
  213. 0x00, /* 16/22 - la3mic/reserved */
  214. 0x00, /* 17/23 - ra3mic/reserved */
  215. 0x00, /* 18/24 - afs */
  216. 0x00, /* 19/25 - lamoc/version */
  217. 0x00, /* 1a/26 - mioc */
  218. 0x00, /* 1b/27 - ramoc/reserved */
  219. 0x20, /* 1c/28 - cdfr */
  220. 0x00, /* 1d/29 - res4 */
  221. 0x00, /* 1e/30 - cbru */
  222. 0x00, /* 1f/31 - cbrl */
  223. };
  224. static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
  225. {
  226. if (cp->flags & CS4231_FLAG_EBUS)
  227. return readb(reg_addr);
  228. else
  229. return sbus_readb(reg_addr);
  230. }
  231. static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val,
  232. void __iomem *reg_addr)
  233. {
  234. if (cp->flags & CS4231_FLAG_EBUS)
  235. return writeb(val, reg_addr);
  236. else
  237. return sbus_writeb(val, reg_addr);
  238. }
  239. /*
  240. * Basic I/O functions
  241. */
  242. static void snd_cs4231_ready(struct snd_cs4231 *chip)
  243. {
  244. int timeout;
  245. for (timeout = 250; timeout > 0; timeout--) {
  246. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  247. if ((val & CS4231_INIT) == 0)
  248. break;
  249. udelay(100);
  250. }
  251. }
  252. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
  253. unsigned char value)
  254. {
  255. snd_cs4231_ready(chip);
  256. #ifdef CONFIG_SND_DEBUG
  257. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  258. snd_printdd("out: auto calibration time out - reg = 0x%x, "
  259. "value = 0x%x\n",
  260. reg, value);
  261. #endif
  262. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  263. wmb();
  264. __cs4231_writeb(chip, value, CS4231U(chip, REG));
  265. mb();
  266. }
  267. static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  268. unsigned char mask, unsigned char value)
  269. {
  270. unsigned char tmp = (chip->image[reg] & mask) | value;
  271. chip->image[reg] = tmp;
  272. if (!chip->calibrate_mute)
  273. snd_cs4231_dout(chip, reg, tmp);
  274. }
  275. static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
  276. unsigned char value)
  277. {
  278. snd_cs4231_dout(chip, reg, value);
  279. chip->image[reg] = value;
  280. mb();
  281. }
  282. static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  283. {
  284. snd_cs4231_ready(chip);
  285. #ifdef CONFIG_SND_DEBUG
  286. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  287. snd_printdd("in: auto calibration time out - reg = 0x%x\n",
  288. reg);
  289. #endif
  290. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  291. mb();
  292. return __cs4231_readb(chip, CS4231U(chip, REG));
  293. }
  294. /*
  295. * CS4231 detection / MCE routines
  296. */
  297. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  298. {
  299. int timeout;
  300. /* looks like this sequence is proper for CS4231A chip (GUS MAX) */
  301. for (timeout = 5; timeout > 0; timeout--)
  302. __cs4231_readb(chip, CS4231U(chip, REGSEL));
  303. /* end of cleanup sequence */
  304. for (timeout = 500; timeout > 0; timeout--) {
  305. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  306. if ((val & CS4231_INIT) == 0)
  307. break;
  308. msleep(1);
  309. }
  310. }
  311. static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  312. {
  313. unsigned long flags;
  314. int timeout;
  315. spin_lock_irqsave(&chip->lock, flags);
  316. snd_cs4231_ready(chip);
  317. #ifdef CONFIG_SND_DEBUG
  318. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  319. snd_printdd("mce_up - auto calibration time out (0)\n");
  320. #endif
  321. chip->mce_bit |= CS4231_MCE;
  322. timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  323. if (timeout == 0x80)
  324. snd_printdd("mce_up [%p]: serious init problem - "
  325. "codec still busy\n",
  326. chip->port);
  327. if (!(timeout & CS4231_MCE))
  328. __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
  329. CS4231U(chip, REGSEL));
  330. spin_unlock_irqrestore(&chip->lock, flags);
  331. }
  332. static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  333. {
  334. unsigned long flags, timeout;
  335. int reg;
  336. snd_cs4231_busy_wait(chip);
  337. spin_lock_irqsave(&chip->lock, flags);
  338. #ifdef CONFIG_SND_DEBUG
  339. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  340. snd_printdd("mce_down [%p] - auto calibration time out (0)\n",
  341. CS4231U(chip, REGSEL));
  342. #endif
  343. chip->mce_bit &= ~CS4231_MCE;
  344. reg = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  345. __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f),
  346. CS4231U(chip, REGSEL));
  347. if (reg == 0x80)
  348. snd_printdd("mce_down [%p]: serious init problem "
  349. "- codec still busy\n", chip->port);
  350. if ((reg & CS4231_MCE) == 0) {
  351. spin_unlock_irqrestore(&chip->lock, flags);
  352. return;
  353. }
  354. /*
  355. * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
  356. */
  357. timeout = jiffies + msecs_to_jiffies(250);
  358. do {
  359. spin_unlock_irqrestore(&chip->lock, flags);
  360. msleep(1);
  361. spin_lock_irqsave(&chip->lock, flags);
  362. reg = snd_cs4231_in(chip, CS4231_TEST_INIT);
  363. reg &= CS4231_CALIB_IN_PROGRESS;
  364. } while (reg && time_before(jiffies, timeout));
  365. spin_unlock_irqrestore(&chip->lock, flags);
  366. if (reg)
  367. snd_printk(KERN_ERR
  368. "mce_down - auto calibration time out (2)\n");
  369. }
  370. static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
  371. struct snd_pcm_substream *substream,
  372. unsigned int *periods_sent)
  373. {
  374. struct snd_pcm_runtime *runtime = substream->runtime;
  375. while (1) {
  376. unsigned int period_size = snd_pcm_lib_period_bytes(substream);
  377. unsigned int offset = period_size * (*periods_sent);
  378. BUG_ON(period_size >= (1 << 24));
  379. if (dma_cont->request(dma_cont,
  380. runtime->dma_addr + offset, period_size))
  381. return;
  382. (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
  383. }
  384. }
  385. static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
  386. unsigned int what, int on)
  387. {
  388. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  389. struct cs4231_dma_control *dma_cont;
  390. if (what & CS4231_PLAYBACK_ENABLE) {
  391. dma_cont = &chip->p_dma;
  392. if (on) {
  393. dma_cont->prepare(dma_cont, 0);
  394. dma_cont->enable(dma_cont, 1);
  395. snd_cs4231_advance_dma(dma_cont,
  396. chip->playback_substream,
  397. &chip->p_periods_sent);
  398. } else {
  399. dma_cont->enable(dma_cont, 0);
  400. }
  401. }
  402. if (what & CS4231_RECORD_ENABLE) {
  403. dma_cont = &chip->c_dma;
  404. if (on) {
  405. dma_cont->prepare(dma_cont, 1);
  406. dma_cont->enable(dma_cont, 1);
  407. snd_cs4231_advance_dma(dma_cont,
  408. chip->capture_substream,
  409. &chip->c_periods_sent);
  410. } else {
  411. dma_cont->enable(dma_cont, 0);
  412. }
  413. }
  414. }
  415. static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
  416. {
  417. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  418. int result = 0;
  419. switch (cmd) {
  420. case SNDRV_PCM_TRIGGER_START:
  421. case SNDRV_PCM_TRIGGER_STOP:
  422. {
  423. unsigned int what = 0;
  424. struct snd_pcm_substream *s;
  425. unsigned long flags;
  426. snd_pcm_group_for_each_entry(s, substream) {
  427. if (s == chip->playback_substream) {
  428. what |= CS4231_PLAYBACK_ENABLE;
  429. snd_pcm_trigger_done(s, substream);
  430. } else if (s == chip->capture_substream) {
  431. what |= CS4231_RECORD_ENABLE;
  432. snd_pcm_trigger_done(s, substream);
  433. }
  434. }
  435. spin_lock_irqsave(&chip->lock, flags);
  436. if (cmd == SNDRV_PCM_TRIGGER_START) {
  437. cs4231_dma_trigger(substream, what, 1);
  438. chip->image[CS4231_IFACE_CTRL] |= what;
  439. } else {
  440. cs4231_dma_trigger(substream, what, 0);
  441. chip->image[CS4231_IFACE_CTRL] &= ~what;
  442. }
  443. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  444. chip->image[CS4231_IFACE_CTRL]);
  445. spin_unlock_irqrestore(&chip->lock, flags);
  446. break;
  447. }
  448. default:
  449. result = -EINVAL;
  450. break;
  451. }
  452. return result;
  453. }
  454. /*
  455. * CODEC I/O
  456. */
  457. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  458. {
  459. int i;
  460. for (i = 0; i < 14; i++)
  461. if (rate == rates[i])
  462. return freq_bits[i];
  463. return freq_bits[13];
  464. }
  465. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format,
  466. int channels)
  467. {
  468. unsigned char rformat;
  469. rformat = CS4231_LINEAR_8;
  470. switch (format) {
  471. case SNDRV_PCM_FORMAT_MU_LAW:
  472. rformat = CS4231_ULAW_8;
  473. break;
  474. case SNDRV_PCM_FORMAT_A_LAW:
  475. rformat = CS4231_ALAW_8;
  476. break;
  477. case SNDRV_PCM_FORMAT_S16_LE:
  478. rformat = CS4231_LINEAR_16;
  479. break;
  480. case SNDRV_PCM_FORMAT_S16_BE:
  481. rformat = CS4231_LINEAR_16_BIG;
  482. break;
  483. case SNDRV_PCM_FORMAT_IMA_ADPCM:
  484. rformat = CS4231_ADPCM_16;
  485. break;
  486. }
  487. if (channels > 1)
  488. rformat |= CS4231_STEREO;
  489. return rformat;
  490. }
  491. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  492. {
  493. unsigned long flags;
  494. mute = mute ? 1 : 0;
  495. spin_lock_irqsave(&chip->lock, flags);
  496. if (chip->calibrate_mute == mute) {
  497. spin_unlock_irqrestore(&chip->lock, flags);
  498. return;
  499. }
  500. if (!mute) {
  501. snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
  502. chip->image[CS4231_LEFT_INPUT]);
  503. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
  504. chip->image[CS4231_RIGHT_INPUT]);
  505. snd_cs4231_dout(chip, CS4231_LOOPBACK,
  506. chip->image[CS4231_LOOPBACK]);
  507. }
  508. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
  509. mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  510. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
  511. mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  512. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
  513. mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  514. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
  515. mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  516. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
  517. mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  518. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
  519. mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  520. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
  521. mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  522. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
  523. mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  524. snd_cs4231_dout(chip, CS4231_MONO_CTRL,
  525. mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  526. chip->calibrate_mute = mute;
  527. spin_unlock_irqrestore(&chip->lock, flags);
  528. }
  529. static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
  530. struct snd_pcm_hw_params *params,
  531. unsigned char pdfr)
  532. {
  533. unsigned long flags;
  534. mutex_lock(&chip->mce_mutex);
  535. snd_cs4231_calibrate_mute(chip, 1);
  536. snd_cs4231_mce_up(chip);
  537. spin_lock_irqsave(&chip->lock, flags);
  538. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  539. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  540. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  541. pdfr);
  542. spin_unlock_irqrestore(&chip->lock, flags);
  543. snd_cs4231_mce_down(chip);
  544. snd_cs4231_calibrate_mute(chip, 0);
  545. mutex_unlock(&chip->mce_mutex);
  546. }
  547. static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
  548. struct snd_pcm_hw_params *params,
  549. unsigned char cdfr)
  550. {
  551. unsigned long flags;
  552. mutex_lock(&chip->mce_mutex);
  553. snd_cs4231_calibrate_mute(chip, 1);
  554. snd_cs4231_mce_up(chip);
  555. spin_lock_irqsave(&chip->lock, flags);
  556. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  557. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  558. ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  559. (cdfr & 0x0f));
  560. spin_unlock_irqrestore(&chip->lock, flags);
  561. snd_cs4231_mce_down(chip);
  562. snd_cs4231_mce_up(chip);
  563. spin_lock_irqsave(&chip->lock, flags);
  564. }
  565. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  566. spin_unlock_irqrestore(&chip->lock, flags);
  567. snd_cs4231_mce_down(chip);
  568. snd_cs4231_calibrate_mute(chip, 0);
  569. mutex_unlock(&chip->mce_mutex);
  570. }
  571. /*
  572. * Timer interface
  573. */
  574. static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
  575. {
  576. struct snd_cs4231 *chip = snd_timer_chip(timer);
  577. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  578. }
  579. static int snd_cs4231_timer_start(struct snd_timer *timer)
  580. {
  581. unsigned long flags;
  582. unsigned int ticks;
  583. struct snd_cs4231 *chip = snd_timer_chip(timer);
  584. spin_lock_irqsave(&chip->lock, flags);
  585. ticks = timer->sticks;
  586. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  587. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  588. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  589. snd_cs4231_out(chip, CS4231_TIMER_HIGH,
  590. chip->image[CS4231_TIMER_HIGH] =
  591. (unsigned char) (ticks >> 8));
  592. snd_cs4231_out(chip, CS4231_TIMER_LOW,
  593. chip->image[CS4231_TIMER_LOW] =
  594. (unsigned char) ticks);
  595. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  596. chip->image[CS4231_ALT_FEATURE_1] |
  597. CS4231_TIMER_ENABLE);
  598. }
  599. spin_unlock_irqrestore(&chip->lock, flags);
  600. return 0;
  601. }
  602. static int snd_cs4231_timer_stop(struct snd_timer *timer)
  603. {
  604. unsigned long flags;
  605. struct snd_cs4231 *chip = snd_timer_chip(timer);
  606. spin_lock_irqsave(&chip->lock, flags);
  607. chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
  608. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  609. chip->image[CS4231_ALT_FEATURE_1]);
  610. spin_unlock_irqrestore(&chip->lock, flags);
  611. return 0;
  612. }
  613. static void __devinit snd_cs4231_init(struct snd_cs4231 *chip)
  614. {
  615. unsigned long flags;
  616. snd_cs4231_mce_down(chip);
  617. #ifdef SNDRV_DEBUG_MCE
  618. snd_printdd("init: (1)\n");
  619. #endif
  620. snd_cs4231_mce_up(chip);
  621. spin_lock_irqsave(&chip->lock, flags);
  622. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  623. CS4231_PLAYBACK_PIO |
  624. CS4231_RECORD_ENABLE |
  625. CS4231_RECORD_PIO |
  626. CS4231_CALIB_MODE);
  627. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  628. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  629. spin_unlock_irqrestore(&chip->lock, flags);
  630. snd_cs4231_mce_down(chip);
  631. #ifdef SNDRV_DEBUG_MCE
  632. snd_printdd("init: (2)\n");
  633. #endif
  634. snd_cs4231_mce_up(chip);
  635. spin_lock_irqsave(&chip->lock, flags);
  636. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  637. chip->image[CS4231_ALT_FEATURE_1]);
  638. spin_unlock_irqrestore(&chip->lock, flags);
  639. snd_cs4231_mce_down(chip);
  640. #ifdef SNDRV_DEBUG_MCE
  641. snd_printdd("init: (3) - afei = 0x%x\n",
  642. chip->image[CS4231_ALT_FEATURE_1]);
  643. #endif
  644. spin_lock_irqsave(&chip->lock, flags);
  645. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2,
  646. chip->image[CS4231_ALT_FEATURE_2]);
  647. spin_unlock_irqrestore(&chip->lock, flags);
  648. snd_cs4231_mce_up(chip);
  649. spin_lock_irqsave(&chip->lock, flags);
  650. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  651. chip->image[CS4231_PLAYBK_FORMAT]);
  652. spin_unlock_irqrestore(&chip->lock, flags);
  653. snd_cs4231_mce_down(chip);
  654. #ifdef SNDRV_DEBUG_MCE
  655. snd_printdd("init: (4)\n");
  656. #endif
  657. snd_cs4231_mce_up(chip);
  658. spin_lock_irqsave(&chip->lock, flags);
  659. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  660. spin_unlock_irqrestore(&chip->lock, flags);
  661. snd_cs4231_mce_down(chip);
  662. #ifdef SNDRV_DEBUG_MCE
  663. snd_printdd("init: (5)\n");
  664. #endif
  665. }
  666. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  667. {
  668. unsigned long flags;
  669. mutex_lock(&chip->open_mutex);
  670. if ((chip->mode & mode)) {
  671. mutex_unlock(&chip->open_mutex);
  672. return -EAGAIN;
  673. }
  674. if (chip->mode & CS4231_MODE_OPEN) {
  675. chip->mode |= mode;
  676. mutex_unlock(&chip->open_mutex);
  677. return 0;
  678. }
  679. /* ok. now enable and ack CODEC IRQ */
  680. spin_lock_irqsave(&chip->lock, flags);
  681. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  682. CS4231_RECORD_IRQ |
  683. CS4231_TIMER_IRQ);
  684. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  685. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  686. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  687. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  688. CS4231_RECORD_IRQ |
  689. CS4231_TIMER_IRQ);
  690. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  691. spin_unlock_irqrestore(&chip->lock, flags);
  692. chip->mode = mode;
  693. mutex_unlock(&chip->open_mutex);
  694. return 0;
  695. }
  696. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  697. {
  698. unsigned long flags;
  699. mutex_lock(&chip->open_mutex);
  700. chip->mode &= ~mode;
  701. if (chip->mode & CS4231_MODE_OPEN) {
  702. mutex_unlock(&chip->open_mutex);
  703. return;
  704. }
  705. snd_cs4231_calibrate_mute(chip, 1);
  706. /* disable IRQ */
  707. spin_lock_irqsave(&chip->lock, flags);
  708. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  709. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  710. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  711. /* now disable record & playback */
  712. if (chip->image[CS4231_IFACE_CTRL] &
  713. (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  714. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  715. spin_unlock_irqrestore(&chip->lock, flags);
  716. snd_cs4231_mce_up(chip);
  717. spin_lock_irqsave(&chip->lock, flags);
  718. chip->image[CS4231_IFACE_CTRL] &=
  719. ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  720. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  721. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  722. chip->image[CS4231_IFACE_CTRL]);
  723. spin_unlock_irqrestore(&chip->lock, flags);
  724. snd_cs4231_mce_down(chip);
  725. spin_lock_irqsave(&chip->lock, flags);
  726. }
  727. /* clear IRQ again */
  728. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  729. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  730. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  731. spin_unlock_irqrestore(&chip->lock, flags);
  732. snd_cs4231_calibrate_mute(chip, 0);
  733. chip->mode = 0;
  734. mutex_unlock(&chip->open_mutex);
  735. }
  736. /*
  737. * timer open/close
  738. */
  739. static int snd_cs4231_timer_open(struct snd_timer *timer)
  740. {
  741. struct snd_cs4231 *chip = snd_timer_chip(timer);
  742. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  743. return 0;
  744. }
  745. static int snd_cs4231_timer_close(struct snd_timer *timer)
  746. {
  747. struct snd_cs4231 *chip = snd_timer_chip(timer);
  748. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  749. return 0;
  750. }
  751. static struct snd_timer_hardware snd_cs4231_timer_table = {
  752. .flags = SNDRV_TIMER_HW_AUTO,
  753. .resolution = 9945,
  754. .ticks = 65535,
  755. .open = snd_cs4231_timer_open,
  756. .close = snd_cs4231_timer_close,
  757. .c_resolution = snd_cs4231_timer_resolution,
  758. .start = snd_cs4231_timer_start,
  759. .stop = snd_cs4231_timer_stop,
  760. };
  761. /*
  762. * ok.. exported functions..
  763. */
  764. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  765. struct snd_pcm_hw_params *hw_params)
  766. {
  767. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  768. unsigned char new_pdfr;
  769. int err;
  770. err = snd_pcm_lib_malloc_pages(substream,
  771. params_buffer_bytes(hw_params));
  772. if (err < 0)
  773. return err;
  774. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  775. params_channels(hw_params)) |
  776. snd_cs4231_get_rate(params_rate(hw_params));
  777. snd_cs4231_playback_format(chip, hw_params, new_pdfr);
  778. return 0;
  779. }
  780. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  781. {
  782. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  783. struct snd_pcm_runtime *runtime = substream->runtime;
  784. unsigned long flags;
  785. spin_lock_irqsave(&chip->lock, flags);
  786. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  787. CS4231_PLAYBACK_PIO);
  788. BUG_ON(runtime->period_size > 0xffff + 1);
  789. chip->p_periods_sent = 0;
  790. spin_unlock_irqrestore(&chip->lock, flags);
  791. return 0;
  792. }
  793. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  794. struct snd_pcm_hw_params *hw_params)
  795. {
  796. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  797. unsigned char new_cdfr;
  798. int err;
  799. err = snd_pcm_lib_malloc_pages(substream,
  800. params_buffer_bytes(hw_params));
  801. if (err < 0)
  802. return err;
  803. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  804. params_channels(hw_params)) |
  805. snd_cs4231_get_rate(params_rate(hw_params));
  806. snd_cs4231_capture_format(chip, hw_params, new_cdfr);
  807. return 0;
  808. }
  809. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  810. {
  811. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  812. unsigned long flags;
  813. spin_lock_irqsave(&chip->lock, flags);
  814. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
  815. CS4231_RECORD_PIO);
  816. chip->c_periods_sent = 0;
  817. spin_unlock_irqrestore(&chip->lock, flags);
  818. return 0;
  819. }
  820. static void snd_cs4231_overrange(struct snd_cs4231 *chip)
  821. {
  822. unsigned long flags;
  823. unsigned char res;
  824. spin_lock_irqsave(&chip->lock, flags);
  825. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  826. spin_unlock_irqrestore(&chip->lock, flags);
  827. /* detect overrange only above 0dB; may be user selectable? */
  828. if (res & (0x08 | 0x02))
  829. chip->capture_substream->runtime->overrange++;
  830. }
  831. static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
  832. {
  833. if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
  834. snd_pcm_period_elapsed(chip->playback_substream);
  835. snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
  836. &chip->p_periods_sent);
  837. }
  838. }
  839. static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
  840. {
  841. if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
  842. snd_pcm_period_elapsed(chip->capture_substream);
  843. snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
  844. &chip->c_periods_sent);
  845. }
  846. }
  847. static snd_pcm_uframes_t snd_cs4231_playback_pointer(
  848. struct snd_pcm_substream *substream)
  849. {
  850. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  851. struct cs4231_dma_control *dma_cont = &chip->p_dma;
  852. size_t ptr;
  853. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  854. return 0;
  855. ptr = dma_cont->address(dma_cont);
  856. if (ptr != 0)
  857. ptr -= substream->runtime->dma_addr;
  858. return bytes_to_frames(substream->runtime, ptr);
  859. }
  860. static snd_pcm_uframes_t snd_cs4231_capture_pointer(
  861. struct snd_pcm_substream *substream)
  862. {
  863. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  864. struct cs4231_dma_control *dma_cont = &chip->c_dma;
  865. size_t ptr;
  866. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  867. return 0;
  868. ptr = dma_cont->address(dma_cont);
  869. if (ptr != 0)
  870. ptr -= substream->runtime->dma_addr;
  871. return bytes_to_frames(substream->runtime, ptr);
  872. }
  873. static int __devinit snd_cs4231_probe(struct snd_cs4231 *chip)
  874. {
  875. unsigned long flags;
  876. int i;
  877. int id = 0;
  878. int vers = 0;
  879. unsigned char *ptr;
  880. for (i = 0; i < 50; i++) {
  881. mb();
  882. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  883. msleep(2);
  884. else {
  885. spin_lock_irqsave(&chip->lock, flags);
  886. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  887. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  888. vers = snd_cs4231_in(chip, CS4231_VERSION);
  889. spin_unlock_irqrestore(&chip->lock, flags);
  890. if (id == 0x0a)
  891. break; /* this is valid value */
  892. }
  893. }
  894. snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
  895. if (id != 0x0a)
  896. return -ENODEV; /* no valid device found */
  897. spin_lock_irqsave(&chip->lock, flags);
  898. /* clear any pendings IRQ */
  899. __cs4231_readb(chip, CS4231U(chip, STATUS));
  900. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS));
  901. mb();
  902. spin_unlock_irqrestore(&chip->lock, flags);
  903. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  904. chip->image[CS4231_IFACE_CTRL] =
  905. chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
  906. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  907. chip->image[CS4231_ALT_FEATURE_2] = 0x01;
  908. if (vers & 0x20)
  909. chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
  910. ptr = (unsigned char *) &chip->image;
  911. snd_cs4231_mce_down(chip);
  912. spin_lock_irqsave(&chip->lock, flags);
  913. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  914. snd_cs4231_out(chip, i, *ptr++);
  915. spin_unlock_irqrestore(&chip->lock, flags);
  916. snd_cs4231_mce_up(chip);
  917. snd_cs4231_mce_down(chip);
  918. mdelay(2);
  919. return 0; /* all things are ok.. */
  920. }
  921. static struct snd_pcm_hardware snd_cs4231_playback = {
  922. .info = SNDRV_PCM_INFO_MMAP |
  923. SNDRV_PCM_INFO_INTERLEAVED |
  924. SNDRV_PCM_INFO_MMAP_VALID |
  925. SNDRV_PCM_INFO_SYNC_START,
  926. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  927. SNDRV_PCM_FMTBIT_A_LAW |
  928. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  929. SNDRV_PCM_FMTBIT_U8 |
  930. SNDRV_PCM_FMTBIT_S16_LE |
  931. SNDRV_PCM_FMTBIT_S16_BE,
  932. .rates = SNDRV_PCM_RATE_KNOT |
  933. SNDRV_PCM_RATE_8000_48000,
  934. .rate_min = 5510,
  935. .rate_max = 48000,
  936. .channels_min = 1,
  937. .channels_max = 2,
  938. .buffer_bytes_max = 32 * 1024,
  939. .period_bytes_min = 64,
  940. .period_bytes_max = 32 * 1024,
  941. .periods_min = 1,
  942. .periods_max = 1024,
  943. };
  944. static struct snd_pcm_hardware snd_cs4231_capture = {
  945. .info = SNDRV_PCM_INFO_MMAP |
  946. SNDRV_PCM_INFO_INTERLEAVED |
  947. SNDRV_PCM_INFO_MMAP_VALID |
  948. SNDRV_PCM_INFO_SYNC_START,
  949. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  950. SNDRV_PCM_FMTBIT_A_LAW |
  951. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  952. SNDRV_PCM_FMTBIT_U8 |
  953. SNDRV_PCM_FMTBIT_S16_LE |
  954. SNDRV_PCM_FMTBIT_S16_BE,
  955. .rates = SNDRV_PCM_RATE_KNOT |
  956. SNDRV_PCM_RATE_8000_48000,
  957. .rate_min = 5510,
  958. .rate_max = 48000,
  959. .channels_min = 1,
  960. .channels_max = 2,
  961. .buffer_bytes_max = 32 * 1024,
  962. .period_bytes_min = 64,
  963. .period_bytes_max = 32 * 1024,
  964. .periods_min = 1,
  965. .periods_max = 1024,
  966. };
  967. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  968. {
  969. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  970. struct snd_pcm_runtime *runtime = substream->runtime;
  971. int err;
  972. runtime->hw = snd_cs4231_playback;
  973. err = snd_cs4231_open(chip, CS4231_MODE_PLAY);
  974. if (err < 0) {
  975. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  976. return err;
  977. }
  978. chip->playback_substream = substream;
  979. chip->p_periods_sent = 0;
  980. snd_pcm_set_sync(substream);
  981. snd_cs4231_xrate(runtime);
  982. return 0;
  983. }
  984. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  985. {
  986. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  987. struct snd_pcm_runtime *runtime = substream->runtime;
  988. int err;
  989. runtime->hw = snd_cs4231_capture;
  990. err = snd_cs4231_open(chip, CS4231_MODE_RECORD);
  991. if (err < 0) {
  992. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  993. return err;
  994. }
  995. chip->capture_substream = substream;
  996. chip->c_periods_sent = 0;
  997. snd_pcm_set_sync(substream);
  998. snd_cs4231_xrate(runtime);
  999. return 0;
  1000. }
  1001. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  1002. {
  1003. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1004. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1005. chip->playback_substream = NULL;
  1006. return 0;
  1007. }
  1008. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1009. {
  1010. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1011. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1012. chip->capture_substream = NULL;
  1013. return 0;
  1014. }
  1015. /* XXX We can do some power-management, in particular on EBUS using
  1016. * XXX the audio AUXIO register...
  1017. */
  1018. static struct snd_pcm_ops snd_cs4231_playback_ops = {
  1019. .open = snd_cs4231_playback_open,
  1020. .close = snd_cs4231_playback_close,
  1021. .ioctl = snd_pcm_lib_ioctl,
  1022. .hw_params = snd_cs4231_playback_hw_params,
  1023. .hw_free = snd_pcm_lib_free_pages,
  1024. .prepare = snd_cs4231_playback_prepare,
  1025. .trigger = snd_cs4231_trigger,
  1026. .pointer = snd_cs4231_playback_pointer,
  1027. };
  1028. static struct snd_pcm_ops snd_cs4231_capture_ops = {
  1029. .open = snd_cs4231_capture_open,
  1030. .close = snd_cs4231_capture_close,
  1031. .ioctl = snd_pcm_lib_ioctl,
  1032. .hw_params = snd_cs4231_capture_hw_params,
  1033. .hw_free = snd_pcm_lib_free_pages,
  1034. .prepare = snd_cs4231_capture_prepare,
  1035. .trigger = snd_cs4231_trigger,
  1036. .pointer = snd_cs4231_capture_pointer,
  1037. };
  1038. static int __devinit snd_cs4231_pcm(struct snd_card *card)
  1039. {
  1040. struct snd_cs4231 *chip = card->private_data;
  1041. struct snd_pcm *pcm;
  1042. int err;
  1043. err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
  1044. if (err < 0)
  1045. return err;
  1046. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1047. &snd_cs4231_playback_ops);
  1048. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1049. &snd_cs4231_capture_ops);
  1050. /* global setup */
  1051. pcm->private_data = chip;
  1052. pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1053. strcpy(pcm->name, "CS4231");
  1054. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1055. &chip->op->dev,
  1056. 64 * 1024, 128 * 1024);
  1057. chip->pcm = pcm;
  1058. return 0;
  1059. }
  1060. static int __devinit snd_cs4231_timer(struct snd_card *card)
  1061. {
  1062. struct snd_cs4231 *chip = card->private_data;
  1063. struct snd_timer *timer;
  1064. struct snd_timer_id tid;
  1065. int err;
  1066. /* Timer initialization */
  1067. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1068. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1069. tid.card = card->number;
  1070. tid.device = 0;
  1071. tid.subdevice = 0;
  1072. err = snd_timer_new(card, "CS4231", &tid, &timer);
  1073. if (err < 0)
  1074. return err;
  1075. strcpy(timer->name, "CS4231");
  1076. timer->private_data = chip;
  1077. timer->hw = snd_cs4231_timer_table;
  1078. chip->timer = timer;
  1079. return 0;
  1080. }
  1081. /*
  1082. * MIXER part
  1083. */
  1084. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
  1085. struct snd_ctl_elem_info *uinfo)
  1086. {
  1087. static char *texts[4] = {
  1088. "Line", "CD", "Mic", "Mix"
  1089. };
  1090. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1091. uinfo->count = 2;
  1092. uinfo->value.enumerated.items = 4;
  1093. if (uinfo->value.enumerated.item > 3)
  1094. uinfo->value.enumerated.item = 3;
  1095. strcpy(uinfo->value.enumerated.name,
  1096. texts[uinfo->value.enumerated.item]);
  1097. return 0;
  1098. }
  1099. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
  1100. struct snd_ctl_elem_value *ucontrol)
  1101. {
  1102. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1103. unsigned long flags;
  1104. spin_lock_irqsave(&chip->lock, flags);
  1105. ucontrol->value.enumerated.item[0] =
  1106. (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1107. ucontrol->value.enumerated.item[1] =
  1108. (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1109. spin_unlock_irqrestore(&chip->lock, flags);
  1110. return 0;
  1111. }
  1112. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
  1113. struct snd_ctl_elem_value *ucontrol)
  1114. {
  1115. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1116. unsigned long flags;
  1117. unsigned short left, right;
  1118. int change;
  1119. if (ucontrol->value.enumerated.item[0] > 3 ||
  1120. ucontrol->value.enumerated.item[1] > 3)
  1121. return -EINVAL;
  1122. left = ucontrol->value.enumerated.item[0] << 6;
  1123. right = ucontrol->value.enumerated.item[1] << 6;
  1124. spin_lock_irqsave(&chip->lock, flags);
  1125. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1126. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1127. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1128. right != chip->image[CS4231_RIGHT_INPUT];
  1129. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1130. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1131. spin_unlock_irqrestore(&chip->lock, flags);
  1132. return change;
  1133. }
  1134. static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
  1135. struct snd_ctl_elem_info *uinfo)
  1136. {
  1137. int mask = (kcontrol->private_value >> 16) & 0xff;
  1138. uinfo->type = (mask == 1) ?
  1139. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1140. uinfo->count = 1;
  1141. uinfo->value.integer.min = 0;
  1142. uinfo->value.integer.max = mask;
  1143. return 0;
  1144. }
  1145. static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
  1146. struct snd_ctl_elem_value *ucontrol)
  1147. {
  1148. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1149. unsigned long flags;
  1150. int reg = kcontrol->private_value & 0xff;
  1151. int shift = (kcontrol->private_value >> 8) & 0xff;
  1152. int mask = (kcontrol->private_value >> 16) & 0xff;
  1153. int invert = (kcontrol->private_value >> 24) & 0xff;
  1154. spin_lock_irqsave(&chip->lock, flags);
  1155. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1156. spin_unlock_irqrestore(&chip->lock, flags);
  1157. if (invert)
  1158. ucontrol->value.integer.value[0] =
  1159. (mask - ucontrol->value.integer.value[0]);
  1160. return 0;
  1161. }
  1162. static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
  1163. struct snd_ctl_elem_value *ucontrol)
  1164. {
  1165. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1166. unsigned long flags;
  1167. int reg = kcontrol->private_value & 0xff;
  1168. int shift = (kcontrol->private_value >> 8) & 0xff;
  1169. int mask = (kcontrol->private_value >> 16) & 0xff;
  1170. int invert = (kcontrol->private_value >> 24) & 0xff;
  1171. int change;
  1172. unsigned short val;
  1173. val = (ucontrol->value.integer.value[0] & mask);
  1174. if (invert)
  1175. val = mask - val;
  1176. val <<= shift;
  1177. spin_lock_irqsave(&chip->lock, flags);
  1178. val = (chip->image[reg] & ~(mask << shift)) | val;
  1179. change = val != chip->image[reg];
  1180. snd_cs4231_out(chip, reg, val);
  1181. spin_unlock_irqrestore(&chip->lock, flags);
  1182. return change;
  1183. }
  1184. static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
  1185. struct snd_ctl_elem_info *uinfo)
  1186. {
  1187. int mask = (kcontrol->private_value >> 24) & 0xff;
  1188. uinfo->type = mask == 1 ?
  1189. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1190. uinfo->count = 2;
  1191. uinfo->value.integer.min = 0;
  1192. uinfo->value.integer.max = mask;
  1193. return 0;
  1194. }
  1195. static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
  1196. struct snd_ctl_elem_value *ucontrol)
  1197. {
  1198. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1199. unsigned long flags;
  1200. int left_reg = kcontrol->private_value & 0xff;
  1201. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1202. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1203. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1204. int mask = (kcontrol->private_value >> 24) & 0xff;
  1205. int invert = (kcontrol->private_value >> 22) & 1;
  1206. spin_lock_irqsave(&chip->lock, flags);
  1207. ucontrol->value.integer.value[0] =
  1208. (chip->image[left_reg] >> shift_left) & mask;
  1209. ucontrol->value.integer.value[1] =
  1210. (chip->image[right_reg] >> shift_right) & mask;
  1211. spin_unlock_irqrestore(&chip->lock, flags);
  1212. if (invert) {
  1213. ucontrol->value.integer.value[0] =
  1214. (mask - ucontrol->value.integer.value[0]);
  1215. ucontrol->value.integer.value[1] =
  1216. (mask - ucontrol->value.integer.value[1]);
  1217. }
  1218. return 0;
  1219. }
  1220. static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
  1221. struct snd_ctl_elem_value *ucontrol)
  1222. {
  1223. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1224. unsigned long flags;
  1225. int left_reg = kcontrol->private_value & 0xff;
  1226. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1227. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1228. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1229. int mask = (kcontrol->private_value >> 24) & 0xff;
  1230. int invert = (kcontrol->private_value >> 22) & 1;
  1231. int change;
  1232. unsigned short val1, val2;
  1233. val1 = ucontrol->value.integer.value[0] & mask;
  1234. val2 = ucontrol->value.integer.value[1] & mask;
  1235. if (invert) {
  1236. val1 = mask - val1;
  1237. val2 = mask - val2;
  1238. }
  1239. val1 <<= shift_left;
  1240. val2 <<= shift_right;
  1241. spin_lock_irqsave(&chip->lock, flags);
  1242. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1243. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1244. change = val1 != chip->image[left_reg];
  1245. change |= val2 != chip->image[right_reg];
  1246. snd_cs4231_out(chip, left_reg, val1);
  1247. snd_cs4231_out(chip, right_reg, val2);
  1248. spin_unlock_irqrestore(&chip->lock, flags);
  1249. return change;
  1250. }
  1251. #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
  1252. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1253. .info = snd_cs4231_info_single, \
  1254. .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
  1255. .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) }
  1256. #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \
  1257. shift_right, mask, invert) \
  1258. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1259. .info = snd_cs4231_info_double, \
  1260. .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
  1261. .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \
  1262. ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) }
  1263. static struct snd_kcontrol_new snd_cs4231_controls[] __devinitdata = {
  1264. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT,
  1265. CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1266. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT,
  1267. CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1268. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN,
  1269. CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1270. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN,
  1271. CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1272. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT,
  1273. CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1274. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT,
  1275. CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1276. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT,
  1277. CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1278. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT,
  1279. CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1280. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1281. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1282. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1283. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1284. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0,
  1285. 15, 0),
  1286. {
  1287. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1288. .name = "Capture Source",
  1289. .info = snd_cs4231_info_mux,
  1290. .get = snd_cs4231_get_mux,
  1291. .put = snd_cs4231_put_mux,
  1292. },
  1293. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5,
  1294. 1, 0),
  1295. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1296. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
  1297. /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
  1298. CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
  1299. CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
  1300. };
  1301. static int __devinit snd_cs4231_mixer(struct snd_card *card)
  1302. {
  1303. struct snd_cs4231 *chip = card->private_data;
  1304. int err, idx;
  1305. if (snd_BUG_ON(!chip || !chip->pcm))
  1306. return -EINVAL;
  1307. strcpy(card->mixername, chip->pcm->name);
  1308. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1309. err = snd_ctl_add(card,
  1310. snd_ctl_new1(&snd_cs4231_controls[idx], chip));
  1311. if (err < 0)
  1312. return err;
  1313. }
  1314. return 0;
  1315. }
  1316. static int dev;
  1317. static int __devinit cs4231_attach_begin(struct snd_card **rcard)
  1318. {
  1319. struct snd_card *card;
  1320. struct snd_cs4231 *chip;
  1321. int err;
  1322. *rcard = NULL;
  1323. if (dev >= SNDRV_CARDS)
  1324. return -ENODEV;
  1325. if (!enable[dev]) {
  1326. dev++;
  1327. return -ENOENT;
  1328. }
  1329. err = snd_card_create(index[dev], id[dev], THIS_MODULE,
  1330. sizeof(struct snd_cs4231), &card);
  1331. if (err < 0)
  1332. return err;
  1333. strcpy(card->driver, "CS4231");
  1334. strcpy(card->shortname, "Sun CS4231");
  1335. chip = card->private_data;
  1336. chip->card = card;
  1337. *rcard = card;
  1338. return 0;
  1339. }
  1340. static int __devinit cs4231_attach_finish(struct snd_card *card)
  1341. {
  1342. struct snd_cs4231 *chip = card->private_data;
  1343. int err;
  1344. err = snd_cs4231_pcm(card);
  1345. if (err < 0)
  1346. goto out_err;
  1347. err = snd_cs4231_mixer(card);
  1348. if (err < 0)
  1349. goto out_err;
  1350. err = snd_cs4231_timer(card);
  1351. if (err < 0)
  1352. goto out_err;
  1353. err = snd_card_register(card);
  1354. if (err < 0)
  1355. goto out_err;
  1356. dev_set_drvdata(&chip->op->dev, chip);
  1357. dev++;
  1358. return 0;
  1359. out_err:
  1360. snd_card_free(card);
  1361. return err;
  1362. }
  1363. #ifdef SBUS_SUPPORT
  1364. static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
  1365. {
  1366. unsigned long flags;
  1367. unsigned char status;
  1368. u32 csr;
  1369. struct snd_cs4231 *chip = dev_id;
  1370. /*This is IRQ is not raised by the cs4231*/
  1371. if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ))
  1372. return IRQ_NONE;
  1373. /* ACK the APC interrupt. */
  1374. csr = sbus_readl(chip->port + APCCSR);
  1375. sbus_writel(csr, chip->port + APCCSR);
  1376. if ((csr & APC_PDMA_READY) &&
  1377. (csr & APC_PLAY_INT) &&
  1378. (csr & APC_XINT_PNVA) &&
  1379. !(csr & APC_XINT_EMPT))
  1380. snd_cs4231_play_callback(chip);
  1381. if ((csr & APC_CDMA_READY) &&
  1382. (csr & APC_CAPT_INT) &&
  1383. (csr & APC_XINT_CNVA) &&
  1384. !(csr & APC_XINT_EMPT))
  1385. snd_cs4231_capture_callback(chip);
  1386. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  1387. if (status & CS4231_TIMER_IRQ) {
  1388. if (chip->timer)
  1389. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1390. }
  1391. if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
  1392. snd_cs4231_overrange(chip);
  1393. /* ACK the CS4231 interrupt. */
  1394. spin_lock_irqsave(&chip->lock, flags);
  1395. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  1396. spin_unlock_irqrestore(&chip->lock, flags);
  1397. return IRQ_HANDLED;
  1398. }
  1399. /*
  1400. * SBUS DMA routines
  1401. */
  1402. static int sbus_dma_request(struct cs4231_dma_control *dma_cont,
  1403. dma_addr_t bus_addr, size_t len)
  1404. {
  1405. unsigned long flags;
  1406. u32 test, csr;
  1407. int err;
  1408. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1409. if (len >= (1 << 24))
  1410. return -EINVAL;
  1411. spin_lock_irqsave(&base->lock, flags);
  1412. csr = sbus_readl(base->regs + APCCSR);
  1413. err = -EINVAL;
  1414. test = APC_CDMA_READY;
  1415. if (base->dir == APC_PLAY)
  1416. test = APC_PDMA_READY;
  1417. if (!(csr & test))
  1418. goto out;
  1419. err = -EBUSY;
  1420. test = APC_XINT_CNVA;
  1421. if (base->dir == APC_PLAY)
  1422. test = APC_XINT_PNVA;
  1423. if (!(csr & test))
  1424. goto out;
  1425. err = 0;
  1426. sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
  1427. sbus_writel(len, base->regs + base->dir + APCNC);
  1428. out:
  1429. spin_unlock_irqrestore(&base->lock, flags);
  1430. return err;
  1431. }
  1432. static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
  1433. {
  1434. unsigned long flags;
  1435. u32 csr, test;
  1436. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1437. spin_lock_irqsave(&base->lock, flags);
  1438. csr = sbus_readl(base->regs + APCCSR);
  1439. test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
  1440. APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
  1441. APC_XINT_PENA;
  1442. if (base->dir == APC_RECORD)
  1443. test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
  1444. APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
  1445. csr |= test;
  1446. sbus_writel(csr, base->regs + APCCSR);
  1447. spin_unlock_irqrestore(&base->lock, flags);
  1448. }
  1449. static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1450. {
  1451. unsigned long flags;
  1452. u32 csr, shift;
  1453. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1454. spin_lock_irqsave(&base->lock, flags);
  1455. if (!on) {
  1456. sbus_writel(0, base->regs + base->dir + APCNC);
  1457. sbus_writel(0, base->regs + base->dir + APCNVA);
  1458. if (base->dir == APC_PLAY) {
  1459. sbus_writel(0, base->regs + base->dir + APCC);
  1460. sbus_writel(0, base->regs + base->dir + APCVA);
  1461. }
  1462. udelay(1200);
  1463. }
  1464. csr = sbus_readl(base->regs + APCCSR);
  1465. shift = 0;
  1466. if (base->dir == APC_PLAY)
  1467. shift = 1;
  1468. if (on)
  1469. csr &= ~(APC_CPAUSE << shift);
  1470. else
  1471. csr |= (APC_CPAUSE << shift);
  1472. sbus_writel(csr, base->regs + APCCSR);
  1473. if (on)
  1474. csr |= (APC_CDMA_READY << shift);
  1475. else
  1476. csr &= ~(APC_CDMA_READY << shift);
  1477. sbus_writel(csr, base->regs + APCCSR);
  1478. spin_unlock_irqrestore(&base->lock, flags);
  1479. }
  1480. static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
  1481. {
  1482. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1483. return sbus_readl(base->regs + base->dir + APCVA);
  1484. }
  1485. /*
  1486. * Init and exit routines
  1487. */
  1488. static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
  1489. {
  1490. struct of_device *op = chip->op;
  1491. if (chip->irq[0])
  1492. free_irq(chip->irq[0], chip);
  1493. if (chip->port)
  1494. of_iounmap(&op->resource[0], chip->port, chip->regs_size);
  1495. return 0;
  1496. }
  1497. static int snd_cs4231_sbus_dev_free(struct snd_device *device)
  1498. {
  1499. struct snd_cs4231 *cp = device->device_data;
  1500. return snd_cs4231_sbus_free(cp);
  1501. }
  1502. static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
  1503. .dev_free = snd_cs4231_sbus_dev_free,
  1504. };
  1505. static int __devinit snd_cs4231_sbus_create(struct snd_card *card,
  1506. struct of_device *op,
  1507. int dev)
  1508. {
  1509. struct snd_cs4231 *chip = card->private_data;
  1510. int err;
  1511. spin_lock_init(&chip->lock);
  1512. spin_lock_init(&chip->c_dma.sbus_info.lock);
  1513. spin_lock_init(&chip->p_dma.sbus_info.lock);
  1514. mutex_init(&chip->mce_mutex);
  1515. mutex_init(&chip->open_mutex);
  1516. chip->op = op;
  1517. chip->regs_size = resource_size(&op->resource[0]);
  1518. memcpy(&chip->image, &snd_cs4231_original_image,
  1519. sizeof(snd_cs4231_original_image));
  1520. chip->port = of_ioremap(&op->resource[0], 0,
  1521. chip->regs_size, "cs4231");
  1522. if (!chip->port) {
  1523. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1524. return -EIO;
  1525. }
  1526. chip->c_dma.sbus_info.regs = chip->port;
  1527. chip->p_dma.sbus_info.regs = chip->port;
  1528. chip->c_dma.sbus_info.dir = APC_RECORD;
  1529. chip->p_dma.sbus_info.dir = APC_PLAY;
  1530. chip->p_dma.prepare = sbus_dma_prepare;
  1531. chip->p_dma.enable = sbus_dma_enable;
  1532. chip->p_dma.request = sbus_dma_request;
  1533. chip->p_dma.address = sbus_dma_addr;
  1534. chip->c_dma.prepare = sbus_dma_prepare;
  1535. chip->c_dma.enable = sbus_dma_enable;
  1536. chip->c_dma.request = sbus_dma_request;
  1537. chip->c_dma.address = sbus_dma_addr;
  1538. if (request_irq(op->irqs[0], snd_cs4231_sbus_interrupt,
  1539. IRQF_SHARED, "cs4231", chip)) {
  1540. snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
  1541. dev, op->irqs[0]);
  1542. snd_cs4231_sbus_free(chip);
  1543. return -EBUSY;
  1544. }
  1545. chip->irq[0] = op->irqs[0];
  1546. if (snd_cs4231_probe(chip) < 0) {
  1547. snd_cs4231_sbus_free(chip);
  1548. return -ENODEV;
  1549. }
  1550. snd_cs4231_init(chip);
  1551. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1552. chip, &snd_cs4231_sbus_dev_ops)) < 0) {
  1553. snd_cs4231_sbus_free(chip);
  1554. return err;
  1555. }
  1556. return 0;
  1557. }
  1558. static int __devinit cs4231_sbus_probe(struct of_device *op, const struct of_device_id *match)
  1559. {
  1560. struct resource *rp = &op->resource[0];
  1561. struct snd_card *card;
  1562. int err;
  1563. err = cs4231_attach_begin(&card);
  1564. if (err)
  1565. return err;
  1566. sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
  1567. card->shortname,
  1568. rp->flags & 0xffL,
  1569. (unsigned long long)rp->start,
  1570. op->irqs[0]);
  1571. err = snd_cs4231_sbus_create(card, op, dev);
  1572. if (err < 0) {
  1573. snd_card_free(card);
  1574. return err;
  1575. }
  1576. return cs4231_attach_finish(card);
  1577. }
  1578. #endif
  1579. #ifdef EBUS_SUPPORT
  1580. static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event,
  1581. void *cookie)
  1582. {
  1583. struct snd_cs4231 *chip = cookie;
  1584. snd_cs4231_play_callback(chip);
  1585. }
  1586. static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p,
  1587. int event, void *cookie)
  1588. {
  1589. struct snd_cs4231 *chip = cookie;
  1590. snd_cs4231_capture_callback(chip);
  1591. }
  1592. /*
  1593. * EBUS DMA wrappers
  1594. */
  1595. static int _ebus_dma_request(struct cs4231_dma_control *dma_cont,
  1596. dma_addr_t bus_addr, size_t len)
  1597. {
  1598. return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
  1599. }
  1600. static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1601. {
  1602. ebus_dma_enable(&dma_cont->ebus_info, on);
  1603. }
  1604. static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
  1605. {
  1606. ebus_dma_prepare(&dma_cont->ebus_info, dir);
  1607. }
  1608. static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
  1609. {
  1610. return ebus_dma_addr(&dma_cont->ebus_info);
  1611. }
  1612. /*
  1613. * Init and exit routines
  1614. */
  1615. static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
  1616. {
  1617. struct of_device *op = chip->op;
  1618. if (chip->c_dma.ebus_info.regs) {
  1619. ebus_dma_unregister(&chip->c_dma.ebus_info);
  1620. of_iounmap(&op->resource[2], chip->c_dma.ebus_info.regs, 0x10);
  1621. }
  1622. if (chip->p_dma.ebus_info.regs) {
  1623. ebus_dma_unregister(&chip->p_dma.ebus_info);
  1624. of_iounmap(&op->resource[1], chip->p_dma.ebus_info.regs, 0x10);
  1625. }
  1626. if (chip->port)
  1627. of_iounmap(&op->resource[0], chip->port, 0x10);
  1628. return 0;
  1629. }
  1630. static int snd_cs4231_ebus_dev_free(struct snd_device *device)
  1631. {
  1632. struct snd_cs4231 *cp = device->device_data;
  1633. return snd_cs4231_ebus_free(cp);
  1634. }
  1635. static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
  1636. .dev_free = snd_cs4231_ebus_dev_free,
  1637. };
  1638. static int __devinit snd_cs4231_ebus_create(struct snd_card *card,
  1639. struct of_device *op,
  1640. int dev)
  1641. {
  1642. struct snd_cs4231 *chip = card->private_data;
  1643. int err;
  1644. spin_lock_init(&chip->lock);
  1645. spin_lock_init(&chip->c_dma.ebus_info.lock);
  1646. spin_lock_init(&chip->p_dma.ebus_info.lock);
  1647. mutex_init(&chip->mce_mutex);
  1648. mutex_init(&chip->open_mutex);
  1649. chip->flags |= CS4231_FLAG_EBUS;
  1650. chip->op = op;
  1651. memcpy(&chip->image, &snd_cs4231_original_image,
  1652. sizeof(snd_cs4231_original_image));
  1653. strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
  1654. chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1655. chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
  1656. chip->c_dma.ebus_info.client_cookie = chip;
  1657. chip->c_dma.ebus_info.irq = op->irqs[0];
  1658. strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
  1659. chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1660. chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
  1661. chip->p_dma.ebus_info.client_cookie = chip;
  1662. chip->p_dma.ebus_info.irq = op->irqs[1];
  1663. chip->p_dma.prepare = _ebus_dma_prepare;
  1664. chip->p_dma.enable = _ebus_dma_enable;
  1665. chip->p_dma.request = _ebus_dma_request;
  1666. chip->p_dma.address = _ebus_dma_addr;
  1667. chip->c_dma.prepare = _ebus_dma_prepare;
  1668. chip->c_dma.enable = _ebus_dma_enable;
  1669. chip->c_dma.request = _ebus_dma_request;
  1670. chip->c_dma.address = _ebus_dma_addr;
  1671. chip->port = of_ioremap(&op->resource[0], 0, 0x10, "cs4231");
  1672. chip->p_dma.ebus_info.regs =
  1673. of_ioremap(&op->resource[1], 0, 0x10, "cs4231_pdma");
  1674. chip->c_dma.ebus_info.regs =
  1675. of_ioremap(&op->resource[2], 0, 0x10, "cs4231_cdma");
  1676. if (!chip->port || !chip->p_dma.ebus_info.regs ||
  1677. !chip->c_dma.ebus_info.regs) {
  1678. snd_cs4231_ebus_free(chip);
  1679. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1680. return -EIO;
  1681. }
  1682. if (ebus_dma_register(&chip->c_dma.ebus_info)) {
  1683. snd_cs4231_ebus_free(chip);
  1684. snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n",
  1685. dev);
  1686. return -EBUSY;
  1687. }
  1688. if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
  1689. snd_cs4231_ebus_free(chip);
  1690. snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n",
  1691. dev);
  1692. return -EBUSY;
  1693. }
  1694. if (ebus_dma_register(&chip->p_dma.ebus_info)) {
  1695. snd_cs4231_ebus_free(chip);
  1696. snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n",
  1697. dev);
  1698. return -EBUSY;
  1699. }
  1700. if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
  1701. snd_cs4231_ebus_free(chip);
  1702. snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
  1703. return -EBUSY;
  1704. }
  1705. if (snd_cs4231_probe(chip) < 0) {
  1706. snd_cs4231_ebus_free(chip);
  1707. return -ENODEV;
  1708. }
  1709. snd_cs4231_init(chip);
  1710. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1711. chip, &snd_cs4231_ebus_dev_ops)) < 0) {
  1712. snd_cs4231_ebus_free(chip);
  1713. return err;
  1714. }
  1715. return 0;
  1716. }
  1717. static int __devinit cs4231_ebus_probe(struct of_device *op, const struct of_device_id *match)
  1718. {
  1719. struct snd_card *card;
  1720. int err;
  1721. err = cs4231_attach_begin(&card);
  1722. if (err)
  1723. return err;
  1724. sprintf(card->longname, "%s at 0x%llx, irq %d",
  1725. card->shortname,
  1726. op->resource[0].start,
  1727. op->irqs[0]);
  1728. err = snd_cs4231_ebus_create(card, op, dev);
  1729. if (err < 0) {
  1730. snd_card_free(card);
  1731. return err;
  1732. }
  1733. return cs4231_attach_finish(card);
  1734. }
  1735. #endif
  1736. static int __devinit cs4231_probe(struct of_device *op, const struct of_device_id *match)
  1737. {
  1738. #ifdef EBUS_SUPPORT
  1739. if (!strcmp(op->node->parent->name, "ebus"))
  1740. return cs4231_ebus_probe(op, match);
  1741. #endif
  1742. #ifdef SBUS_SUPPORT
  1743. if (!strcmp(op->node->parent->name, "sbus") ||
  1744. !strcmp(op->node->parent->name, "sbi"))
  1745. return cs4231_sbus_probe(op, match);
  1746. #endif
  1747. return -ENODEV;
  1748. }
  1749. static int __devexit cs4231_remove(struct of_device *op)
  1750. {
  1751. struct snd_cs4231 *chip = dev_get_drvdata(&op->dev);
  1752. snd_card_free(chip->card);
  1753. return 0;
  1754. }
  1755. static const struct of_device_id cs4231_match[] = {
  1756. {
  1757. .name = "SUNW,CS4231",
  1758. },
  1759. {
  1760. .name = "audio",
  1761. .compatible = "SUNW,CS4231",
  1762. },
  1763. {},
  1764. };
  1765. MODULE_DEVICE_TABLE(of, cs4231_match);
  1766. static struct of_platform_driver cs4231_driver = {
  1767. .name = "audio",
  1768. .match_table = cs4231_match,
  1769. .probe = cs4231_probe,
  1770. .remove = __devexit_p(cs4231_remove),
  1771. };
  1772. static int __init cs4231_init(void)
  1773. {
  1774. return of_register_driver(&cs4231_driver, &of_bus_type);
  1775. }
  1776. static void __exit cs4231_exit(void)
  1777. {
  1778. of_unregister_driver(&cs4231_driver);
  1779. }
  1780. module_init(cs4231_init);
  1781. module_exit(cs4231_exit);