oxygen_pcm.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750
  1. /*
  2. * C-Media CMI8788 driver - PCM code
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/pci.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include "oxygen.h"
  25. /* most DMA channels have a 16-bit counter for 32-bit words */
  26. #define BUFFER_BYTES_MAX ((1 << 16) * 4)
  27. /* the multichannel DMA channel has a 24-bit counter */
  28. #define BUFFER_BYTES_MAX_MULTICH ((1 << 24) * 4)
  29. #define PERIOD_BYTES_MIN 64
  30. #define DEFAULT_BUFFER_BYTES (BUFFER_BYTES_MAX / 2)
  31. #define DEFAULT_BUFFER_BYTES_MULTICH (1024 * 1024)
  32. static const struct snd_pcm_hardware oxygen_stereo_hardware = {
  33. .info = SNDRV_PCM_INFO_MMAP |
  34. SNDRV_PCM_INFO_MMAP_VALID |
  35. SNDRV_PCM_INFO_INTERLEAVED |
  36. SNDRV_PCM_INFO_PAUSE |
  37. SNDRV_PCM_INFO_SYNC_START,
  38. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  39. SNDRV_PCM_FMTBIT_S32_LE,
  40. .rates = SNDRV_PCM_RATE_32000 |
  41. SNDRV_PCM_RATE_44100 |
  42. SNDRV_PCM_RATE_48000 |
  43. SNDRV_PCM_RATE_64000 |
  44. SNDRV_PCM_RATE_88200 |
  45. SNDRV_PCM_RATE_96000 |
  46. SNDRV_PCM_RATE_176400 |
  47. SNDRV_PCM_RATE_192000,
  48. .rate_min = 32000,
  49. .rate_max = 192000,
  50. .channels_min = 2,
  51. .channels_max = 2,
  52. .buffer_bytes_max = BUFFER_BYTES_MAX,
  53. .period_bytes_min = PERIOD_BYTES_MIN,
  54. .period_bytes_max = BUFFER_BYTES_MAX / 2,
  55. .periods_min = 2,
  56. .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
  57. };
  58. static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
  59. .info = SNDRV_PCM_INFO_MMAP |
  60. SNDRV_PCM_INFO_MMAP_VALID |
  61. SNDRV_PCM_INFO_INTERLEAVED |
  62. SNDRV_PCM_INFO_PAUSE |
  63. SNDRV_PCM_INFO_SYNC_START,
  64. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  65. SNDRV_PCM_FMTBIT_S32_LE,
  66. .rates = SNDRV_PCM_RATE_32000 |
  67. SNDRV_PCM_RATE_44100 |
  68. SNDRV_PCM_RATE_48000 |
  69. SNDRV_PCM_RATE_64000 |
  70. SNDRV_PCM_RATE_88200 |
  71. SNDRV_PCM_RATE_96000 |
  72. SNDRV_PCM_RATE_176400 |
  73. SNDRV_PCM_RATE_192000,
  74. .rate_min = 32000,
  75. .rate_max = 192000,
  76. .channels_min = 2,
  77. .channels_max = 8,
  78. .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
  79. .period_bytes_min = PERIOD_BYTES_MIN,
  80. .period_bytes_max = BUFFER_BYTES_MAX_MULTICH / 2,
  81. .periods_min = 2,
  82. .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
  83. };
  84. static const struct snd_pcm_hardware oxygen_ac97_hardware = {
  85. .info = SNDRV_PCM_INFO_MMAP |
  86. SNDRV_PCM_INFO_MMAP_VALID |
  87. SNDRV_PCM_INFO_INTERLEAVED |
  88. SNDRV_PCM_INFO_PAUSE |
  89. SNDRV_PCM_INFO_SYNC_START,
  90. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  91. .rates = SNDRV_PCM_RATE_48000,
  92. .rate_min = 48000,
  93. .rate_max = 48000,
  94. .channels_min = 2,
  95. .channels_max = 2,
  96. .buffer_bytes_max = BUFFER_BYTES_MAX,
  97. .period_bytes_min = PERIOD_BYTES_MIN,
  98. .period_bytes_max = BUFFER_BYTES_MAX / 2,
  99. .periods_min = 2,
  100. .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
  101. };
  102. static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
  103. [PCM_A] = &oxygen_stereo_hardware,
  104. [PCM_B] = &oxygen_stereo_hardware,
  105. [PCM_C] = &oxygen_stereo_hardware,
  106. [PCM_SPDIF] = &oxygen_stereo_hardware,
  107. [PCM_MULTICH] = &oxygen_multichannel_hardware,
  108. [PCM_AC97] = &oxygen_ac97_hardware,
  109. };
  110. static inline unsigned int
  111. oxygen_substream_channel(struct snd_pcm_substream *substream)
  112. {
  113. return (unsigned int)(uintptr_t)substream->runtime->private_data;
  114. }
  115. static int oxygen_open(struct snd_pcm_substream *substream,
  116. unsigned int channel)
  117. {
  118. struct oxygen *chip = snd_pcm_substream_chip(substream);
  119. struct snd_pcm_runtime *runtime = substream->runtime;
  120. int err;
  121. runtime->private_data = (void *)(uintptr_t)channel;
  122. if (channel == PCM_B && chip->has_ac97_1 &&
  123. (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
  124. runtime->hw = oxygen_ac97_hardware;
  125. else
  126. runtime->hw = *oxygen_hardware[channel];
  127. switch (channel) {
  128. case PCM_C:
  129. runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
  130. SNDRV_PCM_RATE_64000);
  131. runtime->hw.rate_min = 44100;
  132. break;
  133. case PCM_MULTICH:
  134. runtime->hw.channels_max = chip->model.dac_channels;
  135. break;
  136. }
  137. if (chip->model.pcm_hardware_filter)
  138. chip->model.pcm_hardware_filter(channel, &runtime->hw);
  139. err = snd_pcm_hw_constraint_step(runtime, 0,
  140. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
  141. if (err < 0)
  142. return err;
  143. err = snd_pcm_hw_constraint_step(runtime, 0,
  144. SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
  145. if (err < 0)
  146. return err;
  147. if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
  148. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  149. if (err < 0)
  150. return err;
  151. }
  152. if (runtime->hw.channels_max > 2) {
  153. err = snd_pcm_hw_constraint_step(runtime, 0,
  154. SNDRV_PCM_HW_PARAM_CHANNELS,
  155. 2);
  156. if (err < 0)
  157. return err;
  158. }
  159. if (channel == PCM_MULTICH) {
  160. err = snd_pcm_hw_constraint_minmax
  161. (runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 0, 8192000);
  162. if (err < 0)
  163. return err;
  164. }
  165. snd_pcm_set_sync(substream);
  166. chip->streams[channel] = substream;
  167. mutex_lock(&chip->mutex);
  168. chip->pcm_active |= 1 << channel;
  169. if (channel == PCM_SPDIF) {
  170. chip->spdif_pcm_bits = chip->spdif_bits;
  171. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
  172. ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  173. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  174. SNDRV_CTL_EVENT_MASK_INFO,
  175. &chip->controls[CONTROL_SPDIF_PCM]->id);
  176. }
  177. mutex_unlock(&chip->mutex);
  178. return 0;
  179. }
  180. static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
  181. {
  182. return oxygen_open(substream, PCM_A);
  183. }
  184. static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
  185. {
  186. return oxygen_open(substream, PCM_B);
  187. }
  188. static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
  189. {
  190. return oxygen_open(substream, PCM_C);
  191. }
  192. static int oxygen_spdif_open(struct snd_pcm_substream *substream)
  193. {
  194. return oxygen_open(substream, PCM_SPDIF);
  195. }
  196. static int oxygen_multich_open(struct snd_pcm_substream *substream)
  197. {
  198. return oxygen_open(substream, PCM_MULTICH);
  199. }
  200. static int oxygen_ac97_open(struct snd_pcm_substream *substream)
  201. {
  202. return oxygen_open(substream, PCM_AC97);
  203. }
  204. static int oxygen_close(struct snd_pcm_substream *substream)
  205. {
  206. struct oxygen *chip = snd_pcm_substream_chip(substream);
  207. unsigned int channel = oxygen_substream_channel(substream);
  208. mutex_lock(&chip->mutex);
  209. chip->pcm_active &= ~(1 << channel);
  210. if (channel == PCM_SPDIF) {
  211. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
  212. SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  213. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  214. SNDRV_CTL_EVENT_MASK_INFO,
  215. &chip->controls[CONTROL_SPDIF_PCM]->id);
  216. }
  217. if (channel == PCM_SPDIF || channel == PCM_MULTICH)
  218. oxygen_update_spdif_source(chip);
  219. mutex_unlock(&chip->mutex);
  220. chip->streams[channel] = NULL;
  221. return 0;
  222. }
  223. static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
  224. {
  225. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  226. return OXYGEN_FORMAT_24;
  227. else
  228. return OXYGEN_FORMAT_16;
  229. }
  230. static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
  231. {
  232. switch (params_rate(hw_params)) {
  233. case 32000:
  234. return OXYGEN_RATE_32000;
  235. case 44100:
  236. return OXYGEN_RATE_44100;
  237. default: /* 48000 */
  238. return OXYGEN_RATE_48000;
  239. case 64000:
  240. return OXYGEN_RATE_64000;
  241. case 88200:
  242. return OXYGEN_RATE_88200;
  243. case 96000:
  244. return OXYGEN_RATE_96000;
  245. case 176400:
  246. return OXYGEN_RATE_176400;
  247. case 192000:
  248. return OXYGEN_RATE_192000;
  249. }
  250. }
  251. static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
  252. {
  253. if (params_rate(hw_params) <= 96000)
  254. return OXYGEN_I2S_MCLK_256;
  255. else
  256. return OXYGEN_I2S_MCLK_128;
  257. }
  258. static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
  259. {
  260. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  261. return OXYGEN_I2S_BITS_24;
  262. else
  263. return OXYGEN_I2S_BITS_16;
  264. }
  265. static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
  266. {
  267. switch (params_channels(hw_params)) {
  268. default: /* 2 */
  269. return OXYGEN_PLAY_CHANNELS_2;
  270. case 4:
  271. return OXYGEN_PLAY_CHANNELS_4;
  272. case 6:
  273. return OXYGEN_PLAY_CHANNELS_6;
  274. case 8:
  275. return OXYGEN_PLAY_CHANNELS_8;
  276. }
  277. }
  278. static const unsigned int channel_base_registers[PCM_COUNT] = {
  279. [PCM_A] = OXYGEN_DMA_A_ADDRESS,
  280. [PCM_B] = OXYGEN_DMA_B_ADDRESS,
  281. [PCM_C] = OXYGEN_DMA_C_ADDRESS,
  282. [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
  283. [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
  284. [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
  285. };
  286. static int oxygen_hw_params(struct snd_pcm_substream *substream,
  287. struct snd_pcm_hw_params *hw_params)
  288. {
  289. struct oxygen *chip = snd_pcm_substream_chip(substream);
  290. unsigned int channel = oxygen_substream_channel(substream);
  291. int err;
  292. err = snd_pcm_lib_malloc_pages(substream,
  293. params_buffer_bytes(hw_params));
  294. if (err < 0)
  295. return err;
  296. oxygen_write32(chip, channel_base_registers[channel],
  297. (u32)substream->runtime->dma_addr);
  298. if (channel == PCM_MULTICH) {
  299. oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
  300. params_buffer_bytes(hw_params) / 4 - 1);
  301. oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
  302. params_period_bytes(hw_params) / 4 - 1);
  303. } else {
  304. oxygen_write16(chip, channel_base_registers[channel] + 4,
  305. params_buffer_bytes(hw_params) / 4 - 1);
  306. oxygen_write16(chip, channel_base_registers[channel] + 6,
  307. params_period_bytes(hw_params) / 4 - 1);
  308. }
  309. return 0;
  310. }
  311. static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
  312. struct snd_pcm_hw_params *hw_params)
  313. {
  314. struct oxygen *chip = snd_pcm_substream_chip(substream);
  315. int err;
  316. err = oxygen_hw_params(substream, hw_params);
  317. if (err < 0)
  318. return err;
  319. spin_lock_irq(&chip->reg_lock);
  320. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  321. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
  322. OXYGEN_REC_FORMAT_A_MASK);
  323. oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
  324. oxygen_rate(hw_params) |
  325. oxygen_i2s_mclk(hw_params) |
  326. chip->model.adc_i2s_format |
  327. oxygen_i2s_bits(hw_params),
  328. OXYGEN_I2S_RATE_MASK |
  329. OXYGEN_I2S_FORMAT_MASK |
  330. OXYGEN_I2S_MCLK_MASK |
  331. OXYGEN_I2S_BITS_MASK);
  332. spin_unlock_irq(&chip->reg_lock);
  333. mutex_lock(&chip->mutex);
  334. chip->model.set_adc_params(chip, hw_params);
  335. mutex_unlock(&chip->mutex);
  336. return 0;
  337. }
  338. static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
  339. struct snd_pcm_hw_params *hw_params)
  340. {
  341. struct oxygen *chip = snd_pcm_substream_chip(substream);
  342. int is_ac97;
  343. int err;
  344. err = oxygen_hw_params(substream, hw_params);
  345. if (err < 0)
  346. return err;
  347. is_ac97 = chip->has_ac97_1 &&
  348. (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
  349. spin_lock_irq(&chip->reg_lock);
  350. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  351. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
  352. OXYGEN_REC_FORMAT_B_MASK);
  353. if (!is_ac97)
  354. oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
  355. oxygen_rate(hw_params) |
  356. oxygen_i2s_mclk(hw_params) |
  357. chip->model.adc_i2s_format |
  358. oxygen_i2s_bits(hw_params),
  359. OXYGEN_I2S_RATE_MASK |
  360. OXYGEN_I2S_FORMAT_MASK |
  361. OXYGEN_I2S_MCLK_MASK |
  362. OXYGEN_I2S_BITS_MASK);
  363. spin_unlock_irq(&chip->reg_lock);
  364. if (!is_ac97) {
  365. mutex_lock(&chip->mutex);
  366. chip->model.set_adc_params(chip, hw_params);
  367. mutex_unlock(&chip->mutex);
  368. }
  369. return 0;
  370. }
  371. static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
  372. struct snd_pcm_hw_params *hw_params)
  373. {
  374. struct oxygen *chip = snd_pcm_substream_chip(substream);
  375. int err;
  376. err = oxygen_hw_params(substream, hw_params);
  377. if (err < 0)
  378. return err;
  379. spin_lock_irq(&chip->reg_lock);
  380. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  381. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
  382. OXYGEN_REC_FORMAT_C_MASK);
  383. spin_unlock_irq(&chip->reg_lock);
  384. return 0;
  385. }
  386. static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
  387. struct snd_pcm_hw_params *hw_params)
  388. {
  389. struct oxygen *chip = snd_pcm_substream_chip(substream);
  390. int err;
  391. err = oxygen_hw_params(substream, hw_params);
  392. if (err < 0)
  393. return err;
  394. spin_lock_irq(&chip->reg_lock);
  395. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  396. OXYGEN_SPDIF_OUT_ENABLE);
  397. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  398. oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
  399. OXYGEN_SPDIF_FORMAT_MASK);
  400. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  401. oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
  402. OXYGEN_SPDIF_OUT_RATE_MASK);
  403. oxygen_update_spdif_source(chip);
  404. spin_unlock_irq(&chip->reg_lock);
  405. return 0;
  406. }
  407. static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
  408. struct snd_pcm_hw_params *hw_params)
  409. {
  410. struct oxygen *chip = snd_pcm_substream_chip(substream);
  411. int err;
  412. err = oxygen_hw_params(substream, hw_params);
  413. if (err < 0)
  414. return err;
  415. spin_lock_irq(&chip->reg_lock);
  416. oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
  417. oxygen_play_channels(hw_params),
  418. OXYGEN_PLAY_CHANNELS_MASK);
  419. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  420. oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
  421. OXYGEN_MULTICH_FORMAT_MASK);
  422. oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
  423. oxygen_rate(hw_params) |
  424. chip->model.dac_i2s_format |
  425. oxygen_i2s_bits(hw_params),
  426. OXYGEN_I2S_RATE_MASK |
  427. OXYGEN_I2S_FORMAT_MASK |
  428. OXYGEN_I2S_BITS_MASK);
  429. oxygen_update_dac_routing(chip);
  430. oxygen_update_spdif_source(chip);
  431. spin_unlock_irq(&chip->reg_lock);
  432. mutex_lock(&chip->mutex);
  433. chip->model.set_dac_params(chip, hw_params);
  434. mutex_unlock(&chip->mutex);
  435. return 0;
  436. }
  437. static int oxygen_hw_free(struct snd_pcm_substream *substream)
  438. {
  439. struct oxygen *chip = snd_pcm_substream_chip(substream);
  440. unsigned int channel = oxygen_substream_channel(substream);
  441. unsigned int channel_mask = 1 << channel;
  442. spin_lock_irq(&chip->reg_lock);
  443. chip->interrupt_mask &= ~channel_mask;
  444. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  445. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  446. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  447. spin_unlock_irq(&chip->reg_lock);
  448. return snd_pcm_lib_free_pages(substream);
  449. }
  450. static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
  451. {
  452. struct oxygen *chip = snd_pcm_substream_chip(substream);
  453. spin_lock_irq(&chip->reg_lock);
  454. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  455. OXYGEN_SPDIF_OUT_ENABLE);
  456. spin_unlock_irq(&chip->reg_lock);
  457. return oxygen_hw_free(substream);
  458. }
  459. static int oxygen_prepare(struct snd_pcm_substream *substream)
  460. {
  461. struct oxygen *chip = snd_pcm_substream_chip(substream);
  462. unsigned int channel = oxygen_substream_channel(substream);
  463. unsigned int channel_mask = 1 << channel;
  464. spin_lock_irq(&chip->reg_lock);
  465. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  466. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  467. chip->interrupt_mask |= channel_mask;
  468. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  469. spin_unlock_irq(&chip->reg_lock);
  470. return 0;
  471. }
  472. static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
  473. {
  474. struct oxygen *chip = snd_pcm_substream_chip(substream);
  475. struct snd_pcm_substream *s;
  476. unsigned int mask = 0;
  477. int pausing;
  478. switch (cmd) {
  479. case SNDRV_PCM_TRIGGER_STOP:
  480. case SNDRV_PCM_TRIGGER_START:
  481. case SNDRV_PCM_TRIGGER_SUSPEND:
  482. pausing = 0;
  483. break;
  484. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  485. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  486. pausing = 1;
  487. break;
  488. default:
  489. return -EINVAL;
  490. }
  491. snd_pcm_group_for_each_entry(s, substream) {
  492. if (snd_pcm_substream_chip(s) == chip) {
  493. mask |= 1 << oxygen_substream_channel(s);
  494. snd_pcm_trigger_done(s, substream);
  495. }
  496. }
  497. spin_lock(&chip->reg_lock);
  498. if (!pausing) {
  499. if (cmd == SNDRV_PCM_TRIGGER_START)
  500. chip->pcm_running |= mask;
  501. else
  502. chip->pcm_running &= ~mask;
  503. oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
  504. } else {
  505. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  506. oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  507. else
  508. oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  509. }
  510. spin_unlock(&chip->reg_lock);
  511. return 0;
  512. }
  513. static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
  514. {
  515. struct oxygen *chip = snd_pcm_substream_chip(substream);
  516. struct snd_pcm_runtime *runtime = substream->runtime;
  517. unsigned int channel = oxygen_substream_channel(substream);
  518. u32 curr_addr;
  519. /* no spinlock, this read should be atomic */
  520. curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
  521. return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
  522. }
  523. static struct snd_pcm_ops oxygen_rec_a_ops = {
  524. .open = oxygen_rec_a_open,
  525. .close = oxygen_close,
  526. .ioctl = snd_pcm_lib_ioctl,
  527. .hw_params = oxygen_rec_a_hw_params,
  528. .hw_free = oxygen_hw_free,
  529. .prepare = oxygen_prepare,
  530. .trigger = oxygen_trigger,
  531. .pointer = oxygen_pointer,
  532. };
  533. static struct snd_pcm_ops oxygen_rec_b_ops = {
  534. .open = oxygen_rec_b_open,
  535. .close = oxygen_close,
  536. .ioctl = snd_pcm_lib_ioctl,
  537. .hw_params = oxygen_rec_b_hw_params,
  538. .hw_free = oxygen_hw_free,
  539. .prepare = oxygen_prepare,
  540. .trigger = oxygen_trigger,
  541. .pointer = oxygen_pointer,
  542. };
  543. static struct snd_pcm_ops oxygen_rec_c_ops = {
  544. .open = oxygen_rec_c_open,
  545. .close = oxygen_close,
  546. .ioctl = snd_pcm_lib_ioctl,
  547. .hw_params = oxygen_rec_c_hw_params,
  548. .hw_free = oxygen_hw_free,
  549. .prepare = oxygen_prepare,
  550. .trigger = oxygen_trigger,
  551. .pointer = oxygen_pointer,
  552. };
  553. static struct snd_pcm_ops oxygen_spdif_ops = {
  554. .open = oxygen_spdif_open,
  555. .close = oxygen_close,
  556. .ioctl = snd_pcm_lib_ioctl,
  557. .hw_params = oxygen_spdif_hw_params,
  558. .hw_free = oxygen_spdif_hw_free,
  559. .prepare = oxygen_prepare,
  560. .trigger = oxygen_trigger,
  561. .pointer = oxygen_pointer,
  562. };
  563. static struct snd_pcm_ops oxygen_multich_ops = {
  564. .open = oxygen_multich_open,
  565. .close = oxygen_close,
  566. .ioctl = snd_pcm_lib_ioctl,
  567. .hw_params = oxygen_multich_hw_params,
  568. .hw_free = oxygen_hw_free,
  569. .prepare = oxygen_prepare,
  570. .trigger = oxygen_trigger,
  571. .pointer = oxygen_pointer,
  572. };
  573. static struct snd_pcm_ops oxygen_ac97_ops = {
  574. .open = oxygen_ac97_open,
  575. .close = oxygen_close,
  576. .ioctl = snd_pcm_lib_ioctl,
  577. .hw_params = oxygen_hw_params,
  578. .hw_free = oxygen_hw_free,
  579. .prepare = oxygen_prepare,
  580. .trigger = oxygen_trigger,
  581. .pointer = oxygen_pointer,
  582. };
  583. static void oxygen_pcm_free(struct snd_pcm *pcm)
  584. {
  585. snd_pcm_lib_preallocate_free_for_all(pcm);
  586. }
  587. int oxygen_pcm_init(struct oxygen *chip)
  588. {
  589. struct snd_pcm *pcm;
  590. int outs, ins;
  591. int err;
  592. outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
  593. ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
  594. CAPTURE_0_FROM_I2S_2));
  595. if (outs | ins) {
  596. err = snd_pcm_new(chip->card, "Multichannel",
  597. 0, outs, ins, &pcm);
  598. if (err < 0)
  599. return err;
  600. if (outs)
  601. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  602. &oxygen_multich_ops);
  603. if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
  604. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  605. &oxygen_rec_a_ops);
  606. else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
  607. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  608. &oxygen_rec_b_ops);
  609. pcm->private_data = chip;
  610. pcm->private_free = oxygen_pcm_free;
  611. strcpy(pcm->name, "Multichannel");
  612. if (outs)
  613. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
  614. SNDRV_DMA_TYPE_DEV,
  615. snd_dma_pci_data(chip->pci),
  616. DEFAULT_BUFFER_BYTES_MULTICH,
  617. BUFFER_BYTES_MAX_MULTICH);
  618. if (ins)
  619. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
  620. SNDRV_DMA_TYPE_DEV,
  621. snd_dma_pci_data(chip->pci),
  622. DEFAULT_BUFFER_BYTES,
  623. BUFFER_BYTES_MAX);
  624. }
  625. outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
  626. ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
  627. if (outs | ins) {
  628. err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
  629. if (err < 0)
  630. return err;
  631. if (outs)
  632. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  633. &oxygen_spdif_ops);
  634. if (ins)
  635. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  636. &oxygen_rec_c_ops);
  637. pcm->private_data = chip;
  638. pcm->private_free = oxygen_pcm_free;
  639. strcpy(pcm->name, "Digital");
  640. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  641. snd_dma_pci_data(chip->pci),
  642. DEFAULT_BUFFER_BYTES,
  643. BUFFER_BYTES_MAX);
  644. }
  645. if (chip->has_ac97_1) {
  646. outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
  647. ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
  648. } else {
  649. outs = 0;
  650. ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
  651. }
  652. if (outs | ins) {
  653. err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
  654. 2, outs, ins, &pcm);
  655. if (err < 0)
  656. return err;
  657. if (outs) {
  658. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  659. &oxygen_ac97_ops);
  660. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  661. OXYGEN_REC_B_ROUTE_AC97_1,
  662. OXYGEN_REC_B_ROUTE_MASK);
  663. }
  664. if (ins)
  665. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  666. &oxygen_rec_b_ops);
  667. pcm->private_data = chip;
  668. pcm->private_free = oxygen_pcm_free;
  669. strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
  670. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  671. snd_dma_pci_data(chip->pci),
  672. DEFAULT_BUFFER_BYTES,
  673. BUFFER_BYTES_MAX);
  674. }
  675. return 0;
  676. }