dsp_spos.c 54 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License as published by
  4. * the Free Software Foundation; either version 2 of the License, or
  5. * (at your option) any later version.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  15. *
  16. */
  17. /*
  18. * 2002-07 Benny Sjostrand benny@hostmobility.com
  19. */
  20. #include <asm/io.h>
  21. #include <linux/delay.h>
  22. #include <linux/pm.h>
  23. #include <linux/init.h>
  24. #include <linux/slab.h>
  25. #include <linux/vmalloc.h>
  26. #include <linux/mutex.h>
  27. #include <sound/core.h>
  28. #include <sound/control.h>
  29. #include <sound/info.h>
  30. #include <sound/asoundef.h>
  31. #include <sound/cs46xx.h>
  32. #include "cs46xx_lib.h"
  33. #include "dsp_spos.h"
  34. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  35. struct dsp_scb_descriptor * fg_entry);
  36. static enum wide_opcode wide_opcodes[] = {
  37. WIDE_FOR_BEGIN_LOOP,
  38. WIDE_FOR_BEGIN_LOOP2,
  39. WIDE_COND_GOTO_ADDR,
  40. WIDE_COND_GOTO_CALL,
  41. WIDE_TBEQ_COND_GOTO_ADDR,
  42. WIDE_TBEQ_COND_CALL_ADDR,
  43. WIDE_TBEQ_NCOND_GOTO_ADDR,
  44. WIDE_TBEQ_NCOND_CALL_ADDR,
  45. WIDE_TBEQ_COND_GOTO1_ADDR,
  46. WIDE_TBEQ_COND_CALL1_ADDR,
  47. WIDE_TBEQ_NCOND_GOTOI_ADDR,
  48. WIDE_TBEQ_NCOND_CALL1_ADDR
  49. };
  50. static int shadow_and_reallocate_code (struct snd_cs46xx * chip, u32 * data, u32 size,
  51. u32 overlay_begin_address)
  52. {
  53. unsigned int i = 0, j, nreallocated = 0;
  54. u32 hival,loval,address;
  55. u32 mop_operands,mop_type,wide_op;
  56. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  57. if (snd_BUG_ON(size %2))
  58. return -EINVAL;
  59. while (i < size) {
  60. loval = data[i++];
  61. hival = data[i++];
  62. if (ins->code.offset > 0) {
  63. mop_operands = (hival >> 6) & 0x03fff;
  64. mop_type = mop_operands >> 10;
  65. /* check for wide type instruction */
  66. if (mop_type == 0 &&
  67. (mop_operands & WIDE_LADD_INSTR_MASK) == 0 &&
  68. (mop_operands & WIDE_INSTR_MASK) != 0) {
  69. wide_op = loval & 0x7f;
  70. for (j = 0;j < ARRAY_SIZE(wide_opcodes); ++j) {
  71. if (wide_opcodes[j] == wide_op) {
  72. /* need to reallocate instruction */
  73. address = (hival & 0x00FFF) << 5;
  74. address |= loval >> 15;
  75. snd_printdd("handle_wideop[1]: %05x:%05x addr %04x\n",hival,loval,address);
  76. if ( !(address & 0x8000) ) {
  77. address += (ins->code.offset / 2) - overlay_begin_address;
  78. } else {
  79. snd_printdd("handle_wideop[1]: ROM symbol not reallocated\n");
  80. }
  81. hival &= 0xFF000;
  82. loval &= 0x07FFF;
  83. hival |= ( (address >> 5) & 0x00FFF);
  84. loval |= ( (address << 15) & 0xF8000);
  85. address = (hival & 0x00FFF) << 5;
  86. address |= loval >> 15;
  87. snd_printdd("handle_wideop:[2] %05x:%05x addr %04x\n",hival,loval,address);
  88. nreallocated ++;
  89. } /* wide_opcodes[j] == wide_op */
  90. } /* for */
  91. } /* mod_type == 0 ... */
  92. } /* ins->code.offset > 0 */
  93. ins->code.data[ins->code.size++] = loval;
  94. ins->code.data[ins->code.size++] = hival;
  95. }
  96. snd_printdd("dsp_spos: %d instructions reallocated\n",nreallocated);
  97. return nreallocated;
  98. }
  99. static struct dsp_segment_desc * get_segment_desc (struct dsp_module_desc * module, int seg_type)
  100. {
  101. int i;
  102. for (i = 0;i < module->nsegments; ++i) {
  103. if (module->segments[i].segment_type == seg_type) {
  104. return (module->segments + i);
  105. }
  106. }
  107. return NULL;
  108. };
  109. static int find_free_symbol_index (struct dsp_spos_instance * ins)
  110. {
  111. int index = ins->symbol_table.nsymbols,i;
  112. for (i = ins->symbol_table.highest_frag_index; i < ins->symbol_table.nsymbols; ++i) {
  113. if (ins->symbol_table.symbols[i].deleted) {
  114. index = i;
  115. break;
  116. }
  117. }
  118. return index;
  119. }
  120. static int add_symbols (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  121. {
  122. int i;
  123. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  124. if (module->symbol_table.nsymbols > 0) {
  125. if (!strcmp(module->symbol_table.symbols[0].symbol_name, "OVERLAYBEGINADDRESS") &&
  126. module->symbol_table.symbols[0].symbol_type == SYMBOL_CONSTANT ) {
  127. module->overlay_begin_address = module->symbol_table.symbols[0].address;
  128. }
  129. }
  130. for (i = 0;i < module->symbol_table.nsymbols; ++i) {
  131. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  132. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  133. return -ENOMEM;
  134. }
  135. if (cs46xx_dsp_lookup_symbol(chip,
  136. module->symbol_table.symbols[i].symbol_name,
  137. module->symbol_table.symbols[i].symbol_type) == NULL) {
  138. ins->symbol_table.symbols[ins->symbol_table.nsymbols] = module->symbol_table.symbols[i];
  139. ins->symbol_table.symbols[ins->symbol_table.nsymbols].address += ((ins->code.offset / 2) - module->overlay_begin_address);
  140. ins->symbol_table.symbols[ins->symbol_table.nsymbols].module = module;
  141. ins->symbol_table.symbols[ins->symbol_table.nsymbols].deleted = 0;
  142. if (ins->symbol_table.nsymbols > ins->symbol_table.highest_frag_index)
  143. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  144. ins->symbol_table.nsymbols++;
  145. } else {
  146. /* if (0) printk ("dsp_spos: symbol <%s> duplicated, probably nothing wrong with that (Cirrus?)\n",
  147. module->symbol_table.symbols[i].symbol_name); */
  148. }
  149. }
  150. return 0;
  151. }
  152. static struct dsp_symbol_entry *
  153. add_symbol (struct snd_cs46xx * chip, char * symbol_name, u32 address, int type)
  154. {
  155. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  156. struct dsp_symbol_entry * symbol = NULL;
  157. int index;
  158. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  159. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  160. return NULL;
  161. }
  162. if (cs46xx_dsp_lookup_symbol(chip,
  163. symbol_name,
  164. type) != NULL) {
  165. snd_printk(KERN_ERR "dsp_spos: symbol <%s> duplicated\n", symbol_name);
  166. return NULL;
  167. }
  168. index = find_free_symbol_index (ins);
  169. strcpy (ins->symbol_table.symbols[index].symbol_name, symbol_name);
  170. ins->symbol_table.symbols[index].address = address;
  171. ins->symbol_table.symbols[index].symbol_type = type;
  172. ins->symbol_table.symbols[index].module = NULL;
  173. ins->symbol_table.symbols[index].deleted = 0;
  174. symbol = (ins->symbol_table.symbols + index);
  175. if (index > ins->symbol_table.highest_frag_index)
  176. ins->symbol_table.highest_frag_index = index;
  177. if (index == ins->symbol_table.nsymbols)
  178. ins->symbol_table.nsymbols++; /* no frag. in list */
  179. return symbol;
  180. }
  181. struct dsp_spos_instance *cs46xx_dsp_spos_create (struct snd_cs46xx * chip)
  182. {
  183. struct dsp_spos_instance * ins = kzalloc(sizeof(struct dsp_spos_instance), GFP_KERNEL);
  184. if (ins == NULL)
  185. return NULL;
  186. /* better to use vmalloc for this big table */
  187. ins->symbol_table.nsymbols = 0;
  188. ins->symbol_table.symbols = vmalloc(sizeof(struct dsp_symbol_entry) *
  189. DSP_MAX_SYMBOLS);
  190. ins->symbol_table.highest_frag_index = 0;
  191. if (ins->symbol_table.symbols == NULL) {
  192. cs46xx_dsp_spos_destroy(chip);
  193. goto error;
  194. }
  195. ins->code.offset = 0;
  196. ins->code.size = 0;
  197. ins->code.data = kmalloc(DSP_CODE_BYTE_SIZE, GFP_KERNEL);
  198. if (ins->code.data == NULL) {
  199. cs46xx_dsp_spos_destroy(chip);
  200. goto error;
  201. }
  202. ins->nscb = 0;
  203. ins->ntask = 0;
  204. ins->nmodules = 0;
  205. ins->modules = kmalloc(sizeof(struct dsp_module_desc) * DSP_MAX_MODULES, GFP_KERNEL);
  206. if (ins->modules == NULL) {
  207. cs46xx_dsp_spos_destroy(chip);
  208. goto error;
  209. }
  210. /* default SPDIF input sample rate
  211. to 48000 khz */
  212. ins->spdif_in_sample_rate = 48000;
  213. /* maximize volume */
  214. ins->dac_volume_right = 0x8000;
  215. ins->dac_volume_left = 0x8000;
  216. ins->spdif_input_volume_right = 0x8000;
  217. ins->spdif_input_volume_left = 0x8000;
  218. /* set left and right validity bits and
  219. default channel status */
  220. ins->spdif_csuv_default =
  221. ins->spdif_csuv_stream =
  222. /* byte 0 */ ((unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF & 0xff)) << 24) |
  223. /* byte 1 */ ((unsigned int)_wrap_all_bits( ((SNDRV_PCM_DEFAULT_CON_SPDIF >> 8) & 0xff)) << 16) |
  224. /* byte 3 */ (unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF >> 24) & 0xff) |
  225. /* left and right validity bits */ (1 << 13) | (1 << 12);
  226. return ins;
  227. error:
  228. kfree(ins);
  229. return NULL;
  230. }
  231. void cs46xx_dsp_spos_destroy (struct snd_cs46xx * chip)
  232. {
  233. int i;
  234. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  235. if (snd_BUG_ON(!ins))
  236. return;
  237. mutex_lock(&chip->spos_mutex);
  238. for (i = 0; i < ins->nscb; ++i) {
  239. if (ins->scbs[i].deleted) continue;
  240. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  241. }
  242. kfree(ins->code.data);
  243. vfree(ins->symbol_table.symbols);
  244. kfree(ins->modules);
  245. kfree(ins);
  246. mutex_unlock(&chip->spos_mutex);
  247. }
  248. static int dsp_load_parameter(struct snd_cs46xx *chip,
  249. struct dsp_segment_desc *parameter)
  250. {
  251. u32 doffset, dsize;
  252. if (!parameter) {
  253. snd_printdd("dsp_spos: module got no parameter segment\n");
  254. return 0;
  255. }
  256. doffset = (parameter->offset * 4 + DSP_PARAMETER_BYTE_OFFSET);
  257. dsize = parameter->size * 4;
  258. snd_printdd("dsp_spos: "
  259. "downloading parameter data to chip (%08x-%08x)\n",
  260. doffset,doffset + dsize);
  261. if (snd_cs46xx_download (chip, parameter->data, doffset, dsize)) {
  262. snd_printk(KERN_ERR "dsp_spos: "
  263. "failed to download parameter data to DSP\n");
  264. return -EINVAL;
  265. }
  266. return 0;
  267. }
  268. static int dsp_load_sample(struct snd_cs46xx *chip,
  269. struct dsp_segment_desc *sample)
  270. {
  271. u32 doffset, dsize;
  272. if (!sample) {
  273. snd_printdd("dsp_spos: module got no sample segment\n");
  274. return 0;
  275. }
  276. doffset = (sample->offset * 4 + DSP_SAMPLE_BYTE_OFFSET);
  277. dsize = sample->size * 4;
  278. snd_printdd("dsp_spos: downloading sample data to chip (%08x-%08x)\n",
  279. doffset,doffset + dsize);
  280. if (snd_cs46xx_download (chip,sample->data,doffset,dsize)) {
  281. snd_printk(KERN_ERR "dsp_spos: failed to sample data to DSP\n");
  282. return -EINVAL;
  283. }
  284. return 0;
  285. }
  286. int cs46xx_dsp_load_module (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  287. {
  288. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  289. struct dsp_segment_desc * code = get_segment_desc (module,SEGTYPE_SP_PROGRAM);
  290. u32 doffset, dsize;
  291. int err;
  292. if (ins->nmodules == DSP_MAX_MODULES - 1) {
  293. snd_printk(KERN_ERR "dsp_spos: to many modules loaded into DSP\n");
  294. return -ENOMEM;
  295. }
  296. snd_printdd("dsp_spos: loading module %s into DSP\n", module->module_name);
  297. if (ins->nmodules == 0) {
  298. snd_printdd("dsp_spos: clearing parameter area\n");
  299. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET, DSP_PARAMETER_BYTE_SIZE);
  300. }
  301. err = dsp_load_parameter(chip, get_segment_desc(module,
  302. SEGTYPE_SP_PARAMETER));
  303. if (err < 0)
  304. return err;
  305. if (ins->nmodules == 0) {
  306. snd_printdd("dsp_spos: clearing sample area\n");
  307. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET, DSP_SAMPLE_BYTE_SIZE);
  308. }
  309. err = dsp_load_sample(chip, get_segment_desc(module,
  310. SEGTYPE_SP_SAMPLE));
  311. if (err < 0)
  312. return err;
  313. if (ins->nmodules == 0) {
  314. snd_printdd("dsp_spos: clearing code area\n");
  315. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  316. }
  317. if (code == NULL) {
  318. snd_printdd("dsp_spos: module got no code segment\n");
  319. } else {
  320. if (ins->code.offset + code->size > DSP_CODE_BYTE_SIZE) {
  321. snd_printk(KERN_ERR "dsp_spos: no space available in DSP\n");
  322. return -ENOMEM;
  323. }
  324. module->load_address = ins->code.offset;
  325. module->overlay_begin_address = 0x000;
  326. /* if module has a code segment it must have
  327. symbol table */
  328. if (snd_BUG_ON(!module->symbol_table.symbols))
  329. return -ENOMEM;
  330. if (add_symbols(chip,module)) {
  331. snd_printk(KERN_ERR "dsp_spos: failed to load symbol table\n");
  332. return -ENOMEM;
  333. }
  334. doffset = (code->offset * 4 + ins->code.offset * 4 + DSP_CODE_BYTE_OFFSET);
  335. dsize = code->size * 4;
  336. snd_printdd("dsp_spos: downloading code to chip (%08x-%08x)\n",
  337. doffset,doffset + dsize);
  338. module->nfixups = shadow_and_reallocate_code(chip,code->data,code->size,module->overlay_begin_address);
  339. if (snd_cs46xx_download (chip,(ins->code.data + ins->code.offset),doffset,dsize)) {
  340. snd_printk(KERN_ERR "dsp_spos: failed to download code to DSP\n");
  341. return -EINVAL;
  342. }
  343. ins->code.offset += code->size;
  344. }
  345. /* NOTE: module segments and symbol table must be
  346. statically allocated. Case that module data is
  347. not generated by the ospparser */
  348. ins->modules[ins->nmodules] = *module;
  349. ins->nmodules++;
  350. return 0;
  351. }
  352. struct dsp_symbol_entry *
  353. cs46xx_dsp_lookup_symbol (struct snd_cs46xx * chip, char * symbol_name, int symbol_type)
  354. {
  355. int i;
  356. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  357. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  358. if (ins->symbol_table.symbols[i].deleted)
  359. continue;
  360. if (!strcmp(ins->symbol_table.symbols[i].symbol_name,symbol_name) &&
  361. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  362. return (ins->symbol_table.symbols + i);
  363. }
  364. }
  365. #if 0
  366. printk ("dsp_spos: symbol <%s> type %02x not found\n",
  367. symbol_name,symbol_type);
  368. #endif
  369. return NULL;
  370. }
  371. #ifdef CONFIG_PROC_FS
  372. static struct dsp_symbol_entry *
  373. cs46xx_dsp_lookup_symbol_addr (struct snd_cs46xx * chip, u32 address, int symbol_type)
  374. {
  375. int i;
  376. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  377. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  378. if (ins->symbol_table.symbols[i].deleted)
  379. continue;
  380. if (ins->symbol_table.symbols[i].address == address &&
  381. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  382. return (ins->symbol_table.symbols + i);
  383. }
  384. }
  385. return NULL;
  386. }
  387. static void cs46xx_dsp_proc_symbol_table_read (struct snd_info_entry *entry,
  388. struct snd_info_buffer *buffer)
  389. {
  390. struct snd_cs46xx *chip = entry->private_data;
  391. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  392. int i;
  393. snd_iprintf(buffer, "SYMBOLS:\n");
  394. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  395. char *module_str = "system";
  396. if (ins->symbol_table.symbols[i].deleted)
  397. continue;
  398. if (ins->symbol_table.symbols[i].module != NULL) {
  399. module_str = ins->symbol_table.symbols[i].module->module_name;
  400. }
  401. snd_iprintf(buffer, "%04X <%02X> %s [%s]\n",
  402. ins->symbol_table.symbols[i].address,
  403. ins->symbol_table.symbols[i].symbol_type,
  404. ins->symbol_table.symbols[i].symbol_name,
  405. module_str);
  406. }
  407. }
  408. static void cs46xx_dsp_proc_modules_read (struct snd_info_entry *entry,
  409. struct snd_info_buffer *buffer)
  410. {
  411. struct snd_cs46xx *chip = entry->private_data;
  412. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  413. int i,j;
  414. mutex_lock(&chip->spos_mutex);
  415. snd_iprintf(buffer, "MODULES:\n");
  416. for ( i = 0; i < ins->nmodules; ++i ) {
  417. snd_iprintf(buffer, "\n%s:\n", ins->modules[i].module_name);
  418. snd_iprintf(buffer, " %d symbols\n", ins->modules[i].symbol_table.nsymbols);
  419. snd_iprintf(buffer, " %d fixups\n", ins->modules[i].nfixups);
  420. for (j = 0; j < ins->modules[i].nsegments; ++ j) {
  421. struct dsp_segment_desc * desc = (ins->modules[i].segments + j);
  422. snd_iprintf(buffer, " segment %02x offset %08x size %08x\n",
  423. desc->segment_type,desc->offset, desc->size);
  424. }
  425. }
  426. mutex_unlock(&chip->spos_mutex);
  427. }
  428. static void cs46xx_dsp_proc_task_tree_read (struct snd_info_entry *entry,
  429. struct snd_info_buffer *buffer)
  430. {
  431. struct snd_cs46xx *chip = entry->private_data;
  432. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  433. int i, j, col;
  434. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  435. mutex_lock(&chip->spos_mutex);
  436. snd_iprintf(buffer, "TASK TREES:\n");
  437. for ( i = 0; i < ins->ntask; ++i) {
  438. snd_iprintf(buffer,"\n%04x %s:\n",ins->tasks[i].address,ins->tasks[i].task_name);
  439. for (col = 0,j = 0;j < ins->tasks[i].size; j++,col++) {
  440. u32 val;
  441. if (col == 4) {
  442. snd_iprintf(buffer,"\n");
  443. col = 0;
  444. }
  445. val = readl(dst + (ins->tasks[i].address + j) * sizeof(u32));
  446. snd_iprintf(buffer,"%08x ",val);
  447. }
  448. }
  449. snd_iprintf(buffer,"\n");
  450. mutex_unlock(&chip->spos_mutex);
  451. }
  452. static void cs46xx_dsp_proc_scb_read (struct snd_info_entry *entry,
  453. struct snd_info_buffer *buffer)
  454. {
  455. struct snd_cs46xx *chip = entry->private_data;
  456. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  457. int i;
  458. mutex_lock(&chip->spos_mutex);
  459. snd_iprintf(buffer, "SCB's:\n");
  460. for ( i = 0; i < ins->nscb; ++i) {
  461. if (ins->scbs[i].deleted)
  462. continue;
  463. snd_iprintf(buffer,"\n%04x %s:\n\n",ins->scbs[i].address,ins->scbs[i].scb_name);
  464. if (ins->scbs[i].parent_scb_ptr != NULL) {
  465. snd_iprintf(buffer,"parent [%s:%04x] ",
  466. ins->scbs[i].parent_scb_ptr->scb_name,
  467. ins->scbs[i].parent_scb_ptr->address);
  468. } else snd_iprintf(buffer,"parent [none] ");
  469. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  470. ins->scbs[i].sub_list_ptr->scb_name,
  471. ins->scbs[i].sub_list_ptr->address,
  472. ins->scbs[i].next_scb_ptr->scb_name,
  473. ins->scbs[i].next_scb_ptr->address,
  474. ins->scbs[i].task_entry->symbol_name,
  475. ins->scbs[i].task_entry->address);
  476. }
  477. snd_iprintf(buffer,"\n");
  478. mutex_unlock(&chip->spos_mutex);
  479. }
  480. static void cs46xx_dsp_proc_parameter_dump_read (struct snd_info_entry *entry,
  481. struct snd_info_buffer *buffer)
  482. {
  483. struct snd_cs46xx *chip = entry->private_data;
  484. /*struct dsp_spos_instance * ins = chip->dsp_spos_instance; */
  485. unsigned int i, col = 0;
  486. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  487. struct dsp_symbol_entry * symbol;
  488. for (i = 0;i < DSP_PARAMETER_BYTE_SIZE; i += sizeof(u32),col ++) {
  489. if (col == 4) {
  490. snd_iprintf(buffer,"\n");
  491. col = 0;
  492. }
  493. if ( (symbol = cs46xx_dsp_lookup_symbol_addr (chip,i / sizeof(u32), SYMBOL_PARAMETER)) != NULL) {
  494. col = 0;
  495. snd_iprintf (buffer,"\n%s:\n",symbol->symbol_name);
  496. }
  497. if (col == 0) {
  498. snd_iprintf(buffer, "%04X ", i / (unsigned int)sizeof(u32));
  499. }
  500. snd_iprintf(buffer,"%08X ",readl(dst + i));
  501. }
  502. }
  503. static void cs46xx_dsp_proc_sample_dump_read (struct snd_info_entry *entry,
  504. struct snd_info_buffer *buffer)
  505. {
  506. struct snd_cs46xx *chip = entry->private_data;
  507. int i,col = 0;
  508. void __iomem *dst = chip->region.idx[2].remap_addr;
  509. snd_iprintf(buffer,"PCMREADER:\n");
  510. for (i = PCM_READER_BUF1;i < PCM_READER_BUF1 + 0x30; i += sizeof(u32),col ++) {
  511. if (col == 4) {
  512. snd_iprintf(buffer,"\n");
  513. col = 0;
  514. }
  515. if (col == 0) {
  516. snd_iprintf(buffer, "%04X ",i);
  517. }
  518. snd_iprintf(buffer,"%08X ",readl(dst + i));
  519. }
  520. snd_iprintf(buffer,"\nMIX_SAMPLE_BUF1:\n");
  521. col = 0;
  522. for (i = MIX_SAMPLE_BUF1;i < MIX_SAMPLE_BUF1 + 0x40; i += sizeof(u32),col ++) {
  523. if (col == 4) {
  524. snd_iprintf(buffer,"\n");
  525. col = 0;
  526. }
  527. if (col == 0) {
  528. snd_iprintf(buffer, "%04X ",i);
  529. }
  530. snd_iprintf(buffer,"%08X ",readl(dst + i));
  531. }
  532. snd_iprintf(buffer,"\nSRC_TASK_SCB1:\n");
  533. col = 0;
  534. for (i = 0x2480 ; i < 0x2480 + 0x40 ; i += sizeof(u32),col ++) {
  535. if (col == 4) {
  536. snd_iprintf(buffer,"\n");
  537. col = 0;
  538. }
  539. if (col == 0) {
  540. snd_iprintf(buffer, "%04X ",i);
  541. }
  542. snd_iprintf(buffer,"%08X ",readl(dst + i));
  543. }
  544. snd_iprintf(buffer,"\nSPDIFO_BUFFER:\n");
  545. col = 0;
  546. for (i = SPDIFO_IP_OUTPUT_BUFFER1;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x30; i += sizeof(u32),col ++) {
  547. if (col == 4) {
  548. snd_iprintf(buffer,"\n");
  549. col = 0;
  550. }
  551. if (col == 0) {
  552. snd_iprintf(buffer, "%04X ",i);
  553. }
  554. snd_iprintf(buffer,"%08X ",readl(dst + i));
  555. }
  556. snd_iprintf(buffer,"\n...\n");
  557. col = 0;
  558. for (i = SPDIFO_IP_OUTPUT_BUFFER1+0xD0;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x110; i += sizeof(u32),col ++) {
  559. if (col == 4) {
  560. snd_iprintf(buffer,"\n");
  561. col = 0;
  562. }
  563. if (col == 0) {
  564. snd_iprintf(buffer, "%04X ",i);
  565. }
  566. snd_iprintf(buffer,"%08X ",readl(dst + i));
  567. }
  568. snd_iprintf(buffer,"\nOUTPUT_SNOOP:\n");
  569. col = 0;
  570. for (i = OUTPUT_SNOOP_BUFFER;i < OUTPUT_SNOOP_BUFFER + 0x40; i += sizeof(u32),col ++) {
  571. if (col == 4) {
  572. snd_iprintf(buffer,"\n");
  573. col = 0;
  574. }
  575. if (col == 0) {
  576. snd_iprintf(buffer, "%04X ",i);
  577. }
  578. snd_iprintf(buffer,"%08X ",readl(dst + i));
  579. }
  580. snd_iprintf(buffer,"\nCODEC_INPUT_BUF1: \n");
  581. col = 0;
  582. for (i = CODEC_INPUT_BUF1;i < CODEC_INPUT_BUF1 + 0x40; i += sizeof(u32),col ++) {
  583. if (col == 4) {
  584. snd_iprintf(buffer,"\n");
  585. col = 0;
  586. }
  587. if (col == 0) {
  588. snd_iprintf(buffer, "%04X ",i);
  589. }
  590. snd_iprintf(buffer,"%08X ",readl(dst + i));
  591. }
  592. #if 0
  593. snd_iprintf(buffer,"\nWRITE_BACK_BUF1: \n");
  594. col = 0;
  595. for (i = WRITE_BACK_BUF1;i < WRITE_BACK_BUF1 + 0x40; i += sizeof(u32),col ++) {
  596. if (col == 4) {
  597. snd_iprintf(buffer,"\n");
  598. col = 0;
  599. }
  600. if (col == 0) {
  601. snd_iprintf(buffer, "%04X ",i);
  602. }
  603. snd_iprintf(buffer,"%08X ",readl(dst + i));
  604. }
  605. #endif
  606. snd_iprintf(buffer,"\nSPDIFI_IP_OUTPUT_BUFFER1: \n");
  607. col = 0;
  608. for (i = SPDIFI_IP_OUTPUT_BUFFER1;i < SPDIFI_IP_OUTPUT_BUFFER1 + 0x80; i += sizeof(u32),col ++) {
  609. if (col == 4) {
  610. snd_iprintf(buffer,"\n");
  611. col = 0;
  612. }
  613. if (col == 0) {
  614. snd_iprintf(buffer, "%04X ",i);
  615. }
  616. snd_iprintf(buffer,"%08X ",readl(dst + i));
  617. }
  618. snd_iprintf(buffer,"\n");
  619. }
  620. int cs46xx_dsp_proc_init (struct snd_card *card, struct snd_cs46xx *chip)
  621. {
  622. struct snd_info_entry *entry;
  623. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  624. int i;
  625. ins->snd_card = card;
  626. if ((entry = snd_info_create_card_entry(card, "dsp", card->proc_root)) != NULL) {
  627. entry->content = SNDRV_INFO_CONTENT_TEXT;
  628. entry->mode = S_IFDIR | S_IRUGO | S_IXUGO;
  629. if (snd_info_register(entry) < 0) {
  630. snd_info_free_entry(entry);
  631. entry = NULL;
  632. }
  633. }
  634. ins->proc_dsp_dir = entry;
  635. if (!ins->proc_dsp_dir)
  636. return -ENOMEM;
  637. if ((entry = snd_info_create_card_entry(card, "spos_symbols", ins->proc_dsp_dir)) != NULL) {
  638. entry->content = SNDRV_INFO_CONTENT_TEXT;
  639. entry->private_data = chip;
  640. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  641. entry->c.text.read = cs46xx_dsp_proc_symbol_table_read;
  642. if (snd_info_register(entry) < 0) {
  643. snd_info_free_entry(entry);
  644. entry = NULL;
  645. }
  646. }
  647. ins->proc_sym_info_entry = entry;
  648. if ((entry = snd_info_create_card_entry(card, "spos_modules", ins->proc_dsp_dir)) != NULL) {
  649. entry->content = SNDRV_INFO_CONTENT_TEXT;
  650. entry->private_data = chip;
  651. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  652. entry->c.text.read = cs46xx_dsp_proc_modules_read;
  653. if (snd_info_register(entry) < 0) {
  654. snd_info_free_entry(entry);
  655. entry = NULL;
  656. }
  657. }
  658. ins->proc_modules_info_entry = entry;
  659. if ((entry = snd_info_create_card_entry(card, "parameter", ins->proc_dsp_dir)) != NULL) {
  660. entry->content = SNDRV_INFO_CONTENT_TEXT;
  661. entry->private_data = chip;
  662. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  663. entry->c.text.read = cs46xx_dsp_proc_parameter_dump_read;
  664. if (snd_info_register(entry) < 0) {
  665. snd_info_free_entry(entry);
  666. entry = NULL;
  667. }
  668. }
  669. ins->proc_parameter_dump_info_entry = entry;
  670. if ((entry = snd_info_create_card_entry(card, "sample", ins->proc_dsp_dir)) != NULL) {
  671. entry->content = SNDRV_INFO_CONTENT_TEXT;
  672. entry->private_data = chip;
  673. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  674. entry->c.text.read = cs46xx_dsp_proc_sample_dump_read;
  675. if (snd_info_register(entry) < 0) {
  676. snd_info_free_entry(entry);
  677. entry = NULL;
  678. }
  679. }
  680. ins->proc_sample_dump_info_entry = entry;
  681. if ((entry = snd_info_create_card_entry(card, "task_tree", ins->proc_dsp_dir)) != NULL) {
  682. entry->content = SNDRV_INFO_CONTENT_TEXT;
  683. entry->private_data = chip;
  684. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  685. entry->c.text.read = cs46xx_dsp_proc_task_tree_read;
  686. if (snd_info_register(entry) < 0) {
  687. snd_info_free_entry(entry);
  688. entry = NULL;
  689. }
  690. }
  691. ins->proc_task_info_entry = entry;
  692. if ((entry = snd_info_create_card_entry(card, "scb_info", ins->proc_dsp_dir)) != NULL) {
  693. entry->content = SNDRV_INFO_CONTENT_TEXT;
  694. entry->private_data = chip;
  695. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  696. entry->c.text.read = cs46xx_dsp_proc_scb_read;
  697. if (snd_info_register(entry) < 0) {
  698. snd_info_free_entry(entry);
  699. entry = NULL;
  700. }
  701. }
  702. ins->proc_scb_info_entry = entry;
  703. mutex_lock(&chip->spos_mutex);
  704. /* register/update SCB's entries on proc */
  705. for (i = 0; i < ins->nscb; ++i) {
  706. if (ins->scbs[i].deleted) continue;
  707. cs46xx_dsp_proc_register_scb_desc (chip, (ins->scbs + i));
  708. }
  709. mutex_unlock(&chip->spos_mutex);
  710. return 0;
  711. }
  712. int cs46xx_dsp_proc_done (struct snd_cs46xx *chip)
  713. {
  714. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  715. int i;
  716. snd_info_free_entry(ins->proc_sym_info_entry);
  717. ins->proc_sym_info_entry = NULL;
  718. snd_info_free_entry(ins->proc_modules_info_entry);
  719. ins->proc_modules_info_entry = NULL;
  720. snd_info_free_entry(ins->proc_parameter_dump_info_entry);
  721. ins->proc_parameter_dump_info_entry = NULL;
  722. snd_info_free_entry(ins->proc_sample_dump_info_entry);
  723. ins->proc_sample_dump_info_entry = NULL;
  724. snd_info_free_entry(ins->proc_scb_info_entry);
  725. ins->proc_scb_info_entry = NULL;
  726. snd_info_free_entry(ins->proc_task_info_entry);
  727. ins->proc_task_info_entry = NULL;
  728. mutex_lock(&chip->spos_mutex);
  729. for (i = 0; i < ins->nscb; ++i) {
  730. if (ins->scbs[i].deleted) continue;
  731. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  732. }
  733. mutex_unlock(&chip->spos_mutex);
  734. snd_info_free_entry(ins->proc_dsp_dir);
  735. ins->proc_dsp_dir = NULL;
  736. return 0;
  737. }
  738. #endif /* CONFIG_PROC_FS */
  739. static int debug_tree;
  740. static void _dsp_create_task_tree (struct snd_cs46xx *chip, u32 * task_data,
  741. u32 dest, int size)
  742. {
  743. void __iomem *spdst = chip->region.idx[1].remap_addr +
  744. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  745. int i;
  746. for (i = 0; i < size; ++i) {
  747. if (debug_tree) printk ("addr %p, val %08x\n",spdst,task_data[i]);
  748. writel(task_data[i],spdst);
  749. spdst += sizeof(u32);
  750. }
  751. }
  752. static int debug_scb;
  753. static void _dsp_create_scb (struct snd_cs46xx *chip, u32 * scb_data, u32 dest)
  754. {
  755. void __iomem *spdst = chip->region.idx[1].remap_addr +
  756. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  757. int i;
  758. for (i = 0; i < 0x10; ++i) {
  759. if (debug_scb) printk ("addr %p, val %08x\n",spdst,scb_data[i]);
  760. writel(scb_data[i],spdst);
  761. spdst += sizeof(u32);
  762. }
  763. }
  764. static int find_free_scb_index (struct dsp_spos_instance * ins)
  765. {
  766. int index = ins->nscb, i;
  767. for (i = ins->scb_highest_frag_index; i < ins->nscb; ++i) {
  768. if (ins->scbs[i].deleted) {
  769. index = i;
  770. break;
  771. }
  772. }
  773. return index;
  774. }
  775. static struct dsp_scb_descriptor * _map_scb (struct snd_cs46xx *chip, char * name, u32 dest)
  776. {
  777. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  778. struct dsp_scb_descriptor * desc = NULL;
  779. int index;
  780. if (ins->nscb == DSP_MAX_SCB_DESC - 1) {
  781. snd_printk(KERN_ERR "dsp_spos: got no place for other SCB\n");
  782. return NULL;
  783. }
  784. index = find_free_scb_index (ins);
  785. strcpy(ins->scbs[index].scb_name, name);
  786. ins->scbs[index].address = dest;
  787. ins->scbs[index].index = index;
  788. ins->scbs[index].proc_info = NULL;
  789. ins->scbs[index].ref_count = 1;
  790. ins->scbs[index].deleted = 0;
  791. spin_lock_init(&ins->scbs[index].lock);
  792. desc = (ins->scbs + index);
  793. ins->scbs[index].scb_symbol = add_symbol (chip, name, dest, SYMBOL_PARAMETER);
  794. if (index > ins->scb_highest_frag_index)
  795. ins->scb_highest_frag_index = index;
  796. if (index == ins->nscb)
  797. ins->nscb++;
  798. return desc;
  799. }
  800. static struct dsp_task_descriptor *
  801. _map_task_tree (struct snd_cs46xx *chip, char * name, u32 dest, u32 size)
  802. {
  803. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  804. struct dsp_task_descriptor * desc = NULL;
  805. if (ins->ntask == DSP_MAX_TASK_DESC - 1) {
  806. snd_printk(KERN_ERR "dsp_spos: got no place for other TASK\n");
  807. return NULL;
  808. }
  809. if (name)
  810. strcpy(ins->tasks[ins->ntask].task_name, name);
  811. else
  812. strcpy(ins->tasks[ins->ntask].task_name, "(NULL)");
  813. ins->tasks[ins->ntask].address = dest;
  814. ins->tasks[ins->ntask].size = size;
  815. /* quick find in list */
  816. ins->tasks[ins->ntask].index = ins->ntask;
  817. desc = (ins->tasks + ins->ntask);
  818. ins->ntask++;
  819. if (name)
  820. add_symbol (chip,name,dest,SYMBOL_PARAMETER);
  821. return desc;
  822. }
  823. struct dsp_scb_descriptor *
  824. cs46xx_dsp_create_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest)
  825. {
  826. struct dsp_scb_descriptor * desc;
  827. desc = _map_scb (chip,name,dest);
  828. if (desc) {
  829. desc->data = scb_data;
  830. _dsp_create_scb(chip,scb_data,dest);
  831. } else {
  832. snd_printk(KERN_ERR "dsp_spos: failed to map SCB\n");
  833. }
  834. return desc;
  835. }
  836. static struct dsp_task_descriptor *
  837. cs46xx_dsp_create_task_tree (struct snd_cs46xx *chip, char * name, u32 * task_data,
  838. u32 dest, int size)
  839. {
  840. struct dsp_task_descriptor * desc;
  841. desc = _map_task_tree (chip,name,dest,size);
  842. if (desc) {
  843. desc->data = task_data;
  844. _dsp_create_task_tree(chip,task_data,dest,size);
  845. } else {
  846. snd_printk(KERN_ERR "dsp_spos: failed to map TASK\n");
  847. }
  848. return desc;
  849. }
  850. int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip)
  851. {
  852. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  853. struct dsp_symbol_entry * fg_task_tree_header_code;
  854. struct dsp_symbol_entry * task_tree_header_code;
  855. struct dsp_symbol_entry * task_tree_thread;
  856. struct dsp_symbol_entry * null_algorithm;
  857. struct dsp_symbol_entry * magic_snoop_task;
  858. struct dsp_scb_descriptor * timing_master_scb;
  859. struct dsp_scb_descriptor * codec_out_scb;
  860. struct dsp_scb_descriptor * codec_in_scb;
  861. struct dsp_scb_descriptor * src_task_scb;
  862. struct dsp_scb_descriptor * master_mix_scb;
  863. struct dsp_scb_descriptor * rear_mix_scb;
  864. struct dsp_scb_descriptor * record_mix_scb;
  865. struct dsp_scb_descriptor * write_back_scb;
  866. struct dsp_scb_descriptor * vari_decimate_scb;
  867. struct dsp_scb_descriptor * rear_codec_out_scb;
  868. struct dsp_scb_descriptor * clfe_codec_out_scb;
  869. struct dsp_scb_descriptor * magic_snoop_scb;
  870. int fifo_addr, fifo_span, valid_slots;
  871. static struct dsp_spos_control_block sposcb = {
  872. /* 0 */ HFG_TREE_SCB,HFG_STACK,
  873. /* 1 */ SPOSCB_ADDR,BG_TREE_SCB_ADDR,
  874. /* 2 */ DSP_SPOS_DC,0,
  875. /* 3 */ DSP_SPOS_DC,DSP_SPOS_DC,
  876. /* 4 */ 0,0,
  877. /* 5 */ DSP_SPOS_UU,0,
  878. /* 6 */ FG_TASK_HEADER_ADDR,0,
  879. /* 7 */ 0,0,
  880. /* 8 */ DSP_SPOS_UU,DSP_SPOS_DC,
  881. /* 9 */ 0,
  882. /* A */ 0,HFG_FIRST_EXECUTE_MODE,
  883. /* B */ DSP_SPOS_UU,DSP_SPOS_UU,
  884. /* C */ DSP_SPOS_DC_DC,
  885. /* D */ DSP_SPOS_DC_DC,
  886. /* E */ DSP_SPOS_DC_DC,
  887. /* F */ DSP_SPOS_DC_DC
  888. };
  889. cs46xx_dsp_create_task_tree(chip, "sposCB", (u32 *)&sposcb, SPOSCB_ADDR, 0x10);
  890. null_algorithm = cs46xx_dsp_lookup_symbol(chip, "NULLALGORITHM", SYMBOL_CODE);
  891. if (null_algorithm == NULL) {
  892. snd_printk(KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  893. return -EIO;
  894. }
  895. fg_task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "FGTASKTREEHEADERCODE", SYMBOL_CODE);
  896. if (fg_task_tree_header_code == NULL) {
  897. snd_printk(KERN_ERR "dsp_spos: symbol FGTASKTREEHEADERCODE not found\n");
  898. return -EIO;
  899. }
  900. task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "TASKTREEHEADERCODE", SYMBOL_CODE);
  901. if (task_tree_header_code == NULL) {
  902. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREEHEADERCODE not found\n");
  903. return -EIO;
  904. }
  905. task_tree_thread = cs46xx_dsp_lookup_symbol(chip, "TASKTREETHREAD", SYMBOL_CODE);
  906. if (task_tree_thread == NULL) {
  907. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREETHREAD not found\n");
  908. return -EIO;
  909. }
  910. magic_snoop_task = cs46xx_dsp_lookup_symbol(chip, "MAGICSNOOPTASK", SYMBOL_CODE);
  911. if (magic_snoop_task == NULL) {
  912. snd_printk(KERN_ERR "dsp_spos: symbol MAGICSNOOPTASK not found\n");
  913. return -EIO;
  914. }
  915. {
  916. /* create the null SCB */
  917. static struct dsp_generic_scb null_scb = {
  918. { 0, 0, 0, 0 },
  919. { 0, 0, 0, 0, 0 },
  920. NULL_SCB_ADDR, NULL_SCB_ADDR,
  921. 0, 0, 0, 0, 0,
  922. {
  923. 0,0,
  924. 0,0,
  925. }
  926. };
  927. null_scb.entry_point = null_algorithm->address;
  928. ins->the_null_scb = cs46xx_dsp_create_scb(chip, "nullSCB", (u32 *)&null_scb, NULL_SCB_ADDR);
  929. ins->the_null_scb->task_entry = null_algorithm;
  930. ins->the_null_scb->sub_list_ptr = ins->the_null_scb;
  931. ins->the_null_scb->next_scb_ptr = ins->the_null_scb;
  932. ins->the_null_scb->parent_scb_ptr = NULL;
  933. cs46xx_dsp_proc_register_scb_desc (chip,ins->the_null_scb);
  934. }
  935. {
  936. /* setup foreground task tree */
  937. static struct dsp_task_tree_control_block fg_task_tree_hdr = {
  938. { FG_TASK_HEADER_ADDR | (DSP_SPOS_DC << 0x10),
  939. DSP_SPOS_DC_DC,
  940. DSP_SPOS_DC_DC,
  941. 0x0000,DSP_SPOS_DC,
  942. DSP_SPOS_DC, DSP_SPOS_DC,
  943. DSP_SPOS_DC_DC,
  944. DSP_SPOS_DC_DC,
  945. DSP_SPOS_DC_DC,
  946. DSP_SPOS_DC,DSP_SPOS_DC },
  947. {
  948. BG_TREE_SCB_ADDR,TIMINGMASTER_SCB_ADDR,
  949. 0,
  950. FG_TASK_HEADER_ADDR + TCBData,
  951. },
  952. {
  953. 4,0,
  954. 1,0,
  955. 2,SPOSCB_ADDR + HFGFlags,
  956. 0,0,
  957. FG_TASK_HEADER_ADDR + TCBContextBlk,FG_STACK
  958. },
  959. {
  960. DSP_SPOS_DC,0,
  961. DSP_SPOS_DC,DSP_SPOS_DC,
  962. DSP_SPOS_DC,DSP_SPOS_DC,
  963. DSP_SPOS_DC,DSP_SPOS_DC,
  964. DSP_SPOS_DC,DSP_SPOS_DC,
  965. DSP_SPOS_DCDC,
  966. DSP_SPOS_UU,1,
  967. DSP_SPOS_DCDC,
  968. DSP_SPOS_DCDC,
  969. DSP_SPOS_DCDC,
  970. DSP_SPOS_DCDC,
  971. DSP_SPOS_DCDC,
  972. DSP_SPOS_DCDC,
  973. DSP_SPOS_DCDC,
  974. DSP_SPOS_DCDC,
  975. DSP_SPOS_DCDC,
  976. DSP_SPOS_DCDC,
  977. DSP_SPOS_DCDC,
  978. DSP_SPOS_DCDC,
  979. DSP_SPOS_DCDC,
  980. DSP_SPOS_DCDC,
  981. DSP_SPOS_DCDC,
  982. DSP_SPOS_DCDC,
  983. DSP_SPOS_DCDC,
  984. DSP_SPOS_DCDC,
  985. DSP_SPOS_DCDC,
  986. DSP_SPOS_DCDC,
  987. DSP_SPOS_DCDC,
  988. DSP_SPOS_DCDC,
  989. DSP_SPOS_DCDC,
  990. DSP_SPOS_DCDC,
  991. DSP_SPOS_DCDC,
  992. DSP_SPOS_DCDC,
  993. DSP_SPOS_DCDC,
  994. DSP_SPOS_DCDC
  995. },
  996. {
  997. FG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  998. 0,0
  999. }
  1000. };
  1001. fg_task_tree_hdr.links.entry_point = fg_task_tree_header_code->address;
  1002. fg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1003. cs46xx_dsp_create_task_tree(chip,"FGtaskTreeHdr",(u32 *)&fg_task_tree_hdr,FG_TASK_HEADER_ADDR,0x35);
  1004. }
  1005. {
  1006. /* setup foreground task tree */
  1007. static struct dsp_task_tree_control_block bg_task_tree_hdr = {
  1008. { DSP_SPOS_DC_DC,
  1009. DSP_SPOS_DC_DC,
  1010. DSP_SPOS_DC_DC,
  1011. DSP_SPOS_DC, DSP_SPOS_DC,
  1012. DSP_SPOS_DC, DSP_SPOS_DC,
  1013. DSP_SPOS_DC_DC,
  1014. DSP_SPOS_DC_DC,
  1015. DSP_SPOS_DC_DC,
  1016. DSP_SPOS_DC,DSP_SPOS_DC },
  1017. {
  1018. NULL_SCB_ADDR,NULL_SCB_ADDR, /* Set up the background to do nothing */
  1019. 0,
  1020. BG_TREE_SCB_ADDR + TCBData,
  1021. },
  1022. {
  1023. 9999,0,
  1024. 0,1,
  1025. 0,SPOSCB_ADDR + HFGFlags,
  1026. 0,0,
  1027. BG_TREE_SCB_ADDR + TCBContextBlk,BG_STACK
  1028. },
  1029. {
  1030. DSP_SPOS_DC,0,
  1031. DSP_SPOS_DC,DSP_SPOS_DC,
  1032. DSP_SPOS_DC,DSP_SPOS_DC,
  1033. DSP_SPOS_DC,DSP_SPOS_DC,
  1034. DSP_SPOS_DC,DSP_SPOS_DC,
  1035. DSP_SPOS_DCDC,
  1036. DSP_SPOS_UU,1,
  1037. DSP_SPOS_DCDC,
  1038. DSP_SPOS_DCDC,
  1039. DSP_SPOS_DCDC,
  1040. DSP_SPOS_DCDC,
  1041. DSP_SPOS_DCDC,
  1042. DSP_SPOS_DCDC,
  1043. DSP_SPOS_DCDC,
  1044. DSP_SPOS_DCDC,
  1045. DSP_SPOS_DCDC,
  1046. DSP_SPOS_DCDC,
  1047. DSP_SPOS_DCDC,
  1048. DSP_SPOS_DCDC,
  1049. DSP_SPOS_DCDC,
  1050. DSP_SPOS_DCDC,
  1051. DSP_SPOS_DCDC,
  1052. DSP_SPOS_DCDC,
  1053. DSP_SPOS_DCDC,
  1054. DSP_SPOS_DCDC,
  1055. DSP_SPOS_DCDC,
  1056. DSP_SPOS_DCDC,
  1057. DSP_SPOS_DCDC,
  1058. DSP_SPOS_DCDC,
  1059. DSP_SPOS_DCDC,
  1060. DSP_SPOS_DCDC,
  1061. DSP_SPOS_DCDC,
  1062. DSP_SPOS_DCDC,
  1063. DSP_SPOS_DCDC,
  1064. DSP_SPOS_DCDC
  1065. },
  1066. {
  1067. BG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  1068. 0,0
  1069. }
  1070. };
  1071. bg_task_tree_hdr.links.entry_point = task_tree_header_code->address;
  1072. bg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1073. cs46xx_dsp_create_task_tree(chip,"BGtaskTreeHdr",(u32 *)&bg_task_tree_hdr,BG_TREE_SCB_ADDR,0x35);
  1074. }
  1075. /* create timing master SCB */
  1076. timing_master_scb = cs46xx_dsp_create_timing_master_scb(chip);
  1077. /* create the CODEC output task */
  1078. codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_I",0x0010,0x0000,
  1079. MASTERMIX_SCB_ADDR,
  1080. CODECOUT_SCB_ADDR,timing_master_scb,
  1081. SCB_ON_PARENT_SUBLIST_SCB);
  1082. if (!codec_out_scb) goto _fail_end;
  1083. /* create the master mix SCB */
  1084. master_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"MasterMixSCB",
  1085. MIX_SAMPLE_BUF1,MASTERMIX_SCB_ADDR,
  1086. codec_out_scb,
  1087. SCB_ON_PARENT_SUBLIST_SCB);
  1088. ins->master_mix_scb = master_mix_scb;
  1089. if (!master_mix_scb) goto _fail_end;
  1090. /* create codec in */
  1091. codec_in_scb = cs46xx_dsp_create_codec_in_scb(chip,"CodecInSCB",0x0010,0x00A0,
  1092. CODEC_INPUT_BUF1,
  1093. CODECIN_SCB_ADDR,codec_out_scb,
  1094. SCB_ON_PARENT_NEXT_SCB);
  1095. if (!codec_in_scb) goto _fail_end;
  1096. ins->codec_in_scb = codec_in_scb;
  1097. /* create write back scb */
  1098. write_back_scb = cs46xx_dsp_create_mix_to_ostream_scb(chip,"WriteBackSCB",
  1099. WRITE_BACK_BUF1,WRITE_BACK_SPB,
  1100. WRITEBACK_SCB_ADDR,
  1101. timing_master_scb,
  1102. SCB_ON_PARENT_NEXT_SCB);
  1103. if (!write_back_scb) goto _fail_end;
  1104. {
  1105. static struct dsp_mix2_ostream_spb mix2_ostream_spb = {
  1106. 0x00020000,
  1107. 0x0000ffff
  1108. };
  1109. if (!cs46xx_dsp_create_task_tree(chip, NULL,
  1110. (u32 *)&mix2_ostream_spb,
  1111. WRITE_BACK_SPB, 2))
  1112. goto _fail_end;
  1113. }
  1114. /* input sample converter */
  1115. vari_decimate_scb = cs46xx_dsp_create_vari_decimate_scb(chip,"VariDecimateSCB",
  1116. VARI_DECIMATE_BUF0,
  1117. VARI_DECIMATE_BUF1,
  1118. VARIDECIMATE_SCB_ADDR,
  1119. write_back_scb,
  1120. SCB_ON_PARENT_SUBLIST_SCB);
  1121. if (!vari_decimate_scb) goto _fail_end;
  1122. /* create the record mixer SCB */
  1123. record_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RecordMixerSCB",
  1124. MIX_SAMPLE_BUF2,
  1125. RECORD_MIXER_SCB_ADDR,
  1126. vari_decimate_scb,
  1127. SCB_ON_PARENT_SUBLIST_SCB);
  1128. ins->record_mixer_scb = record_mix_scb;
  1129. if (!record_mix_scb) goto _fail_end;
  1130. valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
  1131. if (snd_BUG_ON(chip->nr_ac97_codecs != 1 && chip->nr_ac97_codecs != 2))
  1132. goto _fail_end;
  1133. if (chip->nr_ac97_codecs == 1) {
  1134. /* output on slot 5 and 11
  1135. on primary CODEC */
  1136. fifo_addr = 0x20;
  1137. fifo_span = 0x60;
  1138. /* enable slot 5 and 11 */
  1139. valid_slots |= ACOSV_SLV5 | ACOSV_SLV11;
  1140. } else {
  1141. /* output on slot 7 and 8
  1142. on secondary CODEC */
  1143. fifo_addr = 0x40;
  1144. fifo_span = 0x10;
  1145. /* enable slot 7 and 8 */
  1146. valid_slots |= ACOSV_SLV7 | ACOSV_SLV8;
  1147. }
  1148. /* create CODEC tasklet for rear speakers output*/
  1149. rear_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_Rear",fifo_span,fifo_addr,
  1150. REAR_MIXER_SCB_ADDR,
  1151. REAR_CODECOUT_SCB_ADDR,codec_in_scb,
  1152. SCB_ON_PARENT_NEXT_SCB);
  1153. if (!rear_codec_out_scb) goto _fail_end;
  1154. /* create the rear PCM channel mixer SCB */
  1155. rear_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RearMixerSCB",
  1156. MIX_SAMPLE_BUF3,
  1157. REAR_MIXER_SCB_ADDR,
  1158. rear_codec_out_scb,
  1159. SCB_ON_PARENT_SUBLIST_SCB);
  1160. ins->rear_mix_scb = rear_mix_scb;
  1161. if (!rear_mix_scb) goto _fail_end;
  1162. if (chip->nr_ac97_codecs == 2) {
  1163. /* create CODEC tasklet for rear Center/LFE output
  1164. slot 6 and 9 on seconadry CODEC */
  1165. clfe_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_CLFE",0x0030,0x0030,
  1166. CLFE_MIXER_SCB_ADDR,
  1167. CLFE_CODEC_SCB_ADDR,
  1168. rear_codec_out_scb,
  1169. SCB_ON_PARENT_NEXT_SCB);
  1170. if (!clfe_codec_out_scb) goto _fail_end;
  1171. /* create the rear PCM channel mixer SCB */
  1172. ins->center_lfe_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"CLFEMixerSCB",
  1173. MIX_SAMPLE_BUF4,
  1174. CLFE_MIXER_SCB_ADDR,
  1175. clfe_codec_out_scb,
  1176. SCB_ON_PARENT_SUBLIST_SCB);
  1177. if (!ins->center_lfe_mix_scb) goto _fail_end;
  1178. /* enable slot 6 and 9 */
  1179. valid_slots |= ACOSV_SLV6 | ACOSV_SLV9;
  1180. } else {
  1181. clfe_codec_out_scb = rear_codec_out_scb;
  1182. ins->center_lfe_mix_scb = rear_mix_scb;
  1183. }
  1184. /* enable slots depending on CODEC configuration */
  1185. snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
  1186. /* the magic snooper */
  1187. magic_snoop_scb = cs46xx_dsp_create_magic_snoop_scb (chip,"MagicSnoopSCB_I",OUTPUTSNOOP_SCB_ADDR,
  1188. OUTPUT_SNOOP_BUFFER,
  1189. codec_out_scb,
  1190. clfe_codec_out_scb,
  1191. SCB_ON_PARENT_NEXT_SCB);
  1192. if (!magic_snoop_scb) goto _fail_end;
  1193. ins->ref_snoop_scb = magic_snoop_scb;
  1194. /* SP IO access */
  1195. if (!cs46xx_dsp_create_spio_write_scb(chip,"SPIOWriteSCB",SPIOWRITE_SCB_ADDR,
  1196. magic_snoop_scb,
  1197. SCB_ON_PARENT_NEXT_SCB))
  1198. goto _fail_end;
  1199. /* SPDIF input sampel rate converter */
  1200. src_task_scb = cs46xx_dsp_create_src_task_scb(chip,"SrcTaskSCB_SPDIFI",
  1201. ins->spdif_in_sample_rate,
  1202. SRC_OUTPUT_BUF1,
  1203. SRC_DELAY_BUF1,SRCTASK_SCB_ADDR,
  1204. master_mix_scb,
  1205. SCB_ON_PARENT_SUBLIST_SCB,1);
  1206. if (!src_task_scb) goto _fail_end;
  1207. cs46xx_src_unlink(chip,src_task_scb);
  1208. /* NOTE: when we now how to detect the SPDIF input
  1209. sample rate we will use this SRC to adjust it */
  1210. ins->spdif_in_src = src_task_scb;
  1211. cs46xx_dsp_async_init(chip,timing_master_scb);
  1212. return 0;
  1213. _fail_end:
  1214. snd_printk(KERN_ERR "dsp_spos: failed to setup SCB's in DSP\n");
  1215. return -EINVAL;
  1216. }
  1217. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  1218. struct dsp_scb_descriptor * fg_entry)
  1219. {
  1220. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1221. struct dsp_symbol_entry * s16_async_codec_input_task;
  1222. struct dsp_symbol_entry * spdifo_task;
  1223. struct dsp_symbol_entry * spdifi_task;
  1224. struct dsp_scb_descriptor * spdifi_scb_desc, * spdifo_scb_desc, * async_codec_scb_desc;
  1225. s16_async_codec_input_task = cs46xx_dsp_lookup_symbol(chip, "S16_ASYNCCODECINPUTTASK", SYMBOL_CODE);
  1226. if (s16_async_codec_input_task == NULL) {
  1227. snd_printk(KERN_ERR "dsp_spos: symbol S16_ASYNCCODECINPUTTASK not found\n");
  1228. return -EIO;
  1229. }
  1230. spdifo_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFOTASK", SYMBOL_CODE);
  1231. if (spdifo_task == NULL) {
  1232. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFOTASK not found\n");
  1233. return -EIO;
  1234. }
  1235. spdifi_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFITASK", SYMBOL_CODE);
  1236. if (spdifi_task == NULL) {
  1237. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFITASK not found\n");
  1238. return -EIO;
  1239. }
  1240. {
  1241. /* 0xBC0 */
  1242. struct dsp_spdifoscb spdifo_scb = {
  1243. /* 0 */ DSP_SPOS_UUUU,
  1244. {
  1245. /* 1 */ 0xb0,
  1246. /* 2 */ 0,
  1247. /* 3 */ 0,
  1248. /* 4 */ 0,
  1249. },
  1250. /* NOTE: the SPDIF output task read samples in mono
  1251. format, the AsynchFGTxSCB task writes to buffer
  1252. in stereo format
  1253. */
  1254. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_256,
  1255. /* 6 */ ( SPDIFO_IP_OUTPUT_BUFFER1 << 0x10 ) | 0xFFFC,
  1256. /* 7 */ 0,0,
  1257. /* 8 */ 0,
  1258. /* 9 */ FG_TASK_HEADER_ADDR, NULL_SCB_ADDR,
  1259. /* A */ spdifo_task->address,
  1260. SPDIFO_SCB_INST + SPDIFOFIFOPointer,
  1261. {
  1262. /* B */ 0x0040, /*DSP_SPOS_UUUU,*/
  1263. /* C */ 0x20ff, /*DSP_SPOS_UUUU,*/
  1264. },
  1265. /* D */ 0x804c,0, /* SPDIFOFIFOPointer:SPDIFOStatRegAddr; */
  1266. /* E */ 0x0108,0x0001, /* SPDIFOStMoFormat:SPDIFOFIFOBaseAddr; */
  1267. /* F */ DSP_SPOS_UUUU /* SPDIFOFree; */
  1268. };
  1269. /* 0xBB0 */
  1270. struct dsp_spdifiscb spdifi_scb = {
  1271. /* 0 */ DSP_SPOS_UULO,DSP_SPOS_UUHI,
  1272. /* 1 */ 0,
  1273. /* 2 */ 0,
  1274. /* 3 */ 1,4000, /* SPDIFICountLimit SPDIFICount */
  1275. /* 4 */ DSP_SPOS_UUUU, /* SPDIFIStatusData */
  1276. /* 5 */ 0,DSP_SPOS_UUHI, /* StatusData, Free4 */
  1277. /* 6 */ DSP_SPOS_UUUU, /* Free3 */
  1278. /* 7 */ DSP_SPOS_UU,DSP_SPOS_DC, /* Free2 BitCount*/
  1279. /* 8 */ DSP_SPOS_UUUU, /* TempStatus */
  1280. /* 9 */ SPDIFO_SCB_INST, NULL_SCB_ADDR,
  1281. /* A */ spdifi_task->address,
  1282. SPDIFI_SCB_INST + SPDIFIFIFOPointer,
  1283. /* NOTE: The SPDIF input task write the sample in mono
  1284. format from the HW FIFO, the AsynchFGRxSCB task reads
  1285. them in stereo
  1286. */
  1287. /* B */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_128,
  1288. /* C */ (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1289. /* D */ 0x8048,0,
  1290. /* E */ 0x01f0,0x0001,
  1291. /* F */ DSP_SPOS_UUUU /* SPDIN_STATUS monitor */
  1292. };
  1293. /* 0xBA0 */
  1294. struct dsp_async_codec_input_scb async_codec_input_scb = {
  1295. /* 0 */ DSP_SPOS_UUUU,
  1296. /* 1 */ 0,
  1297. /* 2 */ 0,
  1298. /* 3 */ 1,4000,
  1299. /* 4 */ 0x0118,0x0001,
  1300. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_64,
  1301. /* 6 */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1302. /* 7 */ DSP_SPOS_UU,0x3,
  1303. /* 8 */ DSP_SPOS_UUUU,
  1304. /* 9 */ SPDIFI_SCB_INST,NULL_SCB_ADDR,
  1305. /* A */ s16_async_codec_input_task->address,
  1306. HFG_TREE_SCB + AsyncCIOFIFOPointer,
  1307. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  1308. /* C */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10), /*(ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,*/
  1309. #ifdef UseASER1Input
  1310. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1311. Init. 0000:8042: for ASER1
  1312. 0000:8044: for ASER2 */
  1313. /* D */ 0x8042,0,
  1314. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1315. Init 1 stero:8050 ASER1
  1316. Init 0 mono:8070 ASER2
  1317. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1318. /* E */ 0x0100,0x0001,
  1319. #endif
  1320. #ifdef UseASER2Input
  1321. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1322. Init. 0000:8042: for ASER1
  1323. 0000:8044: for ASER2 */
  1324. /* D */ 0x8044,0,
  1325. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1326. Init 1 stero:8050 ASER1
  1327. Init 0 mono:8070 ASER2
  1328. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1329. /* E */ 0x0110,0x0001,
  1330. #endif
  1331. /* short AsyncCIOutputBufModulo:AsyncCIFree;
  1332. AsyncCIOutputBufModulo: The modulo size for
  1333. the output buffer of this task */
  1334. /* F */ 0, /* DSP_SPOS_UUUU */
  1335. };
  1336. spdifo_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFOSCB",(u32 *)&spdifo_scb,SPDIFO_SCB_INST);
  1337. if (snd_BUG_ON(!spdifo_scb_desc))
  1338. return -EIO;
  1339. spdifi_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFISCB",(u32 *)&spdifi_scb,SPDIFI_SCB_INST);
  1340. if (snd_BUG_ON(!spdifi_scb_desc))
  1341. return -EIO;
  1342. async_codec_scb_desc = cs46xx_dsp_create_scb(chip,"AsynCodecInputSCB",(u32 *)&async_codec_input_scb, HFG_TREE_SCB);
  1343. if (snd_BUG_ON(!async_codec_scb_desc))
  1344. return -EIO;
  1345. async_codec_scb_desc->parent_scb_ptr = NULL;
  1346. async_codec_scb_desc->next_scb_ptr = spdifi_scb_desc;
  1347. async_codec_scb_desc->sub_list_ptr = ins->the_null_scb;
  1348. async_codec_scb_desc->task_entry = s16_async_codec_input_task;
  1349. spdifi_scb_desc->parent_scb_ptr = async_codec_scb_desc;
  1350. spdifi_scb_desc->next_scb_ptr = spdifo_scb_desc;
  1351. spdifi_scb_desc->sub_list_ptr = ins->the_null_scb;
  1352. spdifi_scb_desc->task_entry = spdifi_task;
  1353. spdifo_scb_desc->parent_scb_ptr = spdifi_scb_desc;
  1354. spdifo_scb_desc->next_scb_ptr = fg_entry;
  1355. spdifo_scb_desc->sub_list_ptr = ins->the_null_scb;
  1356. spdifo_scb_desc->task_entry = spdifo_task;
  1357. /* this one is faked, as the parnet of SPDIFO task
  1358. is the FG task tree */
  1359. fg_entry->parent_scb_ptr = spdifo_scb_desc;
  1360. /* for proc fs */
  1361. cs46xx_dsp_proc_register_scb_desc (chip,spdifo_scb_desc);
  1362. cs46xx_dsp_proc_register_scb_desc (chip,spdifi_scb_desc);
  1363. cs46xx_dsp_proc_register_scb_desc (chip,async_codec_scb_desc);
  1364. /* Async MASTER ENABLE, affects both SPDIF input and output */
  1365. snd_cs46xx_pokeBA0(chip, BA0_ASER_MASTER, 0x1 );
  1366. }
  1367. return 0;
  1368. }
  1369. static void cs46xx_dsp_disable_spdif_hw (struct snd_cs46xx *chip)
  1370. {
  1371. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1372. /* set SPDIF output FIFO slot */
  1373. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, 0);
  1374. /* SPDIF output MASTER ENABLE */
  1375. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0);
  1376. /* right and left validate bit */
  1377. /*cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);*/
  1378. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, 0x0);
  1379. /* clear fifo pointer */
  1380. cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);
  1381. /* monitor state */
  1382. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_HW_ENABLED;
  1383. }
  1384. int cs46xx_dsp_enable_spdif_hw (struct snd_cs46xx *chip)
  1385. {
  1386. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1387. /* if hw-ctrl already enabled, turn off to reset logic ... */
  1388. cs46xx_dsp_disable_spdif_hw (chip);
  1389. udelay(50);
  1390. /* set SPDIF output FIFO slot */
  1391. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, ( 0x8000 | ((SP_SPDOUT_FIFO >> 4) << 4) ));
  1392. /* SPDIF output MASTER ENABLE */
  1393. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0x80000000);
  1394. /* right and left validate bit */
  1395. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1396. /* monitor state */
  1397. ins->spdif_status_out |= DSP_SPDIF_STATUS_HW_ENABLED;
  1398. return 0;
  1399. }
  1400. int cs46xx_dsp_enable_spdif_in (struct snd_cs46xx *chip)
  1401. {
  1402. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1403. /* turn on amplifier */
  1404. chip->active_ctrl(chip, 1);
  1405. chip->amplifier_ctrl(chip, 1);
  1406. if (snd_BUG_ON(ins->asynch_rx_scb))
  1407. return -EINVAL;
  1408. if (snd_BUG_ON(!ins->spdif_in_src))
  1409. return -EINVAL;
  1410. mutex_lock(&chip->spos_mutex);
  1411. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED) ) {
  1412. /* time countdown enable */
  1413. cs46xx_poke_via_dsp (chip,SP_ASER_COUNTDOWN, 0x80000005);
  1414. /* NOTE: 80000005 value is just magic. With all values
  1415. that I've tested this one seem to give the best result.
  1416. Got no explication why. (Benny) */
  1417. /* SPDIF input MASTER ENABLE */
  1418. cs46xx_poke_via_dsp (chip,SP_SPDIN_CONTROL, 0x800003ff);
  1419. ins->spdif_status_out |= DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED;
  1420. }
  1421. /* create and start the asynchronous receiver SCB */
  1422. ins->asynch_rx_scb = cs46xx_dsp_create_asynch_fg_rx_scb(chip,"AsynchFGRxSCB",
  1423. ASYNCRX_SCB_ADDR,
  1424. SPDIFI_SCB_INST,
  1425. SPDIFI_IP_OUTPUT_BUFFER1,
  1426. ins->spdif_in_src,
  1427. SCB_ON_PARENT_SUBLIST_SCB);
  1428. spin_lock_irq(&chip->reg_lock);
  1429. /* reset SPDIF input sample buffer pointer */
  1430. /*snd_cs46xx_poke (chip, (SPDIFI_SCB_INST + 0x0c) << 2,
  1431. (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC);*/
  1432. /* reset FIFO ptr */
  1433. /*cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);*/
  1434. cs46xx_src_link(chip,ins->spdif_in_src);
  1435. /* unmute SRC volume */
  1436. cs46xx_dsp_scb_set_volume (chip,ins->spdif_in_src,0x7fff,0x7fff);
  1437. spin_unlock_irq(&chip->reg_lock);
  1438. /* set SPDIF input sample rate and unmute
  1439. NOTE: only 48khz support for SPDIF input this time */
  1440. /* cs46xx_dsp_set_src_sample_rate(chip,ins->spdif_in_src,48000); */
  1441. /* monitor state */
  1442. ins->spdif_status_in = 1;
  1443. mutex_unlock(&chip->spos_mutex);
  1444. return 0;
  1445. }
  1446. int cs46xx_dsp_disable_spdif_in (struct snd_cs46xx *chip)
  1447. {
  1448. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1449. if (snd_BUG_ON(!ins->asynch_rx_scb))
  1450. return -EINVAL;
  1451. if (snd_BUG_ON(!ins->spdif_in_src))
  1452. return -EINVAL;
  1453. mutex_lock(&chip->spos_mutex);
  1454. /* Remove the asynchronous receiver SCB */
  1455. cs46xx_dsp_remove_scb (chip,ins->asynch_rx_scb);
  1456. ins->asynch_rx_scb = NULL;
  1457. cs46xx_src_unlink(chip,ins->spdif_in_src);
  1458. /* monitor state */
  1459. ins->spdif_status_in = 0;
  1460. mutex_unlock(&chip->spos_mutex);
  1461. /* restore amplifier */
  1462. chip->active_ctrl(chip, -1);
  1463. chip->amplifier_ctrl(chip, -1);
  1464. return 0;
  1465. }
  1466. int cs46xx_dsp_enable_pcm_capture (struct snd_cs46xx *chip)
  1467. {
  1468. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1469. if (snd_BUG_ON(ins->pcm_input))
  1470. return -EINVAL;
  1471. if (snd_BUG_ON(!ins->ref_snoop_scb))
  1472. return -EINVAL;
  1473. mutex_lock(&chip->spos_mutex);
  1474. ins->pcm_input = cs46xx_add_record_source(chip,ins->ref_snoop_scb,PCMSERIALIN_PCM_SCB_ADDR,
  1475. "PCMSerialInput_Wave");
  1476. mutex_unlock(&chip->spos_mutex);
  1477. return 0;
  1478. }
  1479. int cs46xx_dsp_disable_pcm_capture (struct snd_cs46xx *chip)
  1480. {
  1481. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1482. if (snd_BUG_ON(!ins->pcm_input))
  1483. return -EINVAL;
  1484. mutex_lock(&chip->spos_mutex);
  1485. cs46xx_dsp_remove_scb (chip,ins->pcm_input);
  1486. ins->pcm_input = NULL;
  1487. mutex_unlock(&chip->spos_mutex);
  1488. return 0;
  1489. }
  1490. int cs46xx_dsp_enable_adc_capture (struct snd_cs46xx *chip)
  1491. {
  1492. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1493. if (snd_BUG_ON(ins->adc_input))
  1494. return -EINVAL;
  1495. if (snd_BUG_ON(!ins->codec_in_scb))
  1496. return -EINVAL;
  1497. mutex_lock(&chip->spos_mutex);
  1498. ins->adc_input = cs46xx_add_record_source(chip,ins->codec_in_scb,PCMSERIALIN_SCB_ADDR,
  1499. "PCMSerialInput_ADC");
  1500. mutex_unlock(&chip->spos_mutex);
  1501. return 0;
  1502. }
  1503. int cs46xx_dsp_disable_adc_capture (struct snd_cs46xx *chip)
  1504. {
  1505. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1506. if (snd_BUG_ON(!ins->adc_input))
  1507. return -EINVAL;
  1508. mutex_lock(&chip->spos_mutex);
  1509. cs46xx_dsp_remove_scb (chip,ins->adc_input);
  1510. ins->adc_input = NULL;
  1511. mutex_unlock(&chip->spos_mutex);
  1512. return 0;
  1513. }
  1514. int cs46xx_poke_via_dsp (struct snd_cs46xx *chip, u32 address, u32 data)
  1515. {
  1516. u32 temp;
  1517. int i;
  1518. /* santiy check the parameters. (These numbers are not 100% correct. They are
  1519. a rough guess from looking at the controller spec.) */
  1520. if (address < 0x8000 || address >= 0x9000)
  1521. return -EINVAL;
  1522. /* initialize the SP_IO_WRITE SCB with the data. */
  1523. temp = ( address << 16 ) | ( address & 0x0000FFFF); /* offset 0 <-- address2 : address1 */
  1524. snd_cs46xx_poke(chip,( SPIOWRITE_SCB_ADDR << 2), temp);
  1525. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 1) << 2), data); /* offset 1 <-- data1 */
  1526. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 2) << 2), data); /* offset 1 <-- data2 */
  1527. /* Poke this location to tell the task to start */
  1528. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 6) << 2), SPIOWRITE_SCB_ADDR << 0x10);
  1529. /* Verify that the task ran */
  1530. for (i=0; i<25; i++) {
  1531. udelay(125);
  1532. temp = snd_cs46xx_peek(chip,((SPIOWRITE_SCB_ADDR + 6) << 2));
  1533. if (temp == 0x00000000)
  1534. break;
  1535. }
  1536. if (i == 25) {
  1537. snd_printk(KERN_ERR "dsp_spos: SPIOWriteTask not responding\n");
  1538. return -EBUSY;
  1539. }
  1540. return 0;
  1541. }
  1542. int cs46xx_dsp_set_dac_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1543. {
  1544. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1545. struct dsp_scb_descriptor * scb;
  1546. mutex_lock(&chip->spos_mutex);
  1547. /* main output */
  1548. scb = ins->master_mix_scb->sub_list_ptr;
  1549. while (scb != ins->the_null_scb) {
  1550. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1551. scb = scb->next_scb_ptr;
  1552. }
  1553. /* rear output */
  1554. scb = ins->rear_mix_scb->sub_list_ptr;
  1555. while (scb != ins->the_null_scb) {
  1556. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1557. scb = scb->next_scb_ptr;
  1558. }
  1559. ins->dac_volume_left = left;
  1560. ins->dac_volume_right = right;
  1561. mutex_unlock(&chip->spos_mutex);
  1562. return 0;
  1563. }
  1564. int cs46xx_dsp_set_iec958_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1565. {
  1566. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1567. mutex_lock(&chip->spos_mutex);
  1568. if (ins->asynch_rx_scb != NULL)
  1569. cs46xx_dsp_scb_set_volume (chip,ins->asynch_rx_scb,
  1570. left,right);
  1571. ins->spdif_input_volume_left = left;
  1572. ins->spdif_input_volume_right = right;
  1573. mutex_unlock(&chip->spos_mutex);
  1574. return 0;
  1575. }
  1576. #ifdef CONFIG_PM
  1577. int cs46xx_dsp_resume(struct snd_cs46xx * chip)
  1578. {
  1579. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1580. int i, err;
  1581. /* clear parameter, sample and code areas */
  1582. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET,
  1583. DSP_PARAMETER_BYTE_SIZE);
  1584. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET,
  1585. DSP_SAMPLE_BYTE_SIZE);
  1586. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  1587. for (i = 0; i < ins->nmodules; i++) {
  1588. struct dsp_module_desc *module = &ins->modules[i];
  1589. struct dsp_segment_desc *seg;
  1590. u32 doffset, dsize;
  1591. seg = get_segment_desc(module, SEGTYPE_SP_PARAMETER);
  1592. err = dsp_load_parameter(chip, seg);
  1593. if (err < 0)
  1594. return err;
  1595. seg = get_segment_desc(module, SEGTYPE_SP_SAMPLE);
  1596. err = dsp_load_sample(chip, seg);
  1597. if (err < 0)
  1598. return err;
  1599. seg = get_segment_desc(module, SEGTYPE_SP_PROGRAM);
  1600. if (!seg)
  1601. continue;
  1602. doffset = seg->offset * 4 + module->load_address * 4
  1603. + DSP_CODE_BYTE_OFFSET;
  1604. dsize = seg->size * 4;
  1605. err = snd_cs46xx_download(chip,
  1606. ins->code.data + module->load_address,
  1607. doffset, dsize);
  1608. if (err < 0)
  1609. return err;
  1610. }
  1611. for (i = 0; i < ins->ntask; i++) {
  1612. struct dsp_task_descriptor *t = &ins->tasks[i];
  1613. _dsp_create_task_tree(chip, t->data, t->address, t->size);
  1614. }
  1615. for (i = 0; i < ins->nscb; i++) {
  1616. struct dsp_scb_descriptor *s = &ins->scbs[i];
  1617. if (s->deleted)
  1618. continue;
  1619. _dsp_create_scb(chip, s->data, s->address);
  1620. }
  1621. return 0;
  1622. }
  1623. #endif