musb_gadget_ep0.c 25 KB

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  1. /*
  2. * MUSB OTG peripheral driver ep0 handling
  3. *
  4. * Copyright 2005 Mentor Graphics Corporation
  5. * Copyright (C) 2005-2006 by Texas Instruments
  6. * Copyright (C) 2006-2007 Nokia Corporation
  7. * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * version 2 as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21. * 02110-1301 USA
  22. *
  23. * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  24. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  26. * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  28. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  29. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. *
  34. */
  35. #include <linux/kernel.h>
  36. #include <linux/list.h>
  37. #include <linux/timer.h>
  38. #include <linux/spinlock.h>
  39. #include <linux/init.h>
  40. #include <linux/device.h>
  41. #include <linux/interrupt.h>
  42. #include "musb_core.h"
  43. /* ep0 is always musb->endpoints[0].ep_in */
  44. #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
  45. /*
  46. * locking note: we use only the controller lock, for simpler correctness.
  47. * It's always held with IRQs blocked.
  48. *
  49. * It protects the ep0 request queue as well as ep0_state, not just the
  50. * controller and indexed registers. And that lock stays held unless it
  51. * needs to be dropped to allow reentering this driver ... like upcalls to
  52. * the gadget driver, or adjusting endpoint halt status.
  53. */
  54. static char *decode_ep0stage(u8 stage)
  55. {
  56. switch (stage) {
  57. case MUSB_EP0_STAGE_IDLE: return "idle";
  58. case MUSB_EP0_STAGE_SETUP: return "setup";
  59. case MUSB_EP0_STAGE_TX: return "in";
  60. case MUSB_EP0_STAGE_RX: return "out";
  61. case MUSB_EP0_STAGE_ACKWAIT: return "wait";
  62. case MUSB_EP0_STAGE_STATUSIN: return "in/status";
  63. case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
  64. default: return "?";
  65. }
  66. }
  67. /* handle a standard GET_STATUS request
  68. * Context: caller holds controller lock
  69. */
  70. static int service_tx_status_request(
  71. struct musb *musb,
  72. const struct usb_ctrlrequest *ctrlrequest)
  73. {
  74. void __iomem *mbase = musb->mregs;
  75. int handled = 1;
  76. u8 result[2], epnum = 0;
  77. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  78. result[1] = 0;
  79. switch (recip) {
  80. case USB_RECIP_DEVICE:
  81. result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
  82. result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  83. #ifdef CONFIG_USB_MUSB_OTG
  84. if (musb->g.is_otg) {
  85. result[0] |= musb->g.b_hnp_enable
  86. << USB_DEVICE_B_HNP_ENABLE;
  87. result[0] |= musb->g.a_alt_hnp_support
  88. << USB_DEVICE_A_ALT_HNP_SUPPORT;
  89. result[0] |= musb->g.a_hnp_support
  90. << USB_DEVICE_A_HNP_SUPPORT;
  91. }
  92. #endif
  93. break;
  94. case USB_RECIP_INTERFACE:
  95. result[0] = 0;
  96. break;
  97. case USB_RECIP_ENDPOINT: {
  98. int is_in;
  99. struct musb_ep *ep;
  100. u16 tmp;
  101. void __iomem *regs;
  102. epnum = (u8) ctrlrequest->wIndex;
  103. if (!epnum) {
  104. result[0] = 0;
  105. break;
  106. }
  107. is_in = epnum & USB_DIR_IN;
  108. if (is_in) {
  109. epnum &= 0x0f;
  110. ep = &musb->endpoints[epnum].ep_in;
  111. } else {
  112. ep = &musb->endpoints[epnum].ep_out;
  113. }
  114. regs = musb->endpoints[epnum].regs;
  115. if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
  116. handled = -EINVAL;
  117. break;
  118. }
  119. musb_ep_select(mbase, epnum);
  120. if (is_in)
  121. tmp = musb_readw(regs, MUSB_TXCSR)
  122. & MUSB_TXCSR_P_SENDSTALL;
  123. else
  124. tmp = musb_readw(regs, MUSB_RXCSR)
  125. & MUSB_RXCSR_P_SENDSTALL;
  126. musb_ep_select(mbase, 0);
  127. result[0] = tmp ? 1 : 0;
  128. } break;
  129. default:
  130. /* class, vendor, etc ... delegate */
  131. handled = 0;
  132. break;
  133. }
  134. /* fill up the fifo; caller updates csr0 */
  135. if (handled > 0) {
  136. u16 len = le16_to_cpu(ctrlrequest->wLength);
  137. if (len > 2)
  138. len = 2;
  139. musb_write_fifo(&musb->endpoints[0], len, result);
  140. }
  141. return handled;
  142. }
  143. /*
  144. * handle a control-IN request, the end0 buffer contains the current request
  145. * that is supposed to be a standard control request. Assumes the fifo to
  146. * be at least 2 bytes long.
  147. *
  148. * @return 0 if the request was NOT HANDLED,
  149. * < 0 when error
  150. * > 0 when the request is processed
  151. *
  152. * Context: caller holds controller lock
  153. */
  154. static int
  155. service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  156. {
  157. int handled = 0; /* not handled */
  158. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  159. == USB_TYPE_STANDARD) {
  160. switch (ctrlrequest->bRequest) {
  161. case USB_REQ_GET_STATUS:
  162. handled = service_tx_status_request(musb,
  163. ctrlrequest);
  164. break;
  165. /* case USB_REQ_SYNC_FRAME: */
  166. default:
  167. break;
  168. }
  169. }
  170. return handled;
  171. }
  172. /*
  173. * Context: caller holds controller lock
  174. */
  175. static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
  176. {
  177. musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
  178. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  179. }
  180. /*
  181. * Tries to start B-device HNP negotiation if enabled via sysfs
  182. */
  183. static inline void musb_try_b_hnp_enable(struct musb *musb)
  184. {
  185. void __iomem *mbase = musb->mregs;
  186. u8 devctl;
  187. DBG(1, "HNP: Setting HR\n");
  188. devctl = musb_readb(mbase, MUSB_DEVCTL);
  189. musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
  190. }
  191. /*
  192. * Handle all control requests with no DATA stage, including standard
  193. * requests such as:
  194. * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
  195. * always delegated to the gadget driver
  196. * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
  197. * always handled here, except for class/vendor/... features
  198. *
  199. * Context: caller holds controller lock
  200. */
  201. static int
  202. service_zero_data_request(struct musb *musb,
  203. struct usb_ctrlrequest *ctrlrequest)
  204. __releases(musb->lock)
  205. __acquires(musb->lock)
  206. {
  207. int handled = -EINVAL;
  208. void __iomem *mbase = musb->mregs;
  209. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  210. /* the gadget driver handles everything except what we MUST handle */
  211. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  212. == USB_TYPE_STANDARD) {
  213. switch (ctrlrequest->bRequest) {
  214. case USB_REQ_SET_ADDRESS:
  215. /* change it after the status stage */
  216. musb->set_address = true;
  217. musb->address = (u8) (ctrlrequest->wValue & 0x7f);
  218. handled = 1;
  219. break;
  220. case USB_REQ_CLEAR_FEATURE:
  221. switch (recip) {
  222. case USB_RECIP_DEVICE:
  223. if (ctrlrequest->wValue
  224. != USB_DEVICE_REMOTE_WAKEUP)
  225. break;
  226. musb->may_wakeup = 0;
  227. handled = 1;
  228. break;
  229. case USB_RECIP_INTERFACE:
  230. break;
  231. case USB_RECIP_ENDPOINT:{
  232. const u8 num = ctrlrequest->wIndex & 0x0f;
  233. struct musb_ep *musb_ep;
  234. if (num == 0
  235. || num >= MUSB_C_NUM_EPS
  236. || ctrlrequest->wValue
  237. != USB_ENDPOINT_HALT)
  238. break;
  239. if (ctrlrequest->wIndex & USB_DIR_IN)
  240. musb_ep = &musb->endpoints[num].ep_in;
  241. else
  242. musb_ep = &musb->endpoints[num].ep_out;
  243. if (!musb_ep->desc)
  244. break;
  245. /* REVISIT do it directly, no locking games */
  246. spin_unlock(&musb->lock);
  247. musb_gadget_set_halt(&musb_ep->end_point, 0);
  248. spin_lock(&musb->lock);
  249. /* select ep0 again */
  250. musb_ep_select(mbase, 0);
  251. handled = 1;
  252. } break;
  253. default:
  254. /* class, vendor, etc ... delegate */
  255. handled = 0;
  256. break;
  257. }
  258. break;
  259. case USB_REQ_SET_FEATURE:
  260. switch (recip) {
  261. case USB_RECIP_DEVICE:
  262. handled = 1;
  263. switch (ctrlrequest->wValue) {
  264. case USB_DEVICE_REMOTE_WAKEUP:
  265. musb->may_wakeup = 1;
  266. break;
  267. case USB_DEVICE_TEST_MODE:
  268. if (musb->g.speed != USB_SPEED_HIGH)
  269. goto stall;
  270. if (ctrlrequest->wIndex & 0xff)
  271. goto stall;
  272. switch (ctrlrequest->wIndex >> 8) {
  273. case 1:
  274. pr_debug("TEST_J\n");
  275. /* TEST_J */
  276. musb->test_mode_nr =
  277. MUSB_TEST_J;
  278. break;
  279. case 2:
  280. /* TEST_K */
  281. pr_debug("TEST_K\n");
  282. musb->test_mode_nr =
  283. MUSB_TEST_K;
  284. break;
  285. case 3:
  286. /* TEST_SE0_NAK */
  287. pr_debug("TEST_SE0_NAK\n");
  288. musb->test_mode_nr =
  289. MUSB_TEST_SE0_NAK;
  290. break;
  291. case 4:
  292. /* TEST_PACKET */
  293. pr_debug("TEST_PACKET\n");
  294. musb->test_mode_nr =
  295. MUSB_TEST_PACKET;
  296. break;
  297. default:
  298. goto stall;
  299. }
  300. /* enter test mode after irq */
  301. if (handled > 0)
  302. musb->test_mode = true;
  303. break;
  304. #ifdef CONFIG_USB_MUSB_OTG
  305. case USB_DEVICE_B_HNP_ENABLE:
  306. if (!musb->g.is_otg)
  307. goto stall;
  308. musb->g.b_hnp_enable = 1;
  309. musb_try_b_hnp_enable(musb);
  310. break;
  311. case USB_DEVICE_A_HNP_SUPPORT:
  312. if (!musb->g.is_otg)
  313. goto stall;
  314. musb->g.a_hnp_support = 1;
  315. break;
  316. case USB_DEVICE_A_ALT_HNP_SUPPORT:
  317. if (!musb->g.is_otg)
  318. goto stall;
  319. musb->g.a_alt_hnp_support = 1;
  320. break;
  321. #endif
  322. stall:
  323. default:
  324. handled = -EINVAL;
  325. break;
  326. }
  327. break;
  328. case USB_RECIP_INTERFACE:
  329. break;
  330. case USB_RECIP_ENDPOINT:{
  331. const u8 epnum =
  332. ctrlrequest->wIndex & 0x0f;
  333. struct musb_ep *musb_ep;
  334. struct musb_hw_ep *ep;
  335. void __iomem *regs;
  336. int is_in;
  337. u16 csr;
  338. if (epnum == 0
  339. || epnum >= MUSB_C_NUM_EPS
  340. || ctrlrequest->wValue
  341. != USB_ENDPOINT_HALT)
  342. break;
  343. ep = musb->endpoints + epnum;
  344. regs = ep->regs;
  345. is_in = ctrlrequest->wIndex & USB_DIR_IN;
  346. if (is_in)
  347. musb_ep = &ep->ep_in;
  348. else
  349. musb_ep = &ep->ep_out;
  350. if (!musb_ep->desc)
  351. break;
  352. musb_ep_select(mbase, epnum);
  353. if (is_in) {
  354. csr = musb_readw(regs,
  355. MUSB_TXCSR);
  356. if (csr & MUSB_TXCSR_FIFONOTEMPTY)
  357. csr |= MUSB_TXCSR_FLUSHFIFO;
  358. csr |= MUSB_TXCSR_P_SENDSTALL
  359. | MUSB_TXCSR_CLRDATATOG
  360. | MUSB_TXCSR_P_WZC_BITS;
  361. musb_writew(regs, MUSB_TXCSR,
  362. csr);
  363. } else {
  364. csr = musb_readw(regs,
  365. MUSB_RXCSR);
  366. csr |= MUSB_RXCSR_P_SENDSTALL
  367. | MUSB_RXCSR_FLUSHFIFO
  368. | MUSB_RXCSR_CLRDATATOG
  369. | MUSB_TXCSR_P_WZC_BITS;
  370. musb_writew(regs, MUSB_RXCSR,
  371. csr);
  372. }
  373. /* select ep0 again */
  374. musb_ep_select(mbase, 0);
  375. handled = 1;
  376. } break;
  377. default:
  378. /* class, vendor, etc ... delegate */
  379. handled = 0;
  380. break;
  381. }
  382. break;
  383. default:
  384. /* delegate SET_CONFIGURATION, etc */
  385. handled = 0;
  386. }
  387. } else
  388. handled = 0;
  389. return handled;
  390. }
  391. /* we have an ep0out data packet
  392. * Context: caller holds controller lock
  393. */
  394. static void ep0_rxstate(struct musb *musb)
  395. {
  396. void __iomem *regs = musb->control_ep->regs;
  397. struct usb_request *req;
  398. u16 count, csr;
  399. req = next_ep0_request(musb);
  400. /* read packet and ack; or stall because of gadget driver bug:
  401. * should have provided the rx buffer before setup() returned.
  402. */
  403. if (req) {
  404. void *buf = req->buf + req->actual;
  405. unsigned len = req->length - req->actual;
  406. /* read the buffer */
  407. count = musb_readb(regs, MUSB_COUNT0);
  408. if (count > len) {
  409. req->status = -EOVERFLOW;
  410. count = len;
  411. }
  412. musb_read_fifo(&musb->endpoints[0], count, buf);
  413. req->actual += count;
  414. csr = MUSB_CSR0_P_SVDRXPKTRDY;
  415. if (count < 64 || req->actual == req->length) {
  416. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  417. csr |= MUSB_CSR0_P_DATAEND;
  418. } else
  419. req = NULL;
  420. } else
  421. csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
  422. /* Completion handler may choose to stall, e.g. because the
  423. * message just received holds invalid data.
  424. */
  425. if (req) {
  426. musb->ackpend = csr;
  427. musb_g_ep0_giveback(musb, req);
  428. if (!musb->ackpend)
  429. return;
  430. musb->ackpend = 0;
  431. }
  432. musb_ep_select(musb->mregs, 0);
  433. musb_writew(regs, MUSB_CSR0, csr);
  434. }
  435. /*
  436. * transmitting to the host (IN), this code might be called from IRQ
  437. * and from kernel thread.
  438. *
  439. * Context: caller holds controller lock
  440. */
  441. static void ep0_txstate(struct musb *musb)
  442. {
  443. void __iomem *regs = musb->control_ep->regs;
  444. struct usb_request *request = next_ep0_request(musb);
  445. u16 csr = MUSB_CSR0_TXPKTRDY;
  446. u8 *fifo_src;
  447. u8 fifo_count;
  448. if (!request) {
  449. /* WARN_ON(1); */
  450. DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
  451. return;
  452. }
  453. /* load the data */
  454. fifo_src = (u8 *) request->buf + request->actual;
  455. fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
  456. request->length - request->actual);
  457. musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
  458. request->actual += fifo_count;
  459. /* update the flags */
  460. if (fifo_count < MUSB_MAX_END0_PACKET
  461. || request->actual == request->length) {
  462. musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
  463. csr |= MUSB_CSR0_P_DATAEND;
  464. } else
  465. request = NULL;
  466. /* report completions as soon as the fifo's loaded; there's no
  467. * win in waiting till this last packet gets acked. (other than
  468. * very precise fault reporting, needed by USB TMC; possible with
  469. * this hardware, but not usable from portable gadget drivers.)
  470. */
  471. if (request) {
  472. musb->ackpend = csr;
  473. musb_g_ep0_giveback(musb, request);
  474. if (!musb->ackpend)
  475. return;
  476. musb->ackpend = 0;
  477. }
  478. /* send it out, triggering a "txpktrdy cleared" irq */
  479. musb_ep_select(musb->mregs, 0);
  480. musb_writew(regs, MUSB_CSR0, csr);
  481. }
  482. /*
  483. * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
  484. * Fields are left in USB byte-order.
  485. *
  486. * Context: caller holds controller lock.
  487. */
  488. static void
  489. musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
  490. {
  491. struct usb_request *r;
  492. void __iomem *regs = musb->control_ep->regs;
  493. musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
  494. /* NOTE: earlier 2.6 versions changed setup packets to host
  495. * order, but now USB packets always stay in USB byte order.
  496. */
  497. DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
  498. req->bRequestType,
  499. req->bRequest,
  500. le16_to_cpu(req->wValue),
  501. le16_to_cpu(req->wIndex),
  502. le16_to_cpu(req->wLength));
  503. /* clean up any leftover transfers */
  504. r = next_ep0_request(musb);
  505. if (r)
  506. musb_g_ep0_giveback(musb, r);
  507. /* For zero-data requests we want to delay the STATUS stage to
  508. * avoid SETUPEND errors. If we read data (OUT), delay accepting
  509. * packets until there's a buffer to store them in.
  510. *
  511. * If we write data, the controller acts happier if we enable
  512. * the TX FIFO right away, and give the controller a moment
  513. * to switch modes...
  514. */
  515. musb->set_address = false;
  516. musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
  517. if (req->wLength == 0) {
  518. if (req->bRequestType & USB_DIR_IN)
  519. musb->ackpend |= MUSB_CSR0_TXPKTRDY;
  520. musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
  521. } else if (req->bRequestType & USB_DIR_IN) {
  522. musb->ep0_state = MUSB_EP0_STAGE_TX;
  523. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
  524. while ((musb_readw(regs, MUSB_CSR0)
  525. & MUSB_CSR0_RXPKTRDY) != 0)
  526. cpu_relax();
  527. musb->ackpend = 0;
  528. } else
  529. musb->ep0_state = MUSB_EP0_STAGE_RX;
  530. }
  531. static int
  532. forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  533. __releases(musb->lock)
  534. __acquires(musb->lock)
  535. {
  536. int retval;
  537. if (!musb->gadget_driver)
  538. return -EOPNOTSUPP;
  539. spin_unlock(&musb->lock);
  540. retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
  541. spin_lock(&musb->lock);
  542. return retval;
  543. }
  544. /*
  545. * Handle peripheral ep0 interrupt
  546. *
  547. * Context: irq handler; we won't re-enter the driver that way.
  548. */
  549. irqreturn_t musb_g_ep0_irq(struct musb *musb)
  550. {
  551. u16 csr;
  552. u16 len;
  553. void __iomem *mbase = musb->mregs;
  554. void __iomem *regs = musb->endpoints[0].regs;
  555. irqreturn_t retval = IRQ_NONE;
  556. musb_ep_select(mbase, 0); /* select ep0 */
  557. csr = musb_readw(regs, MUSB_CSR0);
  558. len = musb_readb(regs, MUSB_COUNT0);
  559. DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
  560. csr, len,
  561. musb_readb(mbase, MUSB_FADDR),
  562. decode_ep0stage(musb->ep0_state));
  563. /* I sent a stall.. need to acknowledge it now.. */
  564. if (csr & MUSB_CSR0_P_SENTSTALL) {
  565. musb_writew(regs, MUSB_CSR0,
  566. csr & ~MUSB_CSR0_P_SENTSTALL);
  567. retval = IRQ_HANDLED;
  568. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  569. csr = musb_readw(regs, MUSB_CSR0);
  570. }
  571. /* request ended "early" */
  572. if (csr & MUSB_CSR0_P_SETUPEND) {
  573. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
  574. retval = IRQ_HANDLED;
  575. /* Transition into the early status phase */
  576. switch (musb->ep0_state) {
  577. case MUSB_EP0_STAGE_TX:
  578. musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
  579. break;
  580. case MUSB_EP0_STAGE_RX:
  581. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  582. break;
  583. default:
  584. ERR("SetupEnd came in a wrong ep0stage %s",
  585. decode_ep0stage(musb->ep0_state));
  586. }
  587. csr = musb_readw(regs, MUSB_CSR0);
  588. /* NOTE: request may need completion */
  589. }
  590. /* docs from Mentor only describe tx, rx, and idle/setup states.
  591. * we need to handle nuances around status stages, and also the
  592. * case where status and setup stages come back-to-back ...
  593. */
  594. switch (musb->ep0_state) {
  595. case MUSB_EP0_STAGE_TX:
  596. /* irq on clearing txpktrdy */
  597. if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
  598. ep0_txstate(musb);
  599. retval = IRQ_HANDLED;
  600. }
  601. break;
  602. case MUSB_EP0_STAGE_RX:
  603. /* irq on set rxpktrdy */
  604. if (csr & MUSB_CSR0_RXPKTRDY) {
  605. ep0_rxstate(musb);
  606. retval = IRQ_HANDLED;
  607. }
  608. break;
  609. case MUSB_EP0_STAGE_STATUSIN:
  610. /* end of sequence #2 (OUT/RX state) or #3 (no data) */
  611. /* update address (if needed) only @ the end of the
  612. * status phase per usb spec, which also guarantees
  613. * we get 10 msec to receive this irq... until this
  614. * is done we won't see the next packet.
  615. */
  616. if (musb->set_address) {
  617. musb->set_address = false;
  618. musb_writeb(mbase, MUSB_FADDR, musb->address);
  619. }
  620. /* enter test mode if needed (exit by reset) */
  621. else if (musb->test_mode) {
  622. DBG(1, "entering TESTMODE\n");
  623. if (MUSB_TEST_PACKET == musb->test_mode_nr)
  624. musb_load_testpacket(musb);
  625. musb_writeb(mbase, MUSB_TESTMODE,
  626. musb->test_mode_nr);
  627. }
  628. /* FALLTHROUGH */
  629. case MUSB_EP0_STAGE_STATUSOUT:
  630. /* end of sequence #1: write to host (TX state) */
  631. {
  632. struct usb_request *req;
  633. req = next_ep0_request(musb);
  634. if (req)
  635. musb_g_ep0_giveback(musb, req);
  636. }
  637. /*
  638. * In case when several interrupts can get coalesced,
  639. * check to see if we've already received a SETUP packet...
  640. */
  641. if (csr & MUSB_CSR0_RXPKTRDY)
  642. goto setup;
  643. retval = IRQ_HANDLED;
  644. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  645. break;
  646. case MUSB_EP0_STAGE_IDLE:
  647. /*
  648. * This state is typically (but not always) indiscernible
  649. * from the status states since the corresponding interrupts
  650. * tend to happen within too little period of time (with only
  651. * a zero-length packet in between) and so get coalesced...
  652. */
  653. retval = IRQ_HANDLED;
  654. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  655. /* FALLTHROUGH */
  656. case MUSB_EP0_STAGE_SETUP:
  657. setup:
  658. if (csr & MUSB_CSR0_RXPKTRDY) {
  659. struct usb_ctrlrequest setup;
  660. int handled = 0;
  661. if (len != 8) {
  662. ERR("SETUP packet len %d != 8 ?\n", len);
  663. break;
  664. }
  665. musb_read_setup(musb, &setup);
  666. retval = IRQ_HANDLED;
  667. /* sometimes the RESET won't be reported */
  668. if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
  669. u8 power;
  670. printk(KERN_NOTICE "%s: peripheral reset "
  671. "irq lost!\n",
  672. musb_driver_name);
  673. power = musb_readb(mbase, MUSB_POWER);
  674. musb->g.speed = (power & MUSB_POWER_HSMODE)
  675. ? USB_SPEED_HIGH : USB_SPEED_FULL;
  676. }
  677. switch (musb->ep0_state) {
  678. /* sequence #3 (no data stage), includes requests
  679. * we can't forward (notably SET_ADDRESS and the
  680. * device/endpoint feature set/clear operations)
  681. * plus SET_CONFIGURATION and others we must
  682. */
  683. case MUSB_EP0_STAGE_ACKWAIT:
  684. handled = service_zero_data_request(
  685. musb, &setup);
  686. /* status stage might be immediate */
  687. if (handled > 0) {
  688. musb->ackpend |= MUSB_CSR0_P_DATAEND;
  689. musb->ep0_state =
  690. MUSB_EP0_STAGE_STATUSIN;
  691. }
  692. break;
  693. /* sequence #1 (IN to host), includes GET_STATUS
  694. * requests that we can't forward, GET_DESCRIPTOR
  695. * and others that we must
  696. */
  697. case MUSB_EP0_STAGE_TX:
  698. handled = service_in_request(musb, &setup);
  699. if (handled > 0) {
  700. musb->ackpend = MUSB_CSR0_TXPKTRDY
  701. | MUSB_CSR0_P_DATAEND;
  702. musb->ep0_state =
  703. MUSB_EP0_STAGE_STATUSOUT;
  704. }
  705. break;
  706. /* sequence #2 (OUT from host), always forward */
  707. default: /* MUSB_EP0_STAGE_RX */
  708. break;
  709. }
  710. DBG(3, "handled %d, csr %04x, ep0stage %s\n",
  711. handled, csr,
  712. decode_ep0stage(musb->ep0_state));
  713. /* unless we need to delegate this to the gadget
  714. * driver, we know how to wrap this up: csr0 has
  715. * not yet been written.
  716. */
  717. if (handled < 0)
  718. goto stall;
  719. else if (handled > 0)
  720. goto finish;
  721. handled = forward_to_driver(musb, &setup);
  722. if (handled < 0) {
  723. musb_ep_select(mbase, 0);
  724. stall:
  725. DBG(3, "stall (%d)\n", handled);
  726. musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
  727. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  728. finish:
  729. musb_writew(regs, MUSB_CSR0,
  730. musb->ackpend);
  731. musb->ackpend = 0;
  732. }
  733. }
  734. break;
  735. case MUSB_EP0_STAGE_ACKWAIT:
  736. /* This should not happen. But happens with tusb6010 with
  737. * g_file_storage and high speed. Do nothing.
  738. */
  739. retval = IRQ_HANDLED;
  740. break;
  741. default:
  742. /* "can't happen" */
  743. WARN_ON(1);
  744. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
  745. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  746. break;
  747. }
  748. return retval;
  749. }
  750. static int
  751. musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
  752. {
  753. /* always enabled */
  754. return -EINVAL;
  755. }
  756. static int musb_g_ep0_disable(struct usb_ep *e)
  757. {
  758. /* always enabled */
  759. return -EINVAL;
  760. }
  761. static int
  762. musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
  763. {
  764. struct musb_ep *ep;
  765. struct musb_request *req;
  766. struct musb *musb;
  767. int status;
  768. unsigned long lockflags;
  769. void __iomem *regs;
  770. if (!e || !r)
  771. return -EINVAL;
  772. ep = to_musb_ep(e);
  773. musb = ep->musb;
  774. regs = musb->control_ep->regs;
  775. req = to_musb_request(r);
  776. req->musb = musb;
  777. req->request.actual = 0;
  778. req->request.status = -EINPROGRESS;
  779. req->tx = ep->is_in;
  780. spin_lock_irqsave(&musb->lock, lockflags);
  781. if (!list_empty(&ep->req_list)) {
  782. status = -EBUSY;
  783. goto cleanup;
  784. }
  785. switch (musb->ep0_state) {
  786. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  787. case MUSB_EP0_STAGE_TX: /* control-IN data */
  788. case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
  789. status = 0;
  790. break;
  791. default:
  792. DBG(1, "ep0 request queued in state %d\n",
  793. musb->ep0_state);
  794. status = -EINVAL;
  795. goto cleanup;
  796. }
  797. /* add request to the list */
  798. list_add_tail(&(req->request.list), &(ep->req_list));
  799. DBG(3, "queue to %s (%s), length=%d\n",
  800. ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
  801. req->request.length);
  802. musb_ep_select(musb->mregs, 0);
  803. /* sequence #1, IN ... start writing the data */
  804. if (musb->ep0_state == MUSB_EP0_STAGE_TX)
  805. ep0_txstate(musb);
  806. /* sequence #3, no-data ... issue IN status */
  807. else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
  808. if (req->request.length)
  809. status = -EINVAL;
  810. else {
  811. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  812. musb_writew(regs, MUSB_CSR0,
  813. musb->ackpend | MUSB_CSR0_P_DATAEND);
  814. musb->ackpend = 0;
  815. musb_g_ep0_giveback(ep->musb, r);
  816. }
  817. /* else for sequence #2 (OUT), caller provides a buffer
  818. * before the next packet arrives. deferred responses
  819. * (after SETUP is acked) are racey.
  820. */
  821. } else if (musb->ackpend) {
  822. musb_writew(regs, MUSB_CSR0, musb->ackpend);
  823. musb->ackpend = 0;
  824. }
  825. cleanup:
  826. spin_unlock_irqrestore(&musb->lock, lockflags);
  827. return status;
  828. }
  829. static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
  830. {
  831. /* we just won't support this */
  832. return -EINVAL;
  833. }
  834. static int musb_g_ep0_halt(struct usb_ep *e, int value)
  835. {
  836. struct musb_ep *ep;
  837. struct musb *musb;
  838. void __iomem *base, *regs;
  839. unsigned long flags;
  840. int status;
  841. u16 csr;
  842. if (!e || !value)
  843. return -EINVAL;
  844. ep = to_musb_ep(e);
  845. musb = ep->musb;
  846. base = musb->mregs;
  847. regs = musb->control_ep->regs;
  848. status = 0;
  849. spin_lock_irqsave(&musb->lock, flags);
  850. if (!list_empty(&ep->req_list)) {
  851. status = -EBUSY;
  852. goto cleanup;
  853. }
  854. musb_ep_select(base, 0);
  855. csr = musb->ackpend;
  856. switch (musb->ep0_state) {
  857. /* Stalls are usually issued after parsing SETUP packet, either
  858. * directly in irq context from setup() or else later.
  859. */
  860. case MUSB_EP0_STAGE_TX: /* control-IN data */
  861. case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
  862. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  863. csr = musb_readw(regs, MUSB_CSR0);
  864. /* FALLTHROUGH */
  865. /* It's also OK to issue stalls during callbacks when a non-empty
  866. * DATA stage buffer has been read (or even written).
  867. */
  868. case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
  869. case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
  870. csr |= MUSB_CSR0_P_SENDSTALL;
  871. musb_writew(regs, MUSB_CSR0, csr);
  872. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  873. musb->ackpend = 0;
  874. break;
  875. default:
  876. DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
  877. status = -EINVAL;
  878. }
  879. cleanup:
  880. spin_unlock_irqrestore(&musb->lock, flags);
  881. return status;
  882. }
  883. const struct usb_ep_ops musb_g_ep0_ops = {
  884. .enable = musb_g_ep0_enable,
  885. .disable = musb_g_ep0_disable,
  886. .alloc_request = musb_alloc_request,
  887. .free_request = musb_free_request,
  888. .queue = musb_g_ep0_queue,
  889. .dequeue = musb_g_ep0_dequeue,
  890. .set_halt = musb_g_ep0_halt,
  891. };