uhci-hcd.c 27 KB

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  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
  17. *
  18. * Intel documents this fairly well, and as far as I know there
  19. * are no royalties or anything like that, but even so there are
  20. * people who decided that they want to do the same thing in a
  21. * completely different way.
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/pci.h>
  26. #include <linux/kernel.h>
  27. #include <linux/init.h>
  28. #include <linux/delay.h>
  29. #include <linux/ioport.h>
  30. #include <linux/slab.h>
  31. #include <linux/errno.h>
  32. #include <linux/unistd.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/spinlock.h>
  35. #include <linux/debugfs.h>
  36. #include <linux/pm.h>
  37. #include <linux/dmapool.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/usb.h>
  40. #include <linux/bitops.h>
  41. #include <linux/dmi.h>
  42. #include <asm/uaccess.h>
  43. #include <asm/io.h>
  44. #include <asm/irq.h>
  45. #include <asm/system.h>
  46. #include "../core/hcd.h"
  47. #include "uhci-hcd.h"
  48. #include "pci-quirks.h"
  49. /*
  50. * Version Information
  51. */
  52. #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
  53. Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
  54. Alan Stern"
  55. #define DRIVER_DESC "USB Universal Host Controller Interface driver"
  56. /* for flakey hardware, ignore overcurrent indicators */
  57. static int ignore_oc;
  58. module_param(ignore_oc, bool, S_IRUGO);
  59. MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications");
  60. /*
  61. * debug = 0, no debugging messages
  62. * debug = 1, dump failed URBs except for stalls
  63. * debug = 2, dump all failed URBs (including stalls)
  64. * show all queues in /debug/uhci/[pci_addr]
  65. * debug = 3, show all TDs in URBs when dumping
  66. */
  67. #ifdef DEBUG
  68. #define DEBUG_CONFIGURED 1
  69. static int debug = 1;
  70. module_param(debug, int, S_IRUGO | S_IWUSR);
  71. MODULE_PARM_DESC(debug, "Debug level");
  72. #else
  73. #define DEBUG_CONFIGURED 0
  74. #define debug 0
  75. #endif
  76. static char *errbuf;
  77. #define ERRBUF_LEN (32 * 1024)
  78. static struct kmem_cache *uhci_up_cachep; /* urb_priv */
  79. static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state);
  80. static void wakeup_rh(struct uhci_hcd *uhci);
  81. static void uhci_get_current_frame_number(struct uhci_hcd *uhci);
  82. /*
  83. * Calculate the link pointer DMA value for the first Skeleton QH in a frame.
  84. */
  85. static __le32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame)
  86. {
  87. int skelnum;
  88. /*
  89. * The interrupt queues will be interleaved as evenly as possible.
  90. * There's not much to be done about period-1 interrupts; they have
  91. * to occur in every frame. But we can schedule period-2 interrupts
  92. * in odd-numbered frames, period-4 interrupts in frames congruent
  93. * to 2 (mod 4), and so on. This way each frame only has two
  94. * interrupt QHs, which will help spread out bandwidth utilization.
  95. *
  96. * ffs (Find First bit Set) does exactly what we need:
  97. * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8],
  98. * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc.
  99. * ffs >= 7 => not on any high-period queue, so use
  100. * period-1 QH = skelqh[9].
  101. * Add in UHCI_NUMFRAMES to insure at least one bit is set.
  102. */
  103. skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES);
  104. if (skelnum <= 1)
  105. skelnum = 9;
  106. return LINK_TO_QH(uhci->skelqh[skelnum]);
  107. }
  108. #include "uhci-debug.c"
  109. #include "uhci-q.c"
  110. #include "uhci-hub.c"
  111. /*
  112. * Finish up a host controller reset and update the recorded state.
  113. */
  114. static void finish_reset(struct uhci_hcd *uhci)
  115. {
  116. int port;
  117. /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
  118. * bits in the port status and control registers.
  119. * We have to clear them by hand.
  120. */
  121. for (port = 0; port < uhci->rh_numports; ++port)
  122. outw(0, uhci->io_addr + USBPORTSC1 + (port * 2));
  123. uhci->port_c_suspend = uhci->resuming_ports = 0;
  124. uhci->rh_state = UHCI_RH_RESET;
  125. uhci->is_stopped = UHCI_IS_STOPPED;
  126. uhci_to_hcd(uhci)->state = HC_STATE_HALT;
  127. uhci_to_hcd(uhci)->poll_rh = 0;
  128. uhci->dead = 0; /* Full reset resurrects the controller */
  129. }
  130. /*
  131. * Last rites for a defunct/nonfunctional controller
  132. * or one we don't want to use any more.
  133. */
  134. static void uhci_hc_died(struct uhci_hcd *uhci)
  135. {
  136. uhci_get_current_frame_number(uhci);
  137. uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr);
  138. finish_reset(uhci);
  139. uhci->dead = 1;
  140. /* The current frame may already be partway finished */
  141. ++uhci->frame_number;
  142. }
  143. /*
  144. * Initialize a controller that was newly discovered or has lost power
  145. * or otherwise been reset while it was suspended. In none of these cases
  146. * can we be sure of its previous state.
  147. */
  148. static void check_and_reset_hc(struct uhci_hcd *uhci)
  149. {
  150. if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr))
  151. finish_reset(uhci);
  152. }
  153. /*
  154. * Store the basic register settings needed by the controller.
  155. */
  156. static void configure_hc(struct uhci_hcd *uhci)
  157. {
  158. /* Set the frame length to the default: 1 ms exactly */
  159. outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF);
  160. /* Store the frame list base address */
  161. outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD);
  162. /* Set the current frame number */
  163. outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER,
  164. uhci->io_addr + USBFRNUM);
  165. /* Mark controller as not halted before we enable interrupts */
  166. uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED;
  167. mb();
  168. /* Enable PIRQ */
  169. pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
  170. USBLEGSUP_DEFAULT);
  171. }
  172. static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
  173. {
  174. int port;
  175. /* If we have to ignore overcurrent events then almost by definition
  176. * we can't depend on resume-detect interrupts. */
  177. if (ignore_oc)
  178. return 1;
  179. switch (to_pci_dev(uhci_dev(uhci))->vendor) {
  180. default:
  181. break;
  182. case PCI_VENDOR_ID_GENESYS:
  183. /* Genesys Logic's GL880S controllers don't generate
  184. * resume-detect interrupts.
  185. */
  186. return 1;
  187. case PCI_VENDOR_ID_INTEL:
  188. /* Some of Intel's USB controllers have a bug that causes
  189. * resume-detect interrupts if any port has an over-current
  190. * condition. To make matters worse, some motherboards
  191. * hardwire unused USB ports' over-current inputs active!
  192. * To prevent problems, we will not enable resume-detect
  193. * interrupts if any ports are OC.
  194. */
  195. for (port = 0; port < uhci->rh_numports; ++port) {
  196. if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
  197. USBPORTSC_OC)
  198. return 1;
  199. }
  200. break;
  201. }
  202. return 0;
  203. }
  204. static int global_suspend_mode_is_broken(struct uhci_hcd *uhci)
  205. {
  206. int port;
  207. const char *sys_info;
  208. static char bad_Asus_board[] = "A7V8X";
  209. /* One of Asus's motherboards has a bug which causes it to
  210. * wake up immediately from suspend-to-RAM if any of the ports
  211. * are connected. In such cases we will not set EGSM.
  212. */
  213. sys_info = dmi_get_system_info(DMI_BOARD_NAME);
  214. if (sys_info && !strcmp(sys_info, bad_Asus_board)) {
  215. for (port = 0; port < uhci->rh_numports; ++port) {
  216. if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
  217. USBPORTSC_CCS)
  218. return 1;
  219. }
  220. }
  221. return 0;
  222. }
  223. static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state)
  224. __releases(uhci->lock)
  225. __acquires(uhci->lock)
  226. {
  227. int auto_stop;
  228. int int_enable, egsm_enable, wakeup_enable;
  229. struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub;
  230. auto_stop = (new_state == UHCI_RH_AUTO_STOPPED);
  231. dev_dbg(&rhdev->dev, "%s%s\n", __func__,
  232. (auto_stop ? " (auto-stop)" : ""));
  233. /* Start off by assuming Resume-Detect interrupts and EGSM work
  234. * and that remote wakeups should be enabled.
  235. */
  236. egsm_enable = USBCMD_EGSM;
  237. uhci->RD_enable = 1;
  238. int_enable = USBINTR_RESUME;
  239. wakeup_enable = 1;
  240. /* In auto-stop mode wakeups must always be detected, but
  241. * Resume-Detect interrupts may be prohibited. (In the absence
  242. * of CONFIG_PM, they are always disallowed.)
  243. */
  244. if (auto_stop) {
  245. if (!device_may_wakeup(&rhdev->dev))
  246. int_enable = 0;
  247. /* In bus-suspend mode wakeups may be disabled, but if they are
  248. * allowed then so are Resume-Detect interrupts.
  249. */
  250. } else {
  251. #ifdef CONFIG_PM
  252. if (!rhdev->do_remote_wakeup)
  253. wakeup_enable = 0;
  254. #endif
  255. }
  256. /* EGSM causes the root hub to echo a 'K' signal (resume) out any
  257. * port which requests a remote wakeup. According to the USB spec,
  258. * every hub is supposed to do this. But if we are ignoring
  259. * remote-wakeup requests anyway then there's no point to it.
  260. * We also shouldn't enable EGSM if it's broken.
  261. */
  262. if (!wakeup_enable || global_suspend_mode_is_broken(uhci))
  263. egsm_enable = 0;
  264. /* If we're ignoring wakeup events then there's no reason to
  265. * enable Resume-Detect interrupts. We also shouldn't enable
  266. * them if they are broken or disallowed.
  267. *
  268. * This logic may lead us to enabling RD but not EGSM. The UHCI
  269. * spec foolishly says that RD works only when EGSM is on, but
  270. * there's no harm in enabling it anyway -- perhaps some chips
  271. * will implement it!
  272. */
  273. if (!wakeup_enable || resume_detect_interrupts_are_broken(uhci) ||
  274. !int_enable)
  275. uhci->RD_enable = int_enable = 0;
  276. outw(int_enable, uhci->io_addr + USBINTR);
  277. outw(egsm_enable | USBCMD_CF, uhci->io_addr + USBCMD);
  278. mb();
  279. udelay(5);
  280. /* If we're auto-stopping then no devices have been attached
  281. * for a while, so there shouldn't be any active URBs and the
  282. * controller should stop after a few microseconds. Otherwise
  283. * we will give the controller one frame to stop.
  284. */
  285. if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) {
  286. uhci->rh_state = UHCI_RH_SUSPENDING;
  287. spin_unlock_irq(&uhci->lock);
  288. msleep(1);
  289. spin_lock_irq(&uhci->lock);
  290. if (uhci->dead)
  291. return;
  292. }
  293. if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH))
  294. dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n");
  295. uhci_get_current_frame_number(uhci);
  296. uhci->rh_state = new_state;
  297. uhci->is_stopped = UHCI_IS_STOPPED;
  298. /* If interrupts don't work and remote wakeup is enabled then
  299. * the suspended root hub needs to be polled.
  300. */
  301. uhci_to_hcd(uhci)->poll_rh = (!int_enable && wakeup_enable);
  302. uhci_scan_schedule(uhci);
  303. uhci_fsbr_off(uhci);
  304. }
  305. static void start_rh(struct uhci_hcd *uhci)
  306. {
  307. uhci_to_hcd(uhci)->state = HC_STATE_RUNNING;
  308. uhci->is_stopped = 0;
  309. /* Mark it configured and running with a 64-byte max packet.
  310. * All interrupts are enabled, even though RESUME won't do anything.
  311. */
  312. outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD);
  313. outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP,
  314. uhci->io_addr + USBINTR);
  315. mb();
  316. uhci->rh_state = UHCI_RH_RUNNING;
  317. uhci_to_hcd(uhci)->poll_rh = 1;
  318. }
  319. static void wakeup_rh(struct uhci_hcd *uhci)
  320. __releases(uhci->lock)
  321. __acquires(uhci->lock)
  322. {
  323. dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev,
  324. "%s%s\n", __func__,
  325. uhci->rh_state == UHCI_RH_AUTO_STOPPED ?
  326. " (auto-start)" : "");
  327. /* If we are auto-stopped then no devices are attached so there's
  328. * no need for wakeup signals. Otherwise we send Global Resume
  329. * for 20 ms.
  330. */
  331. if (uhci->rh_state == UHCI_RH_SUSPENDED) {
  332. unsigned egsm;
  333. /* Keep EGSM on if it was set before */
  334. egsm = inw(uhci->io_addr + USBCMD) & USBCMD_EGSM;
  335. uhci->rh_state = UHCI_RH_RESUMING;
  336. outw(USBCMD_FGR | USBCMD_CF | egsm, uhci->io_addr + USBCMD);
  337. spin_unlock_irq(&uhci->lock);
  338. msleep(20);
  339. spin_lock_irq(&uhci->lock);
  340. if (uhci->dead)
  341. return;
  342. /* End Global Resume and wait for EOP to be sent */
  343. outw(USBCMD_CF, uhci->io_addr + USBCMD);
  344. mb();
  345. udelay(4);
  346. if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR)
  347. dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n");
  348. }
  349. start_rh(uhci);
  350. /* Restart root hub polling */
  351. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  352. }
  353. static irqreturn_t uhci_irq(struct usb_hcd *hcd)
  354. {
  355. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  356. unsigned short status;
  357. /*
  358. * Read the interrupt status, and write it back to clear the
  359. * interrupt cause. Contrary to the UHCI specification, the
  360. * "HC Halted" status bit is persistent: it is RO, not R/WC.
  361. */
  362. status = inw(uhci->io_addr + USBSTS);
  363. if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
  364. return IRQ_NONE;
  365. outw(status, uhci->io_addr + USBSTS); /* Clear it */
  366. if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
  367. if (status & USBSTS_HSE)
  368. dev_err(uhci_dev(uhci), "host system error, "
  369. "PCI problems?\n");
  370. if (status & USBSTS_HCPE)
  371. dev_err(uhci_dev(uhci), "host controller process "
  372. "error, something bad happened!\n");
  373. if (status & USBSTS_HCH) {
  374. spin_lock(&uhci->lock);
  375. if (uhci->rh_state >= UHCI_RH_RUNNING) {
  376. dev_err(uhci_dev(uhci),
  377. "host controller halted, "
  378. "very bad!\n");
  379. if (debug > 1 && errbuf) {
  380. /* Print the schedule for debugging */
  381. uhci_sprint_schedule(uhci,
  382. errbuf, ERRBUF_LEN);
  383. lprintk(errbuf);
  384. }
  385. uhci_hc_died(uhci);
  386. /* Force a callback in case there are
  387. * pending unlinks */
  388. mod_timer(&hcd->rh_timer, jiffies);
  389. }
  390. spin_unlock(&uhci->lock);
  391. }
  392. }
  393. if (status & USBSTS_RD)
  394. usb_hcd_poll_rh_status(hcd);
  395. else {
  396. spin_lock(&uhci->lock);
  397. uhci_scan_schedule(uhci);
  398. spin_unlock(&uhci->lock);
  399. }
  400. return IRQ_HANDLED;
  401. }
  402. /*
  403. * Store the current frame number in uhci->frame_number if the controller
  404. * is runnning. Expand from 11 bits (of which we use only 10) to a
  405. * full-sized integer.
  406. *
  407. * Like many other parts of the driver, this code relies on being polled
  408. * more than once per second as long as the controller is running.
  409. */
  410. static void uhci_get_current_frame_number(struct uhci_hcd *uhci)
  411. {
  412. if (!uhci->is_stopped) {
  413. unsigned delta;
  414. delta = (inw(uhci->io_addr + USBFRNUM) - uhci->frame_number) &
  415. (UHCI_NUMFRAMES - 1);
  416. uhci->frame_number += delta;
  417. }
  418. }
  419. /*
  420. * De-allocate all resources
  421. */
  422. static void release_uhci(struct uhci_hcd *uhci)
  423. {
  424. int i;
  425. if (DEBUG_CONFIGURED) {
  426. spin_lock_irq(&uhci->lock);
  427. uhci->is_initialized = 0;
  428. spin_unlock_irq(&uhci->lock);
  429. debugfs_remove(uhci->dentry);
  430. }
  431. for (i = 0; i < UHCI_NUM_SKELQH; i++)
  432. uhci_free_qh(uhci, uhci->skelqh[i]);
  433. uhci_free_td(uhci, uhci->term_td);
  434. dma_pool_destroy(uhci->qh_pool);
  435. dma_pool_destroy(uhci->td_pool);
  436. kfree(uhci->frame_cpu);
  437. dma_free_coherent(uhci_dev(uhci),
  438. UHCI_NUMFRAMES * sizeof(*uhci->frame),
  439. uhci->frame, uhci->frame_dma_handle);
  440. }
  441. static int uhci_init(struct usb_hcd *hcd)
  442. {
  443. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  444. unsigned io_size = (unsigned) hcd->rsrc_len;
  445. int port;
  446. uhci->io_addr = (unsigned long) hcd->rsrc_start;
  447. /* The UHCI spec says devices must have 2 ports, and goes on to say
  448. * they may have more but gives no way to determine how many there
  449. * are. However according to the UHCI spec, Bit 7 of the port
  450. * status and control register is always set to 1. So we try to
  451. * use this to our advantage. Another common failure mode when
  452. * a nonexistent register is addressed is to return all ones, so
  453. * we test for that also.
  454. */
  455. for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) {
  456. unsigned int portstatus;
  457. portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2));
  458. if (!(portstatus & 0x0080) || portstatus == 0xffff)
  459. break;
  460. }
  461. if (debug)
  462. dev_info(uhci_dev(uhci), "detected %d ports\n", port);
  463. /* Anything greater than 7 is weird so we'll ignore it. */
  464. if (port > UHCI_RH_MAXCHILD) {
  465. dev_info(uhci_dev(uhci), "port count misdetected? "
  466. "forcing to 2 ports\n");
  467. port = 2;
  468. }
  469. uhci->rh_numports = port;
  470. /* Kick BIOS off this hardware and reset if the controller
  471. * isn't already safely quiescent.
  472. */
  473. check_and_reset_hc(uhci);
  474. return 0;
  475. }
  476. /* Make sure the controller is quiescent and that we're not using it
  477. * any more. This is mainly for the benefit of programs which, like kexec,
  478. * expect the hardware to be idle: not doing DMA or generating IRQs.
  479. *
  480. * This routine may be called in a damaged or failing kernel. Hence we
  481. * do not acquire the spinlock before shutting down the controller.
  482. */
  483. static void uhci_shutdown(struct pci_dev *pdev)
  484. {
  485. struct usb_hcd *hcd = (struct usb_hcd *) pci_get_drvdata(pdev);
  486. uhci_hc_died(hcd_to_uhci(hcd));
  487. }
  488. /*
  489. * Allocate a frame list, and then setup the skeleton
  490. *
  491. * The hardware doesn't really know any difference
  492. * in the queues, but the order does matter for the
  493. * protocols higher up. The order in which the queues
  494. * are encountered by the hardware is:
  495. *
  496. * - All isochronous events are handled before any
  497. * of the queues. We don't do that here, because
  498. * we'll create the actual TD entries on demand.
  499. * - The first queue is the high-period interrupt queue.
  500. * - The second queue is the period-1 interrupt and async
  501. * (low-speed control, full-speed control, then bulk) queue.
  502. * - The third queue is the terminating bandwidth reclamation queue,
  503. * which contains no members, loops back to itself, and is present
  504. * only when FSBR is on and there are no full-speed control or bulk QHs.
  505. */
  506. static int uhci_start(struct usb_hcd *hcd)
  507. {
  508. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  509. int retval = -EBUSY;
  510. int i;
  511. struct dentry *dentry;
  512. hcd->uses_new_polling = 1;
  513. spin_lock_init(&uhci->lock);
  514. setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout,
  515. (unsigned long) uhci);
  516. INIT_LIST_HEAD(&uhci->idle_qh_list);
  517. init_waitqueue_head(&uhci->waitqh);
  518. if (DEBUG_CONFIGURED) {
  519. dentry = debugfs_create_file(hcd->self.bus_name,
  520. S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root,
  521. uhci, &uhci_debug_operations);
  522. if (!dentry) {
  523. dev_err(uhci_dev(uhci), "couldn't create uhci "
  524. "debugfs entry\n");
  525. retval = -ENOMEM;
  526. goto err_create_debug_entry;
  527. }
  528. uhci->dentry = dentry;
  529. }
  530. uhci->frame = dma_alloc_coherent(uhci_dev(uhci),
  531. UHCI_NUMFRAMES * sizeof(*uhci->frame),
  532. &uhci->frame_dma_handle, 0);
  533. if (!uhci->frame) {
  534. dev_err(uhci_dev(uhci), "unable to allocate "
  535. "consistent memory for frame list\n");
  536. goto err_alloc_frame;
  537. }
  538. memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame));
  539. uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu),
  540. GFP_KERNEL);
  541. if (!uhci->frame_cpu) {
  542. dev_err(uhci_dev(uhci), "unable to allocate "
  543. "memory for frame pointers\n");
  544. goto err_alloc_frame_cpu;
  545. }
  546. uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),
  547. sizeof(struct uhci_td), 16, 0);
  548. if (!uhci->td_pool) {
  549. dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");
  550. goto err_create_td_pool;
  551. }
  552. uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),
  553. sizeof(struct uhci_qh), 16, 0);
  554. if (!uhci->qh_pool) {
  555. dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");
  556. goto err_create_qh_pool;
  557. }
  558. uhci->term_td = uhci_alloc_td(uhci);
  559. if (!uhci->term_td) {
  560. dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");
  561. goto err_alloc_term_td;
  562. }
  563. for (i = 0; i < UHCI_NUM_SKELQH; i++) {
  564. uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL);
  565. if (!uhci->skelqh[i]) {
  566. dev_err(uhci_dev(uhci), "unable to allocate QH\n");
  567. goto err_alloc_skelqh;
  568. }
  569. }
  570. /*
  571. * 8 Interrupt queues; link all higher int queues to int1 = async
  572. */
  573. for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i)
  574. uhci->skelqh[i]->link = LINK_TO_QH(uhci->skel_async_qh);
  575. uhci->skel_async_qh->link = UHCI_PTR_TERM;
  576. uhci->skel_term_qh->link = LINK_TO_QH(uhci->skel_term_qh);
  577. /* This dummy TD is to work around a bug in Intel PIIX controllers */
  578. uhci_fill_td(uhci->term_td, 0, uhci_explen(0) |
  579. (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
  580. uhci->term_td->link = UHCI_PTR_TERM;
  581. uhci->skel_async_qh->element = uhci->skel_term_qh->element =
  582. LINK_TO_TD(uhci->term_td);
  583. /*
  584. * Fill the frame list: make all entries point to the proper
  585. * interrupt queue.
  586. */
  587. for (i = 0; i < UHCI_NUMFRAMES; i++) {
  588. /* Only place we don't use the frame list routines */
  589. uhci->frame[i] = uhci_frame_skel_link(uhci, i);
  590. }
  591. /*
  592. * Some architectures require a full mb() to enforce completion of
  593. * the memory writes above before the I/O transfers in configure_hc().
  594. */
  595. mb();
  596. configure_hc(uhci);
  597. uhci->is_initialized = 1;
  598. start_rh(uhci);
  599. return 0;
  600. /*
  601. * error exits:
  602. */
  603. err_alloc_skelqh:
  604. for (i = 0; i < UHCI_NUM_SKELQH; i++) {
  605. if (uhci->skelqh[i])
  606. uhci_free_qh(uhci, uhci->skelqh[i]);
  607. }
  608. uhci_free_td(uhci, uhci->term_td);
  609. err_alloc_term_td:
  610. dma_pool_destroy(uhci->qh_pool);
  611. err_create_qh_pool:
  612. dma_pool_destroy(uhci->td_pool);
  613. err_create_td_pool:
  614. kfree(uhci->frame_cpu);
  615. err_alloc_frame_cpu:
  616. dma_free_coherent(uhci_dev(uhci),
  617. UHCI_NUMFRAMES * sizeof(*uhci->frame),
  618. uhci->frame, uhci->frame_dma_handle);
  619. err_alloc_frame:
  620. debugfs_remove(uhci->dentry);
  621. err_create_debug_entry:
  622. return retval;
  623. }
  624. static void uhci_stop(struct usb_hcd *hcd)
  625. {
  626. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  627. spin_lock_irq(&uhci->lock);
  628. if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && !uhci->dead)
  629. uhci_hc_died(uhci);
  630. uhci_scan_schedule(uhci);
  631. spin_unlock_irq(&uhci->lock);
  632. del_timer_sync(&uhci->fsbr_timer);
  633. release_uhci(uhci);
  634. }
  635. #ifdef CONFIG_PM
  636. static int uhci_rh_suspend(struct usb_hcd *hcd)
  637. {
  638. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  639. int rc = 0;
  640. spin_lock_irq(&uhci->lock);
  641. if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
  642. rc = -ESHUTDOWN;
  643. else if (!uhci->dead)
  644. suspend_rh(uhci, UHCI_RH_SUSPENDED);
  645. spin_unlock_irq(&uhci->lock);
  646. return rc;
  647. }
  648. static int uhci_rh_resume(struct usb_hcd *hcd)
  649. {
  650. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  651. int rc = 0;
  652. spin_lock_irq(&uhci->lock);
  653. if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
  654. rc = -ESHUTDOWN;
  655. else if (!uhci->dead)
  656. wakeup_rh(uhci);
  657. spin_unlock_irq(&uhci->lock);
  658. return rc;
  659. }
  660. static int uhci_pci_suspend(struct usb_hcd *hcd)
  661. {
  662. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  663. int rc = 0;
  664. dev_dbg(uhci_dev(uhci), "%s\n", __func__);
  665. spin_lock_irq(&uhci->lock);
  666. if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) || uhci->dead)
  667. goto done_okay; /* Already suspended or dead */
  668. if (uhci->rh_state > UHCI_RH_SUSPENDED) {
  669. dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n");
  670. rc = -EBUSY;
  671. goto done;
  672. };
  673. /* All PCI host controllers are required to disable IRQ generation
  674. * at the source, so we must turn off PIRQ.
  675. */
  676. pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0);
  677. mb();
  678. hcd->poll_rh = 0;
  679. /* FIXME: Enable non-PME# remote wakeup? */
  680. done_okay:
  681. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  682. done:
  683. spin_unlock_irq(&uhci->lock);
  684. return rc;
  685. }
  686. static int uhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
  687. {
  688. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  689. dev_dbg(uhci_dev(uhci), "%s\n", __func__);
  690. /* Since we aren't in D3 any more, it's safe to set this flag
  691. * even if the controller was dead.
  692. */
  693. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  694. mb();
  695. spin_lock_irq(&uhci->lock);
  696. /* Make sure resume from hibernation re-enumerates everything */
  697. if (hibernated)
  698. uhci_hc_died(uhci);
  699. /* FIXME: Disable non-PME# remote wakeup? */
  700. /* The firmware or a boot kernel may have changed the controller
  701. * settings during a system wakeup. Check it and reconfigure
  702. * to avoid problems.
  703. */
  704. check_and_reset_hc(uhci);
  705. /* If the controller was dead before, it's back alive now */
  706. configure_hc(uhci);
  707. if (uhci->rh_state == UHCI_RH_RESET) {
  708. /* The controller had to be reset */
  709. usb_root_hub_lost_power(hcd->self.root_hub);
  710. suspend_rh(uhci, UHCI_RH_SUSPENDED);
  711. }
  712. spin_unlock_irq(&uhci->lock);
  713. /* If interrupts don't work and remote wakeup is enabled then
  714. * the suspended root hub needs to be polled.
  715. */
  716. if (!uhci->RD_enable && hcd->self.root_hub->do_remote_wakeup) {
  717. hcd->poll_rh = 1;
  718. usb_hcd_poll_rh_status(hcd);
  719. }
  720. return 0;
  721. }
  722. #endif
  723. /* Wait until a particular device/endpoint's QH is idle, and free it */
  724. static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd,
  725. struct usb_host_endpoint *hep)
  726. {
  727. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  728. struct uhci_qh *qh;
  729. spin_lock_irq(&uhci->lock);
  730. qh = (struct uhci_qh *) hep->hcpriv;
  731. if (qh == NULL)
  732. goto done;
  733. while (qh->state != QH_STATE_IDLE) {
  734. ++uhci->num_waiting;
  735. spin_unlock_irq(&uhci->lock);
  736. wait_event_interruptible(uhci->waitqh,
  737. qh->state == QH_STATE_IDLE);
  738. spin_lock_irq(&uhci->lock);
  739. --uhci->num_waiting;
  740. }
  741. uhci_free_qh(uhci, qh);
  742. done:
  743. spin_unlock_irq(&uhci->lock);
  744. }
  745. static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
  746. {
  747. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  748. unsigned frame_number;
  749. unsigned delta;
  750. /* Minimize latency by avoiding the spinlock */
  751. frame_number = uhci->frame_number;
  752. barrier();
  753. delta = (inw(uhci->io_addr + USBFRNUM) - frame_number) &
  754. (UHCI_NUMFRAMES - 1);
  755. return frame_number + delta;
  756. }
  757. static const char hcd_name[] = "uhci_hcd";
  758. static const struct hc_driver uhci_driver = {
  759. .description = hcd_name,
  760. .product_desc = "UHCI Host Controller",
  761. .hcd_priv_size = sizeof(struct uhci_hcd),
  762. /* Generic hardware linkage */
  763. .irq = uhci_irq,
  764. .flags = HCD_USB11,
  765. /* Basic lifecycle operations */
  766. .reset = uhci_init,
  767. .start = uhci_start,
  768. #ifdef CONFIG_PM
  769. .pci_suspend = uhci_pci_suspend,
  770. .pci_resume = uhci_pci_resume,
  771. .bus_suspend = uhci_rh_suspend,
  772. .bus_resume = uhci_rh_resume,
  773. #endif
  774. .stop = uhci_stop,
  775. .urb_enqueue = uhci_urb_enqueue,
  776. .urb_dequeue = uhci_urb_dequeue,
  777. .endpoint_disable = uhci_hcd_endpoint_disable,
  778. .get_frame_number = uhci_hcd_get_frame_number,
  779. .hub_status_data = uhci_hub_status_data,
  780. .hub_control = uhci_hub_control,
  781. };
  782. static const struct pci_device_id uhci_pci_ids[] = { {
  783. /* handle any USB UHCI controller */
  784. PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0),
  785. .driver_data = (unsigned long) &uhci_driver,
  786. }, { /* end: all zeroes */ }
  787. };
  788. MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
  789. static struct pci_driver uhci_pci_driver = {
  790. .name = (char *)hcd_name,
  791. .id_table = uhci_pci_ids,
  792. .probe = usb_hcd_pci_probe,
  793. .remove = usb_hcd_pci_remove,
  794. .shutdown = uhci_shutdown,
  795. #ifdef CONFIG_PM_SLEEP
  796. .driver = {
  797. .pm = &usb_hcd_pci_pm_ops
  798. },
  799. #endif
  800. };
  801. static int __init uhci_hcd_init(void)
  802. {
  803. int retval = -ENOMEM;
  804. if (usb_disabled())
  805. return -ENODEV;
  806. printk(KERN_INFO "uhci_hcd: " DRIVER_DESC "%s\n",
  807. ignore_oc ? ", overcurrent ignored" : "");
  808. set_bit(USB_UHCI_LOADED, &usb_hcds_loaded);
  809. if (DEBUG_CONFIGURED) {
  810. errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
  811. if (!errbuf)
  812. goto errbuf_failed;
  813. uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root);
  814. if (!uhci_debugfs_root)
  815. goto debug_failed;
  816. }
  817. uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
  818. sizeof(struct urb_priv), 0, 0, NULL);
  819. if (!uhci_up_cachep)
  820. goto up_failed;
  821. retval = pci_register_driver(&uhci_pci_driver);
  822. if (retval)
  823. goto init_failed;
  824. return 0;
  825. init_failed:
  826. kmem_cache_destroy(uhci_up_cachep);
  827. up_failed:
  828. debugfs_remove(uhci_debugfs_root);
  829. debug_failed:
  830. kfree(errbuf);
  831. errbuf_failed:
  832. clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded);
  833. return retval;
  834. }
  835. static void __exit uhci_hcd_cleanup(void)
  836. {
  837. pci_unregister_driver(&uhci_pci_driver);
  838. kmem_cache_destroy(uhci_up_cachep);
  839. debugfs_remove(uhci_debugfs_root);
  840. kfree(errbuf);
  841. clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded);
  842. }
  843. module_init(uhci_hcd_init);
  844. module_exit(uhci_hcd_cleanup);
  845. MODULE_AUTHOR(DRIVER_AUTHOR);
  846. MODULE_DESCRIPTION(DRIVER_DESC);
  847. MODULE_LICENSE("GPL");