ehci-mem.c 6.1 KB

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  1. /*
  2. * Copyright (c) 2001 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* this file is part of ehci-hcd.c */
  19. /*-------------------------------------------------------------------------*/
  20. /*
  21. * There's basically three types of memory:
  22. * - data used only by the HCD ... kmalloc is fine
  23. * - async and periodic schedules, shared by HC and HCD ... these
  24. * need to use dma_pool or dma_alloc_coherent
  25. * - driver buffers, read/written by HC ... single shot DMA mapped
  26. *
  27. * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
  28. * No memory seen by this driver is pageable.
  29. */
  30. /*-------------------------------------------------------------------------*/
  31. /* Allocate the key transfer structures from the previously allocated pool */
  32. static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
  33. dma_addr_t dma)
  34. {
  35. memset (qtd, 0, sizeof *qtd);
  36. qtd->qtd_dma = dma;
  37. qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
  38. qtd->hw_next = EHCI_LIST_END(ehci);
  39. qtd->hw_alt_next = EHCI_LIST_END(ehci);
  40. INIT_LIST_HEAD (&qtd->qtd_list);
  41. }
  42. static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
  43. {
  44. struct ehci_qtd *qtd;
  45. dma_addr_t dma;
  46. qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
  47. if (qtd != NULL) {
  48. ehci_qtd_init(ehci, qtd, dma);
  49. }
  50. return qtd;
  51. }
  52. static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
  53. {
  54. dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
  55. }
  56. static void qh_destroy(struct ehci_qh *qh)
  57. {
  58. struct ehci_hcd *ehci = qh->ehci;
  59. /* clean qtds first, and know this is not linked */
  60. if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
  61. ehci_dbg (ehci, "unused qh not empty!\n");
  62. BUG ();
  63. }
  64. if (qh->dummy)
  65. ehci_qtd_free (ehci, qh->dummy);
  66. dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
  67. }
  68. static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
  69. {
  70. struct ehci_qh *qh;
  71. dma_addr_t dma;
  72. qh = (struct ehci_qh *)
  73. dma_pool_alloc (ehci->qh_pool, flags, &dma);
  74. if (!qh)
  75. return qh;
  76. memset (qh, 0, sizeof *qh);
  77. qh->refcount = 1;
  78. qh->ehci = ehci;
  79. qh->qh_dma = dma;
  80. // INIT_LIST_HEAD (&qh->qh_list);
  81. INIT_LIST_HEAD (&qh->qtd_list);
  82. /* dummy td enables safe urb queuing */
  83. qh->dummy = ehci_qtd_alloc (ehci, flags);
  84. if (qh->dummy == NULL) {
  85. ehci_dbg (ehci, "no dummy td\n");
  86. dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
  87. qh = NULL;
  88. }
  89. return qh;
  90. }
  91. /* to share a qh (cpu threads, or hc) */
  92. static inline struct ehci_qh *qh_get (struct ehci_qh *qh)
  93. {
  94. WARN_ON(!qh->refcount);
  95. qh->refcount++;
  96. return qh;
  97. }
  98. static inline void qh_put (struct ehci_qh *qh)
  99. {
  100. if (!--qh->refcount)
  101. qh_destroy(qh);
  102. }
  103. /*-------------------------------------------------------------------------*/
  104. /* The queue heads and transfer descriptors are managed from pools tied
  105. * to each of the "per device" structures.
  106. * This is the initialisation and cleanup code.
  107. */
  108. static void ehci_mem_cleanup (struct ehci_hcd *ehci)
  109. {
  110. free_cached_itd_list(ehci);
  111. if (ehci->async)
  112. qh_put (ehci->async);
  113. ehci->async = NULL;
  114. /* DMA consistent memory and pools */
  115. if (ehci->qtd_pool)
  116. dma_pool_destroy (ehci->qtd_pool);
  117. ehci->qtd_pool = NULL;
  118. if (ehci->qh_pool) {
  119. dma_pool_destroy (ehci->qh_pool);
  120. ehci->qh_pool = NULL;
  121. }
  122. if (ehci->itd_pool)
  123. dma_pool_destroy (ehci->itd_pool);
  124. ehci->itd_pool = NULL;
  125. if (ehci->sitd_pool)
  126. dma_pool_destroy (ehci->sitd_pool);
  127. ehci->sitd_pool = NULL;
  128. if (ehci->periodic)
  129. dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
  130. ehci->periodic_size * sizeof (u32),
  131. ehci->periodic, ehci->periodic_dma);
  132. ehci->periodic = NULL;
  133. /* shadow periodic table */
  134. kfree(ehci->pshadow);
  135. ehci->pshadow = NULL;
  136. }
  137. /* remember to add cleanup code (above) if you add anything here */
  138. static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
  139. {
  140. int i;
  141. /* QTDs for control/bulk/intr transfers */
  142. ehci->qtd_pool = dma_pool_create ("ehci_qtd",
  143. ehci_to_hcd(ehci)->self.controller,
  144. sizeof (struct ehci_qtd),
  145. 32 /* byte alignment (for hw parts) */,
  146. 4096 /* can't cross 4K */);
  147. if (!ehci->qtd_pool) {
  148. goto fail;
  149. }
  150. /* QHs for control/bulk/intr transfers */
  151. ehci->qh_pool = dma_pool_create ("ehci_qh",
  152. ehci_to_hcd(ehci)->self.controller,
  153. sizeof (struct ehci_qh),
  154. 32 /* byte alignment (for hw parts) */,
  155. 4096 /* can't cross 4K */);
  156. if (!ehci->qh_pool) {
  157. goto fail;
  158. }
  159. ehci->async = ehci_qh_alloc (ehci, flags);
  160. if (!ehci->async) {
  161. goto fail;
  162. }
  163. /* ITD for high speed ISO transfers */
  164. ehci->itd_pool = dma_pool_create ("ehci_itd",
  165. ehci_to_hcd(ehci)->self.controller,
  166. sizeof (struct ehci_itd),
  167. 32 /* byte alignment (for hw parts) */,
  168. 4096 /* can't cross 4K */);
  169. if (!ehci->itd_pool) {
  170. goto fail;
  171. }
  172. /* SITD for full/low speed split ISO transfers */
  173. ehci->sitd_pool = dma_pool_create ("ehci_sitd",
  174. ehci_to_hcd(ehci)->self.controller,
  175. sizeof (struct ehci_sitd),
  176. 32 /* byte alignment (for hw parts) */,
  177. 4096 /* can't cross 4K */);
  178. if (!ehci->sitd_pool) {
  179. goto fail;
  180. }
  181. /* Hardware periodic table */
  182. ehci->periodic = (__le32 *)
  183. dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
  184. ehci->periodic_size * sizeof(__le32),
  185. &ehci->periodic_dma, 0);
  186. if (ehci->periodic == NULL) {
  187. goto fail;
  188. }
  189. for (i = 0; i < ehci->periodic_size; i++)
  190. ehci->periodic [i] = EHCI_LIST_END(ehci);
  191. /* software shadow of hardware table */
  192. ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
  193. if (ehci->pshadow != NULL)
  194. return 0;
  195. fail:
  196. ehci_dbg (ehci, "couldn't init memory\n");
  197. ehci_mem_cleanup (ehci);
  198. return -ENOMEM;
  199. }