dpt_i2o.c 94 KB

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  1. /***************************************************************************
  2. dpti.c - description
  3. -------------------
  4. begin : Thu Sep 7 2000
  5. copyright : (C) 2000 by Adaptec
  6. July 30, 2001 First version being submitted
  7. for inclusion in the kernel. V2.4
  8. See Documentation/scsi/dpti.txt for history, notes, license info
  9. and credits
  10. ***************************************************************************/
  11. /***************************************************************************
  12. * *
  13. * This program is free software; you can redistribute it and/or modify *
  14. * it under the terms of the GNU General Public License as published by *
  15. * the Free Software Foundation; either version 2 of the License, or *
  16. * (at your option) any later version. *
  17. * *
  18. ***************************************************************************/
  19. /***************************************************************************
  20. * Sat Dec 20 2003 Go Taniguchi <go@turbolinux.co.jp>
  21. - Support 2.6 kernel and DMA-mapping
  22. - ioctl fix for raid tools
  23. - use schedule_timeout in long long loop
  24. **************************************************************************/
  25. /*#define DEBUG 1 */
  26. /*#define UARTDELAY 1 */
  27. #include <linux/module.h>
  28. MODULE_AUTHOR("Deanna Bonds, with _lots_ of help from Mark Salyzyn");
  29. MODULE_DESCRIPTION("Adaptec I2O RAID Driver");
  30. ////////////////////////////////////////////////////////////////
  31. #include <linux/ioctl.h> /* For SCSI-Passthrough */
  32. #include <asm/uaccess.h>
  33. #include <linux/stat.h>
  34. #include <linux/slab.h> /* for kmalloc() */
  35. #include <linux/pci.h> /* for PCI support */
  36. #include <linux/proc_fs.h>
  37. #include <linux/blkdev.h>
  38. #include <linux/delay.h> /* for udelay */
  39. #include <linux/interrupt.h>
  40. #include <linux/kernel.h> /* for printk */
  41. #include <linux/sched.h>
  42. #include <linux/reboot.h>
  43. #include <linux/smp_lock.h>
  44. #include <linux/spinlock.h>
  45. #include <linux/dma-mapping.h>
  46. #include <linux/timer.h>
  47. #include <linux/string.h>
  48. #include <linux/ioport.h>
  49. #include <linux/mutex.h>
  50. #include <asm/processor.h> /* for boot_cpu_data */
  51. #include <asm/pgtable.h>
  52. #include <asm/io.h> /* for virt_to_bus, etc. */
  53. #include <scsi/scsi.h>
  54. #include <scsi/scsi_cmnd.h>
  55. #include <scsi/scsi_device.h>
  56. #include <scsi/scsi_host.h>
  57. #include <scsi/scsi_tcq.h>
  58. #include "dpt/dptsig.h"
  59. #include "dpti.h"
  60. /*============================================================================
  61. * Create a binary signature - this is read by dptsig
  62. * Needed for our management apps
  63. *============================================================================
  64. */
  65. static dpt_sig_S DPTI_sig = {
  66. {'d', 'P', 't', 'S', 'i', 'G'}, SIG_VERSION,
  67. #ifdef __i386__
  68. PROC_INTEL, PROC_386 | PROC_486 | PROC_PENTIUM | PROC_SEXIUM,
  69. #elif defined(__ia64__)
  70. PROC_INTEL, PROC_IA64,
  71. #elif defined(__sparc__)
  72. PROC_ULTRASPARC, PROC_ULTRASPARC,
  73. #elif defined(__alpha__)
  74. PROC_ALPHA, PROC_ALPHA,
  75. #else
  76. (-1),(-1),
  77. #endif
  78. FT_HBADRVR, 0, OEM_DPT, OS_LINUX, CAP_OVERLAP, DEV_ALL,
  79. ADF_ALL_SC5, 0, 0, DPT_VERSION, DPT_REVISION, DPT_SUBREVISION,
  80. DPT_MONTH, DPT_DAY, DPT_YEAR, "Adaptec Linux I2O RAID Driver"
  81. };
  82. /*============================================================================
  83. * Globals
  84. *============================================================================
  85. */
  86. static DEFINE_MUTEX(adpt_configuration_lock);
  87. static struct i2o_sys_tbl *sys_tbl;
  88. static dma_addr_t sys_tbl_pa;
  89. static int sys_tbl_ind;
  90. static int sys_tbl_len;
  91. static adpt_hba* hba_chain = NULL;
  92. static int hba_count = 0;
  93. static struct class *adpt_sysfs_class;
  94. #ifdef CONFIG_COMPAT
  95. static long compat_adpt_ioctl(struct file *, unsigned int, unsigned long);
  96. #endif
  97. static const struct file_operations adpt_fops = {
  98. .ioctl = adpt_ioctl,
  99. .open = adpt_open,
  100. .release = adpt_close,
  101. #ifdef CONFIG_COMPAT
  102. .compat_ioctl = compat_adpt_ioctl,
  103. #endif
  104. };
  105. /* Structures and definitions for synchronous message posting.
  106. * See adpt_i2o_post_wait() for description
  107. * */
  108. struct adpt_i2o_post_wait_data
  109. {
  110. int status;
  111. u32 id;
  112. adpt_wait_queue_head_t *wq;
  113. struct adpt_i2o_post_wait_data *next;
  114. };
  115. static struct adpt_i2o_post_wait_data *adpt_post_wait_queue = NULL;
  116. static u32 adpt_post_wait_id = 0;
  117. static DEFINE_SPINLOCK(adpt_post_wait_lock);
  118. /*============================================================================
  119. * Functions
  120. *============================================================================
  121. */
  122. static inline int dpt_dma64(adpt_hba *pHba)
  123. {
  124. return (sizeof(dma_addr_t) > 4 && (pHba)->dma64);
  125. }
  126. static inline u32 dma_high(dma_addr_t addr)
  127. {
  128. return upper_32_bits(addr);
  129. }
  130. static inline u32 dma_low(dma_addr_t addr)
  131. {
  132. return (u32)addr;
  133. }
  134. static u8 adpt_read_blink_led(adpt_hba* host)
  135. {
  136. if (host->FwDebugBLEDflag_P) {
  137. if( readb(host->FwDebugBLEDflag_P) == 0xbc ){
  138. return readb(host->FwDebugBLEDvalue_P);
  139. }
  140. }
  141. return 0;
  142. }
  143. /*============================================================================
  144. * Scsi host template interface functions
  145. *============================================================================
  146. */
  147. static struct pci_device_id dptids[] = {
  148. { PCI_DPT_VENDOR_ID, PCI_DPT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  149. { PCI_DPT_VENDOR_ID, PCI_DPT_RAPTOR_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  150. { 0, }
  151. };
  152. MODULE_DEVICE_TABLE(pci,dptids);
  153. static int adpt_detect(struct scsi_host_template* sht)
  154. {
  155. struct pci_dev *pDev = NULL;
  156. adpt_hba* pHba;
  157. PINFO("Detecting Adaptec I2O RAID controllers...\n");
  158. /* search for all Adatpec I2O RAID cards */
  159. while ((pDev = pci_get_device( PCI_DPT_VENDOR_ID, PCI_ANY_ID, pDev))) {
  160. if(pDev->device == PCI_DPT_DEVICE_ID ||
  161. pDev->device == PCI_DPT_RAPTOR_DEVICE_ID){
  162. if(adpt_install_hba(sht, pDev) ){
  163. PERROR("Could not Init an I2O RAID device\n");
  164. PERROR("Will not try to detect others.\n");
  165. return hba_count-1;
  166. }
  167. pci_dev_get(pDev);
  168. }
  169. }
  170. /* In INIT state, Activate IOPs */
  171. for (pHba = hba_chain; pHba; pHba = pHba->next) {
  172. // Activate does get status , init outbound, and get hrt
  173. if (adpt_i2o_activate_hba(pHba) < 0) {
  174. adpt_i2o_delete_hba(pHba);
  175. }
  176. }
  177. /* Active IOPs in HOLD state */
  178. rebuild_sys_tab:
  179. if (hba_chain == NULL)
  180. return 0;
  181. /*
  182. * If build_sys_table fails, we kill everything and bail
  183. * as we can't init the IOPs w/o a system table
  184. */
  185. if (adpt_i2o_build_sys_table() < 0) {
  186. adpt_i2o_sys_shutdown();
  187. return 0;
  188. }
  189. PDEBUG("HBA's in HOLD state\n");
  190. /* If IOP don't get online, we need to rebuild the System table */
  191. for (pHba = hba_chain; pHba; pHba = pHba->next) {
  192. if (adpt_i2o_online_hba(pHba) < 0) {
  193. adpt_i2o_delete_hba(pHba);
  194. goto rebuild_sys_tab;
  195. }
  196. }
  197. /* Active IOPs now in OPERATIONAL state */
  198. PDEBUG("HBA's in OPERATIONAL state\n");
  199. printk("dpti: If you have a lot of devices this could take a few minutes.\n");
  200. for (pHba = hba_chain; pHba; pHba = pHba->next) {
  201. printk(KERN_INFO"%s: Reading the hardware resource table.\n", pHba->name);
  202. if (adpt_i2o_lct_get(pHba) < 0){
  203. adpt_i2o_delete_hba(pHba);
  204. continue;
  205. }
  206. if (adpt_i2o_parse_lct(pHba) < 0){
  207. adpt_i2o_delete_hba(pHba);
  208. continue;
  209. }
  210. adpt_inquiry(pHba);
  211. }
  212. adpt_sysfs_class = class_create(THIS_MODULE, "dpt_i2o");
  213. if (IS_ERR(adpt_sysfs_class)) {
  214. printk(KERN_WARNING"dpti: unable to create dpt_i2o class\n");
  215. adpt_sysfs_class = NULL;
  216. }
  217. for (pHba = hba_chain; pHba; pHba = pHba->next) {
  218. if (adpt_scsi_host_alloc(pHba, sht) < 0){
  219. adpt_i2o_delete_hba(pHba);
  220. continue;
  221. }
  222. pHba->initialized = TRUE;
  223. pHba->state &= ~DPTI_STATE_RESET;
  224. if (adpt_sysfs_class) {
  225. struct device *dev = device_create(adpt_sysfs_class,
  226. NULL, MKDEV(DPTI_I2O_MAJOR, pHba->unit), NULL,
  227. "dpti%d", pHba->unit);
  228. if (IS_ERR(dev)) {
  229. printk(KERN_WARNING"dpti%d: unable to "
  230. "create device in dpt_i2o class\n",
  231. pHba->unit);
  232. }
  233. }
  234. }
  235. // Register our control device node
  236. // nodes will need to be created in /dev to access this
  237. // the nodes can not be created from within the driver
  238. if (hba_count && register_chrdev(DPTI_I2O_MAJOR, DPT_DRIVER, &adpt_fops)) {
  239. adpt_i2o_sys_shutdown();
  240. return 0;
  241. }
  242. return hba_count;
  243. }
  244. /*
  245. * scsi_unregister will be called AFTER we return.
  246. */
  247. static int adpt_release(struct Scsi_Host *host)
  248. {
  249. adpt_hba* pHba = (adpt_hba*) host->hostdata[0];
  250. // adpt_i2o_quiesce_hba(pHba);
  251. adpt_i2o_delete_hba(pHba);
  252. scsi_unregister(host);
  253. return 0;
  254. }
  255. static void adpt_inquiry(adpt_hba* pHba)
  256. {
  257. u32 msg[17];
  258. u32 *mptr;
  259. u32 *lenptr;
  260. int direction;
  261. int scsidir;
  262. u32 len;
  263. u32 reqlen;
  264. u8* buf;
  265. dma_addr_t addr;
  266. u8 scb[16];
  267. s32 rcode;
  268. memset(msg, 0, sizeof(msg));
  269. buf = dma_alloc_coherent(&pHba->pDev->dev, 80, &addr, GFP_KERNEL);
  270. if(!buf){
  271. printk(KERN_ERR"%s: Could not allocate buffer\n",pHba->name);
  272. return;
  273. }
  274. memset((void*)buf, 0, 36);
  275. len = 36;
  276. direction = 0x00000000;
  277. scsidir =0x40000000; // DATA IN (iop<--dev)
  278. if (dpt_dma64(pHba))
  279. reqlen = 17; // SINGLE SGE, 64 bit
  280. else
  281. reqlen = 14; // SINGLE SGE, 32 bit
  282. /* Stick the headers on */
  283. msg[0] = reqlen<<16 | SGL_OFFSET_12;
  284. msg[1] = (0xff<<24|HOST_TID<<12|ADAPTER_TID);
  285. msg[2] = 0;
  286. msg[3] = 0;
  287. // Adaptec/DPT Private stuff
  288. msg[4] = I2O_CMD_SCSI_EXEC|DPT_ORGANIZATION_ID<<16;
  289. msg[5] = ADAPTER_TID | 1<<16 /* Interpret*/;
  290. /* Direction, disconnect ok | sense data | simple queue , CDBLen */
  291. // I2O_SCB_FLAG_ENABLE_DISCONNECT |
  292. // I2O_SCB_FLAG_SIMPLE_QUEUE_TAG |
  293. // I2O_SCB_FLAG_SENSE_DATA_IN_MESSAGE;
  294. msg[6] = scsidir|0x20a00000| 6 /* cmd len*/;
  295. mptr=msg+7;
  296. memset(scb, 0, sizeof(scb));
  297. // Write SCSI command into the message - always 16 byte block
  298. scb[0] = INQUIRY;
  299. scb[1] = 0;
  300. scb[2] = 0;
  301. scb[3] = 0;
  302. scb[4] = 36;
  303. scb[5] = 0;
  304. // Don't care about the rest of scb
  305. memcpy(mptr, scb, sizeof(scb));
  306. mptr+=4;
  307. lenptr=mptr++; /* Remember me - fill in when we know */
  308. /* Now fill in the SGList and command */
  309. *lenptr = len;
  310. if (dpt_dma64(pHba)) {
  311. *mptr++ = (0x7C<<24)+(2<<16)+0x02; /* Enable 64 bit */
  312. *mptr++ = 1 << PAGE_SHIFT;
  313. *mptr++ = 0xD0000000|direction|len;
  314. *mptr++ = dma_low(addr);
  315. *mptr++ = dma_high(addr);
  316. } else {
  317. *mptr++ = 0xD0000000|direction|len;
  318. *mptr++ = addr;
  319. }
  320. // Send it on it's way
  321. rcode = adpt_i2o_post_wait(pHba, msg, reqlen<<2, 120);
  322. if (rcode != 0) {
  323. sprintf(pHba->detail, "Adaptec I2O RAID");
  324. printk(KERN_INFO "%s: Inquiry Error (%d)\n",pHba->name,rcode);
  325. if (rcode != -ETIME && rcode != -EINTR)
  326. dma_free_coherent(&pHba->pDev->dev, 80, buf, addr);
  327. } else {
  328. memset(pHba->detail, 0, sizeof(pHba->detail));
  329. memcpy(&(pHba->detail), "Vendor: Adaptec ", 16);
  330. memcpy(&(pHba->detail[16]), " Model: ", 8);
  331. memcpy(&(pHba->detail[24]), (u8*) &buf[16], 16);
  332. memcpy(&(pHba->detail[40]), " FW: ", 4);
  333. memcpy(&(pHba->detail[44]), (u8*) &buf[32], 4);
  334. pHba->detail[48] = '\0'; /* precautionary */
  335. dma_free_coherent(&pHba->pDev->dev, 80, buf, addr);
  336. }
  337. adpt_i2o_status_get(pHba);
  338. return ;
  339. }
  340. static int adpt_slave_configure(struct scsi_device * device)
  341. {
  342. struct Scsi_Host *host = device->host;
  343. adpt_hba* pHba;
  344. pHba = (adpt_hba *) host->hostdata[0];
  345. if (host->can_queue && device->tagged_supported) {
  346. scsi_adjust_queue_depth(device, MSG_SIMPLE_TAG,
  347. host->can_queue - 1);
  348. } else {
  349. scsi_adjust_queue_depth(device, 0, 1);
  350. }
  351. return 0;
  352. }
  353. static int adpt_queue(struct scsi_cmnd * cmd, void (*done) (struct scsi_cmnd *))
  354. {
  355. adpt_hba* pHba = NULL;
  356. struct adpt_device* pDev = NULL; /* dpt per device information */
  357. cmd->scsi_done = done;
  358. /*
  359. * SCSI REQUEST_SENSE commands will be executed automatically by the
  360. * Host Adapter for any errors, so they should not be executed
  361. * explicitly unless the Sense Data is zero indicating that no error
  362. * occurred.
  363. */
  364. if ((cmd->cmnd[0] == REQUEST_SENSE) && (cmd->sense_buffer[0] != 0)) {
  365. cmd->result = (DID_OK << 16);
  366. cmd->scsi_done(cmd);
  367. return 0;
  368. }
  369. pHba = (adpt_hba*)cmd->device->host->hostdata[0];
  370. if (!pHba) {
  371. return FAILED;
  372. }
  373. rmb();
  374. /*
  375. * TODO: I need to block here if I am processing ioctl cmds
  376. * but if the outstanding cmds all finish before the ioctl,
  377. * the scsi-core will not know to start sending cmds to me again.
  378. * I need to a way to restart the scsi-cores queues or should I block
  379. * calling scsi_done on the outstanding cmds instead
  380. * for now we don't set the IOCTL state
  381. */
  382. if(((pHba->state) & DPTI_STATE_IOCTL) || ((pHba->state) & DPTI_STATE_RESET)) {
  383. pHba->host->last_reset = jiffies;
  384. pHba->host->resetting = 1;
  385. return 1;
  386. }
  387. // TODO if the cmd->device if offline then I may need to issue a bus rescan
  388. // followed by a get_lct to see if the device is there anymore
  389. if((pDev = (struct adpt_device*) (cmd->device->hostdata)) == NULL) {
  390. /*
  391. * First command request for this device. Set up a pointer
  392. * to the device structure. This should be a TEST_UNIT_READY
  393. * command from scan_scsis_single.
  394. */
  395. if ((pDev = adpt_find_device(pHba, (u32)cmd->device->channel, (u32)cmd->device->id, (u32)cmd->device->lun)) == NULL) {
  396. // TODO: if any luns are at this bus, scsi id then fake a TEST_UNIT_READY and INQUIRY response
  397. // with type 7F (for all luns less than the max for this bus,id) so the lun scan will continue.
  398. cmd->result = (DID_NO_CONNECT << 16);
  399. cmd->scsi_done(cmd);
  400. return 0;
  401. }
  402. cmd->device->hostdata = pDev;
  403. }
  404. pDev->pScsi_dev = cmd->device;
  405. /*
  406. * If we are being called from when the device is being reset,
  407. * delay processing of the command until later.
  408. */
  409. if (pDev->state & DPTI_DEV_RESET ) {
  410. return FAILED;
  411. }
  412. return adpt_scsi_to_i2o(pHba, cmd, pDev);
  413. }
  414. static int adpt_bios_param(struct scsi_device *sdev, struct block_device *dev,
  415. sector_t capacity, int geom[])
  416. {
  417. int heads=-1;
  418. int sectors=-1;
  419. int cylinders=-1;
  420. // *** First lets set the default geometry ****
  421. // If the capacity is less than ox2000
  422. if (capacity < 0x2000 ) { // floppy
  423. heads = 18;
  424. sectors = 2;
  425. }
  426. // else if between 0x2000 and 0x20000
  427. else if (capacity < 0x20000) {
  428. heads = 64;
  429. sectors = 32;
  430. }
  431. // else if between 0x20000 and 0x40000
  432. else if (capacity < 0x40000) {
  433. heads = 65;
  434. sectors = 63;
  435. }
  436. // else if between 0x4000 and 0x80000
  437. else if (capacity < 0x80000) {
  438. heads = 128;
  439. sectors = 63;
  440. }
  441. // else if greater than 0x80000
  442. else {
  443. heads = 255;
  444. sectors = 63;
  445. }
  446. cylinders = sector_div(capacity, heads * sectors);
  447. // Special case if CDROM
  448. if(sdev->type == 5) { // CDROM
  449. heads = 252;
  450. sectors = 63;
  451. cylinders = 1111;
  452. }
  453. geom[0] = heads;
  454. geom[1] = sectors;
  455. geom[2] = cylinders;
  456. PDEBUG("adpt_bios_param: exit\n");
  457. return 0;
  458. }
  459. static const char *adpt_info(struct Scsi_Host *host)
  460. {
  461. adpt_hba* pHba;
  462. pHba = (adpt_hba *) host->hostdata[0];
  463. return (char *) (pHba->detail);
  464. }
  465. static int adpt_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
  466. int length, int inout)
  467. {
  468. struct adpt_device* d;
  469. int id;
  470. int chan;
  471. int len = 0;
  472. int begin = 0;
  473. int pos = 0;
  474. adpt_hba* pHba;
  475. int unit;
  476. *start = buffer;
  477. if (inout == TRUE) {
  478. /*
  479. * The user has done a write and wants us to take the
  480. * data in the buffer and do something with it.
  481. * proc_scsiwrite calls us with inout = 1
  482. *
  483. * Read data from buffer (writing to us) - NOT SUPPORTED
  484. */
  485. return -EINVAL;
  486. }
  487. /*
  488. * inout = 0 means the user has done a read and wants information
  489. * returned, so we write information about the cards into the buffer
  490. * proc_scsiread() calls us with inout = 0
  491. */
  492. // Find HBA (host bus adapter) we are looking for
  493. mutex_lock(&adpt_configuration_lock);
  494. for (pHba = hba_chain; pHba; pHba = pHba->next) {
  495. if (pHba->host == host) {
  496. break; /* found adapter */
  497. }
  498. }
  499. mutex_unlock(&adpt_configuration_lock);
  500. if (pHba == NULL) {
  501. return 0;
  502. }
  503. host = pHba->host;
  504. len = sprintf(buffer , "Adaptec I2O RAID Driver Version: %s\n\n", DPT_I2O_VERSION);
  505. len += sprintf(buffer+len, "%s\n", pHba->detail);
  506. len += sprintf(buffer+len, "SCSI Host=scsi%d Control Node=/dev/%s irq=%d\n",
  507. pHba->host->host_no, pHba->name, host->irq);
  508. len += sprintf(buffer+len, "\tpost fifo size = %d\n\treply fifo size = %d\n\tsg table size = %d\n\n",
  509. host->can_queue, (int) pHba->reply_fifo_size , host->sg_tablesize);
  510. pos = begin + len;
  511. /* CHECKPOINT */
  512. if(pos > offset + length) {
  513. goto stop_output;
  514. }
  515. if(pos <= offset) {
  516. /*
  517. * If we haven't even written to where we last left
  518. * off (the last time we were called), reset the
  519. * beginning pointer.
  520. */
  521. len = 0;
  522. begin = pos;
  523. }
  524. len += sprintf(buffer+len, "Devices:\n");
  525. for(chan = 0; chan < MAX_CHANNEL; chan++) {
  526. for(id = 0; id < MAX_ID; id++) {
  527. d = pHba->channel[chan].device[id];
  528. while(d){
  529. len += sprintf(buffer+len,"\t%-24.24s", d->pScsi_dev->vendor);
  530. len += sprintf(buffer+len," Rev: %-8.8s\n", d->pScsi_dev->rev);
  531. pos = begin + len;
  532. /* CHECKPOINT */
  533. if(pos > offset + length) {
  534. goto stop_output;
  535. }
  536. if(pos <= offset) {
  537. len = 0;
  538. begin = pos;
  539. }
  540. unit = d->pI2o_dev->lct_data.tid;
  541. len += sprintf(buffer+len, "\tTID=%d, (Channel=%d, Target=%d, Lun=%d) (%s)\n\n",
  542. unit, (int)d->scsi_channel, (int)d->scsi_id, (int)d->scsi_lun,
  543. scsi_device_online(d->pScsi_dev)? "online":"offline");
  544. pos = begin + len;
  545. /* CHECKPOINT */
  546. if(pos > offset + length) {
  547. goto stop_output;
  548. }
  549. if(pos <= offset) {
  550. len = 0;
  551. begin = pos;
  552. }
  553. d = d->next_lun;
  554. }
  555. }
  556. }
  557. /*
  558. * begin is where we last checked our position with regards to offset
  559. * begin is always less than offset. len is relative to begin. It
  560. * is the number of bytes written past begin
  561. *
  562. */
  563. stop_output:
  564. /* stop the output and calculate the correct length */
  565. *(buffer + len) = '\0';
  566. *start = buffer + (offset - begin); /* Start of wanted data */
  567. len -= (offset - begin);
  568. if(len > length) {
  569. len = length;
  570. } else if(len < 0){
  571. len = 0;
  572. **start = '\0';
  573. }
  574. return len;
  575. }
  576. /*
  577. * Turn a struct scsi_cmnd * into a unique 32 bit 'context'.
  578. */
  579. static u32 adpt_cmd_to_context(struct scsi_cmnd *cmd)
  580. {
  581. return (u32)cmd->serial_number;
  582. }
  583. /*
  584. * Go from a u32 'context' to a struct scsi_cmnd * .
  585. * This could probably be made more efficient.
  586. */
  587. static struct scsi_cmnd *
  588. adpt_cmd_from_context(adpt_hba * pHba, u32 context)
  589. {
  590. struct scsi_cmnd * cmd;
  591. struct scsi_device * d;
  592. if (context == 0)
  593. return NULL;
  594. spin_unlock(pHba->host->host_lock);
  595. shost_for_each_device(d, pHba->host) {
  596. unsigned long flags;
  597. spin_lock_irqsave(&d->list_lock, flags);
  598. list_for_each_entry(cmd, &d->cmd_list, list) {
  599. if (((u32)cmd->serial_number == context)) {
  600. spin_unlock_irqrestore(&d->list_lock, flags);
  601. scsi_device_put(d);
  602. spin_lock(pHba->host->host_lock);
  603. return cmd;
  604. }
  605. }
  606. spin_unlock_irqrestore(&d->list_lock, flags);
  607. }
  608. spin_lock(pHba->host->host_lock);
  609. return NULL;
  610. }
  611. /*
  612. * Turn a pointer to ioctl reply data into an u32 'context'
  613. */
  614. static u32 adpt_ioctl_to_context(adpt_hba * pHba, void *reply)
  615. {
  616. #if BITS_PER_LONG == 32
  617. return (u32)(unsigned long)reply;
  618. #else
  619. ulong flags = 0;
  620. u32 nr, i;
  621. spin_lock_irqsave(pHba->host->host_lock, flags);
  622. nr = ARRAY_SIZE(pHba->ioctl_reply_context);
  623. for (i = 0; i < nr; i++) {
  624. if (pHba->ioctl_reply_context[i] == NULL) {
  625. pHba->ioctl_reply_context[i] = reply;
  626. break;
  627. }
  628. }
  629. spin_unlock_irqrestore(pHba->host->host_lock, flags);
  630. if (i >= nr) {
  631. kfree (reply);
  632. printk(KERN_WARNING"%s: Too many outstanding "
  633. "ioctl commands\n", pHba->name);
  634. return (u32)-1;
  635. }
  636. return i;
  637. #endif
  638. }
  639. /*
  640. * Go from an u32 'context' to a pointer to ioctl reply data.
  641. */
  642. static void *adpt_ioctl_from_context(adpt_hba *pHba, u32 context)
  643. {
  644. #if BITS_PER_LONG == 32
  645. return (void *)(unsigned long)context;
  646. #else
  647. void *p = pHba->ioctl_reply_context[context];
  648. pHba->ioctl_reply_context[context] = NULL;
  649. return p;
  650. #endif
  651. }
  652. /*===========================================================================
  653. * Error Handling routines
  654. *===========================================================================
  655. */
  656. static int adpt_abort(struct scsi_cmnd * cmd)
  657. {
  658. adpt_hba* pHba = NULL; /* host bus adapter structure */
  659. struct adpt_device* dptdevice; /* dpt per device information */
  660. u32 msg[5];
  661. int rcode;
  662. if(cmd->serial_number == 0){
  663. return FAILED;
  664. }
  665. pHba = (adpt_hba*) cmd->device->host->hostdata[0];
  666. printk(KERN_INFO"%s: Trying to Abort cmd=%ld\n",pHba->name, cmd->serial_number);
  667. if ((dptdevice = (void*) (cmd->device->hostdata)) == NULL) {
  668. printk(KERN_ERR "%s: Unable to abort: No device in cmnd\n",pHba->name);
  669. return FAILED;
  670. }
  671. memset(msg, 0, sizeof(msg));
  672. msg[0] = FIVE_WORD_MSG_SIZE|SGL_OFFSET_0;
  673. msg[1] = I2O_CMD_SCSI_ABORT<<24|HOST_TID<<12|dptdevice->tid;
  674. msg[2] = 0;
  675. msg[3]= 0;
  676. msg[4] = adpt_cmd_to_context(cmd);
  677. if (pHba->host)
  678. spin_lock_irq(pHba->host->host_lock);
  679. rcode = adpt_i2o_post_wait(pHba, msg, sizeof(msg), FOREVER);
  680. if (pHba->host)
  681. spin_unlock_irq(pHba->host->host_lock);
  682. if (rcode != 0) {
  683. if(rcode == -EOPNOTSUPP ){
  684. printk(KERN_INFO"%s: Abort cmd not supported\n",pHba->name);
  685. return FAILED;
  686. }
  687. printk(KERN_INFO"%s: Abort cmd=%ld failed.\n",pHba->name, cmd->serial_number);
  688. return FAILED;
  689. }
  690. printk(KERN_INFO"%s: Abort cmd=%ld complete.\n",pHba->name, cmd->serial_number);
  691. return SUCCESS;
  692. }
  693. #define I2O_DEVICE_RESET 0x27
  694. // This is the same for BLK and SCSI devices
  695. // NOTE this is wrong in the i2o.h definitions
  696. // This is not currently supported by our adapter but we issue it anyway
  697. static int adpt_device_reset(struct scsi_cmnd* cmd)
  698. {
  699. adpt_hba* pHba;
  700. u32 msg[4];
  701. u32 rcode;
  702. int old_state;
  703. struct adpt_device* d = cmd->device->hostdata;
  704. pHba = (void*) cmd->device->host->hostdata[0];
  705. printk(KERN_INFO"%s: Trying to reset device\n",pHba->name);
  706. if (!d) {
  707. printk(KERN_INFO"%s: Reset Device: Device Not found\n",pHba->name);
  708. return FAILED;
  709. }
  710. memset(msg, 0, sizeof(msg));
  711. msg[0] = FOUR_WORD_MSG_SIZE|SGL_OFFSET_0;
  712. msg[1] = (I2O_DEVICE_RESET<<24|HOST_TID<<12|d->tid);
  713. msg[2] = 0;
  714. msg[3] = 0;
  715. if (pHba->host)
  716. spin_lock_irq(pHba->host->host_lock);
  717. old_state = d->state;
  718. d->state |= DPTI_DEV_RESET;
  719. rcode = adpt_i2o_post_wait(pHba, msg,sizeof(msg), FOREVER);
  720. d->state = old_state;
  721. if (pHba->host)
  722. spin_unlock_irq(pHba->host->host_lock);
  723. if (rcode != 0) {
  724. if(rcode == -EOPNOTSUPP ){
  725. printk(KERN_INFO"%s: Device reset not supported\n",pHba->name);
  726. return FAILED;
  727. }
  728. printk(KERN_INFO"%s: Device reset failed\n",pHba->name);
  729. return FAILED;
  730. } else {
  731. printk(KERN_INFO"%s: Device reset successful\n",pHba->name);
  732. return SUCCESS;
  733. }
  734. }
  735. #define I2O_HBA_BUS_RESET 0x87
  736. // This version of bus reset is called by the eh_error handler
  737. static int adpt_bus_reset(struct scsi_cmnd* cmd)
  738. {
  739. adpt_hba* pHba;
  740. u32 msg[4];
  741. u32 rcode;
  742. pHba = (adpt_hba*)cmd->device->host->hostdata[0];
  743. memset(msg, 0, sizeof(msg));
  744. printk(KERN_WARNING"%s: Bus reset: SCSI Bus %d: tid: %d\n",pHba->name, cmd->device->channel,pHba->channel[cmd->device->channel].tid );
  745. msg[0] = FOUR_WORD_MSG_SIZE|SGL_OFFSET_0;
  746. msg[1] = (I2O_HBA_BUS_RESET<<24|HOST_TID<<12|pHba->channel[cmd->device->channel].tid);
  747. msg[2] = 0;
  748. msg[3] = 0;
  749. if (pHba->host)
  750. spin_lock_irq(pHba->host->host_lock);
  751. rcode = adpt_i2o_post_wait(pHba, msg,sizeof(msg), FOREVER);
  752. if (pHba->host)
  753. spin_unlock_irq(pHba->host->host_lock);
  754. if (rcode != 0) {
  755. printk(KERN_WARNING"%s: Bus reset failed.\n",pHba->name);
  756. return FAILED;
  757. } else {
  758. printk(KERN_WARNING"%s: Bus reset success.\n",pHba->name);
  759. return SUCCESS;
  760. }
  761. }
  762. // This version of reset is called by the eh_error_handler
  763. static int __adpt_reset(struct scsi_cmnd* cmd)
  764. {
  765. adpt_hba* pHba;
  766. int rcode;
  767. pHba = (adpt_hba*)cmd->device->host->hostdata[0];
  768. printk(KERN_WARNING"%s: Hba Reset: scsi id %d: tid: %d\n",pHba->name,cmd->device->channel,pHba->channel[cmd->device->channel].tid );
  769. rcode = adpt_hba_reset(pHba);
  770. if(rcode == 0){
  771. printk(KERN_WARNING"%s: HBA reset complete\n",pHba->name);
  772. return SUCCESS;
  773. } else {
  774. printk(KERN_WARNING"%s: HBA reset failed (%x)\n",pHba->name, rcode);
  775. return FAILED;
  776. }
  777. }
  778. static int adpt_reset(struct scsi_cmnd* cmd)
  779. {
  780. int rc;
  781. spin_lock_irq(cmd->device->host->host_lock);
  782. rc = __adpt_reset(cmd);
  783. spin_unlock_irq(cmd->device->host->host_lock);
  784. return rc;
  785. }
  786. // This version of reset is called by the ioctls and indirectly from eh_error_handler via adpt_reset
  787. static int adpt_hba_reset(adpt_hba* pHba)
  788. {
  789. int rcode;
  790. pHba->state |= DPTI_STATE_RESET;
  791. // Activate does get status , init outbound, and get hrt
  792. if ((rcode=adpt_i2o_activate_hba(pHba)) < 0) {
  793. printk(KERN_ERR "%s: Could not activate\n", pHba->name);
  794. adpt_i2o_delete_hba(pHba);
  795. return rcode;
  796. }
  797. if ((rcode=adpt_i2o_build_sys_table()) < 0) {
  798. adpt_i2o_delete_hba(pHba);
  799. return rcode;
  800. }
  801. PDEBUG("%s: in HOLD state\n",pHba->name);
  802. if ((rcode=adpt_i2o_online_hba(pHba)) < 0) {
  803. adpt_i2o_delete_hba(pHba);
  804. return rcode;
  805. }
  806. PDEBUG("%s: in OPERATIONAL state\n",pHba->name);
  807. if ((rcode=adpt_i2o_lct_get(pHba)) < 0){
  808. adpt_i2o_delete_hba(pHba);
  809. return rcode;
  810. }
  811. if ((rcode=adpt_i2o_reparse_lct(pHba)) < 0){
  812. adpt_i2o_delete_hba(pHba);
  813. return rcode;
  814. }
  815. pHba->state &= ~DPTI_STATE_RESET;
  816. adpt_fail_posted_scbs(pHba);
  817. return 0; /* return success */
  818. }
  819. /*===========================================================================
  820. *
  821. *===========================================================================
  822. */
  823. static void adpt_i2o_sys_shutdown(void)
  824. {
  825. adpt_hba *pHba, *pNext;
  826. struct adpt_i2o_post_wait_data *p1, *old;
  827. printk(KERN_INFO"Shutting down Adaptec I2O controllers.\n");
  828. printk(KERN_INFO" This could take a few minutes if there are many devices attached\n");
  829. /* Delete all IOPs from the controller chain */
  830. /* They should have already been released by the
  831. * scsi-core
  832. */
  833. for (pHba = hba_chain; pHba; pHba = pNext) {
  834. pNext = pHba->next;
  835. adpt_i2o_delete_hba(pHba);
  836. }
  837. /* Remove any timedout entries from the wait queue. */
  838. // spin_lock_irqsave(&adpt_post_wait_lock, flags);
  839. /* Nothing should be outstanding at this point so just
  840. * free them
  841. */
  842. for(p1 = adpt_post_wait_queue; p1;) {
  843. old = p1;
  844. p1 = p1->next;
  845. kfree(old);
  846. }
  847. // spin_unlock_irqrestore(&adpt_post_wait_lock, flags);
  848. adpt_post_wait_queue = NULL;
  849. printk(KERN_INFO "Adaptec I2O controllers down.\n");
  850. }
  851. static int adpt_install_hba(struct scsi_host_template* sht, struct pci_dev* pDev)
  852. {
  853. adpt_hba* pHba = NULL;
  854. adpt_hba* p = NULL;
  855. ulong base_addr0_phys = 0;
  856. ulong base_addr1_phys = 0;
  857. u32 hba_map0_area_size = 0;
  858. u32 hba_map1_area_size = 0;
  859. void __iomem *base_addr_virt = NULL;
  860. void __iomem *msg_addr_virt = NULL;
  861. int dma64 = 0;
  862. int raptorFlag = FALSE;
  863. if(pci_enable_device(pDev)) {
  864. return -EINVAL;
  865. }
  866. if (pci_request_regions(pDev, "dpt_i2o")) {
  867. PERROR("dpti: adpt_config_hba: pci request region failed\n");
  868. return -EINVAL;
  869. }
  870. pci_set_master(pDev);
  871. /*
  872. * See if we should enable dma64 mode.
  873. */
  874. if (sizeof(dma_addr_t) > 4 &&
  875. pci_set_dma_mask(pDev, DMA_BIT_MASK(64)) == 0) {
  876. if (dma_get_required_mask(&pDev->dev) > DMA_BIT_MASK(32))
  877. dma64 = 1;
  878. }
  879. if (!dma64 && pci_set_dma_mask(pDev, DMA_BIT_MASK(32)) != 0)
  880. return -EINVAL;
  881. /* adapter only supports message blocks below 4GB */
  882. pci_set_consistent_dma_mask(pDev, DMA_BIT_MASK(32));
  883. base_addr0_phys = pci_resource_start(pDev,0);
  884. hba_map0_area_size = pci_resource_len(pDev,0);
  885. // Check if standard PCI card or single BAR Raptor
  886. if(pDev->device == PCI_DPT_DEVICE_ID){
  887. if(pDev->subsystem_device >=0xc032 && pDev->subsystem_device <= 0xc03b){
  888. // Raptor card with this device id needs 4M
  889. hba_map0_area_size = 0x400000;
  890. } else { // Not Raptor - it is a PCI card
  891. if(hba_map0_area_size > 0x100000 ){
  892. hba_map0_area_size = 0x100000;
  893. }
  894. }
  895. } else {// Raptor split BAR config
  896. // Use BAR1 in this configuration
  897. base_addr1_phys = pci_resource_start(pDev,1);
  898. hba_map1_area_size = pci_resource_len(pDev,1);
  899. raptorFlag = TRUE;
  900. }
  901. #if BITS_PER_LONG == 64
  902. /*
  903. * The original Adaptec 64 bit driver has this comment here:
  904. * "x86_64 machines need more optimal mappings"
  905. *
  906. * I assume some HBAs report ridiculously large mappings
  907. * and we need to limit them on platforms with IOMMUs.
  908. */
  909. if (raptorFlag == TRUE) {
  910. if (hba_map0_area_size > 128)
  911. hba_map0_area_size = 128;
  912. if (hba_map1_area_size > 524288)
  913. hba_map1_area_size = 524288;
  914. } else {
  915. if (hba_map0_area_size > 524288)
  916. hba_map0_area_size = 524288;
  917. }
  918. #endif
  919. base_addr_virt = ioremap(base_addr0_phys,hba_map0_area_size);
  920. if (!base_addr_virt) {
  921. pci_release_regions(pDev);
  922. PERROR("dpti: adpt_config_hba: io remap failed\n");
  923. return -EINVAL;
  924. }
  925. if(raptorFlag == TRUE) {
  926. msg_addr_virt = ioremap(base_addr1_phys, hba_map1_area_size );
  927. if (!msg_addr_virt) {
  928. PERROR("dpti: adpt_config_hba: io remap failed on BAR1\n");
  929. iounmap(base_addr_virt);
  930. pci_release_regions(pDev);
  931. return -EINVAL;
  932. }
  933. } else {
  934. msg_addr_virt = base_addr_virt;
  935. }
  936. // Allocate and zero the data structure
  937. pHba = kzalloc(sizeof(adpt_hba), GFP_KERNEL);
  938. if (!pHba) {
  939. if (msg_addr_virt != base_addr_virt)
  940. iounmap(msg_addr_virt);
  941. iounmap(base_addr_virt);
  942. pci_release_regions(pDev);
  943. return -ENOMEM;
  944. }
  945. mutex_lock(&adpt_configuration_lock);
  946. if(hba_chain != NULL){
  947. for(p = hba_chain; p->next; p = p->next);
  948. p->next = pHba;
  949. } else {
  950. hba_chain = pHba;
  951. }
  952. pHba->next = NULL;
  953. pHba->unit = hba_count;
  954. sprintf(pHba->name, "dpti%d", hba_count);
  955. hba_count++;
  956. mutex_unlock(&adpt_configuration_lock);
  957. pHba->pDev = pDev;
  958. pHba->base_addr_phys = base_addr0_phys;
  959. // Set up the Virtual Base Address of the I2O Device
  960. pHba->base_addr_virt = base_addr_virt;
  961. pHba->msg_addr_virt = msg_addr_virt;
  962. pHba->irq_mask = base_addr_virt+0x30;
  963. pHba->post_port = base_addr_virt+0x40;
  964. pHba->reply_port = base_addr_virt+0x44;
  965. pHba->hrt = NULL;
  966. pHba->lct = NULL;
  967. pHba->lct_size = 0;
  968. pHba->status_block = NULL;
  969. pHba->post_count = 0;
  970. pHba->state = DPTI_STATE_RESET;
  971. pHba->pDev = pDev;
  972. pHba->devices = NULL;
  973. pHba->dma64 = dma64;
  974. // Initializing the spinlocks
  975. spin_lock_init(&pHba->state_lock);
  976. spin_lock_init(&adpt_post_wait_lock);
  977. if(raptorFlag == 0){
  978. printk(KERN_INFO "Adaptec I2O RAID controller"
  979. " %d at %p size=%x irq=%d%s\n",
  980. hba_count-1, base_addr_virt,
  981. hba_map0_area_size, pDev->irq,
  982. dma64 ? " (64-bit DMA)" : "");
  983. } else {
  984. printk(KERN_INFO"Adaptec I2O RAID controller %d irq=%d%s\n",
  985. hba_count-1, pDev->irq,
  986. dma64 ? " (64-bit DMA)" : "");
  987. printk(KERN_INFO" BAR0 %p - size= %x\n",base_addr_virt,hba_map0_area_size);
  988. printk(KERN_INFO" BAR1 %p - size= %x\n",msg_addr_virt,hba_map1_area_size);
  989. }
  990. if (request_irq (pDev->irq, adpt_isr, IRQF_SHARED, pHba->name, pHba)) {
  991. printk(KERN_ERR"%s: Couldn't register IRQ %d\n", pHba->name, pDev->irq);
  992. adpt_i2o_delete_hba(pHba);
  993. return -EINVAL;
  994. }
  995. return 0;
  996. }
  997. static void adpt_i2o_delete_hba(adpt_hba* pHba)
  998. {
  999. adpt_hba* p1;
  1000. adpt_hba* p2;
  1001. struct i2o_device* d;
  1002. struct i2o_device* next;
  1003. int i;
  1004. int j;
  1005. struct adpt_device* pDev;
  1006. struct adpt_device* pNext;
  1007. mutex_lock(&adpt_configuration_lock);
  1008. // scsi_unregister calls our adpt_release which
  1009. // does a quiese
  1010. if(pHba->host){
  1011. free_irq(pHba->host->irq, pHba);
  1012. }
  1013. p2 = NULL;
  1014. for( p1 = hba_chain; p1; p2 = p1,p1=p1->next){
  1015. if(p1 == pHba) {
  1016. if(p2) {
  1017. p2->next = p1->next;
  1018. } else {
  1019. hba_chain = p1->next;
  1020. }
  1021. break;
  1022. }
  1023. }
  1024. hba_count--;
  1025. mutex_unlock(&adpt_configuration_lock);
  1026. iounmap(pHba->base_addr_virt);
  1027. pci_release_regions(pHba->pDev);
  1028. if(pHba->msg_addr_virt != pHba->base_addr_virt){
  1029. iounmap(pHba->msg_addr_virt);
  1030. }
  1031. if(pHba->FwDebugBuffer_P)
  1032. iounmap(pHba->FwDebugBuffer_P);
  1033. if(pHba->hrt) {
  1034. dma_free_coherent(&pHba->pDev->dev,
  1035. pHba->hrt->num_entries * pHba->hrt->entry_len << 2,
  1036. pHba->hrt, pHba->hrt_pa);
  1037. }
  1038. if(pHba->lct) {
  1039. dma_free_coherent(&pHba->pDev->dev, pHba->lct_size,
  1040. pHba->lct, pHba->lct_pa);
  1041. }
  1042. if(pHba->status_block) {
  1043. dma_free_coherent(&pHba->pDev->dev, sizeof(i2o_status_block),
  1044. pHba->status_block, pHba->status_block_pa);
  1045. }
  1046. if(pHba->reply_pool) {
  1047. dma_free_coherent(&pHba->pDev->dev,
  1048. pHba->reply_fifo_size * REPLY_FRAME_SIZE * 4,
  1049. pHba->reply_pool, pHba->reply_pool_pa);
  1050. }
  1051. for(d = pHba->devices; d ; d = next){
  1052. next = d->next;
  1053. kfree(d);
  1054. }
  1055. for(i = 0 ; i < pHba->top_scsi_channel ; i++){
  1056. for(j = 0; j < MAX_ID; j++){
  1057. if(pHba->channel[i].device[j] != NULL){
  1058. for(pDev = pHba->channel[i].device[j]; pDev; pDev = pNext){
  1059. pNext = pDev->next_lun;
  1060. kfree(pDev);
  1061. }
  1062. }
  1063. }
  1064. }
  1065. pci_dev_put(pHba->pDev);
  1066. kfree(pHba);
  1067. if (adpt_sysfs_class)
  1068. device_destroy(adpt_sysfs_class,
  1069. MKDEV(DPTI_I2O_MAJOR, pHba->unit));
  1070. if(hba_count <= 0){
  1071. unregister_chrdev(DPTI_I2O_MAJOR, DPT_DRIVER);
  1072. if (adpt_sysfs_class) {
  1073. class_destroy(adpt_sysfs_class);
  1074. adpt_sysfs_class = NULL;
  1075. }
  1076. }
  1077. }
  1078. static struct adpt_device* adpt_find_device(adpt_hba* pHba, u32 chan, u32 id, u32 lun)
  1079. {
  1080. struct adpt_device* d;
  1081. if(chan < 0 || chan >= MAX_CHANNEL)
  1082. return NULL;
  1083. if( pHba->channel[chan].device == NULL){
  1084. printk(KERN_DEBUG"Adaptec I2O RAID: Trying to find device before they are allocated\n");
  1085. return NULL;
  1086. }
  1087. d = pHba->channel[chan].device[id];
  1088. if(!d || d->tid == 0) {
  1089. return NULL;
  1090. }
  1091. /* If it is the only lun at that address then this should match*/
  1092. if(d->scsi_lun == lun){
  1093. return d;
  1094. }
  1095. /* else we need to look through all the luns */
  1096. for(d=d->next_lun ; d ; d = d->next_lun){
  1097. if(d->scsi_lun == lun){
  1098. return d;
  1099. }
  1100. }
  1101. return NULL;
  1102. }
  1103. static int adpt_i2o_post_wait(adpt_hba* pHba, u32* msg, int len, int timeout)
  1104. {
  1105. // I used my own version of the WAIT_QUEUE_HEAD
  1106. // to handle some version differences
  1107. // When embedded in the kernel this could go back to the vanilla one
  1108. ADPT_DECLARE_WAIT_QUEUE_HEAD(adpt_wq_i2o_post);
  1109. int status = 0;
  1110. ulong flags = 0;
  1111. struct adpt_i2o_post_wait_data *p1, *p2;
  1112. struct adpt_i2o_post_wait_data *wait_data =
  1113. kmalloc(sizeof(struct adpt_i2o_post_wait_data),GFP_KERNEL);
  1114. DECLARE_WAITQUEUE(wait, current);
  1115. if (!wait_data)
  1116. return -ENOMEM;
  1117. /*
  1118. * The spin locking is needed to keep anyone from playing
  1119. * with the queue pointers and id while we do the same
  1120. */
  1121. spin_lock_irqsave(&adpt_post_wait_lock, flags);
  1122. // TODO we need a MORE unique way of getting ids
  1123. // to support async LCT get
  1124. wait_data->next = adpt_post_wait_queue;
  1125. adpt_post_wait_queue = wait_data;
  1126. adpt_post_wait_id++;
  1127. adpt_post_wait_id &= 0x7fff;
  1128. wait_data->id = adpt_post_wait_id;
  1129. spin_unlock_irqrestore(&adpt_post_wait_lock, flags);
  1130. wait_data->wq = &adpt_wq_i2o_post;
  1131. wait_data->status = -ETIMEDOUT;
  1132. add_wait_queue(&adpt_wq_i2o_post, &wait);
  1133. msg[2] |= 0x80000000 | ((u32)wait_data->id);
  1134. timeout *= HZ;
  1135. if((status = adpt_i2o_post_this(pHba, msg, len)) == 0){
  1136. set_current_state(TASK_INTERRUPTIBLE);
  1137. if(pHba->host)
  1138. spin_unlock_irq(pHba->host->host_lock);
  1139. if (!timeout)
  1140. schedule();
  1141. else{
  1142. timeout = schedule_timeout(timeout);
  1143. if (timeout == 0) {
  1144. // I/O issued, but cannot get result in
  1145. // specified time. Freeing resorces is
  1146. // dangerous.
  1147. status = -ETIME;
  1148. }
  1149. }
  1150. if(pHba->host)
  1151. spin_lock_irq(pHba->host->host_lock);
  1152. }
  1153. remove_wait_queue(&adpt_wq_i2o_post, &wait);
  1154. if(status == -ETIMEDOUT){
  1155. printk(KERN_INFO"dpti%d: POST WAIT TIMEOUT\n",pHba->unit);
  1156. // We will have to free the wait_data memory during shutdown
  1157. return status;
  1158. }
  1159. /* Remove the entry from the queue. */
  1160. p2 = NULL;
  1161. spin_lock_irqsave(&adpt_post_wait_lock, flags);
  1162. for(p1 = adpt_post_wait_queue; p1; p2 = p1, p1 = p1->next) {
  1163. if(p1 == wait_data) {
  1164. if(p1->status == I2O_DETAIL_STATUS_UNSUPPORTED_FUNCTION ) {
  1165. status = -EOPNOTSUPP;
  1166. }
  1167. if(p2) {
  1168. p2->next = p1->next;
  1169. } else {
  1170. adpt_post_wait_queue = p1->next;
  1171. }
  1172. break;
  1173. }
  1174. }
  1175. spin_unlock_irqrestore(&adpt_post_wait_lock, flags);
  1176. kfree(wait_data);
  1177. return status;
  1178. }
  1179. static s32 adpt_i2o_post_this(adpt_hba* pHba, u32* data, int len)
  1180. {
  1181. u32 m = EMPTY_QUEUE;
  1182. u32 __iomem *msg;
  1183. ulong timeout = jiffies + 30*HZ;
  1184. do {
  1185. rmb();
  1186. m = readl(pHba->post_port);
  1187. if (m != EMPTY_QUEUE) {
  1188. break;
  1189. }
  1190. if(time_after(jiffies,timeout)){
  1191. printk(KERN_WARNING"dpti%d: Timeout waiting for message frame!\n", pHba->unit);
  1192. return -ETIMEDOUT;
  1193. }
  1194. schedule_timeout_uninterruptible(1);
  1195. } while(m == EMPTY_QUEUE);
  1196. msg = pHba->msg_addr_virt + m;
  1197. memcpy_toio(msg, data, len);
  1198. wmb();
  1199. //post message
  1200. writel(m, pHba->post_port);
  1201. wmb();
  1202. return 0;
  1203. }
  1204. static void adpt_i2o_post_wait_complete(u32 context, int status)
  1205. {
  1206. struct adpt_i2o_post_wait_data *p1 = NULL;
  1207. /*
  1208. * We need to search through the adpt_post_wait
  1209. * queue to see if the given message is still
  1210. * outstanding. If not, it means that the IOP
  1211. * took longer to respond to the message than we
  1212. * had allowed and timer has already expired.
  1213. * Not much we can do about that except log
  1214. * it for debug purposes, increase timeout, and recompile
  1215. *
  1216. * Lock needed to keep anyone from moving queue pointers
  1217. * around while we're looking through them.
  1218. */
  1219. context &= 0x7fff;
  1220. spin_lock(&adpt_post_wait_lock);
  1221. for(p1 = adpt_post_wait_queue; p1; p1 = p1->next) {
  1222. if(p1->id == context) {
  1223. p1->status = status;
  1224. spin_unlock(&adpt_post_wait_lock);
  1225. wake_up_interruptible(p1->wq);
  1226. return;
  1227. }
  1228. }
  1229. spin_unlock(&adpt_post_wait_lock);
  1230. // If this happens we lose commands that probably really completed
  1231. printk(KERN_DEBUG"dpti: Could Not find task %d in wait queue\n",context);
  1232. printk(KERN_DEBUG" Tasks in wait queue:\n");
  1233. for(p1 = adpt_post_wait_queue; p1; p1 = p1->next) {
  1234. printk(KERN_DEBUG" %d\n",p1->id);
  1235. }
  1236. return;
  1237. }
  1238. static s32 adpt_i2o_reset_hba(adpt_hba* pHba)
  1239. {
  1240. u32 msg[8];
  1241. u8* status;
  1242. dma_addr_t addr;
  1243. u32 m = EMPTY_QUEUE ;
  1244. ulong timeout = jiffies + (TMOUT_IOPRESET*HZ);
  1245. if(pHba->initialized == FALSE) { // First time reset should be quick
  1246. timeout = jiffies + (25*HZ);
  1247. } else {
  1248. adpt_i2o_quiesce_hba(pHba);
  1249. }
  1250. do {
  1251. rmb();
  1252. m = readl(pHba->post_port);
  1253. if (m != EMPTY_QUEUE) {
  1254. break;
  1255. }
  1256. if(time_after(jiffies,timeout)){
  1257. printk(KERN_WARNING"Timeout waiting for message!\n");
  1258. return -ETIMEDOUT;
  1259. }
  1260. schedule_timeout_uninterruptible(1);
  1261. } while (m == EMPTY_QUEUE);
  1262. status = dma_alloc_coherent(&pHba->pDev->dev, 4, &addr, GFP_KERNEL);
  1263. if(status == NULL) {
  1264. adpt_send_nop(pHba, m);
  1265. printk(KERN_ERR"IOP reset failed - no free memory.\n");
  1266. return -ENOMEM;
  1267. }
  1268. memset(status,0,4);
  1269. msg[0]=EIGHT_WORD_MSG_SIZE|SGL_OFFSET_0;
  1270. msg[1]=I2O_CMD_ADAPTER_RESET<<24|HOST_TID<<12|ADAPTER_TID;
  1271. msg[2]=0;
  1272. msg[3]=0;
  1273. msg[4]=0;
  1274. msg[5]=0;
  1275. msg[6]=dma_low(addr);
  1276. msg[7]=dma_high(addr);
  1277. memcpy_toio(pHba->msg_addr_virt+m, msg, sizeof(msg));
  1278. wmb();
  1279. writel(m, pHba->post_port);
  1280. wmb();
  1281. while(*status == 0){
  1282. if(time_after(jiffies,timeout)){
  1283. printk(KERN_WARNING"%s: IOP Reset Timeout\n",pHba->name);
  1284. /* We lose 4 bytes of "status" here, but we cannot
  1285. free these because controller may awake and corrupt
  1286. those bytes at any time */
  1287. /* dma_free_coherent(&pHba->pDev->dev, 4, buf, addr); */
  1288. return -ETIMEDOUT;
  1289. }
  1290. rmb();
  1291. schedule_timeout_uninterruptible(1);
  1292. }
  1293. if(*status == 0x01 /*I2O_EXEC_IOP_RESET_IN_PROGRESS*/) {
  1294. PDEBUG("%s: Reset in progress...\n", pHba->name);
  1295. // Here we wait for message frame to become available
  1296. // indicated that reset has finished
  1297. do {
  1298. rmb();
  1299. m = readl(pHba->post_port);
  1300. if (m != EMPTY_QUEUE) {
  1301. break;
  1302. }
  1303. if(time_after(jiffies,timeout)){
  1304. printk(KERN_ERR "%s:Timeout waiting for IOP Reset.\n",pHba->name);
  1305. /* We lose 4 bytes of "status" here, but we
  1306. cannot free these because controller may
  1307. awake and corrupt those bytes at any time */
  1308. /* dma_free_coherent(&pHba->pDev->dev, 4, buf, addr); */
  1309. return -ETIMEDOUT;
  1310. }
  1311. schedule_timeout_uninterruptible(1);
  1312. } while (m == EMPTY_QUEUE);
  1313. // Flush the offset
  1314. adpt_send_nop(pHba, m);
  1315. }
  1316. adpt_i2o_status_get(pHba);
  1317. if(*status == 0x02 ||
  1318. pHba->status_block->iop_state != ADAPTER_STATE_RESET) {
  1319. printk(KERN_WARNING"%s: Reset reject, trying to clear\n",
  1320. pHba->name);
  1321. } else {
  1322. PDEBUG("%s: Reset completed.\n", pHba->name);
  1323. }
  1324. dma_free_coherent(&pHba->pDev->dev, 4, status, addr);
  1325. #ifdef UARTDELAY
  1326. // This delay is to allow someone attached to the card through the debug UART to
  1327. // set up the dump levels that they want before the rest of the initialization sequence
  1328. adpt_delay(20000);
  1329. #endif
  1330. return 0;
  1331. }
  1332. static int adpt_i2o_parse_lct(adpt_hba* pHba)
  1333. {
  1334. int i;
  1335. int max;
  1336. int tid;
  1337. struct i2o_device *d;
  1338. i2o_lct *lct = pHba->lct;
  1339. u8 bus_no = 0;
  1340. s16 scsi_id;
  1341. s16 scsi_lun;
  1342. u32 buf[10]; // larger than 7, or 8 ...
  1343. struct adpt_device* pDev;
  1344. if (lct == NULL) {
  1345. printk(KERN_ERR "%s: LCT is empty???\n",pHba->name);
  1346. return -1;
  1347. }
  1348. max = lct->table_size;
  1349. max -= 3;
  1350. max /= 9;
  1351. for(i=0;i<max;i++) {
  1352. if( lct->lct_entry[i].user_tid != 0xfff){
  1353. /*
  1354. * If we have hidden devices, we need to inform the upper layers about
  1355. * the possible maximum id reference to handle device access when
  1356. * an array is disassembled. This code has no other purpose but to
  1357. * allow us future access to devices that are currently hidden
  1358. * behind arrays, hotspares or have not been configured (JBOD mode).
  1359. */
  1360. if( lct->lct_entry[i].class_id != I2O_CLASS_RANDOM_BLOCK_STORAGE &&
  1361. lct->lct_entry[i].class_id != I2O_CLASS_SCSI_PERIPHERAL &&
  1362. lct->lct_entry[i].class_id != I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL ){
  1363. continue;
  1364. }
  1365. tid = lct->lct_entry[i].tid;
  1366. // I2O_DPT_DEVICE_INFO_GROUP_NO;
  1367. if(adpt_i2o_query_scalar(pHba, tid, 0x8000, -1, buf, 32)<0) {
  1368. continue;
  1369. }
  1370. bus_no = buf[0]>>16;
  1371. scsi_id = buf[1];
  1372. scsi_lun = (buf[2]>>8 )&0xff;
  1373. if(bus_no >= MAX_CHANNEL) { // Something wrong skip it
  1374. printk(KERN_WARNING"%s: Channel number %d out of range \n", pHba->name, bus_no);
  1375. continue;
  1376. }
  1377. if (scsi_id >= MAX_ID){
  1378. printk(KERN_WARNING"%s: SCSI ID %d out of range \n", pHba->name, bus_no);
  1379. continue;
  1380. }
  1381. if(bus_no > pHba->top_scsi_channel){
  1382. pHba->top_scsi_channel = bus_no;
  1383. }
  1384. if(scsi_id > pHba->top_scsi_id){
  1385. pHba->top_scsi_id = scsi_id;
  1386. }
  1387. if(scsi_lun > pHba->top_scsi_lun){
  1388. pHba->top_scsi_lun = scsi_lun;
  1389. }
  1390. continue;
  1391. }
  1392. d = kmalloc(sizeof(struct i2o_device), GFP_KERNEL);
  1393. if(d==NULL)
  1394. {
  1395. printk(KERN_CRIT"%s: Out of memory for I2O device data.\n",pHba->name);
  1396. return -ENOMEM;
  1397. }
  1398. d->controller = pHba;
  1399. d->next = NULL;
  1400. memcpy(&d->lct_data, &lct->lct_entry[i], sizeof(i2o_lct_entry));
  1401. d->flags = 0;
  1402. tid = d->lct_data.tid;
  1403. adpt_i2o_report_hba_unit(pHba, d);
  1404. adpt_i2o_install_device(pHba, d);
  1405. }
  1406. bus_no = 0;
  1407. for(d = pHba->devices; d ; d = d->next) {
  1408. if(d->lct_data.class_id == I2O_CLASS_BUS_ADAPTER_PORT ||
  1409. d->lct_data.class_id == I2O_CLASS_FIBRE_CHANNEL_PORT){
  1410. tid = d->lct_data.tid;
  1411. // TODO get the bus_no from hrt-but for now they are in order
  1412. //bus_no =
  1413. if(bus_no > pHba->top_scsi_channel){
  1414. pHba->top_scsi_channel = bus_no;
  1415. }
  1416. pHba->channel[bus_no].type = d->lct_data.class_id;
  1417. pHba->channel[bus_no].tid = tid;
  1418. if(adpt_i2o_query_scalar(pHba, tid, 0x0200, -1, buf, 28)>=0)
  1419. {
  1420. pHba->channel[bus_no].scsi_id = buf[1];
  1421. PDEBUG("Bus %d - SCSI ID %d.\n", bus_no, buf[1]);
  1422. }
  1423. // TODO remove - this is just until we get from hrt
  1424. bus_no++;
  1425. if(bus_no >= MAX_CHANNEL) { // Something wrong skip it
  1426. printk(KERN_WARNING"%s: Channel number %d out of range - LCT\n", pHba->name, bus_no);
  1427. break;
  1428. }
  1429. }
  1430. }
  1431. // Setup adpt_device table
  1432. for(d = pHba->devices; d ; d = d->next) {
  1433. if(d->lct_data.class_id == I2O_CLASS_RANDOM_BLOCK_STORAGE ||
  1434. d->lct_data.class_id == I2O_CLASS_SCSI_PERIPHERAL ||
  1435. d->lct_data.class_id == I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL ){
  1436. tid = d->lct_data.tid;
  1437. scsi_id = -1;
  1438. // I2O_DPT_DEVICE_INFO_GROUP_NO;
  1439. if(adpt_i2o_query_scalar(pHba, tid, 0x8000, -1, buf, 32)>=0) {
  1440. bus_no = buf[0]>>16;
  1441. scsi_id = buf[1];
  1442. scsi_lun = (buf[2]>>8 )&0xff;
  1443. if(bus_no >= MAX_CHANNEL) { // Something wrong skip it
  1444. continue;
  1445. }
  1446. if (scsi_id >= MAX_ID) {
  1447. continue;
  1448. }
  1449. if( pHba->channel[bus_no].device[scsi_id] == NULL){
  1450. pDev = kzalloc(sizeof(struct adpt_device),GFP_KERNEL);
  1451. if(pDev == NULL) {
  1452. return -ENOMEM;
  1453. }
  1454. pHba->channel[bus_no].device[scsi_id] = pDev;
  1455. } else {
  1456. for( pDev = pHba->channel[bus_no].device[scsi_id];
  1457. pDev->next_lun; pDev = pDev->next_lun){
  1458. }
  1459. pDev->next_lun = kzalloc(sizeof(struct adpt_device),GFP_KERNEL);
  1460. if(pDev->next_lun == NULL) {
  1461. return -ENOMEM;
  1462. }
  1463. pDev = pDev->next_lun;
  1464. }
  1465. pDev->tid = tid;
  1466. pDev->scsi_channel = bus_no;
  1467. pDev->scsi_id = scsi_id;
  1468. pDev->scsi_lun = scsi_lun;
  1469. pDev->pI2o_dev = d;
  1470. d->owner = pDev;
  1471. pDev->type = (buf[0])&0xff;
  1472. pDev->flags = (buf[0]>>8)&0xff;
  1473. if(scsi_id > pHba->top_scsi_id){
  1474. pHba->top_scsi_id = scsi_id;
  1475. }
  1476. if(scsi_lun > pHba->top_scsi_lun){
  1477. pHba->top_scsi_lun = scsi_lun;
  1478. }
  1479. }
  1480. if(scsi_id == -1){
  1481. printk(KERN_WARNING"Could not find SCSI ID for %s\n",
  1482. d->lct_data.identity_tag);
  1483. }
  1484. }
  1485. }
  1486. return 0;
  1487. }
  1488. /*
  1489. * Each I2O controller has a chain of devices on it - these match
  1490. * the useful parts of the LCT of the board.
  1491. */
  1492. static int adpt_i2o_install_device(adpt_hba* pHba, struct i2o_device *d)
  1493. {
  1494. mutex_lock(&adpt_configuration_lock);
  1495. d->controller=pHba;
  1496. d->owner=NULL;
  1497. d->next=pHba->devices;
  1498. d->prev=NULL;
  1499. if (pHba->devices != NULL){
  1500. pHba->devices->prev=d;
  1501. }
  1502. pHba->devices=d;
  1503. *d->dev_name = 0;
  1504. mutex_unlock(&adpt_configuration_lock);
  1505. return 0;
  1506. }
  1507. static int adpt_open(struct inode *inode, struct file *file)
  1508. {
  1509. int minor;
  1510. adpt_hba* pHba;
  1511. lock_kernel();
  1512. //TODO check for root access
  1513. //
  1514. minor = iminor(inode);
  1515. if (minor >= hba_count) {
  1516. unlock_kernel();
  1517. return -ENXIO;
  1518. }
  1519. mutex_lock(&adpt_configuration_lock);
  1520. for (pHba = hba_chain; pHba; pHba = pHba->next) {
  1521. if (pHba->unit == minor) {
  1522. break; /* found adapter */
  1523. }
  1524. }
  1525. if (pHba == NULL) {
  1526. mutex_unlock(&adpt_configuration_lock);
  1527. unlock_kernel();
  1528. return -ENXIO;
  1529. }
  1530. // if(pHba->in_use){
  1531. // mutex_unlock(&adpt_configuration_lock);
  1532. // return -EBUSY;
  1533. // }
  1534. pHba->in_use = 1;
  1535. mutex_unlock(&adpt_configuration_lock);
  1536. unlock_kernel();
  1537. return 0;
  1538. }
  1539. static int adpt_close(struct inode *inode, struct file *file)
  1540. {
  1541. int minor;
  1542. adpt_hba* pHba;
  1543. minor = iminor(inode);
  1544. if (minor >= hba_count) {
  1545. return -ENXIO;
  1546. }
  1547. mutex_lock(&adpt_configuration_lock);
  1548. for (pHba = hba_chain; pHba; pHba = pHba->next) {
  1549. if (pHba->unit == minor) {
  1550. break; /* found adapter */
  1551. }
  1552. }
  1553. mutex_unlock(&adpt_configuration_lock);
  1554. if (pHba == NULL) {
  1555. return -ENXIO;
  1556. }
  1557. pHba->in_use = 0;
  1558. return 0;
  1559. }
  1560. static int adpt_i2o_passthru(adpt_hba* pHba, u32 __user *arg)
  1561. {
  1562. u32 msg[MAX_MESSAGE_SIZE];
  1563. u32* reply = NULL;
  1564. u32 size = 0;
  1565. u32 reply_size = 0;
  1566. u32 __user *user_msg = arg;
  1567. u32 __user * user_reply = NULL;
  1568. void *sg_list[pHba->sg_tablesize];
  1569. u32 sg_offset = 0;
  1570. u32 sg_count = 0;
  1571. int sg_index = 0;
  1572. u32 i = 0;
  1573. u32 rcode = 0;
  1574. void *p = NULL;
  1575. dma_addr_t addr;
  1576. ulong flags = 0;
  1577. memset(&msg, 0, MAX_MESSAGE_SIZE*4);
  1578. // get user msg size in u32s
  1579. if(get_user(size, &user_msg[0])){
  1580. return -EFAULT;
  1581. }
  1582. size = size>>16;
  1583. user_reply = &user_msg[size];
  1584. if(size > MAX_MESSAGE_SIZE){
  1585. return -EFAULT;
  1586. }
  1587. size *= 4; // Convert to bytes
  1588. /* Copy in the user's I2O command */
  1589. if(copy_from_user(msg, user_msg, size)) {
  1590. return -EFAULT;
  1591. }
  1592. get_user(reply_size, &user_reply[0]);
  1593. reply_size = reply_size>>16;
  1594. if(reply_size > REPLY_FRAME_SIZE){
  1595. reply_size = REPLY_FRAME_SIZE;
  1596. }
  1597. reply_size *= 4;
  1598. reply = kzalloc(REPLY_FRAME_SIZE*4, GFP_KERNEL);
  1599. if(reply == NULL) {
  1600. printk(KERN_WARNING"%s: Could not allocate reply buffer\n",pHba->name);
  1601. return -ENOMEM;
  1602. }
  1603. sg_offset = (msg[0]>>4)&0xf;
  1604. msg[2] = 0x40000000; // IOCTL context
  1605. msg[3] = adpt_ioctl_to_context(pHba, reply);
  1606. if (msg[3] == (u32)-1)
  1607. return -EBUSY;
  1608. memset(sg_list,0, sizeof(sg_list[0])*pHba->sg_tablesize);
  1609. if(sg_offset) {
  1610. // TODO add 64 bit API
  1611. struct sg_simple_element *sg = (struct sg_simple_element*) (msg+sg_offset);
  1612. sg_count = (size - sg_offset*4) / sizeof(struct sg_simple_element);
  1613. if (sg_count > pHba->sg_tablesize){
  1614. printk(KERN_DEBUG"%s:IOCTL SG List too large (%u)\n", pHba->name,sg_count);
  1615. kfree (reply);
  1616. return -EINVAL;
  1617. }
  1618. for(i = 0; i < sg_count; i++) {
  1619. int sg_size;
  1620. if (!(sg[i].flag_count & 0x10000000 /*I2O_SGL_FLAGS_SIMPLE_ADDRESS_ELEMENT*/)) {
  1621. printk(KERN_DEBUG"%s:Bad SG element %d - not simple (%x)\n",pHba->name,i, sg[i].flag_count);
  1622. rcode = -EINVAL;
  1623. goto cleanup;
  1624. }
  1625. sg_size = sg[i].flag_count & 0xffffff;
  1626. /* Allocate memory for the transfer */
  1627. p = dma_alloc_coherent(&pHba->pDev->dev, sg_size, &addr, GFP_KERNEL);
  1628. if(!p) {
  1629. printk(KERN_DEBUG"%s: Could not allocate SG buffer - size = %d buffer number %d of %d\n",
  1630. pHba->name,sg_size,i,sg_count);
  1631. rcode = -ENOMEM;
  1632. goto cleanup;
  1633. }
  1634. sg_list[sg_index++] = p; // sglist indexed with input frame, not our internal frame.
  1635. /* Copy in the user's SG buffer if necessary */
  1636. if(sg[i].flag_count & 0x04000000 /*I2O_SGL_FLAGS_DIR*/) {
  1637. // sg_simple_element API is 32 bit
  1638. if (copy_from_user(p,(void __user *)(ulong)sg[i].addr_bus, sg_size)) {
  1639. printk(KERN_DEBUG"%s: Could not copy SG buf %d FROM user\n",pHba->name,i);
  1640. rcode = -EFAULT;
  1641. goto cleanup;
  1642. }
  1643. }
  1644. /* sg_simple_element API is 32 bit, but addr < 4GB */
  1645. sg[i].addr_bus = addr;
  1646. }
  1647. }
  1648. do {
  1649. if(pHba->host)
  1650. spin_lock_irqsave(pHba->host->host_lock, flags);
  1651. // This state stops any new commands from enterring the
  1652. // controller while processing the ioctl
  1653. // pHba->state |= DPTI_STATE_IOCTL;
  1654. // We can't set this now - The scsi subsystem sets host_blocked and
  1655. // the queue empties and stops. We need a way to restart the queue
  1656. rcode = adpt_i2o_post_wait(pHba, msg, size, FOREVER);
  1657. if (rcode != 0)
  1658. printk("adpt_i2o_passthru: post wait failed %d %p\n",
  1659. rcode, reply);
  1660. // pHba->state &= ~DPTI_STATE_IOCTL;
  1661. if(pHba->host)
  1662. spin_unlock_irqrestore(pHba->host->host_lock, flags);
  1663. } while(rcode == -ETIMEDOUT);
  1664. if(rcode){
  1665. goto cleanup;
  1666. }
  1667. if(sg_offset) {
  1668. /* Copy back the Scatter Gather buffers back to user space */
  1669. u32 j;
  1670. // TODO add 64 bit API
  1671. struct sg_simple_element* sg;
  1672. int sg_size;
  1673. // re-acquire the original message to handle correctly the sg copy operation
  1674. memset(&msg, 0, MAX_MESSAGE_SIZE*4);
  1675. // get user msg size in u32s
  1676. if(get_user(size, &user_msg[0])){
  1677. rcode = -EFAULT;
  1678. goto cleanup;
  1679. }
  1680. size = size>>16;
  1681. size *= 4;
  1682. /* Copy in the user's I2O command */
  1683. if (copy_from_user (msg, user_msg, size)) {
  1684. rcode = -EFAULT;
  1685. goto cleanup;
  1686. }
  1687. sg_count = (size - sg_offset*4) / sizeof(struct sg_simple_element);
  1688. // TODO add 64 bit API
  1689. sg = (struct sg_simple_element*)(msg + sg_offset);
  1690. for (j = 0; j < sg_count; j++) {
  1691. /* Copy out the SG list to user's buffer if necessary */
  1692. if(! (sg[j].flag_count & 0x4000000 /*I2O_SGL_FLAGS_DIR*/)) {
  1693. sg_size = sg[j].flag_count & 0xffffff;
  1694. // sg_simple_element API is 32 bit
  1695. if (copy_to_user((void __user *)(ulong)sg[j].addr_bus,sg_list[j], sg_size)) {
  1696. printk(KERN_WARNING"%s: Could not copy %p TO user %x\n",pHba->name, sg_list[j], sg[j].addr_bus);
  1697. rcode = -EFAULT;
  1698. goto cleanup;
  1699. }
  1700. }
  1701. }
  1702. }
  1703. /* Copy back the reply to user space */
  1704. if (reply_size) {
  1705. // we wrote our own values for context - now restore the user supplied ones
  1706. if(copy_from_user(reply+2, user_msg+2, sizeof(u32)*2)) {
  1707. printk(KERN_WARNING"%s: Could not copy message context FROM user\n",pHba->name);
  1708. rcode = -EFAULT;
  1709. }
  1710. if(copy_to_user(user_reply, reply, reply_size)) {
  1711. printk(KERN_WARNING"%s: Could not copy reply TO user\n",pHba->name);
  1712. rcode = -EFAULT;
  1713. }
  1714. }
  1715. cleanup:
  1716. if (rcode != -ETIME && rcode != -EINTR) {
  1717. struct sg_simple_element *sg =
  1718. (struct sg_simple_element*) (msg +sg_offset);
  1719. kfree (reply);
  1720. while(sg_index) {
  1721. if(sg_list[--sg_index]) {
  1722. dma_free_coherent(&pHba->pDev->dev,
  1723. sg[sg_index].flag_count & 0xffffff,
  1724. sg_list[sg_index],
  1725. sg[sg_index].addr_bus);
  1726. }
  1727. }
  1728. }
  1729. return rcode;
  1730. }
  1731. #if defined __ia64__
  1732. static void adpt_ia64_info(sysInfo_S* si)
  1733. {
  1734. // This is all the info we need for now
  1735. // We will add more info as our new
  1736. // managmenent utility requires it
  1737. si->processorType = PROC_IA64;
  1738. }
  1739. #endif
  1740. #if defined __sparc__
  1741. static void adpt_sparc_info(sysInfo_S* si)
  1742. {
  1743. // This is all the info we need for now
  1744. // We will add more info as our new
  1745. // managmenent utility requires it
  1746. si->processorType = PROC_ULTRASPARC;
  1747. }
  1748. #endif
  1749. #if defined __alpha__
  1750. static void adpt_alpha_info(sysInfo_S* si)
  1751. {
  1752. // This is all the info we need for now
  1753. // We will add more info as our new
  1754. // managmenent utility requires it
  1755. si->processorType = PROC_ALPHA;
  1756. }
  1757. #endif
  1758. #if defined __i386__
  1759. static void adpt_i386_info(sysInfo_S* si)
  1760. {
  1761. // This is all the info we need for now
  1762. // We will add more info as our new
  1763. // managmenent utility requires it
  1764. switch (boot_cpu_data.x86) {
  1765. case CPU_386:
  1766. si->processorType = PROC_386;
  1767. break;
  1768. case CPU_486:
  1769. si->processorType = PROC_486;
  1770. break;
  1771. case CPU_586:
  1772. si->processorType = PROC_PENTIUM;
  1773. break;
  1774. default: // Just in case
  1775. si->processorType = PROC_PENTIUM;
  1776. break;
  1777. }
  1778. }
  1779. #endif
  1780. /*
  1781. * This routine returns information about the system. This does not effect
  1782. * any logic and if the info is wrong - it doesn't matter.
  1783. */
  1784. /* Get all the info we can not get from kernel services */
  1785. static int adpt_system_info(void __user *buffer)
  1786. {
  1787. sysInfo_S si;
  1788. memset(&si, 0, sizeof(si));
  1789. si.osType = OS_LINUX;
  1790. si.osMajorVersion = 0;
  1791. si.osMinorVersion = 0;
  1792. si.osRevision = 0;
  1793. si.busType = SI_PCI_BUS;
  1794. si.processorFamily = DPTI_sig.dsProcessorFamily;
  1795. #if defined __i386__
  1796. adpt_i386_info(&si);
  1797. #elif defined (__ia64__)
  1798. adpt_ia64_info(&si);
  1799. #elif defined(__sparc__)
  1800. adpt_sparc_info(&si);
  1801. #elif defined (__alpha__)
  1802. adpt_alpha_info(&si);
  1803. #else
  1804. si.processorType = 0xff ;
  1805. #endif
  1806. if (copy_to_user(buffer, &si, sizeof(si))){
  1807. printk(KERN_WARNING"dpti: Could not copy buffer TO user\n");
  1808. return -EFAULT;
  1809. }
  1810. return 0;
  1811. }
  1812. static int adpt_ioctl(struct inode *inode, struct file *file, uint cmd,
  1813. ulong arg)
  1814. {
  1815. int minor;
  1816. int error = 0;
  1817. adpt_hba* pHba;
  1818. ulong flags = 0;
  1819. void __user *argp = (void __user *)arg;
  1820. minor = iminor(inode);
  1821. if (minor >= DPTI_MAX_HBA){
  1822. return -ENXIO;
  1823. }
  1824. mutex_lock(&adpt_configuration_lock);
  1825. for (pHba = hba_chain; pHba; pHba = pHba->next) {
  1826. if (pHba->unit == minor) {
  1827. break; /* found adapter */
  1828. }
  1829. }
  1830. mutex_unlock(&adpt_configuration_lock);
  1831. if(pHba == NULL){
  1832. return -ENXIO;
  1833. }
  1834. while((volatile u32) pHba->state & DPTI_STATE_RESET )
  1835. schedule_timeout_uninterruptible(2);
  1836. switch (cmd) {
  1837. // TODO: handle 3 cases
  1838. case DPT_SIGNATURE:
  1839. if (copy_to_user(argp, &DPTI_sig, sizeof(DPTI_sig))) {
  1840. return -EFAULT;
  1841. }
  1842. break;
  1843. case I2OUSRCMD:
  1844. return adpt_i2o_passthru(pHba, argp);
  1845. case DPT_CTRLINFO:{
  1846. drvrHBAinfo_S HbaInfo;
  1847. #define FLG_OSD_PCI_VALID 0x0001
  1848. #define FLG_OSD_DMA 0x0002
  1849. #define FLG_OSD_I2O 0x0004
  1850. memset(&HbaInfo, 0, sizeof(HbaInfo));
  1851. HbaInfo.drvrHBAnum = pHba->unit;
  1852. HbaInfo.baseAddr = (ulong) pHba->base_addr_phys;
  1853. HbaInfo.blinkState = adpt_read_blink_led(pHba);
  1854. HbaInfo.pciBusNum = pHba->pDev->bus->number;
  1855. HbaInfo.pciDeviceNum=PCI_SLOT(pHba->pDev->devfn);
  1856. HbaInfo.Interrupt = pHba->pDev->irq;
  1857. HbaInfo.hbaFlags = FLG_OSD_PCI_VALID | FLG_OSD_DMA | FLG_OSD_I2O;
  1858. if(copy_to_user(argp, &HbaInfo, sizeof(HbaInfo))){
  1859. printk(KERN_WARNING"%s: Could not copy HbaInfo TO user\n",pHba->name);
  1860. return -EFAULT;
  1861. }
  1862. break;
  1863. }
  1864. case DPT_SYSINFO:
  1865. return adpt_system_info(argp);
  1866. case DPT_BLINKLED:{
  1867. u32 value;
  1868. value = (u32)adpt_read_blink_led(pHba);
  1869. if (copy_to_user(argp, &value, sizeof(value))) {
  1870. return -EFAULT;
  1871. }
  1872. break;
  1873. }
  1874. case I2ORESETCMD:
  1875. if(pHba->host)
  1876. spin_lock_irqsave(pHba->host->host_lock, flags);
  1877. adpt_hba_reset(pHba);
  1878. if(pHba->host)
  1879. spin_unlock_irqrestore(pHba->host->host_lock, flags);
  1880. break;
  1881. case I2ORESCANCMD:
  1882. adpt_rescan(pHba);
  1883. break;
  1884. default:
  1885. return -EINVAL;
  1886. }
  1887. return error;
  1888. }
  1889. #ifdef CONFIG_COMPAT
  1890. static long compat_adpt_ioctl(struct file *file,
  1891. unsigned int cmd, unsigned long arg)
  1892. {
  1893. struct inode *inode;
  1894. long ret;
  1895. inode = file->f_dentry->d_inode;
  1896. lock_kernel();
  1897. switch(cmd) {
  1898. case DPT_SIGNATURE:
  1899. case I2OUSRCMD:
  1900. case DPT_CTRLINFO:
  1901. case DPT_SYSINFO:
  1902. case DPT_BLINKLED:
  1903. case I2ORESETCMD:
  1904. case I2ORESCANCMD:
  1905. case (DPT_TARGET_BUSY & 0xFFFF):
  1906. case DPT_TARGET_BUSY:
  1907. ret = adpt_ioctl(inode, file, cmd, arg);
  1908. break;
  1909. default:
  1910. ret = -ENOIOCTLCMD;
  1911. }
  1912. unlock_kernel();
  1913. return ret;
  1914. }
  1915. #endif
  1916. static irqreturn_t adpt_isr(int irq, void *dev_id)
  1917. {
  1918. struct scsi_cmnd* cmd;
  1919. adpt_hba* pHba = dev_id;
  1920. u32 m;
  1921. void __iomem *reply;
  1922. u32 status=0;
  1923. u32 context;
  1924. ulong flags = 0;
  1925. int handled = 0;
  1926. if (pHba == NULL){
  1927. printk(KERN_WARNING"adpt_isr: NULL dev_id\n");
  1928. return IRQ_NONE;
  1929. }
  1930. if(pHba->host)
  1931. spin_lock_irqsave(pHba->host->host_lock, flags);
  1932. while( readl(pHba->irq_mask) & I2O_INTERRUPT_PENDING_B) {
  1933. m = readl(pHba->reply_port);
  1934. if(m == EMPTY_QUEUE){
  1935. // Try twice then give up
  1936. rmb();
  1937. m = readl(pHba->reply_port);
  1938. if(m == EMPTY_QUEUE){
  1939. // This really should not happen
  1940. printk(KERN_ERR"dpti: Could not get reply frame\n");
  1941. goto out;
  1942. }
  1943. }
  1944. if (pHba->reply_pool_pa <= m &&
  1945. m < pHba->reply_pool_pa +
  1946. (pHba->reply_fifo_size * REPLY_FRAME_SIZE * 4)) {
  1947. reply = (u8 *)pHba->reply_pool +
  1948. (m - pHba->reply_pool_pa);
  1949. } else {
  1950. /* Ick, we should *never* be here */
  1951. printk(KERN_ERR "dpti: reply frame not from pool\n");
  1952. reply = (u8 *)bus_to_virt(m);
  1953. }
  1954. if (readl(reply) & MSG_FAIL) {
  1955. u32 old_m = readl(reply+28);
  1956. void __iomem *msg;
  1957. u32 old_context;
  1958. PDEBUG("%s: Failed message\n",pHba->name);
  1959. if(old_m >= 0x100000){
  1960. printk(KERN_ERR"%s: Bad preserved MFA (%x)- dropping frame\n",pHba->name,old_m);
  1961. writel(m,pHba->reply_port);
  1962. continue;
  1963. }
  1964. // Transaction context is 0 in failed reply frame
  1965. msg = pHba->msg_addr_virt + old_m;
  1966. old_context = readl(msg+12);
  1967. writel(old_context, reply+12);
  1968. adpt_send_nop(pHba, old_m);
  1969. }
  1970. context = readl(reply+8);
  1971. if(context & 0x40000000){ // IOCTL
  1972. void *p = adpt_ioctl_from_context(pHba, readl(reply+12));
  1973. if( p != NULL) {
  1974. memcpy_fromio(p, reply, REPLY_FRAME_SIZE * 4);
  1975. }
  1976. // All IOCTLs will also be post wait
  1977. }
  1978. if(context & 0x80000000){ // Post wait message
  1979. status = readl(reply+16);
  1980. if(status >> 24){
  1981. status &= 0xffff; /* Get detail status */
  1982. } else {
  1983. status = I2O_POST_WAIT_OK;
  1984. }
  1985. if(!(context & 0x40000000)) {
  1986. cmd = adpt_cmd_from_context(pHba,
  1987. readl(reply+12));
  1988. if(cmd != NULL) {
  1989. printk(KERN_WARNING"%s: Apparent SCSI cmd in Post Wait Context - cmd=%p context=%x\n", pHba->name, cmd, context);
  1990. }
  1991. }
  1992. adpt_i2o_post_wait_complete(context, status);
  1993. } else { // SCSI message
  1994. cmd = adpt_cmd_from_context (pHba, readl(reply+12));
  1995. if(cmd != NULL){
  1996. scsi_dma_unmap(cmd);
  1997. if(cmd->serial_number != 0) { // If not timedout
  1998. adpt_i2o_to_scsi(reply, cmd);
  1999. }
  2000. }
  2001. }
  2002. writel(m, pHba->reply_port);
  2003. wmb();
  2004. rmb();
  2005. }
  2006. handled = 1;
  2007. out: if(pHba->host)
  2008. spin_unlock_irqrestore(pHba->host->host_lock, flags);
  2009. return IRQ_RETVAL(handled);
  2010. }
  2011. static s32 adpt_scsi_to_i2o(adpt_hba* pHba, struct scsi_cmnd* cmd, struct adpt_device* d)
  2012. {
  2013. int i;
  2014. u32 msg[MAX_MESSAGE_SIZE];
  2015. u32* mptr;
  2016. u32* lptr;
  2017. u32 *lenptr;
  2018. int direction;
  2019. int scsidir;
  2020. int nseg;
  2021. u32 len;
  2022. u32 reqlen;
  2023. s32 rcode;
  2024. dma_addr_t addr;
  2025. memset(msg, 0 , sizeof(msg));
  2026. len = scsi_bufflen(cmd);
  2027. direction = 0x00000000;
  2028. scsidir = 0x00000000; // DATA NO XFER
  2029. if(len) {
  2030. /*
  2031. * Set SCBFlags to indicate if data is being transferred
  2032. * in or out, or no data transfer
  2033. * Note: Do not have to verify index is less than 0 since
  2034. * cmd->cmnd[0] is an unsigned char
  2035. */
  2036. switch(cmd->sc_data_direction){
  2037. case DMA_FROM_DEVICE:
  2038. scsidir =0x40000000; // DATA IN (iop<--dev)
  2039. break;
  2040. case DMA_TO_DEVICE:
  2041. direction=0x04000000; // SGL OUT
  2042. scsidir =0x80000000; // DATA OUT (iop-->dev)
  2043. break;
  2044. case DMA_NONE:
  2045. break;
  2046. case DMA_BIDIRECTIONAL:
  2047. scsidir =0x40000000; // DATA IN (iop<--dev)
  2048. // Assume In - and continue;
  2049. break;
  2050. default:
  2051. printk(KERN_WARNING"%s: scsi opcode 0x%x not supported.\n",
  2052. pHba->name, cmd->cmnd[0]);
  2053. cmd->result = (DID_OK <<16) | (INITIATOR_ERROR << 8);
  2054. cmd->scsi_done(cmd);
  2055. return 0;
  2056. }
  2057. }
  2058. // msg[0] is set later
  2059. // I2O_CMD_SCSI_EXEC
  2060. msg[1] = ((0xff<<24)|(HOST_TID<<12)|d->tid);
  2061. msg[2] = 0;
  2062. msg[3] = adpt_cmd_to_context(cmd); /* Want SCSI control block back */
  2063. // Our cards use the transaction context as the tag for queueing
  2064. // Adaptec/DPT Private stuff
  2065. msg[4] = I2O_CMD_SCSI_EXEC|(DPT_ORGANIZATION_ID<<16);
  2066. msg[5] = d->tid;
  2067. /* Direction, disconnect ok | sense data | simple queue , CDBLen */
  2068. // I2O_SCB_FLAG_ENABLE_DISCONNECT |
  2069. // I2O_SCB_FLAG_SIMPLE_QUEUE_TAG |
  2070. // I2O_SCB_FLAG_SENSE_DATA_IN_MESSAGE;
  2071. msg[6] = scsidir|0x20a00000|cmd->cmd_len;
  2072. mptr=msg+7;
  2073. // Write SCSI command into the message - always 16 byte block
  2074. memset(mptr, 0, 16);
  2075. memcpy(mptr, cmd->cmnd, cmd->cmd_len);
  2076. mptr+=4;
  2077. lenptr=mptr++; /* Remember me - fill in when we know */
  2078. if (dpt_dma64(pHba)) {
  2079. reqlen = 16; // SINGLE SGE
  2080. *mptr++ = (0x7C<<24)+(2<<16)+0x02; /* Enable 64 bit */
  2081. *mptr++ = 1 << PAGE_SHIFT;
  2082. } else {
  2083. reqlen = 14; // SINGLE SGE
  2084. }
  2085. /* Now fill in the SGList and command */
  2086. nseg = scsi_dma_map(cmd);
  2087. BUG_ON(nseg < 0);
  2088. if (nseg) {
  2089. struct scatterlist *sg;
  2090. len = 0;
  2091. scsi_for_each_sg(cmd, sg, nseg, i) {
  2092. lptr = mptr;
  2093. *mptr++ = direction|0x10000000|sg_dma_len(sg);
  2094. len+=sg_dma_len(sg);
  2095. addr = sg_dma_address(sg);
  2096. *mptr++ = dma_low(addr);
  2097. if (dpt_dma64(pHba))
  2098. *mptr++ = dma_high(addr);
  2099. /* Make this an end of list */
  2100. if (i == nseg - 1)
  2101. *lptr = direction|0xD0000000|sg_dma_len(sg);
  2102. }
  2103. reqlen = mptr - msg;
  2104. *lenptr = len;
  2105. if(cmd->underflow && len != cmd->underflow){
  2106. printk(KERN_WARNING"Cmd len %08X Cmd underflow %08X\n",
  2107. len, cmd->underflow);
  2108. }
  2109. } else {
  2110. *lenptr = len = 0;
  2111. reqlen = 12;
  2112. }
  2113. /* Stick the headers on */
  2114. msg[0] = reqlen<<16 | ((reqlen > 12) ? SGL_OFFSET_12 : SGL_OFFSET_0);
  2115. // Send it on it's way
  2116. rcode = adpt_i2o_post_this(pHba, msg, reqlen<<2);
  2117. if (rcode == 0) {
  2118. return 0;
  2119. }
  2120. return rcode;
  2121. }
  2122. static s32 adpt_scsi_host_alloc(adpt_hba* pHba, struct scsi_host_template *sht)
  2123. {
  2124. struct Scsi_Host *host;
  2125. host = scsi_host_alloc(sht, sizeof(adpt_hba*));
  2126. if (host == NULL) {
  2127. printk("%s: scsi_host_alloc returned NULL\n", pHba->name);
  2128. return -1;
  2129. }
  2130. host->hostdata[0] = (unsigned long)pHba;
  2131. pHba->host = host;
  2132. host->irq = pHba->pDev->irq;
  2133. /* no IO ports, so don't have to set host->io_port and
  2134. * host->n_io_port
  2135. */
  2136. host->io_port = 0;
  2137. host->n_io_port = 0;
  2138. /* see comments in scsi_host.h */
  2139. host->max_id = 16;
  2140. host->max_lun = 256;
  2141. host->max_channel = pHba->top_scsi_channel + 1;
  2142. host->cmd_per_lun = 1;
  2143. host->unique_id = (u32)sys_tbl_pa + pHba->unit;
  2144. host->sg_tablesize = pHba->sg_tablesize;
  2145. host->can_queue = pHba->post_fifo_size;
  2146. return 0;
  2147. }
  2148. static s32 adpt_i2o_to_scsi(void __iomem *reply, struct scsi_cmnd* cmd)
  2149. {
  2150. adpt_hba* pHba;
  2151. u32 hba_status;
  2152. u32 dev_status;
  2153. u32 reply_flags = readl(reply) & 0xff00; // Leave it shifted up 8 bits
  2154. // I know this would look cleaner if I just read bytes
  2155. // but the model I have been using for all the rest of the
  2156. // io is in 4 byte words - so I keep that model
  2157. u16 detailed_status = readl(reply+16) &0xffff;
  2158. dev_status = (detailed_status & 0xff);
  2159. hba_status = detailed_status >> 8;
  2160. // calculate resid for sg
  2161. scsi_set_resid(cmd, scsi_bufflen(cmd) - readl(reply+20));
  2162. pHba = (adpt_hba*) cmd->device->host->hostdata[0];
  2163. cmd->sense_buffer[0] = '\0'; // initialize sense valid flag to false
  2164. if(!(reply_flags & MSG_FAIL)) {
  2165. switch(detailed_status & I2O_SCSI_DSC_MASK) {
  2166. case I2O_SCSI_DSC_SUCCESS:
  2167. cmd->result = (DID_OK << 16);
  2168. // handle underflow
  2169. if (readl(reply+20) < cmd->underflow) {
  2170. cmd->result = (DID_ERROR <<16);
  2171. printk(KERN_WARNING"%s: SCSI CMD underflow\n",pHba->name);
  2172. }
  2173. break;
  2174. case I2O_SCSI_DSC_REQUEST_ABORTED:
  2175. cmd->result = (DID_ABORT << 16);
  2176. break;
  2177. case I2O_SCSI_DSC_PATH_INVALID:
  2178. case I2O_SCSI_DSC_DEVICE_NOT_PRESENT:
  2179. case I2O_SCSI_DSC_SELECTION_TIMEOUT:
  2180. case I2O_SCSI_DSC_COMMAND_TIMEOUT:
  2181. case I2O_SCSI_DSC_NO_ADAPTER:
  2182. case I2O_SCSI_DSC_RESOURCE_UNAVAILABLE:
  2183. printk(KERN_WARNING"%s: SCSI Timeout-Device (%d,%d,%d) hba status=0x%x, dev status=0x%x, cmd=0x%x\n",
  2184. pHba->name, (u32)cmd->device->channel, (u32)cmd->device->id, (u32)cmd->device->lun, hba_status, dev_status, cmd->cmnd[0]);
  2185. cmd->result = (DID_TIME_OUT << 16);
  2186. break;
  2187. case I2O_SCSI_DSC_ADAPTER_BUSY:
  2188. case I2O_SCSI_DSC_BUS_BUSY:
  2189. cmd->result = (DID_BUS_BUSY << 16);
  2190. break;
  2191. case I2O_SCSI_DSC_SCSI_BUS_RESET:
  2192. case I2O_SCSI_DSC_BDR_MESSAGE_SENT:
  2193. cmd->result = (DID_RESET << 16);
  2194. break;
  2195. case I2O_SCSI_DSC_PARITY_ERROR_FAILURE:
  2196. printk(KERN_WARNING"%s: SCSI CMD parity error\n",pHba->name);
  2197. cmd->result = (DID_PARITY << 16);
  2198. break;
  2199. case I2O_SCSI_DSC_UNABLE_TO_ABORT:
  2200. case I2O_SCSI_DSC_COMPLETE_WITH_ERROR:
  2201. case I2O_SCSI_DSC_UNABLE_TO_TERMINATE:
  2202. case I2O_SCSI_DSC_MR_MESSAGE_RECEIVED:
  2203. case I2O_SCSI_DSC_AUTOSENSE_FAILED:
  2204. case I2O_SCSI_DSC_DATA_OVERRUN:
  2205. case I2O_SCSI_DSC_UNEXPECTED_BUS_FREE:
  2206. case I2O_SCSI_DSC_SEQUENCE_FAILURE:
  2207. case I2O_SCSI_DSC_REQUEST_LENGTH_ERROR:
  2208. case I2O_SCSI_DSC_PROVIDE_FAILURE:
  2209. case I2O_SCSI_DSC_REQUEST_TERMINATED:
  2210. case I2O_SCSI_DSC_IDE_MESSAGE_SENT:
  2211. case I2O_SCSI_DSC_UNACKNOWLEDGED_EVENT:
  2212. case I2O_SCSI_DSC_MESSAGE_RECEIVED:
  2213. case I2O_SCSI_DSC_INVALID_CDB:
  2214. case I2O_SCSI_DSC_LUN_INVALID:
  2215. case I2O_SCSI_DSC_SCSI_TID_INVALID:
  2216. case I2O_SCSI_DSC_FUNCTION_UNAVAILABLE:
  2217. case I2O_SCSI_DSC_NO_NEXUS:
  2218. case I2O_SCSI_DSC_CDB_RECEIVED:
  2219. case I2O_SCSI_DSC_LUN_ALREADY_ENABLED:
  2220. case I2O_SCSI_DSC_QUEUE_FROZEN:
  2221. case I2O_SCSI_DSC_REQUEST_INVALID:
  2222. default:
  2223. printk(KERN_WARNING"%s: SCSI error %0x-Device(%d,%d,%d) hba_status=0x%x, dev_status=0x%x, cmd=0x%x\n",
  2224. pHba->name, detailed_status & I2O_SCSI_DSC_MASK, (u32)cmd->device->channel, (u32)cmd->device->id, (u32)cmd->device->lun,
  2225. hba_status, dev_status, cmd->cmnd[0]);
  2226. cmd->result = (DID_ERROR << 16);
  2227. break;
  2228. }
  2229. // copy over the request sense data if it was a check
  2230. // condition status
  2231. if (dev_status == SAM_STAT_CHECK_CONDITION) {
  2232. u32 len = min(SCSI_SENSE_BUFFERSIZE, 40);
  2233. // Copy over the sense data
  2234. memcpy_fromio(cmd->sense_buffer, (reply+28) , len);
  2235. if(cmd->sense_buffer[0] == 0x70 /* class 7 */ &&
  2236. cmd->sense_buffer[2] == DATA_PROTECT ){
  2237. /* This is to handle an array failed */
  2238. cmd->result = (DID_TIME_OUT << 16);
  2239. printk(KERN_WARNING"%s: SCSI Data Protect-Device (%d,%d,%d) hba_status=0x%x, dev_status=0x%x, cmd=0x%x\n",
  2240. pHba->name, (u32)cmd->device->channel, (u32)cmd->device->id, (u32)cmd->device->lun,
  2241. hba_status, dev_status, cmd->cmnd[0]);
  2242. }
  2243. }
  2244. } else {
  2245. /* In this condtion we could not talk to the tid
  2246. * the card rejected it. We should signal a retry
  2247. * for a limitted number of retries.
  2248. */
  2249. cmd->result = (DID_TIME_OUT << 16);
  2250. printk(KERN_WARNING"%s: I2O MSG_FAIL - Device (%d,%d,%d) tid=%d, cmd=0x%x\n",
  2251. pHba->name, (u32)cmd->device->channel, (u32)cmd->device->id, (u32)cmd->device->lun,
  2252. ((struct adpt_device*)(cmd->device->hostdata))->tid, cmd->cmnd[0]);
  2253. }
  2254. cmd->result |= (dev_status);
  2255. if(cmd->scsi_done != NULL){
  2256. cmd->scsi_done(cmd);
  2257. }
  2258. return cmd->result;
  2259. }
  2260. static s32 adpt_rescan(adpt_hba* pHba)
  2261. {
  2262. s32 rcode;
  2263. ulong flags = 0;
  2264. if(pHba->host)
  2265. spin_lock_irqsave(pHba->host->host_lock, flags);
  2266. if ((rcode=adpt_i2o_lct_get(pHba)) < 0)
  2267. goto out;
  2268. if ((rcode=adpt_i2o_reparse_lct(pHba)) < 0)
  2269. goto out;
  2270. rcode = 0;
  2271. out: if(pHba->host)
  2272. spin_unlock_irqrestore(pHba->host->host_lock, flags);
  2273. return rcode;
  2274. }
  2275. static s32 adpt_i2o_reparse_lct(adpt_hba* pHba)
  2276. {
  2277. int i;
  2278. int max;
  2279. int tid;
  2280. struct i2o_device *d;
  2281. i2o_lct *lct = pHba->lct;
  2282. u8 bus_no = 0;
  2283. s16 scsi_id;
  2284. s16 scsi_lun;
  2285. u32 buf[10]; // at least 8 u32's
  2286. struct adpt_device* pDev = NULL;
  2287. struct i2o_device* pI2o_dev = NULL;
  2288. if (lct == NULL) {
  2289. printk(KERN_ERR "%s: LCT is empty???\n",pHba->name);
  2290. return -1;
  2291. }
  2292. max = lct->table_size;
  2293. max -= 3;
  2294. max /= 9;
  2295. // Mark each drive as unscanned
  2296. for (d = pHba->devices; d; d = d->next) {
  2297. pDev =(struct adpt_device*) d->owner;
  2298. if(!pDev){
  2299. continue;
  2300. }
  2301. pDev->state |= DPTI_DEV_UNSCANNED;
  2302. }
  2303. printk(KERN_INFO "%s: LCT has %d entries.\n", pHba->name,max);
  2304. for(i=0;i<max;i++) {
  2305. if( lct->lct_entry[i].user_tid != 0xfff){
  2306. continue;
  2307. }
  2308. if( lct->lct_entry[i].class_id == I2O_CLASS_RANDOM_BLOCK_STORAGE ||
  2309. lct->lct_entry[i].class_id == I2O_CLASS_SCSI_PERIPHERAL ||
  2310. lct->lct_entry[i].class_id == I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL ){
  2311. tid = lct->lct_entry[i].tid;
  2312. if(adpt_i2o_query_scalar(pHba, tid, 0x8000, -1, buf, 32)<0) {
  2313. printk(KERN_ERR"%s: Could not query device\n",pHba->name);
  2314. continue;
  2315. }
  2316. bus_no = buf[0]>>16;
  2317. scsi_id = buf[1];
  2318. scsi_lun = (buf[2]>>8 )&0xff;
  2319. pDev = pHba->channel[bus_no].device[scsi_id];
  2320. /* da lun */
  2321. while(pDev) {
  2322. if(pDev->scsi_lun == scsi_lun) {
  2323. break;
  2324. }
  2325. pDev = pDev->next_lun;
  2326. }
  2327. if(!pDev ) { // Something new add it
  2328. d = kmalloc(sizeof(struct i2o_device), GFP_KERNEL);
  2329. if(d==NULL)
  2330. {
  2331. printk(KERN_CRIT "Out of memory for I2O device data.\n");
  2332. return -ENOMEM;
  2333. }
  2334. d->controller = pHba;
  2335. d->next = NULL;
  2336. memcpy(&d->lct_data, &lct->lct_entry[i], sizeof(i2o_lct_entry));
  2337. d->flags = 0;
  2338. adpt_i2o_report_hba_unit(pHba, d);
  2339. adpt_i2o_install_device(pHba, d);
  2340. if(bus_no >= MAX_CHANNEL) { // Something wrong skip it
  2341. printk(KERN_WARNING"%s: Channel number %d out of range \n", pHba->name, bus_no);
  2342. continue;
  2343. }
  2344. pDev = pHba->channel[bus_no].device[scsi_id];
  2345. if( pDev == NULL){
  2346. pDev = kzalloc(sizeof(struct adpt_device),GFP_KERNEL);
  2347. if(pDev == NULL) {
  2348. return -ENOMEM;
  2349. }
  2350. pHba->channel[bus_no].device[scsi_id] = pDev;
  2351. } else {
  2352. while (pDev->next_lun) {
  2353. pDev = pDev->next_lun;
  2354. }
  2355. pDev = pDev->next_lun = kzalloc(sizeof(struct adpt_device),GFP_KERNEL);
  2356. if(pDev == NULL) {
  2357. return -ENOMEM;
  2358. }
  2359. }
  2360. pDev->tid = d->lct_data.tid;
  2361. pDev->scsi_channel = bus_no;
  2362. pDev->scsi_id = scsi_id;
  2363. pDev->scsi_lun = scsi_lun;
  2364. pDev->pI2o_dev = d;
  2365. d->owner = pDev;
  2366. pDev->type = (buf[0])&0xff;
  2367. pDev->flags = (buf[0]>>8)&0xff;
  2368. // Too late, SCSI system has made up it's mind, but what the hey ...
  2369. if(scsi_id > pHba->top_scsi_id){
  2370. pHba->top_scsi_id = scsi_id;
  2371. }
  2372. if(scsi_lun > pHba->top_scsi_lun){
  2373. pHba->top_scsi_lun = scsi_lun;
  2374. }
  2375. continue;
  2376. } // end of new i2o device
  2377. // We found an old device - check it
  2378. while(pDev) {
  2379. if(pDev->scsi_lun == scsi_lun) {
  2380. if(!scsi_device_online(pDev->pScsi_dev)) {
  2381. printk(KERN_WARNING"%s: Setting device (%d,%d,%d) back online\n",
  2382. pHba->name,bus_no,scsi_id,scsi_lun);
  2383. if (pDev->pScsi_dev) {
  2384. scsi_device_set_state(pDev->pScsi_dev, SDEV_RUNNING);
  2385. }
  2386. }
  2387. d = pDev->pI2o_dev;
  2388. if(d->lct_data.tid != tid) { // something changed
  2389. pDev->tid = tid;
  2390. memcpy(&d->lct_data, &lct->lct_entry[i], sizeof(i2o_lct_entry));
  2391. if (pDev->pScsi_dev) {
  2392. pDev->pScsi_dev->changed = TRUE;
  2393. pDev->pScsi_dev->removable = TRUE;
  2394. }
  2395. }
  2396. // Found it - mark it scanned
  2397. pDev->state = DPTI_DEV_ONLINE;
  2398. break;
  2399. }
  2400. pDev = pDev->next_lun;
  2401. }
  2402. }
  2403. }
  2404. for (pI2o_dev = pHba->devices; pI2o_dev; pI2o_dev = pI2o_dev->next) {
  2405. pDev =(struct adpt_device*) pI2o_dev->owner;
  2406. if(!pDev){
  2407. continue;
  2408. }
  2409. // Drive offline drives that previously existed but could not be found
  2410. // in the LCT table
  2411. if (pDev->state & DPTI_DEV_UNSCANNED){
  2412. pDev->state = DPTI_DEV_OFFLINE;
  2413. printk(KERN_WARNING"%s: Device (%d,%d,%d) offline\n",pHba->name,pDev->scsi_channel,pDev->scsi_id,pDev->scsi_lun);
  2414. if (pDev->pScsi_dev) {
  2415. scsi_device_set_state(pDev->pScsi_dev, SDEV_OFFLINE);
  2416. }
  2417. }
  2418. }
  2419. return 0;
  2420. }
  2421. static void adpt_fail_posted_scbs(adpt_hba* pHba)
  2422. {
  2423. struct scsi_cmnd* cmd = NULL;
  2424. struct scsi_device* d = NULL;
  2425. shost_for_each_device(d, pHba->host) {
  2426. unsigned long flags;
  2427. spin_lock_irqsave(&d->list_lock, flags);
  2428. list_for_each_entry(cmd, &d->cmd_list, list) {
  2429. if(cmd->serial_number == 0){
  2430. continue;
  2431. }
  2432. cmd->result = (DID_OK << 16) | (QUEUE_FULL <<1);
  2433. cmd->scsi_done(cmd);
  2434. }
  2435. spin_unlock_irqrestore(&d->list_lock, flags);
  2436. }
  2437. }
  2438. /*============================================================================
  2439. * Routines from i2o subsystem
  2440. *============================================================================
  2441. */
  2442. /*
  2443. * Bring an I2O controller into HOLD state. See the spec.
  2444. */
  2445. static int adpt_i2o_activate_hba(adpt_hba* pHba)
  2446. {
  2447. int rcode;
  2448. if(pHba->initialized ) {
  2449. if (adpt_i2o_status_get(pHba) < 0) {
  2450. if((rcode = adpt_i2o_reset_hba(pHba)) != 0){
  2451. printk(KERN_WARNING"%s: Could NOT reset.\n", pHba->name);
  2452. return rcode;
  2453. }
  2454. if (adpt_i2o_status_get(pHba) < 0) {
  2455. printk(KERN_INFO "HBA not responding.\n");
  2456. return -1;
  2457. }
  2458. }
  2459. if(pHba->status_block->iop_state == ADAPTER_STATE_FAULTED) {
  2460. printk(KERN_CRIT "%s: hardware fault\n", pHba->name);
  2461. return -1;
  2462. }
  2463. if (pHba->status_block->iop_state == ADAPTER_STATE_READY ||
  2464. pHba->status_block->iop_state == ADAPTER_STATE_OPERATIONAL ||
  2465. pHba->status_block->iop_state == ADAPTER_STATE_HOLD ||
  2466. pHba->status_block->iop_state == ADAPTER_STATE_FAILED) {
  2467. adpt_i2o_reset_hba(pHba);
  2468. if (adpt_i2o_status_get(pHba) < 0 || pHba->status_block->iop_state != ADAPTER_STATE_RESET) {
  2469. printk(KERN_ERR "%s: Failed to initialize.\n", pHba->name);
  2470. return -1;
  2471. }
  2472. }
  2473. } else {
  2474. if((rcode = adpt_i2o_reset_hba(pHba)) != 0){
  2475. printk(KERN_WARNING"%s: Could NOT reset.\n", pHba->name);
  2476. return rcode;
  2477. }
  2478. }
  2479. if (adpt_i2o_init_outbound_q(pHba) < 0) {
  2480. return -1;
  2481. }
  2482. /* In HOLD state */
  2483. if (adpt_i2o_hrt_get(pHba) < 0) {
  2484. return -1;
  2485. }
  2486. return 0;
  2487. }
  2488. /*
  2489. * Bring a controller online into OPERATIONAL state.
  2490. */
  2491. static int adpt_i2o_online_hba(adpt_hba* pHba)
  2492. {
  2493. if (adpt_i2o_systab_send(pHba) < 0) {
  2494. adpt_i2o_delete_hba(pHba);
  2495. return -1;
  2496. }
  2497. /* In READY state */
  2498. if (adpt_i2o_enable_hba(pHba) < 0) {
  2499. adpt_i2o_delete_hba(pHba);
  2500. return -1;
  2501. }
  2502. /* In OPERATIONAL state */
  2503. return 0;
  2504. }
  2505. static s32 adpt_send_nop(adpt_hba*pHba,u32 m)
  2506. {
  2507. u32 __iomem *msg;
  2508. ulong timeout = jiffies + 5*HZ;
  2509. while(m == EMPTY_QUEUE){
  2510. rmb();
  2511. m = readl(pHba->post_port);
  2512. if(m != EMPTY_QUEUE){
  2513. break;
  2514. }
  2515. if(time_after(jiffies,timeout)){
  2516. printk(KERN_ERR "%s: Timeout waiting for message frame!\n",pHba->name);
  2517. return 2;
  2518. }
  2519. schedule_timeout_uninterruptible(1);
  2520. }
  2521. msg = (u32 __iomem *)(pHba->msg_addr_virt + m);
  2522. writel( THREE_WORD_MSG_SIZE | SGL_OFFSET_0,&msg[0]);
  2523. writel( I2O_CMD_UTIL_NOP << 24 | HOST_TID << 12 | 0,&msg[1]);
  2524. writel( 0,&msg[2]);
  2525. wmb();
  2526. writel(m, pHba->post_port);
  2527. wmb();
  2528. return 0;
  2529. }
  2530. static s32 adpt_i2o_init_outbound_q(adpt_hba* pHba)
  2531. {
  2532. u8 *status;
  2533. dma_addr_t addr;
  2534. u32 __iomem *msg = NULL;
  2535. int i;
  2536. ulong timeout = jiffies + TMOUT_INITOUTBOUND*HZ;
  2537. u32 m;
  2538. do {
  2539. rmb();
  2540. m = readl(pHba->post_port);
  2541. if (m != EMPTY_QUEUE) {
  2542. break;
  2543. }
  2544. if(time_after(jiffies,timeout)){
  2545. printk(KERN_WARNING"%s: Timeout waiting for message frame\n",pHba->name);
  2546. return -ETIMEDOUT;
  2547. }
  2548. schedule_timeout_uninterruptible(1);
  2549. } while(m == EMPTY_QUEUE);
  2550. msg=(u32 __iomem *)(pHba->msg_addr_virt+m);
  2551. status = dma_alloc_coherent(&pHba->pDev->dev, 4, &addr, GFP_KERNEL);
  2552. if (!status) {
  2553. adpt_send_nop(pHba, m);
  2554. printk(KERN_WARNING"%s: IOP reset failed - no free memory.\n",
  2555. pHba->name);
  2556. return -ENOMEM;
  2557. }
  2558. memset(status, 0, 4);
  2559. writel(EIGHT_WORD_MSG_SIZE| SGL_OFFSET_6, &msg[0]);
  2560. writel(I2O_CMD_OUTBOUND_INIT<<24 | HOST_TID<<12 | ADAPTER_TID, &msg[1]);
  2561. writel(0, &msg[2]);
  2562. writel(0x0106, &msg[3]); /* Transaction context */
  2563. writel(4096, &msg[4]); /* Host page frame size */
  2564. writel((REPLY_FRAME_SIZE)<<16|0x80, &msg[5]); /* Outbound msg frame size and Initcode */
  2565. writel(0xD0000004, &msg[6]); /* Simple SG LE, EOB */
  2566. writel((u32)addr, &msg[7]);
  2567. writel(m, pHba->post_port);
  2568. wmb();
  2569. // Wait for the reply status to come back
  2570. do {
  2571. if (*status) {
  2572. if (*status != 0x01 /*I2O_EXEC_OUTBOUND_INIT_IN_PROGRESS*/) {
  2573. break;
  2574. }
  2575. }
  2576. rmb();
  2577. if(time_after(jiffies,timeout)){
  2578. printk(KERN_WARNING"%s: Timeout Initializing\n",pHba->name);
  2579. /* We lose 4 bytes of "status" here, but we
  2580. cannot free these because controller may
  2581. awake and corrupt those bytes at any time */
  2582. /* dma_free_coherent(&pHba->pDev->dev, 4, status, addr); */
  2583. return -ETIMEDOUT;
  2584. }
  2585. schedule_timeout_uninterruptible(1);
  2586. } while (1);
  2587. // If the command was successful, fill the fifo with our reply
  2588. // message packets
  2589. if(*status != 0x04 /*I2O_EXEC_OUTBOUND_INIT_COMPLETE*/) {
  2590. dma_free_coherent(&pHba->pDev->dev, 4, status, addr);
  2591. return -2;
  2592. }
  2593. dma_free_coherent(&pHba->pDev->dev, 4, status, addr);
  2594. if(pHba->reply_pool != NULL) {
  2595. dma_free_coherent(&pHba->pDev->dev,
  2596. pHba->reply_fifo_size * REPLY_FRAME_SIZE * 4,
  2597. pHba->reply_pool, pHba->reply_pool_pa);
  2598. }
  2599. pHba->reply_pool = dma_alloc_coherent(&pHba->pDev->dev,
  2600. pHba->reply_fifo_size * REPLY_FRAME_SIZE * 4,
  2601. &pHba->reply_pool_pa, GFP_KERNEL);
  2602. if (!pHba->reply_pool) {
  2603. printk(KERN_ERR "%s: Could not allocate reply pool\n", pHba->name);
  2604. return -ENOMEM;
  2605. }
  2606. memset(pHba->reply_pool, 0 , pHba->reply_fifo_size * REPLY_FRAME_SIZE * 4);
  2607. for(i = 0; i < pHba->reply_fifo_size; i++) {
  2608. writel(pHba->reply_pool_pa + (i * REPLY_FRAME_SIZE * 4),
  2609. pHba->reply_port);
  2610. wmb();
  2611. }
  2612. adpt_i2o_status_get(pHba);
  2613. return 0;
  2614. }
  2615. /*
  2616. * I2O System Table. Contains information about
  2617. * all the IOPs in the system. Used to inform IOPs
  2618. * about each other's existence.
  2619. *
  2620. * sys_tbl_ver is the CurrentChangeIndicator that is
  2621. * used by IOPs to track changes.
  2622. */
  2623. static s32 adpt_i2o_status_get(adpt_hba* pHba)
  2624. {
  2625. ulong timeout;
  2626. u32 m;
  2627. u32 __iomem *msg;
  2628. u8 *status_block=NULL;
  2629. if(pHba->status_block == NULL) {
  2630. pHba->status_block = dma_alloc_coherent(&pHba->pDev->dev,
  2631. sizeof(i2o_status_block),
  2632. &pHba->status_block_pa, GFP_KERNEL);
  2633. if(pHba->status_block == NULL) {
  2634. printk(KERN_ERR
  2635. "dpti%d: Get Status Block failed; Out of memory. \n",
  2636. pHba->unit);
  2637. return -ENOMEM;
  2638. }
  2639. }
  2640. memset(pHba->status_block, 0, sizeof(i2o_status_block));
  2641. status_block = (u8*)(pHba->status_block);
  2642. timeout = jiffies+TMOUT_GETSTATUS*HZ;
  2643. do {
  2644. rmb();
  2645. m = readl(pHba->post_port);
  2646. if (m != EMPTY_QUEUE) {
  2647. break;
  2648. }
  2649. if(time_after(jiffies,timeout)){
  2650. printk(KERN_ERR "%s: Timeout waiting for message !\n",
  2651. pHba->name);
  2652. return -ETIMEDOUT;
  2653. }
  2654. schedule_timeout_uninterruptible(1);
  2655. } while(m==EMPTY_QUEUE);
  2656. msg=(u32 __iomem *)(pHba->msg_addr_virt+m);
  2657. writel(NINE_WORD_MSG_SIZE|SGL_OFFSET_0, &msg[0]);
  2658. writel(I2O_CMD_STATUS_GET<<24|HOST_TID<<12|ADAPTER_TID, &msg[1]);
  2659. writel(1, &msg[2]);
  2660. writel(0, &msg[3]);
  2661. writel(0, &msg[4]);
  2662. writel(0, &msg[5]);
  2663. writel( dma_low(pHba->status_block_pa), &msg[6]);
  2664. writel( dma_high(pHba->status_block_pa), &msg[7]);
  2665. writel(sizeof(i2o_status_block), &msg[8]); // 88 bytes
  2666. //post message
  2667. writel(m, pHba->post_port);
  2668. wmb();
  2669. while(status_block[87]!=0xff){
  2670. if(time_after(jiffies,timeout)){
  2671. printk(KERN_ERR"dpti%d: Get status timeout.\n",
  2672. pHba->unit);
  2673. return -ETIMEDOUT;
  2674. }
  2675. rmb();
  2676. schedule_timeout_uninterruptible(1);
  2677. }
  2678. // Set up our number of outbound and inbound messages
  2679. pHba->post_fifo_size = pHba->status_block->max_inbound_frames;
  2680. if (pHba->post_fifo_size > MAX_TO_IOP_MESSAGES) {
  2681. pHba->post_fifo_size = MAX_TO_IOP_MESSAGES;
  2682. }
  2683. pHba->reply_fifo_size = pHba->status_block->max_outbound_frames;
  2684. if (pHba->reply_fifo_size > MAX_FROM_IOP_MESSAGES) {
  2685. pHba->reply_fifo_size = MAX_FROM_IOP_MESSAGES;
  2686. }
  2687. // Calculate the Scatter Gather list size
  2688. if (dpt_dma64(pHba)) {
  2689. pHba->sg_tablesize
  2690. = ((pHba->status_block->inbound_frame_size * 4
  2691. - 14 * sizeof(u32))
  2692. / (sizeof(struct sg_simple_element) + sizeof(u32)));
  2693. } else {
  2694. pHba->sg_tablesize
  2695. = ((pHba->status_block->inbound_frame_size * 4
  2696. - 12 * sizeof(u32))
  2697. / sizeof(struct sg_simple_element));
  2698. }
  2699. if (pHba->sg_tablesize > SG_LIST_ELEMENTS) {
  2700. pHba->sg_tablesize = SG_LIST_ELEMENTS;
  2701. }
  2702. #ifdef DEBUG
  2703. printk("dpti%d: State = ",pHba->unit);
  2704. switch(pHba->status_block->iop_state) {
  2705. case 0x01:
  2706. printk("INIT\n");
  2707. break;
  2708. case 0x02:
  2709. printk("RESET\n");
  2710. break;
  2711. case 0x04:
  2712. printk("HOLD\n");
  2713. break;
  2714. case 0x05:
  2715. printk("READY\n");
  2716. break;
  2717. case 0x08:
  2718. printk("OPERATIONAL\n");
  2719. break;
  2720. case 0x10:
  2721. printk("FAILED\n");
  2722. break;
  2723. case 0x11:
  2724. printk("FAULTED\n");
  2725. break;
  2726. default:
  2727. printk("%x (unknown!!)\n",pHba->status_block->iop_state);
  2728. }
  2729. #endif
  2730. return 0;
  2731. }
  2732. /*
  2733. * Get the IOP's Logical Configuration Table
  2734. */
  2735. static int adpt_i2o_lct_get(adpt_hba* pHba)
  2736. {
  2737. u32 msg[8];
  2738. int ret;
  2739. u32 buf[16];
  2740. if ((pHba->lct_size == 0) || (pHba->lct == NULL)){
  2741. pHba->lct_size = pHba->status_block->expected_lct_size;
  2742. }
  2743. do {
  2744. if (pHba->lct == NULL) {
  2745. pHba->lct = dma_alloc_coherent(&pHba->pDev->dev,
  2746. pHba->lct_size, &pHba->lct_pa,
  2747. GFP_KERNEL);
  2748. if(pHba->lct == NULL) {
  2749. printk(KERN_CRIT "%s: Lct Get failed. Out of memory.\n",
  2750. pHba->name);
  2751. return -ENOMEM;
  2752. }
  2753. }
  2754. memset(pHba->lct, 0, pHba->lct_size);
  2755. msg[0] = EIGHT_WORD_MSG_SIZE|SGL_OFFSET_6;
  2756. msg[1] = I2O_CMD_LCT_NOTIFY<<24 | HOST_TID<<12 | ADAPTER_TID;
  2757. msg[2] = 0;
  2758. msg[3] = 0;
  2759. msg[4] = 0xFFFFFFFF; /* All devices */
  2760. msg[5] = 0x00000000; /* Report now */
  2761. msg[6] = 0xD0000000|pHba->lct_size;
  2762. msg[7] = (u32)pHba->lct_pa;
  2763. if ((ret=adpt_i2o_post_wait(pHba, msg, sizeof(msg), 360))) {
  2764. printk(KERN_ERR "%s: LCT Get failed (status=%#10x.\n",
  2765. pHba->name, ret);
  2766. printk(KERN_ERR"Adaptec: Error Reading Hardware.\n");
  2767. return ret;
  2768. }
  2769. if ((pHba->lct->table_size << 2) > pHba->lct_size) {
  2770. pHba->lct_size = pHba->lct->table_size << 2;
  2771. dma_free_coherent(&pHba->pDev->dev, pHba->lct_size,
  2772. pHba->lct, pHba->lct_pa);
  2773. pHba->lct = NULL;
  2774. }
  2775. } while (pHba->lct == NULL);
  2776. PDEBUG("%s: Hardware resource table read.\n", pHba->name);
  2777. // I2O_DPT_EXEC_IOP_BUFFERS_GROUP_NO;
  2778. if(adpt_i2o_query_scalar(pHba, 0 , 0x8000, -1, buf, sizeof(buf))>=0) {
  2779. pHba->FwDebugBufferSize = buf[1];
  2780. pHba->FwDebugBuffer_P = ioremap(pHba->base_addr_phys + buf[0],
  2781. pHba->FwDebugBufferSize);
  2782. if (pHba->FwDebugBuffer_P) {
  2783. pHba->FwDebugFlags_P = pHba->FwDebugBuffer_P +
  2784. FW_DEBUG_FLAGS_OFFSET;
  2785. pHba->FwDebugBLEDvalue_P = pHba->FwDebugBuffer_P +
  2786. FW_DEBUG_BLED_OFFSET;
  2787. pHba->FwDebugBLEDflag_P = pHba->FwDebugBLEDvalue_P + 1;
  2788. pHba->FwDebugStrLength_P = pHba->FwDebugBuffer_P +
  2789. FW_DEBUG_STR_LENGTH_OFFSET;
  2790. pHba->FwDebugBuffer_P += buf[2];
  2791. pHba->FwDebugFlags = 0;
  2792. }
  2793. }
  2794. return 0;
  2795. }
  2796. static int adpt_i2o_build_sys_table(void)
  2797. {
  2798. adpt_hba* pHba = hba_chain;
  2799. int count = 0;
  2800. if (sys_tbl)
  2801. dma_free_coherent(&pHba->pDev->dev, sys_tbl_len,
  2802. sys_tbl, sys_tbl_pa);
  2803. sys_tbl_len = sizeof(struct i2o_sys_tbl) + // Header + IOPs
  2804. (hba_count) * sizeof(struct i2o_sys_tbl_entry);
  2805. sys_tbl = dma_alloc_coherent(&pHba->pDev->dev,
  2806. sys_tbl_len, &sys_tbl_pa, GFP_KERNEL);
  2807. if (!sys_tbl) {
  2808. printk(KERN_WARNING "SysTab Set failed. Out of memory.\n");
  2809. return -ENOMEM;
  2810. }
  2811. memset(sys_tbl, 0, sys_tbl_len);
  2812. sys_tbl->num_entries = hba_count;
  2813. sys_tbl->version = I2OVERSION;
  2814. sys_tbl->change_ind = sys_tbl_ind++;
  2815. for(pHba = hba_chain; pHba; pHba = pHba->next) {
  2816. u64 addr;
  2817. // Get updated Status Block so we have the latest information
  2818. if (adpt_i2o_status_get(pHba)) {
  2819. sys_tbl->num_entries--;
  2820. continue; // try next one
  2821. }
  2822. sys_tbl->iops[count].org_id = pHba->status_block->org_id;
  2823. sys_tbl->iops[count].iop_id = pHba->unit + 2;
  2824. sys_tbl->iops[count].seg_num = 0;
  2825. sys_tbl->iops[count].i2o_version = pHba->status_block->i2o_version;
  2826. sys_tbl->iops[count].iop_state = pHba->status_block->iop_state;
  2827. sys_tbl->iops[count].msg_type = pHba->status_block->msg_type;
  2828. sys_tbl->iops[count].frame_size = pHba->status_block->inbound_frame_size;
  2829. sys_tbl->iops[count].last_changed = sys_tbl_ind - 1; // ??
  2830. sys_tbl->iops[count].iop_capabilities = pHba->status_block->iop_capabilities;
  2831. addr = pHba->base_addr_phys + 0x40;
  2832. sys_tbl->iops[count].inbound_low = dma_low(addr);
  2833. sys_tbl->iops[count].inbound_high = dma_high(addr);
  2834. count++;
  2835. }
  2836. #ifdef DEBUG
  2837. {
  2838. u32 *table = (u32*)sys_tbl;
  2839. printk(KERN_DEBUG"sys_tbl_len=%d in 32bit words\n",(sys_tbl_len >>2));
  2840. for(count = 0; count < (sys_tbl_len >>2); count++) {
  2841. printk(KERN_INFO "sys_tbl[%d] = %0#10x\n",
  2842. count, table[count]);
  2843. }
  2844. }
  2845. #endif
  2846. return 0;
  2847. }
  2848. /*
  2849. * Dump the information block associated with a given unit (TID)
  2850. */
  2851. static void adpt_i2o_report_hba_unit(adpt_hba* pHba, struct i2o_device *d)
  2852. {
  2853. char buf[64];
  2854. int unit = d->lct_data.tid;
  2855. printk(KERN_INFO "TID %3.3d ", unit);
  2856. if(adpt_i2o_query_scalar(pHba, unit, 0xF100, 3, buf, 16)>=0)
  2857. {
  2858. buf[16]=0;
  2859. printk(" Vendor: %-12.12s", buf);
  2860. }
  2861. if(adpt_i2o_query_scalar(pHba, unit, 0xF100, 4, buf, 16)>=0)
  2862. {
  2863. buf[16]=0;
  2864. printk(" Device: %-12.12s", buf);
  2865. }
  2866. if(adpt_i2o_query_scalar(pHba, unit, 0xF100, 6, buf, 8)>=0)
  2867. {
  2868. buf[8]=0;
  2869. printk(" Rev: %-12.12s\n", buf);
  2870. }
  2871. #ifdef DEBUG
  2872. printk(KERN_INFO "\tClass: %.21s\n", adpt_i2o_get_class_name(d->lct_data.class_id));
  2873. printk(KERN_INFO "\tSubclass: 0x%04X\n", d->lct_data.sub_class);
  2874. printk(KERN_INFO "\tFlags: ");
  2875. if(d->lct_data.device_flags&(1<<0))
  2876. printk("C"); // ConfigDialog requested
  2877. if(d->lct_data.device_flags&(1<<1))
  2878. printk("U"); // Multi-user capable
  2879. if(!(d->lct_data.device_flags&(1<<4)))
  2880. printk("P"); // Peer service enabled!
  2881. if(!(d->lct_data.device_flags&(1<<5)))
  2882. printk("M"); // Mgmt service enabled!
  2883. printk("\n");
  2884. #endif
  2885. }
  2886. #ifdef DEBUG
  2887. /*
  2888. * Do i2o class name lookup
  2889. */
  2890. static const char *adpt_i2o_get_class_name(int class)
  2891. {
  2892. int idx = 16;
  2893. static char *i2o_class_name[] = {
  2894. "Executive",
  2895. "Device Driver Module",
  2896. "Block Device",
  2897. "Tape Device",
  2898. "LAN Interface",
  2899. "WAN Interface",
  2900. "Fibre Channel Port",
  2901. "Fibre Channel Device",
  2902. "SCSI Device",
  2903. "ATE Port",
  2904. "ATE Device",
  2905. "Floppy Controller",
  2906. "Floppy Device",
  2907. "Secondary Bus Port",
  2908. "Peer Transport Agent",
  2909. "Peer Transport",
  2910. "Unknown"
  2911. };
  2912. switch(class&0xFFF) {
  2913. case I2O_CLASS_EXECUTIVE:
  2914. idx = 0; break;
  2915. case I2O_CLASS_DDM:
  2916. idx = 1; break;
  2917. case I2O_CLASS_RANDOM_BLOCK_STORAGE:
  2918. idx = 2; break;
  2919. case I2O_CLASS_SEQUENTIAL_STORAGE:
  2920. idx = 3; break;
  2921. case I2O_CLASS_LAN:
  2922. idx = 4; break;
  2923. case I2O_CLASS_WAN:
  2924. idx = 5; break;
  2925. case I2O_CLASS_FIBRE_CHANNEL_PORT:
  2926. idx = 6; break;
  2927. case I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL:
  2928. idx = 7; break;
  2929. case I2O_CLASS_SCSI_PERIPHERAL:
  2930. idx = 8; break;
  2931. case I2O_CLASS_ATE_PORT:
  2932. idx = 9; break;
  2933. case I2O_CLASS_ATE_PERIPHERAL:
  2934. idx = 10; break;
  2935. case I2O_CLASS_FLOPPY_CONTROLLER:
  2936. idx = 11; break;
  2937. case I2O_CLASS_FLOPPY_DEVICE:
  2938. idx = 12; break;
  2939. case I2O_CLASS_BUS_ADAPTER_PORT:
  2940. idx = 13; break;
  2941. case I2O_CLASS_PEER_TRANSPORT_AGENT:
  2942. idx = 14; break;
  2943. case I2O_CLASS_PEER_TRANSPORT:
  2944. idx = 15; break;
  2945. }
  2946. return i2o_class_name[idx];
  2947. }
  2948. #endif
  2949. static s32 adpt_i2o_hrt_get(adpt_hba* pHba)
  2950. {
  2951. u32 msg[6];
  2952. int ret, size = sizeof(i2o_hrt);
  2953. do {
  2954. if (pHba->hrt == NULL) {
  2955. pHba->hrt = dma_alloc_coherent(&pHba->pDev->dev,
  2956. size, &pHba->hrt_pa, GFP_KERNEL);
  2957. if (pHba->hrt == NULL) {
  2958. printk(KERN_CRIT "%s: Hrt Get failed; Out of memory.\n", pHba->name);
  2959. return -ENOMEM;
  2960. }
  2961. }
  2962. msg[0]= SIX_WORD_MSG_SIZE| SGL_OFFSET_4;
  2963. msg[1]= I2O_CMD_HRT_GET<<24 | HOST_TID<<12 | ADAPTER_TID;
  2964. msg[2]= 0;
  2965. msg[3]= 0;
  2966. msg[4]= (0xD0000000 | size); /* Simple transaction */
  2967. msg[5]= (u32)pHba->hrt_pa; /* Dump it here */
  2968. if ((ret = adpt_i2o_post_wait(pHba, msg, sizeof(msg),20))) {
  2969. printk(KERN_ERR "%s: Unable to get HRT (status=%#10x)\n", pHba->name, ret);
  2970. return ret;
  2971. }
  2972. if (pHba->hrt->num_entries * pHba->hrt->entry_len << 2 > size) {
  2973. int newsize = pHba->hrt->num_entries * pHba->hrt->entry_len << 2;
  2974. dma_free_coherent(&pHba->pDev->dev, size,
  2975. pHba->hrt, pHba->hrt_pa);
  2976. size = newsize;
  2977. pHba->hrt = NULL;
  2978. }
  2979. } while(pHba->hrt == NULL);
  2980. return 0;
  2981. }
  2982. /*
  2983. * Query one scalar group value or a whole scalar group.
  2984. */
  2985. static int adpt_i2o_query_scalar(adpt_hba* pHba, int tid,
  2986. int group, int field, void *buf, int buflen)
  2987. {
  2988. u16 opblk[] = { 1, 0, I2O_PARAMS_FIELD_GET, group, 1, field };
  2989. u8 *opblk_va;
  2990. dma_addr_t opblk_pa;
  2991. u8 *resblk_va;
  2992. dma_addr_t resblk_pa;
  2993. int size;
  2994. /* 8 bytes for header */
  2995. resblk_va = dma_alloc_coherent(&pHba->pDev->dev,
  2996. sizeof(u8) * (8 + buflen), &resblk_pa, GFP_KERNEL);
  2997. if (resblk_va == NULL) {
  2998. printk(KERN_CRIT "%s: query scalar failed; Out of memory.\n", pHba->name);
  2999. return -ENOMEM;
  3000. }
  3001. opblk_va = dma_alloc_coherent(&pHba->pDev->dev,
  3002. sizeof(opblk), &opblk_pa, GFP_KERNEL);
  3003. if (opblk_va == NULL) {
  3004. dma_free_coherent(&pHba->pDev->dev, sizeof(u8) * (8+buflen),
  3005. resblk_va, resblk_pa);
  3006. printk(KERN_CRIT "%s: query operatio failed; Out of memory.\n",
  3007. pHba->name);
  3008. return -ENOMEM;
  3009. }
  3010. if (field == -1) /* whole group */
  3011. opblk[4] = -1;
  3012. memcpy(opblk_va, opblk, sizeof(opblk));
  3013. size = adpt_i2o_issue_params(I2O_CMD_UTIL_PARAMS_GET, pHba, tid,
  3014. opblk_va, opblk_pa, sizeof(opblk),
  3015. resblk_va, resblk_pa, sizeof(u8)*(8+buflen));
  3016. dma_free_coherent(&pHba->pDev->dev, sizeof(opblk), opblk_va, opblk_pa);
  3017. if (size == -ETIME) {
  3018. dma_free_coherent(&pHba->pDev->dev, sizeof(u8) * (8+buflen),
  3019. resblk_va, resblk_pa);
  3020. printk(KERN_WARNING "%s: issue params failed; Timed out.\n", pHba->name);
  3021. return -ETIME;
  3022. } else if (size == -EINTR) {
  3023. dma_free_coherent(&pHba->pDev->dev, sizeof(u8) * (8+buflen),
  3024. resblk_va, resblk_pa);
  3025. printk(KERN_WARNING "%s: issue params failed; Interrupted.\n", pHba->name);
  3026. return -EINTR;
  3027. }
  3028. memcpy(buf, resblk_va+8, buflen); /* cut off header */
  3029. dma_free_coherent(&pHba->pDev->dev, sizeof(u8) * (8+buflen),
  3030. resblk_va, resblk_pa);
  3031. if (size < 0)
  3032. return size;
  3033. return buflen;
  3034. }
  3035. /* Issue UTIL_PARAMS_GET or UTIL_PARAMS_SET
  3036. *
  3037. * This function can be used for all UtilParamsGet/Set operations.
  3038. * The OperationBlock is given in opblk-buffer,
  3039. * and results are returned in resblk-buffer.
  3040. * Note that the minimum sized resblk is 8 bytes and contains
  3041. * ResultCount, ErrorInfoSize, BlockStatus and BlockSize.
  3042. */
  3043. static int adpt_i2o_issue_params(int cmd, adpt_hba* pHba, int tid,
  3044. void *opblk_va, dma_addr_t opblk_pa, int oplen,
  3045. void *resblk_va, dma_addr_t resblk_pa, int reslen)
  3046. {
  3047. u32 msg[9];
  3048. u32 *res = (u32 *)resblk_va;
  3049. int wait_status;
  3050. msg[0] = NINE_WORD_MSG_SIZE | SGL_OFFSET_5;
  3051. msg[1] = cmd << 24 | HOST_TID << 12 | tid;
  3052. msg[2] = 0;
  3053. msg[3] = 0;
  3054. msg[4] = 0;
  3055. msg[5] = 0x54000000 | oplen; /* OperationBlock */
  3056. msg[6] = (u32)opblk_pa;
  3057. msg[7] = 0xD0000000 | reslen; /* ResultBlock */
  3058. msg[8] = (u32)resblk_pa;
  3059. if ((wait_status = adpt_i2o_post_wait(pHba, msg, sizeof(msg), 20))) {
  3060. printk("adpt_i2o_issue_params: post_wait failed (%p)\n", resblk_va);
  3061. return wait_status; /* -DetailedStatus */
  3062. }
  3063. if (res[1]&0x00FF0000) { /* BlockStatus != SUCCESS */
  3064. printk(KERN_WARNING "%s: %s - Error:\n ErrorInfoSize = 0x%02x, "
  3065. "BlockStatus = 0x%02x, BlockSize = 0x%04x\n",
  3066. pHba->name,
  3067. (cmd == I2O_CMD_UTIL_PARAMS_SET) ? "PARAMS_SET"
  3068. : "PARAMS_GET",
  3069. res[1]>>24, (res[1]>>16)&0xFF, res[1]&0xFFFF);
  3070. return -((res[1] >> 16) & 0xFF); /* -BlockStatus */
  3071. }
  3072. return 4 + ((res[1] & 0x0000FFFF) << 2); /* bytes used in resblk */
  3073. }
  3074. static s32 adpt_i2o_quiesce_hba(adpt_hba* pHba)
  3075. {
  3076. u32 msg[4];
  3077. int ret;
  3078. adpt_i2o_status_get(pHba);
  3079. /* SysQuiesce discarded if IOP not in READY or OPERATIONAL state */
  3080. if((pHba->status_block->iop_state != ADAPTER_STATE_READY) &&
  3081. (pHba->status_block->iop_state != ADAPTER_STATE_OPERATIONAL)){
  3082. return 0;
  3083. }
  3084. msg[0] = FOUR_WORD_MSG_SIZE|SGL_OFFSET_0;
  3085. msg[1] = I2O_CMD_SYS_QUIESCE<<24|HOST_TID<<12|ADAPTER_TID;
  3086. msg[2] = 0;
  3087. msg[3] = 0;
  3088. if((ret = adpt_i2o_post_wait(pHba, msg, sizeof(msg), 240))) {
  3089. printk(KERN_INFO"dpti%d: Unable to quiesce (status=%#x).\n",
  3090. pHba->unit, -ret);
  3091. } else {
  3092. printk(KERN_INFO"dpti%d: Quiesced.\n",pHba->unit);
  3093. }
  3094. adpt_i2o_status_get(pHba);
  3095. return ret;
  3096. }
  3097. /*
  3098. * Enable IOP. Allows the IOP to resume external operations.
  3099. */
  3100. static int adpt_i2o_enable_hba(adpt_hba* pHba)
  3101. {
  3102. u32 msg[4];
  3103. int ret;
  3104. adpt_i2o_status_get(pHba);
  3105. if(!pHba->status_block){
  3106. return -ENOMEM;
  3107. }
  3108. /* Enable only allowed on READY state */
  3109. if(pHba->status_block->iop_state == ADAPTER_STATE_OPERATIONAL)
  3110. return 0;
  3111. if(pHba->status_block->iop_state != ADAPTER_STATE_READY)
  3112. return -EINVAL;
  3113. msg[0]=FOUR_WORD_MSG_SIZE|SGL_OFFSET_0;
  3114. msg[1]=I2O_CMD_SYS_ENABLE<<24|HOST_TID<<12|ADAPTER_TID;
  3115. msg[2]= 0;
  3116. msg[3]= 0;
  3117. if ((ret = adpt_i2o_post_wait(pHba, msg, sizeof(msg), 240))) {
  3118. printk(KERN_WARNING"%s: Could not enable (status=%#10x).\n",
  3119. pHba->name, ret);
  3120. } else {
  3121. PDEBUG("%s: Enabled.\n", pHba->name);
  3122. }
  3123. adpt_i2o_status_get(pHba);
  3124. return ret;
  3125. }
  3126. static int adpt_i2o_systab_send(adpt_hba* pHba)
  3127. {
  3128. u32 msg[12];
  3129. int ret;
  3130. msg[0] = I2O_MESSAGE_SIZE(12) | SGL_OFFSET_6;
  3131. msg[1] = I2O_CMD_SYS_TAB_SET<<24 | HOST_TID<<12 | ADAPTER_TID;
  3132. msg[2] = 0;
  3133. msg[3] = 0;
  3134. msg[4] = (0<<16) | ((pHba->unit+2) << 12); /* Host 0 IOP ID (unit + 2) */
  3135. msg[5] = 0; /* Segment 0 */
  3136. /*
  3137. * Provide three SGL-elements:
  3138. * System table (SysTab), Private memory space declaration and
  3139. * Private i/o space declaration
  3140. */
  3141. msg[6] = 0x54000000 | sys_tbl_len;
  3142. msg[7] = (u32)sys_tbl_pa;
  3143. msg[8] = 0x54000000 | 0;
  3144. msg[9] = 0;
  3145. msg[10] = 0xD4000000 | 0;
  3146. msg[11] = 0;
  3147. if ((ret=adpt_i2o_post_wait(pHba, msg, sizeof(msg), 120))) {
  3148. printk(KERN_INFO "%s: Unable to set SysTab (status=%#10x).\n",
  3149. pHba->name, ret);
  3150. }
  3151. #ifdef DEBUG
  3152. else {
  3153. PINFO("%s: SysTab set.\n", pHba->name);
  3154. }
  3155. #endif
  3156. return ret;
  3157. }
  3158. /*============================================================================
  3159. *
  3160. *============================================================================
  3161. */
  3162. #ifdef UARTDELAY
  3163. static static void adpt_delay(int millisec)
  3164. {
  3165. int i;
  3166. for (i = 0; i < millisec; i++) {
  3167. udelay(1000); /* delay for one millisecond */
  3168. }
  3169. }
  3170. #endif
  3171. static struct scsi_host_template driver_template = {
  3172. .module = THIS_MODULE,
  3173. .name = "dpt_i2o",
  3174. .proc_name = "dpt_i2o",
  3175. .proc_info = adpt_proc_info,
  3176. .info = adpt_info,
  3177. .queuecommand = adpt_queue,
  3178. .eh_abort_handler = adpt_abort,
  3179. .eh_device_reset_handler = adpt_device_reset,
  3180. .eh_bus_reset_handler = adpt_bus_reset,
  3181. .eh_host_reset_handler = adpt_reset,
  3182. .bios_param = adpt_bios_param,
  3183. .slave_configure = adpt_slave_configure,
  3184. .can_queue = MAX_TO_IOP_MESSAGES,
  3185. .this_id = 7,
  3186. .cmd_per_lun = 1,
  3187. .use_clustering = ENABLE_CLUSTERING,
  3188. };
  3189. static int __init adpt_init(void)
  3190. {
  3191. int error;
  3192. adpt_hba *pHba, *next;
  3193. printk("Loading Adaptec I2O RAID: Version " DPT_I2O_VERSION "\n");
  3194. error = adpt_detect(&driver_template);
  3195. if (error < 0)
  3196. return error;
  3197. if (hba_chain == NULL)
  3198. return -ENODEV;
  3199. for (pHba = hba_chain; pHba; pHba = pHba->next) {
  3200. error = scsi_add_host(pHba->host, &pHba->pDev->dev);
  3201. if (error)
  3202. goto fail;
  3203. scsi_scan_host(pHba->host);
  3204. }
  3205. return 0;
  3206. fail:
  3207. for (pHba = hba_chain; pHba; pHba = next) {
  3208. next = pHba->next;
  3209. scsi_remove_host(pHba->host);
  3210. }
  3211. return error;
  3212. }
  3213. static void __exit adpt_exit(void)
  3214. {
  3215. adpt_hba *pHba, *next;
  3216. for (pHba = hba_chain; pHba; pHba = pHba->next)
  3217. scsi_remove_host(pHba->host);
  3218. for (pHba = hba_chain; pHba; pHba = next) {
  3219. next = pHba->next;
  3220. adpt_release(pHba->host);
  3221. }
  3222. }
  3223. module_init(adpt_init);
  3224. module_exit(adpt_exit);
  3225. MODULE_LICENSE("GPL");