rtc-vr41xx.c 10 KB

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  1. /*
  2. * Driver for NEC VR4100 series Real Time Clock unit.
  3. *
  4. * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/err.h>
  21. #include <linux/fs.h>
  22. #include <linux/init.h>
  23. #include <linux/ioport.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/module.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/rtc.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/types.h>
  30. #include <linux/log2.h>
  31. #include <asm/div64.h>
  32. #include <asm/io.h>
  33. #include <asm/uaccess.h>
  34. MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
  35. MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
  36. MODULE_LICENSE("GPL v2");
  37. /* RTC 1 registers */
  38. #define ETIMELREG 0x00
  39. #define ETIMEMREG 0x02
  40. #define ETIMEHREG 0x04
  41. /* RFU */
  42. #define ECMPLREG 0x08
  43. #define ECMPMREG 0x0a
  44. #define ECMPHREG 0x0c
  45. /* RFU */
  46. #define RTCL1LREG 0x10
  47. #define RTCL1HREG 0x12
  48. #define RTCL1CNTLREG 0x14
  49. #define RTCL1CNTHREG 0x16
  50. #define RTCL2LREG 0x18
  51. #define RTCL2HREG 0x1a
  52. #define RTCL2CNTLREG 0x1c
  53. #define RTCL2CNTHREG 0x1e
  54. /* RTC 2 registers */
  55. #define TCLKLREG 0x00
  56. #define TCLKHREG 0x02
  57. #define TCLKCNTLREG 0x04
  58. #define TCLKCNTHREG 0x06
  59. /* RFU */
  60. #define RTCINTREG 0x1e
  61. #define TCLOCK_INT 0x08
  62. #define RTCLONG2_INT 0x04
  63. #define RTCLONG1_INT 0x02
  64. #define ELAPSEDTIME_INT 0x01
  65. #define RTC_FREQUENCY 32768
  66. #define MAX_PERIODIC_RATE 6553
  67. static void __iomem *rtc1_base;
  68. static void __iomem *rtc2_base;
  69. #define rtc1_read(offset) readw(rtc1_base + (offset))
  70. #define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
  71. #define rtc2_read(offset) readw(rtc2_base + (offset))
  72. #define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
  73. static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
  74. static DEFINE_SPINLOCK(rtc_lock);
  75. static char rtc_name[] = "RTC";
  76. static unsigned long periodic_count;
  77. static unsigned int alarm_enabled;
  78. static int aie_irq;
  79. static int pie_irq;
  80. static inline unsigned long read_elapsed_second(void)
  81. {
  82. unsigned long first_low, first_mid, first_high;
  83. unsigned long second_low, second_mid, second_high;
  84. do {
  85. first_low = rtc1_read(ETIMELREG);
  86. first_mid = rtc1_read(ETIMEMREG);
  87. first_high = rtc1_read(ETIMEHREG);
  88. second_low = rtc1_read(ETIMELREG);
  89. second_mid = rtc1_read(ETIMEMREG);
  90. second_high = rtc1_read(ETIMEHREG);
  91. } while (first_low != second_low || first_mid != second_mid ||
  92. first_high != second_high);
  93. return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
  94. }
  95. static inline void write_elapsed_second(unsigned long sec)
  96. {
  97. spin_lock_irq(&rtc_lock);
  98. rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
  99. rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
  100. rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
  101. spin_unlock_irq(&rtc_lock);
  102. }
  103. static void vr41xx_rtc_release(struct device *dev)
  104. {
  105. spin_lock_irq(&rtc_lock);
  106. rtc1_write(ECMPLREG, 0);
  107. rtc1_write(ECMPMREG, 0);
  108. rtc1_write(ECMPHREG, 0);
  109. rtc1_write(RTCL1LREG, 0);
  110. rtc1_write(RTCL1HREG, 0);
  111. spin_unlock_irq(&rtc_lock);
  112. disable_irq(aie_irq);
  113. disable_irq(pie_irq);
  114. }
  115. static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
  116. {
  117. unsigned long epoch_sec, elapsed_sec;
  118. epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
  119. elapsed_sec = read_elapsed_second();
  120. rtc_time_to_tm(epoch_sec + elapsed_sec, time);
  121. return 0;
  122. }
  123. static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
  124. {
  125. unsigned long epoch_sec, current_sec;
  126. epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
  127. current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
  128. time->tm_hour, time->tm_min, time->tm_sec);
  129. write_elapsed_second(current_sec - epoch_sec);
  130. return 0;
  131. }
  132. static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  133. {
  134. unsigned long low, mid, high;
  135. struct rtc_time *time = &wkalrm->time;
  136. spin_lock_irq(&rtc_lock);
  137. low = rtc1_read(ECMPLREG);
  138. mid = rtc1_read(ECMPMREG);
  139. high = rtc1_read(ECMPHREG);
  140. wkalrm->enabled = alarm_enabled;
  141. spin_unlock_irq(&rtc_lock);
  142. rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
  143. return 0;
  144. }
  145. static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  146. {
  147. unsigned long alarm_sec;
  148. struct rtc_time *time = &wkalrm->time;
  149. alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
  150. time->tm_hour, time->tm_min, time->tm_sec);
  151. spin_lock_irq(&rtc_lock);
  152. if (alarm_enabled)
  153. disable_irq(aie_irq);
  154. rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
  155. rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
  156. rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
  157. if (wkalrm->enabled)
  158. enable_irq(aie_irq);
  159. alarm_enabled = wkalrm->enabled;
  160. spin_unlock_irq(&rtc_lock);
  161. return 0;
  162. }
  163. static int vr41xx_rtc_irq_set_freq(struct device *dev, int freq)
  164. {
  165. unsigned long count;
  166. if (!is_power_of_2(freq))
  167. return -EINVAL;
  168. count = RTC_FREQUENCY;
  169. do_div(count, freq);
  170. periodic_count = count;
  171. spin_lock_irq(&rtc_lock);
  172. rtc1_write(RTCL1LREG, count);
  173. rtc1_write(RTCL1HREG, count >> 16);
  174. spin_unlock_irq(&rtc_lock);
  175. return 0;
  176. }
  177. static int vr41xx_rtc_irq_set_state(struct device *dev, int enabled)
  178. {
  179. if (enabled)
  180. enable_irq(pie_irq);
  181. else
  182. disable_irq(pie_irq);
  183. return 0;
  184. }
  185. static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
  186. {
  187. switch (cmd) {
  188. case RTC_AIE_ON:
  189. spin_lock_irq(&rtc_lock);
  190. if (!alarm_enabled) {
  191. enable_irq(aie_irq);
  192. alarm_enabled = 1;
  193. }
  194. spin_unlock_irq(&rtc_lock);
  195. break;
  196. case RTC_AIE_OFF:
  197. spin_lock_irq(&rtc_lock);
  198. if (alarm_enabled) {
  199. disable_irq(aie_irq);
  200. alarm_enabled = 0;
  201. }
  202. spin_unlock_irq(&rtc_lock);
  203. break;
  204. case RTC_EPOCH_READ:
  205. return put_user(epoch, (unsigned long __user *)arg);
  206. case RTC_EPOCH_SET:
  207. /* Doesn't support before 1900 */
  208. if (arg < 1900)
  209. return -EINVAL;
  210. epoch = arg;
  211. break;
  212. default:
  213. return -ENOIOCTLCMD;
  214. }
  215. return 0;
  216. }
  217. static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
  218. {
  219. struct platform_device *pdev = (struct platform_device *)dev_id;
  220. struct rtc_device *rtc = platform_get_drvdata(pdev);
  221. rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
  222. rtc_update_irq(rtc, 1, RTC_AF);
  223. return IRQ_HANDLED;
  224. }
  225. static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
  226. {
  227. struct platform_device *pdev = (struct platform_device *)dev_id;
  228. struct rtc_device *rtc = platform_get_drvdata(pdev);
  229. unsigned long count = periodic_count;
  230. rtc2_write(RTCINTREG, RTCLONG1_INT);
  231. rtc1_write(RTCL1LREG, count);
  232. rtc1_write(RTCL1HREG, count >> 16);
  233. rtc_update_irq(rtc, 1, RTC_PF);
  234. return IRQ_HANDLED;
  235. }
  236. static const struct rtc_class_ops vr41xx_rtc_ops = {
  237. .release = vr41xx_rtc_release,
  238. .ioctl = vr41xx_rtc_ioctl,
  239. .read_time = vr41xx_rtc_read_time,
  240. .set_time = vr41xx_rtc_set_time,
  241. .read_alarm = vr41xx_rtc_read_alarm,
  242. .set_alarm = vr41xx_rtc_set_alarm,
  243. .irq_set_freq = vr41xx_rtc_irq_set_freq,
  244. .irq_set_state = vr41xx_rtc_irq_set_state,
  245. };
  246. static int __devinit rtc_probe(struct platform_device *pdev)
  247. {
  248. struct resource *res;
  249. struct rtc_device *rtc;
  250. int retval;
  251. if (pdev->num_resources != 4)
  252. return -EBUSY;
  253. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  254. if (!res)
  255. return -EBUSY;
  256. rtc1_base = ioremap(res->start, res->end - res->start + 1);
  257. if (!rtc1_base)
  258. return -EBUSY;
  259. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  260. if (!res) {
  261. retval = -EBUSY;
  262. goto err_rtc1_iounmap;
  263. }
  264. rtc2_base = ioremap(res->start, res->end - res->start + 1);
  265. if (!rtc2_base) {
  266. retval = -EBUSY;
  267. goto err_rtc1_iounmap;
  268. }
  269. rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
  270. if (IS_ERR(rtc)) {
  271. retval = PTR_ERR(rtc);
  272. goto err_iounmap_all;
  273. }
  274. rtc->max_user_freq = MAX_PERIODIC_RATE;
  275. spin_lock_irq(&rtc_lock);
  276. rtc1_write(ECMPLREG, 0);
  277. rtc1_write(ECMPMREG, 0);
  278. rtc1_write(ECMPHREG, 0);
  279. rtc1_write(RTCL1LREG, 0);
  280. rtc1_write(RTCL1HREG, 0);
  281. spin_unlock_irq(&rtc_lock);
  282. aie_irq = platform_get_irq(pdev, 0);
  283. if (aie_irq <= 0) {
  284. retval = -EBUSY;
  285. goto err_device_unregister;
  286. }
  287. retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED,
  288. "elapsed_time", pdev);
  289. if (retval < 0)
  290. goto err_device_unregister;
  291. pie_irq = platform_get_irq(pdev, 1);
  292. if (pie_irq <= 0)
  293. goto err_free_irq;
  294. retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED,
  295. "rtclong1", pdev);
  296. if (retval < 0)
  297. goto err_free_irq;
  298. platform_set_drvdata(pdev, rtc);
  299. disable_irq(aie_irq);
  300. disable_irq(pie_irq);
  301. printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");
  302. return 0;
  303. err_free_irq:
  304. free_irq(aie_irq, pdev);
  305. err_device_unregister:
  306. rtc_device_unregister(rtc);
  307. err_iounmap_all:
  308. iounmap(rtc2_base);
  309. rtc2_base = NULL;
  310. err_rtc1_iounmap:
  311. iounmap(rtc1_base);
  312. rtc1_base = NULL;
  313. return retval;
  314. }
  315. static int __devexit rtc_remove(struct platform_device *pdev)
  316. {
  317. struct rtc_device *rtc;
  318. rtc = platform_get_drvdata(pdev);
  319. if (rtc)
  320. rtc_device_unregister(rtc);
  321. platform_set_drvdata(pdev, NULL);
  322. free_irq(aie_irq, pdev);
  323. free_irq(pie_irq, pdev);
  324. if (rtc1_base)
  325. iounmap(rtc1_base);
  326. if (rtc2_base)
  327. iounmap(rtc2_base);
  328. return 0;
  329. }
  330. /* work with hotplug and coldplug */
  331. MODULE_ALIAS("platform:RTC");
  332. static struct platform_driver rtc_platform_driver = {
  333. .probe = rtc_probe,
  334. .remove = __devexit_p(rtc_remove),
  335. .driver = {
  336. .name = rtc_name,
  337. .owner = THIS_MODULE,
  338. },
  339. };
  340. static int __init vr41xx_rtc_init(void)
  341. {
  342. return platform_driver_register(&rtc_platform_driver);
  343. }
  344. static void __exit vr41xx_rtc_exit(void)
  345. {
  346. platform_driver_unregister(&rtc_platform_driver);
  347. }
  348. module_init(vr41xx_rtc_init);
  349. module_exit(vr41xx_rtc_exit);