rtc-sh.c 21 KB

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  1. /*
  2. * SuperH On-Chip RTC Support
  3. *
  4. * Copyright (C) 2006 - 2009 Paul Mundt
  5. * Copyright (C) 2006 Jamie Lenehan
  6. * Copyright (C) 2008 Angelo Castello
  7. *
  8. * Based on the old arch/sh/kernel/cpu/rtc.c by:
  9. *
  10. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  11. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  12. *
  13. * This file is subject to the terms and conditions of the GNU General Public
  14. * License. See the file "COPYING" in the main directory of this archive
  15. * for more details.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/kernel.h>
  19. #include <linux/bcd.h>
  20. #include <linux/rtc.h>
  21. #include <linux/init.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/seq_file.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/io.h>
  27. #include <linux/log2.h>
  28. #include <linux/clk.h>
  29. #include <asm/rtc.h>
  30. #define DRV_NAME "sh-rtc"
  31. #define DRV_VERSION "0.2.2"
  32. #define RTC_REG(r) ((r) * rtc_reg_size)
  33. #define R64CNT RTC_REG(0)
  34. #define RSECCNT RTC_REG(1) /* RTC sec */
  35. #define RMINCNT RTC_REG(2) /* RTC min */
  36. #define RHRCNT RTC_REG(3) /* RTC hour */
  37. #define RWKCNT RTC_REG(4) /* RTC week */
  38. #define RDAYCNT RTC_REG(5) /* RTC day */
  39. #define RMONCNT RTC_REG(6) /* RTC month */
  40. #define RYRCNT RTC_REG(7) /* RTC year */
  41. #define RSECAR RTC_REG(8) /* ALARM sec */
  42. #define RMINAR RTC_REG(9) /* ALARM min */
  43. #define RHRAR RTC_REG(10) /* ALARM hour */
  44. #define RWKAR RTC_REG(11) /* ALARM week */
  45. #define RDAYAR RTC_REG(12) /* ALARM day */
  46. #define RMONAR RTC_REG(13) /* ALARM month */
  47. #define RCR1 RTC_REG(14) /* Control */
  48. #define RCR2 RTC_REG(15) /* Control */
  49. /*
  50. * Note on RYRAR and RCR3: Up until this point most of the register
  51. * definitions are consistent across all of the available parts. However,
  52. * the placement of the optional RYRAR and RCR3 (the RYRAR control
  53. * register used to control RYRCNT/RYRAR compare) varies considerably
  54. * across various parts, occasionally being mapped in to a completely
  55. * unrelated address space. For proper RYRAR support a separate resource
  56. * would have to be handed off, but as this is purely optional in
  57. * practice, we simply opt not to support it, thereby keeping the code
  58. * quite a bit more simplified.
  59. */
  60. /* ALARM Bits - or with BCD encoded value */
  61. #define AR_ENB 0x80 /* Enable for alarm cmp */
  62. /* Period Bits */
  63. #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
  64. #define PF_COUNT 0x200 /* Half periodic counter */
  65. #define PF_OXS 0x400 /* Periodic One x Second */
  66. #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
  67. #define PF_MASK 0xf00
  68. /* RCR1 Bits */
  69. #define RCR1_CF 0x80 /* Carry Flag */
  70. #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
  71. #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
  72. #define RCR1_AF 0x01 /* Alarm Flag */
  73. /* RCR2 Bits */
  74. #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
  75. #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
  76. #define RCR2_RTCEN 0x08 /* ENable RTC */
  77. #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
  78. #define RCR2_RESET 0x02 /* Reset bit */
  79. #define RCR2_START 0x01 /* Start bit */
  80. struct sh_rtc {
  81. void __iomem *regbase;
  82. unsigned long regsize;
  83. struct resource *res;
  84. int alarm_irq;
  85. int periodic_irq;
  86. int carry_irq;
  87. struct clk *clk;
  88. struct rtc_device *rtc_dev;
  89. spinlock_t lock;
  90. unsigned long capabilities; /* See asm/rtc.h for cap bits */
  91. unsigned short periodic_freq;
  92. };
  93. static int __sh_rtc_interrupt(struct sh_rtc *rtc)
  94. {
  95. unsigned int tmp, pending;
  96. tmp = readb(rtc->regbase + RCR1);
  97. pending = tmp & RCR1_CF;
  98. tmp &= ~RCR1_CF;
  99. writeb(tmp, rtc->regbase + RCR1);
  100. /* Users have requested One x Second IRQ */
  101. if (pending && rtc->periodic_freq & PF_OXS)
  102. rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
  103. return pending;
  104. }
  105. static int __sh_rtc_alarm(struct sh_rtc *rtc)
  106. {
  107. unsigned int tmp, pending;
  108. tmp = readb(rtc->regbase + RCR1);
  109. pending = tmp & RCR1_AF;
  110. tmp &= ~(RCR1_AF | RCR1_AIE);
  111. writeb(tmp, rtc->regbase + RCR1);
  112. if (pending)
  113. rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
  114. return pending;
  115. }
  116. static int __sh_rtc_periodic(struct sh_rtc *rtc)
  117. {
  118. struct rtc_device *rtc_dev = rtc->rtc_dev;
  119. struct rtc_task *irq_task;
  120. unsigned int tmp, pending;
  121. tmp = readb(rtc->regbase + RCR2);
  122. pending = tmp & RCR2_PEF;
  123. tmp &= ~RCR2_PEF;
  124. writeb(tmp, rtc->regbase + RCR2);
  125. if (!pending)
  126. return 0;
  127. /* Half period enabled than one skipped and the next notified */
  128. if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
  129. rtc->periodic_freq &= ~PF_COUNT;
  130. else {
  131. if (rtc->periodic_freq & PF_HP)
  132. rtc->periodic_freq |= PF_COUNT;
  133. if (rtc->periodic_freq & PF_KOU) {
  134. spin_lock(&rtc_dev->irq_task_lock);
  135. irq_task = rtc_dev->irq_task;
  136. if (irq_task)
  137. irq_task->func(irq_task->private_data);
  138. spin_unlock(&rtc_dev->irq_task_lock);
  139. } else
  140. rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
  141. }
  142. return pending;
  143. }
  144. static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
  145. {
  146. struct sh_rtc *rtc = dev_id;
  147. int ret;
  148. spin_lock(&rtc->lock);
  149. ret = __sh_rtc_interrupt(rtc);
  150. spin_unlock(&rtc->lock);
  151. return IRQ_RETVAL(ret);
  152. }
  153. static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
  154. {
  155. struct sh_rtc *rtc = dev_id;
  156. int ret;
  157. spin_lock(&rtc->lock);
  158. ret = __sh_rtc_alarm(rtc);
  159. spin_unlock(&rtc->lock);
  160. return IRQ_RETVAL(ret);
  161. }
  162. static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
  163. {
  164. struct sh_rtc *rtc = dev_id;
  165. int ret;
  166. spin_lock(&rtc->lock);
  167. ret = __sh_rtc_periodic(rtc);
  168. spin_unlock(&rtc->lock);
  169. return IRQ_RETVAL(ret);
  170. }
  171. static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
  172. {
  173. struct sh_rtc *rtc = dev_id;
  174. int ret;
  175. spin_lock(&rtc->lock);
  176. ret = __sh_rtc_interrupt(rtc);
  177. ret |= __sh_rtc_alarm(rtc);
  178. ret |= __sh_rtc_periodic(rtc);
  179. spin_unlock(&rtc->lock);
  180. return IRQ_RETVAL(ret);
  181. }
  182. static inline void sh_rtc_setpie(struct device *dev, unsigned int enable)
  183. {
  184. struct sh_rtc *rtc = dev_get_drvdata(dev);
  185. unsigned int tmp;
  186. spin_lock_irq(&rtc->lock);
  187. tmp = readb(rtc->regbase + RCR2);
  188. if (enable) {
  189. tmp &= ~RCR2_PEF; /* Clear PES bit */
  190. tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
  191. } else
  192. tmp &= ~(RCR2_PESMASK | RCR2_PEF);
  193. writeb(tmp, rtc->regbase + RCR2);
  194. spin_unlock_irq(&rtc->lock);
  195. }
  196. static inline int sh_rtc_setfreq(struct device *dev, unsigned int freq)
  197. {
  198. struct sh_rtc *rtc = dev_get_drvdata(dev);
  199. int tmp, ret = 0;
  200. spin_lock_irq(&rtc->lock);
  201. tmp = rtc->periodic_freq & PF_MASK;
  202. switch (freq) {
  203. case 0:
  204. rtc->periodic_freq = 0x00;
  205. break;
  206. case 1:
  207. rtc->periodic_freq = 0x60;
  208. break;
  209. case 2:
  210. rtc->periodic_freq = 0x50;
  211. break;
  212. case 4:
  213. rtc->periodic_freq = 0x40;
  214. break;
  215. case 8:
  216. rtc->periodic_freq = 0x30 | PF_HP;
  217. break;
  218. case 16:
  219. rtc->periodic_freq = 0x30;
  220. break;
  221. case 32:
  222. rtc->periodic_freq = 0x20 | PF_HP;
  223. break;
  224. case 64:
  225. rtc->periodic_freq = 0x20;
  226. break;
  227. case 128:
  228. rtc->periodic_freq = 0x10 | PF_HP;
  229. break;
  230. case 256:
  231. rtc->periodic_freq = 0x10;
  232. break;
  233. default:
  234. ret = -ENOTSUPP;
  235. }
  236. if (ret == 0) {
  237. rtc->periodic_freq |= tmp;
  238. rtc->rtc_dev->irq_freq = freq;
  239. }
  240. spin_unlock_irq(&rtc->lock);
  241. return ret;
  242. }
  243. static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
  244. {
  245. struct sh_rtc *rtc = dev_get_drvdata(dev);
  246. unsigned int tmp;
  247. spin_lock_irq(&rtc->lock);
  248. tmp = readb(rtc->regbase + RCR1);
  249. if (enable)
  250. tmp |= RCR1_AIE;
  251. else
  252. tmp &= ~RCR1_AIE;
  253. writeb(tmp, rtc->regbase + RCR1);
  254. spin_unlock_irq(&rtc->lock);
  255. }
  256. static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
  257. {
  258. struct sh_rtc *rtc = dev_get_drvdata(dev);
  259. unsigned int tmp;
  260. tmp = readb(rtc->regbase + RCR1);
  261. seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
  262. tmp = readb(rtc->regbase + RCR2);
  263. seq_printf(seq, "periodic_IRQ\t: %s\n",
  264. (tmp & RCR2_PESMASK) ? "yes" : "no");
  265. return 0;
  266. }
  267. static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
  268. {
  269. struct sh_rtc *rtc = dev_get_drvdata(dev);
  270. unsigned int tmp;
  271. spin_lock_irq(&rtc->lock);
  272. tmp = readb(rtc->regbase + RCR1);
  273. if (!enable)
  274. tmp &= ~RCR1_CIE;
  275. else
  276. tmp |= RCR1_CIE;
  277. writeb(tmp, rtc->regbase + RCR1);
  278. spin_unlock_irq(&rtc->lock);
  279. }
  280. static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
  281. {
  282. struct sh_rtc *rtc = dev_get_drvdata(dev);
  283. unsigned int ret = 0;
  284. switch (cmd) {
  285. case RTC_PIE_OFF:
  286. case RTC_PIE_ON:
  287. sh_rtc_setpie(dev, cmd == RTC_PIE_ON);
  288. break;
  289. case RTC_AIE_OFF:
  290. case RTC_AIE_ON:
  291. sh_rtc_setaie(dev, cmd == RTC_AIE_ON);
  292. break;
  293. case RTC_UIE_OFF:
  294. rtc->periodic_freq &= ~PF_OXS;
  295. sh_rtc_setcie(dev, 0);
  296. break;
  297. case RTC_UIE_ON:
  298. rtc->periodic_freq |= PF_OXS;
  299. sh_rtc_setcie(dev, 1);
  300. break;
  301. case RTC_IRQP_READ:
  302. ret = put_user(rtc->rtc_dev->irq_freq,
  303. (unsigned long __user *)arg);
  304. break;
  305. case RTC_IRQP_SET:
  306. ret = sh_rtc_setfreq(dev, arg);
  307. break;
  308. default:
  309. ret = -ENOIOCTLCMD;
  310. }
  311. return ret;
  312. }
  313. static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
  314. {
  315. struct platform_device *pdev = to_platform_device(dev);
  316. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  317. unsigned int sec128, sec2, yr, yr100, cf_bit;
  318. do {
  319. unsigned int tmp;
  320. spin_lock_irq(&rtc->lock);
  321. tmp = readb(rtc->regbase + RCR1);
  322. tmp &= ~RCR1_CF; /* Clear CF-bit */
  323. tmp |= RCR1_CIE;
  324. writeb(tmp, rtc->regbase + RCR1);
  325. sec128 = readb(rtc->regbase + R64CNT);
  326. tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
  327. tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
  328. tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
  329. tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
  330. tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
  331. tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
  332. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  333. yr = readw(rtc->regbase + RYRCNT);
  334. yr100 = bcd2bin(yr >> 8);
  335. yr &= 0xff;
  336. } else {
  337. yr = readb(rtc->regbase + RYRCNT);
  338. yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
  339. }
  340. tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
  341. sec2 = readb(rtc->regbase + R64CNT);
  342. cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
  343. spin_unlock_irq(&rtc->lock);
  344. } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
  345. #if RTC_BIT_INVERTED != 0
  346. if ((sec128 & RTC_BIT_INVERTED))
  347. tm->tm_sec--;
  348. #endif
  349. /* only keep the carry interrupt enabled if UIE is on */
  350. if (!(rtc->periodic_freq & PF_OXS))
  351. sh_rtc_setcie(dev, 0);
  352. dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  353. "mday=%d, mon=%d, year=%d, wday=%d\n",
  354. __func__,
  355. tm->tm_sec, tm->tm_min, tm->tm_hour,
  356. tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
  357. return rtc_valid_tm(tm);
  358. }
  359. static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
  360. {
  361. struct platform_device *pdev = to_platform_device(dev);
  362. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  363. unsigned int tmp;
  364. int year;
  365. spin_lock_irq(&rtc->lock);
  366. /* Reset pre-scaler & stop RTC */
  367. tmp = readb(rtc->regbase + RCR2);
  368. tmp |= RCR2_RESET;
  369. tmp &= ~RCR2_START;
  370. writeb(tmp, rtc->regbase + RCR2);
  371. writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
  372. writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
  373. writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
  374. writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
  375. writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
  376. writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
  377. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  378. year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
  379. bin2bcd(tm->tm_year % 100);
  380. writew(year, rtc->regbase + RYRCNT);
  381. } else {
  382. year = tm->tm_year % 100;
  383. writeb(bin2bcd(year), rtc->regbase + RYRCNT);
  384. }
  385. /* Start RTC */
  386. tmp = readb(rtc->regbase + RCR2);
  387. tmp &= ~RCR2_RESET;
  388. tmp |= RCR2_RTCEN | RCR2_START;
  389. writeb(tmp, rtc->regbase + RCR2);
  390. spin_unlock_irq(&rtc->lock);
  391. return 0;
  392. }
  393. static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
  394. {
  395. unsigned int byte;
  396. int value = 0xff; /* return 0xff for ignored values */
  397. byte = readb(rtc->regbase + reg_off);
  398. if (byte & AR_ENB) {
  399. byte &= ~AR_ENB; /* strip the enable bit */
  400. value = bcd2bin(byte);
  401. }
  402. return value;
  403. }
  404. static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  405. {
  406. struct platform_device *pdev = to_platform_device(dev);
  407. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  408. struct rtc_time *tm = &wkalrm->time;
  409. spin_lock_irq(&rtc->lock);
  410. tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
  411. tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
  412. tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
  413. tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
  414. tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
  415. tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
  416. if (tm->tm_mon > 0)
  417. tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
  418. tm->tm_year = 0xffff;
  419. wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
  420. spin_unlock_irq(&rtc->lock);
  421. return 0;
  422. }
  423. static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
  424. int value, int reg_off)
  425. {
  426. /* < 0 for a value that is ignored */
  427. if (value < 0)
  428. writeb(0, rtc->regbase + reg_off);
  429. else
  430. writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
  431. }
  432. static int sh_rtc_check_alarm(struct rtc_time *tm)
  433. {
  434. /*
  435. * The original rtc says anything > 0xc0 is "don't care" or "match
  436. * all" - most users use 0xff but rtc-dev uses -1 for the same thing.
  437. * The original rtc doesn't support years - some things use -1 and
  438. * some 0xffff. We use -1 to make out tests easier.
  439. */
  440. if (tm->tm_year == 0xffff)
  441. tm->tm_year = -1;
  442. if (tm->tm_mon >= 0xff)
  443. tm->tm_mon = -1;
  444. if (tm->tm_mday >= 0xff)
  445. tm->tm_mday = -1;
  446. if (tm->tm_wday >= 0xff)
  447. tm->tm_wday = -1;
  448. if (tm->tm_hour >= 0xff)
  449. tm->tm_hour = -1;
  450. if (tm->tm_min >= 0xff)
  451. tm->tm_min = -1;
  452. if (tm->tm_sec >= 0xff)
  453. tm->tm_sec = -1;
  454. if (tm->tm_year > 9999 ||
  455. tm->tm_mon >= 12 ||
  456. tm->tm_mday == 0 || tm->tm_mday >= 32 ||
  457. tm->tm_wday >= 7 ||
  458. tm->tm_hour >= 24 ||
  459. tm->tm_min >= 60 ||
  460. tm->tm_sec >= 60)
  461. return -EINVAL;
  462. return 0;
  463. }
  464. static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  465. {
  466. struct platform_device *pdev = to_platform_device(dev);
  467. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  468. unsigned int rcr1;
  469. struct rtc_time *tm = &wkalrm->time;
  470. int mon, err;
  471. err = sh_rtc_check_alarm(tm);
  472. if (unlikely(err < 0))
  473. return err;
  474. spin_lock_irq(&rtc->lock);
  475. /* disable alarm interrupt and clear the alarm flag */
  476. rcr1 = readb(rtc->regbase + RCR1);
  477. rcr1 &= ~(RCR1_AF | RCR1_AIE);
  478. writeb(rcr1, rtc->regbase + RCR1);
  479. /* set alarm time */
  480. sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
  481. sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
  482. sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
  483. sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
  484. sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
  485. mon = tm->tm_mon;
  486. if (mon >= 0)
  487. mon += 1;
  488. sh_rtc_write_alarm_value(rtc, mon, RMONAR);
  489. if (wkalrm->enabled) {
  490. rcr1 |= RCR1_AIE;
  491. writeb(rcr1, rtc->regbase + RCR1);
  492. }
  493. spin_unlock_irq(&rtc->lock);
  494. return 0;
  495. }
  496. static int sh_rtc_irq_set_state(struct device *dev, int enabled)
  497. {
  498. struct platform_device *pdev = to_platform_device(dev);
  499. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  500. if (enabled) {
  501. rtc->periodic_freq |= PF_KOU;
  502. return sh_rtc_ioctl(dev, RTC_PIE_ON, 0);
  503. } else {
  504. rtc->periodic_freq &= ~PF_KOU;
  505. return sh_rtc_ioctl(dev, RTC_PIE_OFF, 0);
  506. }
  507. }
  508. static int sh_rtc_irq_set_freq(struct device *dev, int freq)
  509. {
  510. if (!is_power_of_2(freq))
  511. return -EINVAL;
  512. return sh_rtc_ioctl(dev, RTC_IRQP_SET, freq);
  513. }
  514. static struct rtc_class_ops sh_rtc_ops = {
  515. .ioctl = sh_rtc_ioctl,
  516. .read_time = sh_rtc_read_time,
  517. .set_time = sh_rtc_set_time,
  518. .read_alarm = sh_rtc_read_alarm,
  519. .set_alarm = sh_rtc_set_alarm,
  520. .irq_set_state = sh_rtc_irq_set_state,
  521. .irq_set_freq = sh_rtc_irq_set_freq,
  522. .proc = sh_rtc_proc,
  523. };
  524. static int __devinit sh_rtc_probe(struct platform_device *pdev)
  525. {
  526. struct sh_rtc *rtc;
  527. struct resource *res;
  528. struct rtc_time r;
  529. char clk_name[6];
  530. int clk_id, ret;
  531. rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL);
  532. if (unlikely(!rtc))
  533. return -ENOMEM;
  534. spin_lock_init(&rtc->lock);
  535. /* get periodic/carry/alarm irqs */
  536. ret = platform_get_irq(pdev, 0);
  537. if (unlikely(ret <= 0)) {
  538. ret = -ENOENT;
  539. dev_err(&pdev->dev, "No IRQ resource\n");
  540. goto err_badres;
  541. }
  542. rtc->periodic_irq = ret;
  543. rtc->carry_irq = platform_get_irq(pdev, 1);
  544. rtc->alarm_irq = platform_get_irq(pdev, 2);
  545. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  546. if (unlikely(res == NULL)) {
  547. ret = -ENOENT;
  548. dev_err(&pdev->dev, "No IO resource\n");
  549. goto err_badres;
  550. }
  551. rtc->regsize = resource_size(res);
  552. rtc->res = request_mem_region(res->start, rtc->regsize, pdev->name);
  553. if (unlikely(!rtc->res)) {
  554. ret = -EBUSY;
  555. goto err_badres;
  556. }
  557. rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize);
  558. if (unlikely(!rtc->regbase)) {
  559. ret = -EINVAL;
  560. goto err_badmap;
  561. }
  562. clk_id = pdev->id;
  563. /* With a single device, the clock id is still "rtc0" */
  564. if (clk_id < 0)
  565. clk_id = 0;
  566. snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
  567. rtc->clk = clk_get(&pdev->dev, clk_name);
  568. if (IS_ERR(rtc->clk)) {
  569. /*
  570. * No error handling for rtc->clk intentionally, not all
  571. * platforms will have a unique clock for the RTC, and
  572. * the clk API can handle the struct clk pointer being
  573. * NULL.
  574. */
  575. rtc->clk = NULL;
  576. }
  577. clk_enable(rtc->clk);
  578. rtc->rtc_dev = rtc_device_register("sh", &pdev->dev,
  579. &sh_rtc_ops, THIS_MODULE);
  580. if (IS_ERR(rtc->rtc_dev)) {
  581. ret = PTR_ERR(rtc->rtc_dev);
  582. goto err_unmap;
  583. }
  584. rtc->capabilities = RTC_DEF_CAPABILITIES;
  585. if (pdev->dev.platform_data) {
  586. struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data;
  587. /*
  588. * Some CPUs have special capabilities in addition to the
  589. * default set. Add those in here.
  590. */
  591. rtc->capabilities |= pinfo->capabilities;
  592. }
  593. rtc->rtc_dev->max_user_freq = 256;
  594. platform_set_drvdata(pdev, rtc);
  595. if (rtc->carry_irq <= 0) {
  596. /* register shared periodic/carry/alarm irq */
  597. ret = request_irq(rtc->periodic_irq, sh_rtc_shared,
  598. IRQF_DISABLED, "sh-rtc", rtc);
  599. if (unlikely(ret)) {
  600. dev_err(&pdev->dev,
  601. "request IRQ failed with %d, IRQ %d\n", ret,
  602. rtc->periodic_irq);
  603. goto err_unmap;
  604. }
  605. } else {
  606. /* register periodic/carry/alarm irqs */
  607. ret = request_irq(rtc->periodic_irq, sh_rtc_periodic,
  608. IRQF_DISABLED, "sh-rtc period", rtc);
  609. if (unlikely(ret)) {
  610. dev_err(&pdev->dev,
  611. "request period IRQ failed with %d, IRQ %d\n",
  612. ret, rtc->periodic_irq);
  613. goto err_unmap;
  614. }
  615. ret = request_irq(rtc->carry_irq, sh_rtc_interrupt,
  616. IRQF_DISABLED, "sh-rtc carry", rtc);
  617. if (unlikely(ret)) {
  618. dev_err(&pdev->dev,
  619. "request carry IRQ failed with %d, IRQ %d\n",
  620. ret, rtc->carry_irq);
  621. free_irq(rtc->periodic_irq, rtc);
  622. goto err_unmap;
  623. }
  624. ret = request_irq(rtc->alarm_irq, sh_rtc_alarm,
  625. IRQF_DISABLED, "sh-rtc alarm", rtc);
  626. if (unlikely(ret)) {
  627. dev_err(&pdev->dev,
  628. "request alarm IRQ failed with %d, IRQ %d\n",
  629. ret, rtc->alarm_irq);
  630. free_irq(rtc->carry_irq, rtc);
  631. free_irq(rtc->periodic_irq, rtc);
  632. goto err_unmap;
  633. }
  634. }
  635. /* everything disabled by default */
  636. rtc->periodic_freq = 0;
  637. rtc->rtc_dev->irq_freq = 0;
  638. sh_rtc_setpie(&pdev->dev, 0);
  639. sh_rtc_setaie(&pdev->dev, 0);
  640. sh_rtc_setcie(&pdev->dev, 0);
  641. /* reset rtc to epoch 0 if time is invalid */
  642. if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
  643. rtc_time_to_tm(0, &r);
  644. rtc_set_time(rtc->rtc_dev, &r);
  645. }
  646. device_init_wakeup(&pdev->dev, 1);
  647. return 0;
  648. err_unmap:
  649. clk_disable(rtc->clk);
  650. clk_put(rtc->clk);
  651. iounmap(rtc->regbase);
  652. err_badmap:
  653. release_resource(rtc->res);
  654. err_badres:
  655. kfree(rtc);
  656. return ret;
  657. }
  658. static int __devexit sh_rtc_remove(struct platform_device *pdev)
  659. {
  660. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  661. if (likely(rtc->rtc_dev))
  662. rtc_device_unregister(rtc->rtc_dev);
  663. sh_rtc_setpie(&pdev->dev, 0);
  664. sh_rtc_setaie(&pdev->dev, 0);
  665. sh_rtc_setcie(&pdev->dev, 0);
  666. free_irq(rtc->periodic_irq, rtc);
  667. if (rtc->carry_irq > 0) {
  668. free_irq(rtc->carry_irq, rtc);
  669. free_irq(rtc->alarm_irq, rtc);
  670. }
  671. release_resource(rtc->res);
  672. iounmap(rtc->regbase);
  673. clk_disable(rtc->clk);
  674. clk_put(rtc->clk);
  675. platform_set_drvdata(pdev, NULL);
  676. kfree(rtc);
  677. return 0;
  678. }
  679. static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
  680. {
  681. struct platform_device *pdev = to_platform_device(dev);
  682. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  683. set_irq_wake(rtc->periodic_irq, enabled);
  684. if (rtc->carry_irq > 0) {
  685. set_irq_wake(rtc->carry_irq, enabled);
  686. set_irq_wake(rtc->alarm_irq, enabled);
  687. }
  688. }
  689. static int sh_rtc_suspend(struct device *dev)
  690. {
  691. if (device_may_wakeup(dev))
  692. sh_rtc_set_irq_wake(dev, 1);
  693. return 0;
  694. }
  695. static int sh_rtc_resume(struct device *dev)
  696. {
  697. if (device_may_wakeup(dev))
  698. sh_rtc_set_irq_wake(dev, 0);
  699. return 0;
  700. }
  701. static struct dev_pm_ops sh_rtc_dev_pm_ops = {
  702. .suspend = sh_rtc_suspend,
  703. .resume = sh_rtc_resume,
  704. };
  705. static struct platform_driver sh_rtc_platform_driver = {
  706. .driver = {
  707. .name = DRV_NAME,
  708. .owner = THIS_MODULE,
  709. .pm = &sh_rtc_dev_pm_ops,
  710. },
  711. .probe = sh_rtc_probe,
  712. .remove = __devexit_p(sh_rtc_remove),
  713. };
  714. static int __init sh_rtc_init(void)
  715. {
  716. return platform_driver_register(&sh_rtc_platform_driver);
  717. }
  718. static void __exit sh_rtc_exit(void)
  719. {
  720. platform_driver_unregister(&sh_rtc_platform_driver);
  721. }
  722. module_init(sh_rtc_init);
  723. module_exit(sh_rtc_exit);
  724. MODULE_DESCRIPTION("SuperH on-chip RTC driver");
  725. MODULE_VERSION(DRV_VERSION);
  726. MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
  727. "Jamie Lenehan <lenehan@twibble.org>, "
  728. "Angelo Castello <angelo.castello@st.com>");
  729. MODULE_LICENSE("GPL");
  730. MODULE_ALIAS("platform:" DRV_NAME);