aer_inject.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473
  1. /*
  2. * PCIE AER software error injection support.
  3. *
  4. * Debuging PCIE AER code is quite difficult because it is hard to
  5. * trigger various real hardware errors. Software based error
  6. * injection can fake almost all kinds of errors with the help of a
  7. * user space helper tool aer-inject, which can be gotten from:
  8. * http://www.kernel.org/pub/linux/utils/pci/aer-inject/
  9. *
  10. * Copyright 2009 Intel Corporation.
  11. * Huang Ying <ying.huang@intel.com>
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License
  15. * as published by the Free Software Foundation; version 2
  16. * of the License.
  17. *
  18. */
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/miscdevice.h>
  22. #include <linux/pci.h>
  23. #include <linux/fs.h>
  24. #include <asm/uaccess.h>
  25. #include "aerdrv.h"
  26. struct aer_error_inj
  27. {
  28. u8 bus;
  29. u8 dev;
  30. u8 fn;
  31. u32 uncor_status;
  32. u32 cor_status;
  33. u32 header_log0;
  34. u32 header_log1;
  35. u32 header_log2;
  36. u32 header_log3;
  37. };
  38. struct aer_error
  39. {
  40. struct list_head list;
  41. unsigned int bus;
  42. unsigned int devfn;
  43. int pos_cap_err;
  44. u32 uncor_status;
  45. u32 cor_status;
  46. u32 header_log0;
  47. u32 header_log1;
  48. u32 header_log2;
  49. u32 header_log3;
  50. u32 root_status;
  51. u32 source_id;
  52. };
  53. struct pci_bus_ops
  54. {
  55. struct list_head list;
  56. struct pci_bus *bus;
  57. struct pci_ops *ops;
  58. };
  59. static LIST_HEAD(einjected);
  60. static LIST_HEAD(pci_bus_ops_list);
  61. /* Protect einjected and pci_bus_ops_list */
  62. static DEFINE_SPINLOCK(inject_lock);
  63. static void aer_error_init(struct aer_error *err, unsigned int bus,
  64. unsigned int devfn, int pos_cap_err)
  65. {
  66. INIT_LIST_HEAD(&err->list);
  67. err->bus = bus;
  68. err->devfn = devfn;
  69. err->pos_cap_err = pos_cap_err;
  70. }
  71. /* inject_lock must be held before calling */
  72. static struct aer_error *__find_aer_error(unsigned int bus, unsigned int devfn)
  73. {
  74. struct aer_error *err;
  75. list_for_each_entry(err, &einjected, list) {
  76. if (bus == err->bus && devfn == err->devfn)
  77. return err;
  78. }
  79. return NULL;
  80. }
  81. /* inject_lock must be held before calling */
  82. static struct aer_error *__find_aer_error_by_dev(struct pci_dev *dev)
  83. {
  84. return __find_aer_error(dev->bus->number, dev->devfn);
  85. }
  86. /* inject_lock must be held before calling */
  87. static struct pci_ops *__find_pci_bus_ops(struct pci_bus *bus)
  88. {
  89. struct pci_bus_ops *bus_ops;
  90. list_for_each_entry(bus_ops, &pci_bus_ops_list, list) {
  91. if (bus_ops->bus == bus)
  92. return bus_ops->ops;
  93. }
  94. return NULL;
  95. }
  96. static struct pci_bus_ops *pci_bus_ops_pop(void)
  97. {
  98. unsigned long flags;
  99. struct pci_bus_ops *bus_ops = NULL;
  100. spin_lock_irqsave(&inject_lock, flags);
  101. if (list_empty(&pci_bus_ops_list))
  102. bus_ops = NULL;
  103. else {
  104. struct list_head *lh = pci_bus_ops_list.next;
  105. list_del(lh);
  106. bus_ops = list_entry(lh, struct pci_bus_ops, list);
  107. }
  108. spin_unlock_irqrestore(&inject_lock, flags);
  109. return bus_ops;
  110. }
  111. static u32 *find_pci_config_dword(struct aer_error *err, int where,
  112. int *prw1cs)
  113. {
  114. int rw1cs = 0;
  115. u32 *target = NULL;
  116. if (err->pos_cap_err == -1)
  117. return NULL;
  118. switch (where - err->pos_cap_err) {
  119. case PCI_ERR_UNCOR_STATUS:
  120. target = &err->uncor_status;
  121. rw1cs = 1;
  122. break;
  123. case PCI_ERR_COR_STATUS:
  124. target = &err->cor_status;
  125. rw1cs = 1;
  126. break;
  127. case PCI_ERR_HEADER_LOG:
  128. target = &err->header_log0;
  129. break;
  130. case PCI_ERR_HEADER_LOG+4:
  131. target = &err->header_log1;
  132. break;
  133. case PCI_ERR_HEADER_LOG+8:
  134. target = &err->header_log2;
  135. break;
  136. case PCI_ERR_HEADER_LOG+12:
  137. target = &err->header_log3;
  138. break;
  139. case PCI_ERR_ROOT_STATUS:
  140. target = &err->root_status;
  141. rw1cs = 1;
  142. break;
  143. case PCI_ERR_ROOT_COR_SRC:
  144. target = &err->source_id;
  145. break;
  146. }
  147. if (prw1cs)
  148. *prw1cs = rw1cs;
  149. return target;
  150. }
  151. static int pci_read_aer(struct pci_bus *bus, unsigned int devfn, int where,
  152. int size, u32 *val)
  153. {
  154. u32 *sim;
  155. struct aer_error *err;
  156. unsigned long flags;
  157. struct pci_ops *ops;
  158. spin_lock_irqsave(&inject_lock, flags);
  159. if (size != sizeof(u32))
  160. goto out;
  161. err = __find_aer_error(bus->number, devfn);
  162. if (!err)
  163. goto out;
  164. sim = find_pci_config_dword(err, where, NULL);
  165. if (sim) {
  166. *val = *sim;
  167. spin_unlock_irqrestore(&inject_lock, flags);
  168. return 0;
  169. }
  170. out:
  171. ops = __find_pci_bus_ops(bus);
  172. spin_unlock_irqrestore(&inject_lock, flags);
  173. return ops->read(bus, devfn, where, size, val);
  174. }
  175. int pci_write_aer(struct pci_bus *bus, unsigned int devfn, int where, int size,
  176. u32 val)
  177. {
  178. u32 *sim;
  179. struct aer_error *err;
  180. unsigned long flags;
  181. int rw1cs;
  182. struct pci_ops *ops;
  183. spin_lock_irqsave(&inject_lock, flags);
  184. if (size != sizeof(u32))
  185. goto out;
  186. err = __find_aer_error(bus->number, devfn);
  187. if (!err)
  188. goto out;
  189. sim = find_pci_config_dword(err, where, &rw1cs);
  190. if (sim) {
  191. if (rw1cs)
  192. *sim ^= val;
  193. else
  194. *sim = val;
  195. spin_unlock_irqrestore(&inject_lock, flags);
  196. return 0;
  197. }
  198. out:
  199. ops = __find_pci_bus_ops(bus);
  200. spin_unlock_irqrestore(&inject_lock, flags);
  201. return ops->write(bus, devfn, where, size, val);
  202. }
  203. static struct pci_ops pci_ops_aer = {
  204. .read = pci_read_aer,
  205. .write = pci_write_aer,
  206. };
  207. static void pci_bus_ops_init(struct pci_bus_ops *bus_ops,
  208. struct pci_bus *bus,
  209. struct pci_ops *ops)
  210. {
  211. INIT_LIST_HEAD(&bus_ops->list);
  212. bus_ops->bus = bus;
  213. bus_ops->ops = ops;
  214. }
  215. static int pci_bus_set_aer_ops(struct pci_bus *bus)
  216. {
  217. struct pci_ops *ops;
  218. struct pci_bus_ops *bus_ops;
  219. unsigned long flags;
  220. bus_ops = kmalloc(sizeof(*bus_ops), GFP_KERNEL);
  221. if (!bus_ops)
  222. return -ENOMEM;
  223. ops = pci_bus_set_ops(bus, &pci_ops_aer);
  224. spin_lock_irqsave(&inject_lock, flags);
  225. if (ops == &pci_ops_aer)
  226. goto out;
  227. pci_bus_ops_init(bus_ops, bus, ops);
  228. list_add(&bus_ops->list, &pci_bus_ops_list);
  229. bus_ops = NULL;
  230. out:
  231. spin_unlock_irqrestore(&inject_lock, flags);
  232. if (bus_ops)
  233. kfree(bus_ops);
  234. return 0;
  235. }
  236. static struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
  237. {
  238. while (1) {
  239. if (!dev->is_pcie)
  240. break;
  241. if (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
  242. return dev;
  243. if (!dev->bus->self)
  244. break;
  245. dev = dev->bus->self;
  246. }
  247. return NULL;
  248. }
  249. static int find_aer_device_iter(struct device *device, void *data)
  250. {
  251. struct pcie_device **result = data;
  252. struct pcie_device *pcie_dev;
  253. if (device->bus == &pcie_port_bus_type) {
  254. pcie_dev = to_pcie_device(device);
  255. if (pcie_dev->service & PCIE_PORT_SERVICE_AER) {
  256. *result = pcie_dev;
  257. return 1;
  258. }
  259. }
  260. return 0;
  261. }
  262. static int find_aer_device(struct pci_dev *dev, struct pcie_device **result)
  263. {
  264. return device_for_each_child(&dev->dev, result, find_aer_device_iter);
  265. }
  266. static int aer_inject(struct aer_error_inj *einj)
  267. {
  268. struct aer_error *err, *rperr;
  269. struct aer_error *err_alloc = NULL, *rperr_alloc = NULL;
  270. struct pci_dev *dev, *rpdev;
  271. struct pcie_device *edev;
  272. unsigned long flags;
  273. unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
  274. int pos_cap_err, rp_pos_cap_err;
  275. u32 sever;
  276. int ret = 0;
  277. dev = pci_get_bus_and_slot(einj->bus, devfn);
  278. if (!dev)
  279. return -EINVAL;
  280. rpdev = pcie_find_root_port(dev);
  281. if (!rpdev) {
  282. ret = -EINVAL;
  283. goto out_put;
  284. }
  285. pos_cap_err = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
  286. if (!pos_cap_err) {
  287. ret = -EIO;
  288. goto out_put;
  289. }
  290. pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever);
  291. rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR);
  292. if (!rp_pos_cap_err) {
  293. ret = -EIO;
  294. goto out_put;
  295. }
  296. err_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
  297. if (!err_alloc) {
  298. ret = -ENOMEM;
  299. goto out_put;
  300. }
  301. rperr_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
  302. if (!rperr_alloc) {
  303. ret = -ENOMEM;
  304. goto out_put;
  305. }
  306. spin_lock_irqsave(&inject_lock, flags);
  307. err = __find_aer_error_by_dev(dev);
  308. if (!err) {
  309. err = err_alloc;
  310. err_alloc = NULL;
  311. aer_error_init(err, einj->bus, devfn, pos_cap_err);
  312. list_add(&err->list, &einjected);
  313. }
  314. err->uncor_status |= einj->uncor_status;
  315. err->cor_status |= einj->cor_status;
  316. err->header_log0 = einj->header_log0;
  317. err->header_log1 = einj->header_log1;
  318. err->header_log2 = einj->header_log2;
  319. err->header_log3 = einj->header_log3;
  320. rperr = __find_aer_error_by_dev(rpdev);
  321. if (!rperr) {
  322. rperr = rperr_alloc;
  323. rperr_alloc = NULL;
  324. aer_error_init(rperr, rpdev->bus->number, rpdev->devfn,
  325. rp_pos_cap_err);
  326. list_add(&rperr->list, &einjected);
  327. }
  328. if (einj->cor_status) {
  329. if (rperr->root_status & PCI_ERR_ROOT_COR_RCV)
  330. rperr->root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
  331. else
  332. rperr->root_status |= PCI_ERR_ROOT_COR_RCV;
  333. rperr->source_id &= 0xffff0000;
  334. rperr->source_id |= (einj->bus << 8) | devfn;
  335. }
  336. if (einj->uncor_status) {
  337. if (rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV)
  338. rperr->root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
  339. if (sever & einj->uncor_status) {
  340. rperr->root_status |= PCI_ERR_ROOT_FATAL_RCV;
  341. if (!(rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV))
  342. rperr->root_status |= PCI_ERR_ROOT_FIRST_FATAL;
  343. } else
  344. rperr->root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
  345. rperr->root_status |= PCI_ERR_ROOT_UNCOR_RCV;
  346. rperr->source_id &= 0x0000ffff;
  347. rperr->source_id |= ((einj->bus << 8) | devfn) << 16;
  348. }
  349. spin_unlock_irqrestore(&inject_lock, flags);
  350. ret = pci_bus_set_aer_ops(dev->bus);
  351. if (ret)
  352. goto out_put;
  353. ret = pci_bus_set_aer_ops(rpdev->bus);
  354. if (ret)
  355. goto out_put;
  356. if (find_aer_device(rpdev, &edev))
  357. aer_irq(-1, edev);
  358. else
  359. ret = -EINVAL;
  360. out_put:
  361. if (err_alloc)
  362. kfree(err_alloc);
  363. if (rperr_alloc)
  364. kfree(rperr_alloc);
  365. pci_dev_put(dev);
  366. return ret;
  367. }
  368. static ssize_t aer_inject_write(struct file *filp, const char __user *ubuf,
  369. size_t usize, loff_t *off)
  370. {
  371. struct aer_error_inj einj;
  372. int ret;
  373. if (!capable(CAP_SYS_ADMIN))
  374. return -EPERM;
  375. if (usize != sizeof(struct aer_error_inj))
  376. return -EINVAL;
  377. if (copy_from_user(&einj, ubuf, usize))
  378. return -EFAULT;
  379. ret = aer_inject(&einj);
  380. return ret ? ret : usize;
  381. }
  382. static const struct file_operations aer_inject_fops = {
  383. .write = aer_inject_write,
  384. .owner = THIS_MODULE,
  385. };
  386. static struct miscdevice aer_inject_device = {
  387. .minor = MISC_DYNAMIC_MINOR,
  388. .name = "aer_inject",
  389. .fops = &aer_inject_fops,
  390. };
  391. static int __init aer_inject_init(void)
  392. {
  393. return misc_register(&aer_inject_device);
  394. }
  395. static void __exit aer_inject_exit(void)
  396. {
  397. struct aer_error *err, *err_next;
  398. unsigned long flags;
  399. struct pci_bus_ops *bus_ops;
  400. misc_deregister(&aer_inject_device);
  401. while ((bus_ops = pci_bus_ops_pop())) {
  402. pci_bus_set_ops(bus_ops->bus, bus_ops->ops);
  403. kfree(bus_ops);
  404. }
  405. spin_lock_irqsave(&inject_lock, flags);
  406. list_for_each_entry_safe(err, err_next,
  407. &pci_bus_ops_list, list) {
  408. list_del(&err->list);
  409. kfree(err);
  410. }
  411. spin_unlock_irqrestore(&inject_lock, flags);
  412. }
  413. module_init(aer_inject_init);
  414. module_exit(aer_inject_exit);
  415. MODULE_DESCRIPTION("PCIE AER software error injector");
  416. MODULE_LICENSE("GPL");