xmit.c 55 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "ath9k.h"
  17. #define BITS_PER_BYTE 8
  18. #define OFDM_PLCP_BITS 22
  19. #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
  20. #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
  21. #define L_STF 8
  22. #define L_LTF 8
  23. #define L_SIG 4
  24. #define HT_SIG 8
  25. #define HT_STF 4
  26. #define HT_LTF(_ns) (4 * (_ns))
  27. #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
  28. #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
  29. #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
  30. #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
  31. #define OFDM_SIFS_TIME 16
  32. static u32 bits_per_symbol[][2] = {
  33. /* 20MHz 40MHz */
  34. { 26, 54 }, /* 0: BPSK */
  35. { 52, 108 }, /* 1: QPSK 1/2 */
  36. { 78, 162 }, /* 2: QPSK 3/4 */
  37. { 104, 216 }, /* 3: 16-QAM 1/2 */
  38. { 156, 324 }, /* 4: 16-QAM 3/4 */
  39. { 208, 432 }, /* 5: 64-QAM 2/3 */
  40. { 234, 486 }, /* 6: 64-QAM 3/4 */
  41. { 260, 540 }, /* 7: 64-QAM 5/6 */
  42. { 52, 108 }, /* 8: BPSK */
  43. { 104, 216 }, /* 9: QPSK 1/2 */
  44. { 156, 324 }, /* 10: QPSK 3/4 */
  45. { 208, 432 }, /* 11: 16-QAM 1/2 */
  46. { 312, 648 }, /* 12: 16-QAM 3/4 */
  47. { 416, 864 }, /* 13: 64-QAM 2/3 */
  48. { 468, 972 }, /* 14: 64-QAM 3/4 */
  49. { 520, 1080 }, /* 15: 64-QAM 5/6 */
  50. };
  51. #define IS_HT_RATE(_rate) ((_rate) & 0x80)
  52. static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
  53. struct ath_atx_tid *tid,
  54. struct list_head *bf_head);
  55. static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
  56. struct list_head *bf_q,
  57. int txok, int sendbar);
  58. static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
  59. struct list_head *head);
  60. static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
  61. static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
  62. int txok);
  63. static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
  64. int nbad, int txok, bool update_rc);
  65. /*********************/
  66. /* Aggregation logic */
  67. /*********************/
  68. static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
  69. {
  70. struct ath_atx_tid *tid;
  71. tid = ATH_AN_2_TID(an, tidno);
  72. if (tid->state & AGGR_ADDBA_COMPLETE ||
  73. tid->state & AGGR_ADDBA_PROGRESS)
  74. return 1;
  75. else
  76. return 0;
  77. }
  78. static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
  79. {
  80. struct ath_atx_ac *ac = tid->ac;
  81. if (tid->paused)
  82. return;
  83. if (tid->sched)
  84. return;
  85. tid->sched = true;
  86. list_add_tail(&tid->list, &ac->tid_q);
  87. if (ac->sched)
  88. return;
  89. ac->sched = true;
  90. list_add_tail(&ac->list, &txq->axq_acq);
  91. }
  92. static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
  93. {
  94. struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
  95. spin_lock_bh(&txq->axq_lock);
  96. tid->paused++;
  97. spin_unlock_bh(&txq->axq_lock);
  98. }
  99. static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
  100. {
  101. struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
  102. ASSERT(tid->paused > 0);
  103. spin_lock_bh(&txq->axq_lock);
  104. tid->paused--;
  105. if (tid->paused > 0)
  106. goto unlock;
  107. if (list_empty(&tid->buf_q))
  108. goto unlock;
  109. ath_tx_queue_tid(txq, tid);
  110. ath_txq_schedule(sc, txq);
  111. unlock:
  112. spin_unlock_bh(&txq->axq_lock);
  113. }
  114. static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
  115. {
  116. struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
  117. struct ath_buf *bf;
  118. struct list_head bf_head;
  119. INIT_LIST_HEAD(&bf_head);
  120. ASSERT(tid->paused > 0);
  121. spin_lock_bh(&txq->axq_lock);
  122. tid->paused--;
  123. if (tid->paused > 0) {
  124. spin_unlock_bh(&txq->axq_lock);
  125. return;
  126. }
  127. while (!list_empty(&tid->buf_q)) {
  128. bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
  129. ASSERT(!bf_isretried(bf));
  130. list_move_tail(&bf->list, &bf_head);
  131. ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
  132. }
  133. spin_unlock_bh(&txq->axq_lock);
  134. }
  135. static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  136. int seqno)
  137. {
  138. int index, cindex;
  139. index = ATH_BA_INDEX(tid->seq_start, seqno);
  140. cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
  141. tid->tx_buf[cindex] = NULL;
  142. while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
  143. INCR(tid->seq_start, IEEE80211_SEQ_MAX);
  144. INCR(tid->baw_head, ATH_TID_MAX_BUFS);
  145. }
  146. }
  147. static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  148. struct ath_buf *bf)
  149. {
  150. int index, cindex;
  151. if (bf_isretried(bf))
  152. return;
  153. index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
  154. cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
  155. ASSERT(tid->tx_buf[cindex] == NULL);
  156. tid->tx_buf[cindex] = bf;
  157. if (index >= ((tid->baw_tail - tid->baw_head) &
  158. (ATH_TID_MAX_BUFS - 1))) {
  159. tid->baw_tail = cindex;
  160. INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
  161. }
  162. }
  163. /*
  164. * TODO: For frame(s) that are in the retry state, we will reuse the
  165. * sequence number(s) without setting the retry bit. The
  166. * alternative is to give up on these and BAR the receiver's window
  167. * forward.
  168. */
  169. static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
  170. struct ath_atx_tid *tid)
  171. {
  172. struct ath_buf *bf;
  173. struct list_head bf_head;
  174. INIT_LIST_HEAD(&bf_head);
  175. for (;;) {
  176. if (list_empty(&tid->buf_q))
  177. break;
  178. bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
  179. list_move_tail(&bf->list, &bf_head);
  180. if (bf_isretried(bf))
  181. ath_tx_update_baw(sc, tid, bf->bf_seqno);
  182. spin_unlock(&txq->axq_lock);
  183. ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
  184. spin_lock(&txq->axq_lock);
  185. }
  186. tid->seq_next = tid->seq_start;
  187. tid->baw_tail = tid->baw_head;
  188. }
  189. static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
  190. {
  191. struct sk_buff *skb;
  192. struct ieee80211_hdr *hdr;
  193. bf->bf_state.bf_type |= BUF_RETRY;
  194. bf->bf_retries++;
  195. skb = bf->bf_mpdu;
  196. hdr = (struct ieee80211_hdr *)skb->data;
  197. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
  198. }
  199. static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
  200. {
  201. struct ath_buf *tbf;
  202. spin_lock_bh(&sc->tx.txbuflock);
  203. ASSERT(!list_empty((&sc->tx.txbuf)));
  204. tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
  205. list_del(&tbf->list);
  206. spin_unlock_bh(&sc->tx.txbuflock);
  207. ATH_TXBUF_RESET(tbf);
  208. tbf->bf_mpdu = bf->bf_mpdu;
  209. tbf->bf_buf_addr = bf->bf_buf_addr;
  210. *(tbf->bf_desc) = *(bf->bf_desc);
  211. tbf->bf_state = bf->bf_state;
  212. tbf->bf_dmacontext = bf->bf_dmacontext;
  213. return tbf;
  214. }
  215. static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
  216. struct ath_buf *bf, struct list_head *bf_q,
  217. int txok)
  218. {
  219. struct ath_node *an = NULL;
  220. struct sk_buff *skb;
  221. struct ieee80211_sta *sta;
  222. struct ieee80211_hdr *hdr;
  223. struct ath_atx_tid *tid = NULL;
  224. struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
  225. struct ath_desc *ds = bf_last->bf_desc;
  226. struct list_head bf_head, bf_pending;
  227. u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
  228. u32 ba[WME_BA_BMP_SIZE >> 5];
  229. int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
  230. bool rc_update = true;
  231. skb = bf->bf_mpdu;
  232. hdr = (struct ieee80211_hdr *)skb->data;
  233. rcu_read_lock();
  234. sta = ieee80211_find_sta(sc->hw, hdr->addr1);
  235. if (!sta) {
  236. rcu_read_unlock();
  237. return;
  238. }
  239. an = (struct ath_node *)sta->drv_priv;
  240. tid = ATH_AN_2_TID(an, bf->bf_tidno);
  241. isaggr = bf_isaggr(bf);
  242. memset(ba, 0, WME_BA_BMP_SIZE >> 3);
  243. if (isaggr && txok) {
  244. if (ATH_DS_TX_BA(ds)) {
  245. seq_st = ATH_DS_BA_SEQ(ds);
  246. memcpy(ba, ATH_DS_BA_BITMAP(ds),
  247. WME_BA_BMP_SIZE >> 3);
  248. } else {
  249. /*
  250. * AR5416 can become deaf/mute when BA
  251. * issue happens. Chip needs to be reset.
  252. * But AP code may have sychronization issues
  253. * when perform internal reset in this routine.
  254. * Only enable reset in STA mode for now.
  255. */
  256. if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
  257. needreset = 1;
  258. }
  259. }
  260. INIT_LIST_HEAD(&bf_pending);
  261. INIT_LIST_HEAD(&bf_head);
  262. nbad = ath_tx_num_badfrms(sc, bf, txok);
  263. while (bf) {
  264. txfail = txpending = 0;
  265. bf_next = bf->bf_next;
  266. if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
  267. /* transmit completion, subframe is
  268. * acked by block ack */
  269. acked_cnt++;
  270. } else if (!isaggr && txok) {
  271. /* transmit completion */
  272. acked_cnt++;
  273. } else {
  274. if (!(tid->state & AGGR_CLEANUP) &&
  275. ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
  276. if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
  277. ath_tx_set_retry(sc, bf);
  278. txpending = 1;
  279. } else {
  280. bf->bf_state.bf_type |= BUF_XRETRY;
  281. txfail = 1;
  282. sendbar = 1;
  283. txfail_cnt++;
  284. }
  285. } else {
  286. /*
  287. * cleanup in progress, just fail
  288. * the un-acked sub-frames
  289. */
  290. txfail = 1;
  291. }
  292. }
  293. if (bf_next == NULL) {
  294. /*
  295. * Make sure the last desc is reclaimed if it
  296. * not a holding desc.
  297. */
  298. if (!bf_last->bf_stale)
  299. list_move_tail(&bf->list, &bf_head);
  300. else
  301. INIT_LIST_HEAD(&bf_head);
  302. } else {
  303. ASSERT(!list_empty(bf_q));
  304. list_move_tail(&bf->list, &bf_head);
  305. }
  306. if (!txpending) {
  307. /*
  308. * complete the acked-ones/xretried ones; update
  309. * block-ack window
  310. */
  311. spin_lock_bh(&txq->axq_lock);
  312. ath_tx_update_baw(sc, tid, bf->bf_seqno);
  313. spin_unlock_bh(&txq->axq_lock);
  314. if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
  315. ath_tx_rc_status(bf, ds, nbad, txok, true);
  316. rc_update = false;
  317. } else {
  318. ath_tx_rc_status(bf, ds, nbad, txok, false);
  319. }
  320. ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
  321. } else {
  322. /* retry the un-acked ones */
  323. if (bf->bf_next == NULL && bf_last->bf_stale) {
  324. struct ath_buf *tbf;
  325. tbf = ath_clone_txbuf(sc, bf_last);
  326. ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
  327. list_add_tail(&tbf->list, &bf_head);
  328. } else {
  329. /*
  330. * Clear descriptor status words for
  331. * software retry
  332. */
  333. ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
  334. }
  335. /*
  336. * Put this buffer to the temporary pending
  337. * queue to retain ordering
  338. */
  339. list_splice_tail_init(&bf_head, &bf_pending);
  340. }
  341. bf = bf_next;
  342. }
  343. if (tid->state & AGGR_CLEANUP) {
  344. if (tid->baw_head == tid->baw_tail) {
  345. tid->state &= ~AGGR_ADDBA_COMPLETE;
  346. tid->addba_exchangeattempts = 0;
  347. tid->state &= ~AGGR_CLEANUP;
  348. /* send buffered frames as singles */
  349. ath_tx_flush_tid(sc, tid);
  350. }
  351. rcu_read_unlock();
  352. return;
  353. }
  354. /* prepend un-acked frames to the beginning of the pending frame queue */
  355. if (!list_empty(&bf_pending)) {
  356. spin_lock_bh(&txq->axq_lock);
  357. list_splice(&bf_pending, &tid->buf_q);
  358. ath_tx_queue_tid(txq, tid);
  359. spin_unlock_bh(&txq->axq_lock);
  360. }
  361. rcu_read_unlock();
  362. if (needreset)
  363. ath_reset(sc, false);
  364. }
  365. static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
  366. struct ath_atx_tid *tid)
  367. {
  368. const struct ath_rate_table *rate_table = sc->cur_rate_table;
  369. struct sk_buff *skb;
  370. struct ieee80211_tx_info *tx_info;
  371. struct ieee80211_tx_rate *rates;
  372. struct ath_tx_info_priv *tx_info_priv;
  373. u32 max_4ms_framelen, frmlen;
  374. u16 aggr_limit, legacy = 0, maxampdu;
  375. int i;
  376. skb = bf->bf_mpdu;
  377. tx_info = IEEE80211_SKB_CB(skb);
  378. rates = tx_info->control.rates;
  379. tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
  380. /*
  381. * Find the lowest frame length among the rate series that will have a
  382. * 4ms transmit duration.
  383. * TODO - TXOP limit needs to be considered.
  384. */
  385. max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
  386. for (i = 0; i < 4; i++) {
  387. if (rates[i].count) {
  388. if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
  389. legacy = 1;
  390. break;
  391. }
  392. frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
  393. max_4ms_framelen = min(max_4ms_framelen, frmlen);
  394. }
  395. }
  396. /*
  397. * limit aggregate size by the minimum rate if rate selected is
  398. * not a probe rate, if rate selected is a probe rate then
  399. * avoid aggregation of this packet.
  400. */
  401. if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
  402. return 0;
  403. aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
  404. /*
  405. * h/w can accept aggregates upto 16 bit lengths (65535).
  406. * The IE, however can hold upto 65536, which shows up here
  407. * as zero. Ignore 65536 since we are constrained by hw.
  408. */
  409. maxampdu = tid->an->maxampdu;
  410. if (maxampdu)
  411. aggr_limit = min(aggr_limit, maxampdu);
  412. return aggr_limit;
  413. }
  414. /*
  415. * Returns the number of delimiters to be added to
  416. * meet the minimum required mpdudensity.
  417. * caller should make sure that the rate is HT rate .
  418. */
  419. static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
  420. struct ath_buf *bf, u16 frmlen)
  421. {
  422. const struct ath_rate_table *rt = sc->cur_rate_table;
  423. struct sk_buff *skb = bf->bf_mpdu;
  424. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  425. u32 nsymbits, nsymbols, mpdudensity;
  426. u16 minlen;
  427. u8 rc, flags, rix;
  428. int width, half_gi, ndelim, mindelim;
  429. /* Select standard number of delimiters based on frame length alone */
  430. ndelim = ATH_AGGR_GET_NDELIM(frmlen);
  431. /*
  432. * If encryption enabled, hardware requires some more padding between
  433. * subframes.
  434. * TODO - this could be improved to be dependent on the rate.
  435. * The hardware can keep up at lower rates, but not higher rates
  436. */
  437. if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
  438. ndelim += ATH_AGGR_ENCRYPTDELIM;
  439. /*
  440. * Convert desired mpdu density from microeconds to bytes based
  441. * on highest rate in rate series (i.e. first rate) to determine
  442. * required minimum length for subframe. Take into account
  443. * whether high rate is 20 or 40Mhz and half or full GI.
  444. */
  445. mpdudensity = tid->an->mpdudensity;
  446. /*
  447. * If there is no mpdu density restriction, no further calculation
  448. * is needed.
  449. */
  450. if (mpdudensity == 0)
  451. return ndelim;
  452. rix = tx_info->control.rates[0].idx;
  453. flags = tx_info->control.rates[0].flags;
  454. rc = rt->info[rix].ratecode;
  455. width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
  456. half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
  457. if (half_gi)
  458. nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
  459. else
  460. nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
  461. if (nsymbols == 0)
  462. nsymbols = 1;
  463. nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
  464. minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
  465. if (frmlen < minlen) {
  466. mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
  467. ndelim = max(mindelim, ndelim);
  468. }
  469. return ndelim;
  470. }
  471. static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
  472. struct ath_atx_tid *tid,
  473. struct list_head *bf_q)
  474. {
  475. #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
  476. struct ath_buf *bf, *bf_first, *bf_prev = NULL;
  477. int rl = 0, nframes = 0, ndelim, prev_al = 0;
  478. u16 aggr_limit = 0, al = 0, bpad = 0,
  479. al_delta, h_baw = tid->baw_size / 2;
  480. enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
  481. bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
  482. do {
  483. bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
  484. /* do not step over block-ack window */
  485. if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
  486. status = ATH_AGGR_BAW_CLOSED;
  487. break;
  488. }
  489. if (!rl) {
  490. aggr_limit = ath_lookup_rate(sc, bf, tid);
  491. rl = 1;
  492. }
  493. /* do not exceed aggregation limit */
  494. al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
  495. if (nframes &&
  496. (aggr_limit < (al + bpad + al_delta + prev_al))) {
  497. status = ATH_AGGR_LIMITED;
  498. break;
  499. }
  500. /* do not exceed subframe limit */
  501. if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
  502. status = ATH_AGGR_LIMITED;
  503. break;
  504. }
  505. nframes++;
  506. /* add padding for previous frame to aggregation length */
  507. al += bpad + al_delta;
  508. /*
  509. * Get the delimiters needed to meet the MPDU
  510. * density for this node.
  511. */
  512. ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
  513. bpad = PADBYTES(al_delta) + (ndelim << 2);
  514. bf->bf_next = NULL;
  515. bf->bf_desc->ds_link = 0;
  516. /* link buffers of this frame to the aggregate */
  517. ath_tx_addto_baw(sc, tid, bf);
  518. ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
  519. list_move_tail(&bf->list, bf_q);
  520. if (bf_prev) {
  521. bf_prev->bf_next = bf;
  522. bf_prev->bf_desc->ds_link = bf->bf_daddr;
  523. }
  524. bf_prev = bf;
  525. } while (!list_empty(&tid->buf_q));
  526. bf_first->bf_al = al;
  527. bf_first->bf_nframes = nframes;
  528. return status;
  529. #undef PADBYTES
  530. }
  531. static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
  532. struct ath_atx_tid *tid)
  533. {
  534. struct ath_buf *bf;
  535. enum ATH_AGGR_STATUS status;
  536. struct list_head bf_q;
  537. do {
  538. if (list_empty(&tid->buf_q))
  539. return;
  540. INIT_LIST_HEAD(&bf_q);
  541. status = ath_tx_form_aggr(sc, tid, &bf_q);
  542. /*
  543. * no frames picked up to be aggregated;
  544. * block-ack window is not open.
  545. */
  546. if (list_empty(&bf_q))
  547. break;
  548. bf = list_first_entry(&bf_q, struct ath_buf, list);
  549. bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
  550. /* if only one frame, send as non-aggregate */
  551. if (bf->bf_nframes == 1) {
  552. bf->bf_state.bf_type &= ~BUF_AGGR;
  553. ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
  554. ath_buf_set_rate(sc, bf);
  555. ath_tx_txqaddbuf(sc, txq, &bf_q);
  556. continue;
  557. }
  558. /* setup first desc of aggregate */
  559. bf->bf_state.bf_type |= BUF_AGGR;
  560. ath_buf_set_rate(sc, bf);
  561. ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
  562. /* anchor last desc of aggregate */
  563. ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
  564. txq->axq_aggr_depth++;
  565. ath_tx_txqaddbuf(sc, txq, &bf_q);
  566. } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
  567. status != ATH_AGGR_BAW_CLOSED);
  568. }
  569. int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
  570. u16 tid, u16 *ssn)
  571. {
  572. struct ath_atx_tid *txtid;
  573. struct ath_node *an;
  574. an = (struct ath_node *)sta->drv_priv;
  575. if (sc->sc_flags & SC_OP_TXAGGR) {
  576. txtid = ATH_AN_2_TID(an, tid);
  577. txtid->state |= AGGR_ADDBA_PROGRESS;
  578. ath_tx_pause_tid(sc, txtid);
  579. *ssn = txtid->seq_start;
  580. }
  581. return 0;
  582. }
  583. int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
  584. {
  585. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  586. struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
  587. struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
  588. struct ath_buf *bf;
  589. struct list_head bf_head;
  590. INIT_LIST_HEAD(&bf_head);
  591. if (txtid->state & AGGR_CLEANUP)
  592. return 0;
  593. if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
  594. txtid->state &= ~AGGR_ADDBA_PROGRESS;
  595. txtid->addba_exchangeattempts = 0;
  596. return 0;
  597. }
  598. ath_tx_pause_tid(sc, txtid);
  599. /* drop all software retried frames and mark this TID */
  600. spin_lock_bh(&txq->axq_lock);
  601. while (!list_empty(&txtid->buf_q)) {
  602. bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
  603. if (!bf_isretried(bf)) {
  604. /*
  605. * NB: it's based on the assumption that
  606. * software retried frame will always stay
  607. * at the head of software queue.
  608. */
  609. break;
  610. }
  611. list_move_tail(&bf->list, &bf_head);
  612. ath_tx_update_baw(sc, txtid, bf->bf_seqno);
  613. ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
  614. }
  615. spin_unlock_bh(&txq->axq_lock);
  616. if (txtid->baw_head != txtid->baw_tail) {
  617. txtid->state |= AGGR_CLEANUP;
  618. } else {
  619. txtid->state &= ~AGGR_ADDBA_COMPLETE;
  620. txtid->addba_exchangeattempts = 0;
  621. ath_tx_flush_tid(sc, txtid);
  622. }
  623. return 0;
  624. }
  625. void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
  626. {
  627. struct ath_atx_tid *txtid;
  628. struct ath_node *an;
  629. an = (struct ath_node *)sta->drv_priv;
  630. if (sc->sc_flags & SC_OP_TXAGGR) {
  631. txtid = ATH_AN_2_TID(an, tid);
  632. txtid->baw_size =
  633. IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
  634. txtid->state |= AGGR_ADDBA_COMPLETE;
  635. txtid->state &= ~AGGR_ADDBA_PROGRESS;
  636. ath_tx_resume_tid(sc, txtid);
  637. }
  638. }
  639. bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
  640. {
  641. struct ath_atx_tid *txtid;
  642. if (!(sc->sc_flags & SC_OP_TXAGGR))
  643. return false;
  644. txtid = ATH_AN_2_TID(an, tidno);
  645. if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
  646. if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
  647. (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
  648. txtid->addba_exchangeattempts++;
  649. return true;
  650. }
  651. }
  652. return false;
  653. }
  654. /********************/
  655. /* Queue Management */
  656. /********************/
  657. static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
  658. struct ath_txq *txq)
  659. {
  660. struct ath_atx_ac *ac, *ac_tmp;
  661. struct ath_atx_tid *tid, *tid_tmp;
  662. list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
  663. list_del(&ac->list);
  664. ac->sched = false;
  665. list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
  666. list_del(&tid->list);
  667. tid->sched = false;
  668. ath_tid_drain(sc, txq, tid);
  669. }
  670. }
  671. }
  672. struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
  673. {
  674. struct ath_hw *ah = sc->sc_ah;
  675. struct ath9k_tx_queue_info qi;
  676. int qnum;
  677. memset(&qi, 0, sizeof(qi));
  678. qi.tqi_subtype = subtype;
  679. qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
  680. qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
  681. qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
  682. qi.tqi_physCompBuf = 0;
  683. /*
  684. * Enable interrupts only for EOL and DESC conditions.
  685. * We mark tx descriptors to receive a DESC interrupt
  686. * when a tx queue gets deep; otherwise waiting for the
  687. * EOL to reap descriptors. Note that this is done to
  688. * reduce interrupt load and this only defers reaping
  689. * descriptors, never transmitting frames. Aside from
  690. * reducing interrupts this also permits more concurrency.
  691. * The only potential downside is if the tx queue backs
  692. * up in which case the top half of the kernel may backup
  693. * due to a lack of tx descriptors.
  694. *
  695. * The UAPSD queue is an exception, since we take a desc-
  696. * based intr on the EOSP frames.
  697. */
  698. if (qtype == ATH9K_TX_QUEUE_UAPSD)
  699. qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
  700. else
  701. qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
  702. TXQ_FLAG_TXDESCINT_ENABLE;
  703. qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
  704. if (qnum == -1) {
  705. /*
  706. * NB: don't print a message, this happens
  707. * normally on parts with too few tx queues
  708. */
  709. return NULL;
  710. }
  711. if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
  712. DPRINTF(sc, ATH_DBG_FATAL,
  713. "qnum %u out of range, max %u!\n",
  714. qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
  715. ath9k_hw_releasetxqueue(ah, qnum);
  716. return NULL;
  717. }
  718. if (!ATH_TXQ_SETUP(sc, qnum)) {
  719. struct ath_txq *txq = &sc->tx.txq[qnum];
  720. txq->axq_qnum = qnum;
  721. txq->axq_link = NULL;
  722. INIT_LIST_HEAD(&txq->axq_q);
  723. INIT_LIST_HEAD(&txq->axq_acq);
  724. spin_lock_init(&txq->axq_lock);
  725. txq->axq_depth = 0;
  726. txq->axq_aggr_depth = 0;
  727. txq->axq_totalqueued = 0;
  728. txq->axq_linkbuf = NULL;
  729. sc->tx.txqsetup |= 1<<qnum;
  730. }
  731. return &sc->tx.txq[qnum];
  732. }
  733. static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
  734. {
  735. int qnum;
  736. switch (qtype) {
  737. case ATH9K_TX_QUEUE_DATA:
  738. if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
  739. DPRINTF(sc, ATH_DBG_FATAL,
  740. "HAL AC %u out of range, max %zu!\n",
  741. haltype, ARRAY_SIZE(sc->tx.hwq_map));
  742. return -1;
  743. }
  744. qnum = sc->tx.hwq_map[haltype];
  745. break;
  746. case ATH9K_TX_QUEUE_BEACON:
  747. qnum = sc->beacon.beaconq;
  748. break;
  749. case ATH9K_TX_QUEUE_CAB:
  750. qnum = sc->beacon.cabq->axq_qnum;
  751. break;
  752. default:
  753. qnum = -1;
  754. }
  755. return qnum;
  756. }
  757. struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
  758. {
  759. struct ath_txq *txq = NULL;
  760. int qnum;
  761. qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
  762. txq = &sc->tx.txq[qnum];
  763. spin_lock_bh(&txq->axq_lock);
  764. if (txq->axq_depth >= (ATH_TXBUF - 20)) {
  765. DPRINTF(sc, ATH_DBG_XMIT,
  766. "TX queue: %d is full, depth: %d\n",
  767. qnum, txq->axq_depth);
  768. ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
  769. txq->stopped = 1;
  770. spin_unlock_bh(&txq->axq_lock);
  771. return NULL;
  772. }
  773. spin_unlock_bh(&txq->axq_lock);
  774. return txq;
  775. }
  776. int ath_txq_update(struct ath_softc *sc, int qnum,
  777. struct ath9k_tx_queue_info *qinfo)
  778. {
  779. struct ath_hw *ah = sc->sc_ah;
  780. int error = 0;
  781. struct ath9k_tx_queue_info qi;
  782. if (qnum == sc->beacon.beaconq) {
  783. /*
  784. * XXX: for beacon queue, we just save the parameter.
  785. * It will be picked up by ath_beaconq_config when
  786. * it's necessary.
  787. */
  788. sc->beacon.beacon_qi = *qinfo;
  789. return 0;
  790. }
  791. ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
  792. ath9k_hw_get_txq_props(ah, qnum, &qi);
  793. qi.tqi_aifs = qinfo->tqi_aifs;
  794. qi.tqi_cwmin = qinfo->tqi_cwmin;
  795. qi.tqi_cwmax = qinfo->tqi_cwmax;
  796. qi.tqi_burstTime = qinfo->tqi_burstTime;
  797. qi.tqi_readyTime = qinfo->tqi_readyTime;
  798. if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
  799. DPRINTF(sc, ATH_DBG_FATAL,
  800. "Unable to update hardware queue %u!\n", qnum);
  801. error = -EIO;
  802. } else {
  803. ath9k_hw_resettxqueue(ah, qnum);
  804. }
  805. return error;
  806. }
  807. int ath_cabq_update(struct ath_softc *sc)
  808. {
  809. struct ath9k_tx_queue_info qi;
  810. int qnum = sc->beacon.cabq->axq_qnum;
  811. ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
  812. /*
  813. * Ensure the readytime % is within the bounds.
  814. */
  815. if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
  816. sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
  817. else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
  818. sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
  819. qi.tqi_readyTime = (sc->beacon_interval *
  820. sc->config.cabqReadytime) / 100;
  821. ath_txq_update(sc, qnum, &qi);
  822. return 0;
  823. }
  824. /*
  825. * Drain a given TX queue (could be Beacon or Data)
  826. *
  827. * This assumes output has been stopped and
  828. * we do not need to block ath_tx_tasklet.
  829. */
  830. void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
  831. {
  832. struct ath_buf *bf, *lastbf;
  833. struct list_head bf_head;
  834. INIT_LIST_HEAD(&bf_head);
  835. for (;;) {
  836. spin_lock_bh(&txq->axq_lock);
  837. if (list_empty(&txq->axq_q)) {
  838. txq->axq_link = NULL;
  839. txq->axq_linkbuf = NULL;
  840. spin_unlock_bh(&txq->axq_lock);
  841. break;
  842. }
  843. bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
  844. if (bf->bf_stale) {
  845. list_del(&bf->list);
  846. spin_unlock_bh(&txq->axq_lock);
  847. spin_lock_bh(&sc->tx.txbuflock);
  848. list_add_tail(&bf->list, &sc->tx.txbuf);
  849. spin_unlock_bh(&sc->tx.txbuflock);
  850. continue;
  851. }
  852. lastbf = bf->bf_lastbf;
  853. if (!retry_tx)
  854. lastbf->bf_desc->ds_txstat.ts_flags =
  855. ATH9K_TX_SW_ABORTED;
  856. /* remove ath_buf's of the same mpdu from txq */
  857. list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
  858. txq->axq_depth--;
  859. spin_unlock_bh(&txq->axq_lock);
  860. if (bf_isampdu(bf))
  861. ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
  862. else
  863. ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
  864. }
  865. /* flush any pending frames if aggregation is enabled */
  866. if (sc->sc_flags & SC_OP_TXAGGR) {
  867. if (!retry_tx) {
  868. spin_lock_bh(&txq->axq_lock);
  869. ath_txq_drain_pending_buffers(sc, txq);
  870. spin_unlock_bh(&txq->axq_lock);
  871. }
  872. }
  873. }
  874. void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
  875. {
  876. struct ath_hw *ah = sc->sc_ah;
  877. struct ath_txq *txq;
  878. int i, npend = 0;
  879. if (sc->sc_flags & SC_OP_INVALID)
  880. return;
  881. /* Stop beacon queue */
  882. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  883. /* Stop data queues */
  884. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  885. if (ATH_TXQ_SETUP(sc, i)) {
  886. txq = &sc->tx.txq[i];
  887. ath9k_hw_stoptxdma(ah, txq->axq_qnum);
  888. npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
  889. }
  890. }
  891. if (npend) {
  892. int r;
  893. DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
  894. spin_lock_bh(&sc->sc_resetlock);
  895. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
  896. if (r)
  897. DPRINTF(sc, ATH_DBG_FATAL,
  898. "Unable to reset hardware; reset status %d\n",
  899. r);
  900. spin_unlock_bh(&sc->sc_resetlock);
  901. }
  902. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  903. if (ATH_TXQ_SETUP(sc, i))
  904. ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
  905. }
  906. }
  907. void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
  908. {
  909. ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
  910. sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
  911. }
  912. void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
  913. {
  914. struct ath_atx_ac *ac;
  915. struct ath_atx_tid *tid;
  916. if (list_empty(&txq->axq_acq))
  917. return;
  918. ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
  919. list_del(&ac->list);
  920. ac->sched = false;
  921. do {
  922. if (list_empty(&ac->tid_q))
  923. return;
  924. tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
  925. list_del(&tid->list);
  926. tid->sched = false;
  927. if (tid->paused)
  928. continue;
  929. if ((txq->axq_depth % 2) == 0)
  930. ath_tx_sched_aggr(sc, txq, tid);
  931. /*
  932. * add tid to round-robin queue if more frames
  933. * are pending for the tid
  934. */
  935. if (!list_empty(&tid->buf_q))
  936. ath_tx_queue_tid(txq, tid);
  937. break;
  938. } while (!list_empty(&ac->tid_q));
  939. if (!list_empty(&ac->tid_q)) {
  940. if (!ac->sched) {
  941. ac->sched = true;
  942. list_add_tail(&ac->list, &txq->axq_acq);
  943. }
  944. }
  945. }
  946. int ath_tx_setup(struct ath_softc *sc, int haltype)
  947. {
  948. struct ath_txq *txq;
  949. if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
  950. DPRINTF(sc, ATH_DBG_FATAL,
  951. "HAL AC %u out of range, max %zu!\n",
  952. haltype, ARRAY_SIZE(sc->tx.hwq_map));
  953. return 0;
  954. }
  955. txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
  956. if (txq != NULL) {
  957. sc->tx.hwq_map[haltype] = txq->axq_qnum;
  958. return 1;
  959. } else
  960. return 0;
  961. }
  962. /***********/
  963. /* TX, DMA */
  964. /***********/
  965. /*
  966. * Insert a chain of ath_buf (descriptors) on a txq and
  967. * assume the descriptors are already chained together by caller.
  968. */
  969. static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
  970. struct list_head *head)
  971. {
  972. struct ath_hw *ah = sc->sc_ah;
  973. struct ath_buf *bf;
  974. /*
  975. * Insert the frame on the outbound list and
  976. * pass it on to the hardware.
  977. */
  978. if (list_empty(head))
  979. return;
  980. bf = list_first_entry(head, struct ath_buf, list);
  981. list_splice_tail_init(head, &txq->axq_q);
  982. txq->axq_depth++;
  983. txq->axq_totalqueued++;
  984. txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
  985. DPRINTF(sc, ATH_DBG_QUEUE,
  986. "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
  987. if (txq->axq_link == NULL) {
  988. ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
  989. DPRINTF(sc, ATH_DBG_XMIT,
  990. "TXDP[%u] = %llx (%p)\n",
  991. txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
  992. } else {
  993. *txq->axq_link = bf->bf_daddr;
  994. DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
  995. txq->axq_qnum, txq->axq_link,
  996. ito64(bf->bf_daddr), bf->bf_desc);
  997. }
  998. txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
  999. ath9k_hw_txstart(ah, txq->axq_qnum);
  1000. }
  1001. static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
  1002. {
  1003. struct ath_buf *bf = NULL;
  1004. spin_lock_bh(&sc->tx.txbuflock);
  1005. if (unlikely(list_empty(&sc->tx.txbuf))) {
  1006. spin_unlock_bh(&sc->tx.txbuflock);
  1007. return NULL;
  1008. }
  1009. bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
  1010. list_del(&bf->list);
  1011. spin_unlock_bh(&sc->tx.txbuflock);
  1012. return bf;
  1013. }
  1014. static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
  1015. struct list_head *bf_head,
  1016. struct ath_tx_control *txctl)
  1017. {
  1018. struct ath_buf *bf;
  1019. bf = list_first_entry(bf_head, struct ath_buf, list);
  1020. bf->bf_state.bf_type |= BUF_AMPDU;
  1021. /*
  1022. * Do not queue to h/w when any of the following conditions is true:
  1023. * - there are pending frames in software queue
  1024. * - the TID is currently paused for ADDBA/BAR request
  1025. * - seqno is not within block-ack window
  1026. * - h/w queue depth exceeds low water mark
  1027. */
  1028. if (!list_empty(&tid->buf_q) || tid->paused ||
  1029. !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
  1030. txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
  1031. /*
  1032. * Add this frame to software queue for scheduling later
  1033. * for aggregation.
  1034. */
  1035. list_move_tail(&bf->list, &tid->buf_q);
  1036. ath_tx_queue_tid(txctl->txq, tid);
  1037. return;
  1038. }
  1039. /* Add sub-frame to BAW */
  1040. ath_tx_addto_baw(sc, tid, bf);
  1041. /* Queue to h/w without aggregation */
  1042. bf->bf_nframes = 1;
  1043. bf->bf_lastbf = bf;
  1044. ath_buf_set_rate(sc, bf);
  1045. ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
  1046. }
  1047. static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
  1048. struct ath_atx_tid *tid,
  1049. struct list_head *bf_head)
  1050. {
  1051. struct ath_buf *bf;
  1052. bf = list_first_entry(bf_head, struct ath_buf, list);
  1053. bf->bf_state.bf_type &= ~BUF_AMPDU;
  1054. /* update starting sequence number for subsequent ADDBA request */
  1055. INCR(tid->seq_start, IEEE80211_SEQ_MAX);
  1056. bf->bf_nframes = 1;
  1057. bf->bf_lastbf = bf;
  1058. ath_buf_set_rate(sc, bf);
  1059. ath_tx_txqaddbuf(sc, txq, bf_head);
  1060. }
  1061. static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
  1062. struct list_head *bf_head)
  1063. {
  1064. struct ath_buf *bf;
  1065. bf = list_first_entry(bf_head, struct ath_buf, list);
  1066. bf->bf_lastbf = bf;
  1067. bf->bf_nframes = 1;
  1068. ath_buf_set_rate(sc, bf);
  1069. ath_tx_txqaddbuf(sc, txq, bf_head);
  1070. }
  1071. static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
  1072. {
  1073. struct ieee80211_hdr *hdr;
  1074. enum ath9k_pkt_type htype;
  1075. __le16 fc;
  1076. hdr = (struct ieee80211_hdr *)skb->data;
  1077. fc = hdr->frame_control;
  1078. if (ieee80211_is_beacon(fc))
  1079. htype = ATH9K_PKT_TYPE_BEACON;
  1080. else if (ieee80211_is_probe_resp(fc))
  1081. htype = ATH9K_PKT_TYPE_PROBE_RESP;
  1082. else if (ieee80211_is_atim(fc))
  1083. htype = ATH9K_PKT_TYPE_ATIM;
  1084. else if (ieee80211_is_pspoll(fc))
  1085. htype = ATH9K_PKT_TYPE_PSPOLL;
  1086. else
  1087. htype = ATH9K_PKT_TYPE_NORMAL;
  1088. return htype;
  1089. }
  1090. static bool is_pae(struct sk_buff *skb)
  1091. {
  1092. struct ieee80211_hdr *hdr;
  1093. __le16 fc;
  1094. hdr = (struct ieee80211_hdr *)skb->data;
  1095. fc = hdr->frame_control;
  1096. if (ieee80211_is_data(fc)) {
  1097. if (ieee80211_is_nullfunc(fc) ||
  1098. /* Port Access Entity (IEEE 802.1X) */
  1099. (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
  1100. return true;
  1101. }
  1102. }
  1103. return false;
  1104. }
  1105. static int get_hw_crypto_keytype(struct sk_buff *skb)
  1106. {
  1107. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1108. if (tx_info->control.hw_key) {
  1109. if (tx_info->control.hw_key->alg == ALG_WEP)
  1110. return ATH9K_KEY_TYPE_WEP;
  1111. else if (tx_info->control.hw_key->alg == ALG_TKIP)
  1112. return ATH9K_KEY_TYPE_TKIP;
  1113. else if (tx_info->control.hw_key->alg == ALG_CCMP)
  1114. return ATH9K_KEY_TYPE_AES;
  1115. }
  1116. return ATH9K_KEY_TYPE_CLEAR;
  1117. }
  1118. static void assign_aggr_tid_seqno(struct sk_buff *skb,
  1119. struct ath_buf *bf)
  1120. {
  1121. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1122. struct ieee80211_hdr *hdr;
  1123. struct ath_node *an;
  1124. struct ath_atx_tid *tid;
  1125. __le16 fc;
  1126. u8 *qc;
  1127. if (!tx_info->control.sta)
  1128. return;
  1129. an = (struct ath_node *)tx_info->control.sta->drv_priv;
  1130. hdr = (struct ieee80211_hdr *)skb->data;
  1131. fc = hdr->frame_control;
  1132. if (ieee80211_is_data_qos(fc)) {
  1133. qc = ieee80211_get_qos_ctl(hdr);
  1134. bf->bf_tidno = qc[0] & 0xf;
  1135. }
  1136. /*
  1137. * For HT capable stations, we save tidno for later use.
  1138. * We also override seqno set by upper layer with the one
  1139. * in tx aggregation state.
  1140. *
  1141. * If fragmentation is on, the sequence number is
  1142. * not overridden, since it has been
  1143. * incremented by the fragmentation routine.
  1144. *
  1145. * FIXME: check if the fragmentation threshold exceeds
  1146. * IEEE80211 max.
  1147. */
  1148. tid = ATH_AN_2_TID(an, bf->bf_tidno);
  1149. hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
  1150. IEEE80211_SEQ_SEQ_SHIFT);
  1151. bf->bf_seqno = tid->seq_next;
  1152. INCR(tid->seq_next, IEEE80211_SEQ_MAX);
  1153. }
  1154. static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
  1155. struct ath_txq *txq)
  1156. {
  1157. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1158. int flags = 0;
  1159. flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
  1160. flags |= ATH9K_TXDESC_INTREQ;
  1161. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
  1162. flags |= ATH9K_TXDESC_NOACK;
  1163. return flags;
  1164. }
  1165. /*
  1166. * rix - rate index
  1167. * pktlen - total bytes (delims + data + fcs + pads + pad delims)
  1168. * width - 0 for 20 MHz, 1 for 40 MHz
  1169. * half_gi - to use 4us v/s 3.6 us for symbol time
  1170. */
  1171. static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
  1172. int width, int half_gi, bool shortPreamble)
  1173. {
  1174. const struct ath_rate_table *rate_table = sc->cur_rate_table;
  1175. u32 nbits, nsymbits, duration, nsymbols;
  1176. u8 rc;
  1177. int streams, pktlen;
  1178. pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
  1179. rc = rate_table->info[rix].ratecode;
  1180. /* for legacy rates, use old function to compute packet duration */
  1181. if (!IS_HT_RATE(rc))
  1182. return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
  1183. rix, shortPreamble);
  1184. /* find number of symbols: PLCP + data */
  1185. nbits = (pktlen << 3) + OFDM_PLCP_BITS;
  1186. nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
  1187. nsymbols = (nbits + nsymbits - 1) / nsymbits;
  1188. if (!half_gi)
  1189. duration = SYMBOL_TIME(nsymbols);
  1190. else
  1191. duration = SYMBOL_TIME_HALFGI(nsymbols);
  1192. /* addup duration for legacy/ht training and signal fields */
  1193. streams = HT_RC_2_STREAMS(rc);
  1194. duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
  1195. return duration;
  1196. }
  1197. static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
  1198. {
  1199. const struct ath_rate_table *rt = sc->cur_rate_table;
  1200. struct ath9k_11n_rate_series series[4];
  1201. struct sk_buff *skb;
  1202. struct ieee80211_tx_info *tx_info;
  1203. struct ieee80211_tx_rate *rates;
  1204. struct ieee80211_hdr *hdr;
  1205. int i, flags = 0;
  1206. u8 rix = 0, ctsrate = 0;
  1207. bool is_pspoll;
  1208. memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
  1209. skb = bf->bf_mpdu;
  1210. tx_info = IEEE80211_SKB_CB(skb);
  1211. rates = tx_info->control.rates;
  1212. hdr = (struct ieee80211_hdr *)skb->data;
  1213. is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
  1214. /*
  1215. * We check if Short Preamble is needed for the CTS rate by
  1216. * checking the BSS's global flag.
  1217. * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
  1218. */
  1219. if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
  1220. ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
  1221. rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
  1222. else
  1223. ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
  1224. /*
  1225. * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
  1226. * Check the first rate in the series to decide whether RTS/CTS
  1227. * or CTS-to-self has to be used.
  1228. */
  1229. if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
  1230. flags = ATH9K_TXDESC_CTSENA;
  1231. else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
  1232. flags = ATH9K_TXDESC_RTSENA;
  1233. /* FIXME: Handle aggregation protection */
  1234. if (sc->config.ath_aggr_prot &&
  1235. (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
  1236. flags = ATH9K_TXDESC_RTSENA;
  1237. }
  1238. /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
  1239. if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
  1240. flags &= ~(ATH9K_TXDESC_RTSENA);
  1241. for (i = 0; i < 4; i++) {
  1242. if (!rates[i].count || (rates[i].idx < 0))
  1243. continue;
  1244. rix = rates[i].idx;
  1245. series[i].Tries = rates[i].count;
  1246. series[i].ChSel = sc->tx_chainmask;
  1247. if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
  1248. series[i].Rate = rt->info[rix].ratecode |
  1249. rt->info[rix].short_preamble;
  1250. else
  1251. series[i].Rate = rt->info[rix].ratecode;
  1252. if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
  1253. series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
  1254. if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
  1255. series[i].RateFlags |= ATH9K_RATESERIES_2040;
  1256. if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
  1257. series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
  1258. series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
  1259. (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
  1260. (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
  1261. (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
  1262. }
  1263. /* set dur_update_en for l-sig computation except for PS-Poll frames */
  1264. ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
  1265. bf->bf_lastbf->bf_desc,
  1266. !is_pspoll, ctsrate,
  1267. 0, series, 4, flags);
  1268. if (sc->config.ath_aggr_prot && flags)
  1269. ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
  1270. }
  1271. static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
  1272. struct sk_buff *skb,
  1273. struct ath_tx_control *txctl)
  1274. {
  1275. struct ath_wiphy *aphy = hw->priv;
  1276. struct ath_softc *sc = aphy->sc;
  1277. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1278. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1279. struct ath_tx_info_priv *tx_info_priv;
  1280. int hdrlen;
  1281. __le16 fc;
  1282. tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
  1283. if (unlikely(!tx_info_priv))
  1284. return -ENOMEM;
  1285. tx_info->rate_driver_data[0] = tx_info_priv;
  1286. tx_info_priv->aphy = aphy;
  1287. tx_info_priv->frame_type = txctl->frame_type;
  1288. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  1289. fc = hdr->frame_control;
  1290. ATH_TXBUF_RESET(bf);
  1291. bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
  1292. if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
  1293. bf->bf_state.bf_type |= BUF_HT;
  1294. bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
  1295. bf->bf_keytype = get_hw_crypto_keytype(skb);
  1296. if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
  1297. bf->bf_frmlen += tx_info->control.hw_key->icv_len;
  1298. bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
  1299. } else {
  1300. bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
  1301. }
  1302. if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
  1303. assign_aggr_tid_seqno(skb, bf);
  1304. bf->bf_mpdu = skb;
  1305. bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
  1306. skb->len, DMA_TO_DEVICE);
  1307. if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
  1308. bf->bf_mpdu = NULL;
  1309. kfree(tx_info_priv);
  1310. tx_info->rate_driver_data[0] = NULL;
  1311. DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n");
  1312. return -ENOMEM;
  1313. }
  1314. bf->bf_buf_addr = bf->bf_dmacontext;
  1315. return 0;
  1316. }
  1317. /* FIXME: tx power */
  1318. static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
  1319. struct ath_tx_control *txctl)
  1320. {
  1321. struct sk_buff *skb = bf->bf_mpdu;
  1322. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1323. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1324. struct ath_node *an = NULL;
  1325. struct list_head bf_head;
  1326. struct ath_desc *ds;
  1327. struct ath_atx_tid *tid;
  1328. struct ath_hw *ah = sc->sc_ah;
  1329. int frm_type;
  1330. __le16 fc;
  1331. frm_type = get_hw_packet_type(skb);
  1332. fc = hdr->frame_control;
  1333. INIT_LIST_HEAD(&bf_head);
  1334. list_add_tail(&bf->list, &bf_head);
  1335. ds = bf->bf_desc;
  1336. ds->ds_link = 0;
  1337. ds->ds_data = bf->bf_buf_addr;
  1338. ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
  1339. bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
  1340. ath9k_hw_filltxdesc(ah, ds,
  1341. skb->len, /* segment length */
  1342. true, /* first segment */
  1343. true, /* last segment */
  1344. ds); /* first descriptor */
  1345. spin_lock_bh(&txctl->txq->axq_lock);
  1346. if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
  1347. tx_info->control.sta) {
  1348. an = (struct ath_node *)tx_info->control.sta->drv_priv;
  1349. tid = ATH_AN_2_TID(an, bf->bf_tidno);
  1350. if (!ieee80211_is_data_qos(fc)) {
  1351. ath_tx_send_normal(sc, txctl->txq, &bf_head);
  1352. goto tx_done;
  1353. }
  1354. if (ath_aggr_query(sc, an, bf->bf_tidno)) {
  1355. /*
  1356. * Try aggregation if it's a unicast data frame
  1357. * and the destination is HT capable.
  1358. */
  1359. ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
  1360. } else {
  1361. /*
  1362. * Send this frame as regular when ADDBA
  1363. * exchange is neither complete nor pending.
  1364. */
  1365. ath_tx_send_ht_normal(sc, txctl->txq,
  1366. tid, &bf_head);
  1367. }
  1368. } else {
  1369. ath_tx_send_normal(sc, txctl->txq, &bf_head);
  1370. }
  1371. tx_done:
  1372. spin_unlock_bh(&txctl->txq->axq_lock);
  1373. }
  1374. /* Upon failure caller should free skb */
  1375. int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
  1376. struct ath_tx_control *txctl)
  1377. {
  1378. struct ath_wiphy *aphy = hw->priv;
  1379. struct ath_softc *sc = aphy->sc;
  1380. struct ath_buf *bf;
  1381. int r;
  1382. bf = ath_tx_get_buffer(sc);
  1383. if (!bf) {
  1384. DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
  1385. return -1;
  1386. }
  1387. r = ath_tx_setup_buffer(hw, bf, skb, txctl);
  1388. if (unlikely(r)) {
  1389. struct ath_txq *txq = txctl->txq;
  1390. DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
  1391. /* upon ath_tx_processq() this TX queue will be resumed, we
  1392. * guarantee this will happen by knowing beforehand that
  1393. * we will at least have to run TX completionon one buffer
  1394. * on the queue */
  1395. spin_lock_bh(&txq->axq_lock);
  1396. if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
  1397. ieee80211_stop_queue(sc->hw,
  1398. skb_get_queue_mapping(skb));
  1399. txq->stopped = 1;
  1400. }
  1401. spin_unlock_bh(&txq->axq_lock);
  1402. spin_lock_bh(&sc->tx.txbuflock);
  1403. list_add_tail(&bf->list, &sc->tx.txbuf);
  1404. spin_unlock_bh(&sc->tx.txbuflock);
  1405. return r;
  1406. }
  1407. ath_tx_start_dma(sc, bf, txctl);
  1408. return 0;
  1409. }
  1410. void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
  1411. {
  1412. struct ath_wiphy *aphy = hw->priv;
  1413. struct ath_softc *sc = aphy->sc;
  1414. int hdrlen, padsize;
  1415. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1416. struct ath_tx_control txctl;
  1417. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1418. /*
  1419. * As a temporary workaround, assign seq# here; this will likely need
  1420. * to be cleaned up to work better with Beacon transmission and virtual
  1421. * BSSes.
  1422. */
  1423. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1424. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1425. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1426. sc->tx.seq_no += 0x10;
  1427. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1428. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1429. }
  1430. /* Add the padding after the header if this is not already done */
  1431. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  1432. if (hdrlen & 3) {
  1433. padsize = hdrlen % 4;
  1434. if (skb_headroom(skb) < padsize) {
  1435. DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
  1436. dev_kfree_skb_any(skb);
  1437. return;
  1438. }
  1439. skb_push(skb, padsize);
  1440. memmove(skb->data, skb->data + padsize, hdrlen);
  1441. }
  1442. txctl.txq = sc->beacon.cabq;
  1443. DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
  1444. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1445. DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
  1446. goto exit;
  1447. }
  1448. return;
  1449. exit:
  1450. dev_kfree_skb_any(skb);
  1451. }
  1452. /*****************/
  1453. /* TX Completion */
  1454. /*****************/
  1455. static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  1456. int tx_flags)
  1457. {
  1458. struct ieee80211_hw *hw = sc->hw;
  1459. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1460. struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
  1461. int hdrlen, padsize;
  1462. int frame_type = ATH9K_NOT_INTERNAL;
  1463. DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
  1464. if (tx_info_priv) {
  1465. hw = tx_info_priv->aphy->hw;
  1466. frame_type = tx_info_priv->frame_type;
  1467. }
  1468. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
  1469. tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
  1470. kfree(tx_info_priv);
  1471. tx_info->rate_driver_data[0] = NULL;
  1472. }
  1473. if (tx_flags & ATH_TX_BAR)
  1474. tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  1475. if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
  1476. /* Frame was ACKed */
  1477. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  1478. }
  1479. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  1480. padsize = hdrlen & 3;
  1481. if (padsize && hdrlen >= 24) {
  1482. /*
  1483. * Remove MAC header padding before giving the frame back to
  1484. * mac80211.
  1485. */
  1486. memmove(skb->data + padsize, skb->data, hdrlen);
  1487. skb_pull(skb, padsize);
  1488. }
  1489. if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
  1490. sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
  1491. DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having "
  1492. "received TX status (0x%x)\n",
  1493. sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
  1494. SC_OP_WAIT_FOR_CAB |
  1495. SC_OP_WAIT_FOR_PSPOLL_DATA |
  1496. SC_OP_WAIT_FOR_TX_ACK));
  1497. }
  1498. if (frame_type == ATH9K_NOT_INTERNAL)
  1499. ieee80211_tx_status(hw, skb);
  1500. else
  1501. ath9k_tx_status(hw, skb);
  1502. }
  1503. static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
  1504. struct list_head *bf_q,
  1505. int txok, int sendbar)
  1506. {
  1507. struct sk_buff *skb = bf->bf_mpdu;
  1508. unsigned long flags;
  1509. int tx_flags = 0;
  1510. if (sendbar)
  1511. tx_flags = ATH_TX_BAR;
  1512. if (!txok) {
  1513. tx_flags |= ATH_TX_ERROR;
  1514. if (bf_isxretried(bf))
  1515. tx_flags |= ATH_TX_XRETRY;
  1516. }
  1517. dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
  1518. ath_tx_complete(sc, skb, tx_flags);
  1519. /*
  1520. * Return the list of ath_buf of this mpdu to free queue
  1521. */
  1522. spin_lock_irqsave(&sc->tx.txbuflock, flags);
  1523. list_splice_tail_init(bf_q, &sc->tx.txbuf);
  1524. spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
  1525. }
  1526. static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
  1527. int txok)
  1528. {
  1529. struct ath_buf *bf_last = bf->bf_lastbf;
  1530. struct ath_desc *ds = bf_last->bf_desc;
  1531. u16 seq_st = 0;
  1532. u32 ba[WME_BA_BMP_SIZE >> 5];
  1533. int ba_index;
  1534. int nbad = 0;
  1535. int isaggr = 0;
  1536. if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
  1537. return 0;
  1538. isaggr = bf_isaggr(bf);
  1539. if (isaggr) {
  1540. seq_st = ATH_DS_BA_SEQ(ds);
  1541. memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
  1542. }
  1543. while (bf) {
  1544. ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
  1545. if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
  1546. nbad++;
  1547. bf = bf->bf_next;
  1548. }
  1549. return nbad;
  1550. }
  1551. static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
  1552. int nbad, int txok, bool update_rc)
  1553. {
  1554. struct sk_buff *skb = bf->bf_mpdu;
  1555. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1556. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1557. struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
  1558. struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
  1559. u8 i, tx_rateindex;
  1560. if (txok)
  1561. tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
  1562. tx_rateindex = ds->ds_txstat.ts_rateindex;
  1563. WARN_ON(tx_rateindex >= hw->max_rates);
  1564. tx_info_priv->update_rc = update_rc;
  1565. if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
  1566. tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
  1567. if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
  1568. (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
  1569. if (ieee80211_is_data(hdr->frame_control)) {
  1570. memcpy(&tx_info_priv->tx, &ds->ds_txstat,
  1571. sizeof(tx_info_priv->tx));
  1572. tx_info_priv->n_frames = bf->bf_nframes;
  1573. tx_info_priv->n_bad_frames = nbad;
  1574. }
  1575. }
  1576. for (i = tx_rateindex + 1; i < hw->max_rates; i++)
  1577. tx_info->status.rates[i].count = 0;
  1578. tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
  1579. }
  1580. static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
  1581. {
  1582. int qnum;
  1583. spin_lock_bh(&txq->axq_lock);
  1584. if (txq->stopped &&
  1585. sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
  1586. qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
  1587. if (qnum != -1) {
  1588. ieee80211_wake_queue(sc->hw, qnum);
  1589. txq->stopped = 0;
  1590. }
  1591. }
  1592. spin_unlock_bh(&txq->axq_lock);
  1593. }
  1594. static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
  1595. {
  1596. struct ath_hw *ah = sc->sc_ah;
  1597. struct ath_buf *bf, *lastbf, *bf_held = NULL;
  1598. struct list_head bf_head;
  1599. struct ath_desc *ds;
  1600. int txok;
  1601. int status;
  1602. DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
  1603. txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
  1604. txq->axq_link);
  1605. for (;;) {
  1606. spin_lock_bh(&txq->axq_lock);
  1607. if (list_empty(&txq->axq_q)) {
  1608. txq->axq_link = NULL;
  1609. txq->axq_linkbuf = NULL;
  1610. spin_unlock_bh(&txq->axq_lock);
  1611. break;
  1612. }
  1613. bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
  1614. /*
  1615. * There is a race condition that a BH gets scheduled
  1616. * after sw writes TxE and before hw re-load the last
  1617. * descriptor to get the newly chained one.
  1618. * Software must keep the last DONE descriptor as a
  1619. * holding descriptor - software does so by marking
  1620. * it with the STALE flag.
  1621. */
  1622. bf_held = NULL;
  1623. if (bf->bf_stale) {
  1624. bf_held = bf;
  1625. if (list_is_last(&bf_held->list, &txq->axq_q)) {
  1626. txq->axq_link = NULL;
  1627. txq->axq_linkbuf = NULL;
  1628. spin_unlock_bh(&txq->axq_lock);
  1629. /*
  1630. * The holding descriptor is the last
  1631. * descriptor in queue. It's safe to remove
  1632. * the last holding descriptor in BH context.
  1633. */
  1634. spin_lock_bh(&sc->tx.txbuflock);
  1635. list_move_tail(&bf_held->list, &sc->tx.txbuf);
  1636. spin_unlock_bh(&sc->tx.txbuflock);
  1637. break;
  1638. } else {
  1639. bf = list_entry(bf_held->list.next,
  1640. struct ath_buf, list);
  1641. }
  1642. }
  1643. lastbf = bf->bf_lastbf;
  1644. ds = lastbf->bf_desc;
  1645. status = ath9k_hw_txprocdesc(ah, ds);
  1646. if (status == -EINPROGRESS) {
  1647. spin_unlock_bh(&txq->axq_lock);
  1648. break;
  1649. }
  1650. if (bf->bf_desc == txq->axq_lastdsWithCTS)
  1651. txq->axq_lastdsWithCTS = NULL;
  1652. if (ds == txq->axq_gatingds)
  1653. txq->axq_gatingds = NULL;
  1654. /*
  1655. * Remove ath_buf's of the same transmit unit from txq,
  1656. * however leave the last descriptor back as the holding
  1657. * descriptor for hw.
  1658. */
  1659. lastbf->bf_stale = true;
  1660. INIT_LIST_HEAD(&bf_head);
  1661. if (!list_is_singular(&lastbf->list))
  1662. list_cut_position(&bf_head,
  1663. &txq->axq_q, lastbf->list.prev);
  1664. txq->axq_depth--;
  1665. if (bf_isaggr(bf))
  1666. txq->axq_aggr_depth--;
  1667. txok = (ds->ds_txstat.ts_status == 0);
  1668. spin_unlock_bh(&txq->axq_lock);
  1669. if (bf_held) {
  1670. spin_lock_bh(&sc->tx.txbuflock);
  1671. list_move_tail(&bf_held->list, &sc->tx.txbuf);
  1672. spin_unlock_bh(&sc->tx.txbuflock);
  1673. }
  1674. if (!bf_isampdu(bf)) {
  1675. /*
  1676. * This frame is sent out as a single frame.
  1677. * Use hardware retry status for this frame.
  1678. */
  1679. bf->bf_retries = ds->ds_txstat.ts_longretry;
  1680. if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
  1681. bf->bf_state.bf_type |= BUF_XRETRY;
  1682. ath_tx_rc_status(bf, ds, 0, txok, true);
  1683. }
  1684. if (bf_isampdu(bf))
  1685. ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
  1686. else
  1687. ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
  1688. ath_wake_mac80211_queue(sc, txq);
  1689. spin_lock_bh(&txq->axq_lock);
  1690. if (sc->sc_flags & SC_OP_TXAGGR)
  1691. ath_txq_schedule(sc, txq);
  1692. spin_unlock_bh(&txq->axq_lock);
  1693. }
  1694. }
  1695. void ath_tx_tasklet(struct ath_softc *sc)
  1696. {
  1697. int i;
  1698. u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
  1699. ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
  1700. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1701. if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
  1702. ath_tx_processq(sc, &sc->tx.txq[i]);
  1703. }
  1704. }
  1705. /*****************/
  1706. /* Init, Cleanup */
  1707. /*****************/
  1708. int ath_tx_init(struct ath_softc *sc, int nbufs)
  1709. {
  1710. int error = 0;
  1711. spin_lock_init(&sc->tx.txbuflock);
  1712. error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
  1713. "tx", nbufs, 1);
  1714. if (error != 0) {
  1715. DPRINTF(sc, ATH_DBG_FATAL,
  1716. "Failed to allocate tx descriptors: %d\n", error);
  1717. goto err;
  1718. }
  1719. error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
  1720. "beacon", ATH_BCBUF, 1);
  1721. if (error != 0) {
  1722. DPRINTF(sc, ATH_DBG_FATAL,
  1723. "Failed to allocate beacon descriptors: %d\n", error);
  1724. goto err;
  1725. }
  1726. err:
  1727. if (error != 0)
  1728. ath_tx_cleanup(sc);
  1729. return error;
  1730. }
  1731. void ath_tx_cleanup(struct ath_softc *sc)
  1732. {
  1733. if (sc->beacon.bdma.dd_desc_len != 0)
  1734. ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
  1735. if (sc->tx.txdma.dd_desc_len != 0)
  1736. ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
  1737. }
  1738. void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
  1739. {
  1740. struct ath_atx_tid *tid;
  1741. struct ath_atx_ac *ac;
  1742. int tidno, acno;
  1743. for (tidno = 0, tid = &an->tid[tidno];
  1744. tidno < WME_NUM_TID;
  1745. tidno++, tid++) {
  1746. tid->an = an;
  1747. tid->tidno = tidno;
  1748. tid->seq_start = tid->seq_next = 0;
  1749. tid->baw_size = WME_MAX_BA;
  1750. tid->baw_head = tid->baw_tail = 0;
  1751. tid->sched = false;
  1752. tid->paused = false;
  1753. tid->state &= ~AGGR_CLEANUP;
  1754. INIT_LIST_HEAD(&tid->buf_q);
  1755. acno = TID_TO_WME_AC(tidno);
  1756. tid->ac = &an->ac[acno];
  1757. tid->state &= ~AGGR_ADDBA_COMPLETE;
  1758. tid->state &= ~AGGR_ADDBA_PROGRESS;
  1759. tid->addba_exchangeattempts = 0;
  1760. }
  1761. for (acno = 0, ac = &an->ac[acno];
  1762. acno < WME_NUM_AC; acno++, ac++) {
  1763. ac->sched = false;
  1764. INIT_LIST_HEAD(&ac->tid_q);
  1765. switch (acno) {
  1766. case WME_AC_BE:
  1767. ac->qnum = ath_tx_get_qnum(sc,
  1768. ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
  1769. break;
  1770. case WME_AC_BK:
  1771. ac->qnum = ath_tx_get_qnum(sc,
  1772. ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
  1773. break;
  1774. case WME_AC_VI:
  1775. ac->qnum = ath_tx_get_qnum(sc,
  1776. ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
  1777. break;
  1778. case WME_AC_VO:
  1779. ac->qnum = ath_tx_get_qnum(sc,
  1780. ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
  1781. break;
  1782. }
  1783. }
  1784. }
  1785. void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
  1786. {
  1787. int i;
  1788. struct ath_atx_ac *ac, *ac_tmp;
  1789. struct ath_atx_tid *tid, *tid_tmp;
  1790. struct ath_txq *txq;
  1791. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1792. if (ATH_TXQ_SETUP(sc, i)) {
  1793. txq = &sc->tx.txq[i];
  1794. spin_lock(&txq->axq_lock);
  1795. list_for_each_entry_safe(ac,
  1796. ac_tmp, &txq->axq_acq, list) {
  1797. tid = list_first_entry(&ac->tid_q,
  1798. struct ath_atx_tid, list);
  1799. if (tid && tid->an != an)
  1800. continue;
  1801. list_del(&ac->list);
  1802. ac->sched = false;
  1803. list_for_each_entry_safe(tid,
  1804. tid_tmp, &ac->tid_q, list) {
  1805. list_del(&tid->list);
  1806. tid->sched = false;
  1807. ath_tid_drain(sc, txq, tid);
  1808. tid->state &= ~AGGR_ADDBA_COMPLETE;
  1809. tid->addba_exchangeattempts = 0;
  1810. tid->state &= ~AGGR_CLEANUP;
  1811. }
  1812. }
  1813. spin_unlock(&txq->axq_lock);
  1814. }
  1815. }
  1816. }