netxen_nic_init.c 37 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void
  47. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  48. struct nx_host_rds_ring *rds_ring);
  49. static void crb_addr_transform_setup(void)
  50. {
  51. crb_addr_transform(XDMA);
  52. crb_addr_transform(TIMR);
  53. crb_addr_transform(SRE);
  54. crb_addr_transform(SQN3);
  55. crb_addr_transform(SQN2);
  56. crb_addr_transform(SQN1);
  57. crb_addr_transform(SQN0);
  58. crb_addr_transform(SQS3);
  59. crb_addr_transform(SQS2);
  60. crb_addr_transform(SQS1);
  61. crb_addr_transform(SQS0);
  62. crb_addr_transform(RPMX7);
  63. crb_addr_transform(RPMX6);
  64. crb_addr_transform(RPMX5);
  65. crb_addr_transform(RPMX4);
  66. crb_addr_transform(RPMX3);
  67. crb_addr_transform(RPMX2);
  68. crb_addr_transform(RPMX1);
  69. crb_addr_transform(RPMX0);
  70. crb_addr_transform(ROMUSB);
  71. crb_addr_transform(SN);
  72. crb_addr_transform(QMN);
  73. crb_addr_transform(QMS);
  74. crb_addr_transform(PGNI);
  75. crb_addr_transform(PGND);
  76. crb_addr_transform(PGN3);
  77. crb_addr_transform(PGN2);
  78. crb_addr_transform(PGN1);
  79. crb_addr_transform(PGN0);
  80. crb_addr_transform(PGSI);
  81. crb_addr_transform(PGSD);
  82. crb_addr_transform(PGS3);
  83. crb_addr_transform(PGS2);
  84. crb_addr_transform(PGS1);
  85. crb_addr_transform(PGS0);
  86. crb_addr_transform(PS);
  87. crb_addr_transform(PH);
  88. crb_addr_transform(NIU);
  89. crb_addr_transform(I2Q);
  90. crb_addr_transform(EG);
  91. crb_addr_transform(MN);
  92. crb_addr_transform(MS);
  93. crb_addr_transform(CAS2);
  94. crb_addr_transform(CAS1);
  95. crb_addr_transform(CAS0);
  96. crb_addr_transform(CAM);
  97. crb_addr_transform(C2C1);
  98. crb_addr_transform(C2C0);
  99. crb_addr_transform(SMB);
  100. crb_addr_transform(OCM0);
  101. crb_addr_transform(I2C0);
  102. }
  103. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  104. {
  105. struct netxen_recv_context *recv_ctx;
  106. struct nx_host_rds_ring *rds_ring;
  107. struct netxen_rx_buffer *rx_buf;
  108. int i, ring;
  109. recv_ctx = &adapter->recv_ctx;
  110. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  111. rds_ring = &recv_ctx->rds_rings[ring];
  112. for (i = 0; i < rds_ring->num_desc; ++i) {
  113. rx_buf = &(rds_ring->rx_buf_arr[i]);
  114. if (rx_buf->state == NETXEN_BUFFER_FREE)
  115. continue;
  116. pci_unmap_single(adapter->pdev,
  117. rx_buf->dma,
  118. rds_ring->dma_size,
  119. PCI_DMA_FROMDEVICE);
  120. if (rx_buf->skb != NULL)
  121. dev_kfree_skb_any(rx_buf->skb);
  122. }
  123. }
  124. }
  125. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  126. {
  127. struct netxen_cmd_buffer *cmd_buf;
  128. struct netxen_skb_frag *buffrag;
  129. int i, j;
  130. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  131. cmd_buf = tx_ring->cmd_buf_arr;
  132. for (i = 0; i < tx_ring->num_desc; i++) {
  133. buffrag = cmd_buf->frag_array;
  134. if (buffrag->dma) {
  135. pci_unmap_single(adapter->pdev, buffrag->dma,
  136. buffrag->length, PCI_DMA_TODEVICE);
  137. buffrag->dma = 0ULL;
  138. }
  139. for (j = 0; j < cmd_buf->frag_count; j++) {
  140. buffrag++;
  141. if (buffrag->dma) {
  142. pci_unmap_page(adapter->pdev, buffrag->dma,
  143. buffrag->length,
  144. PCI_DMA_TODEVICE);
  145. buffrag->dma = 0ULL;
  146. }
  147. }
  148. if (cmd_buf->skb) {
  149. dev_kfree_skb_any(cmd_buf->skb);
  150. cmd_buf->skb = NULL;
  151. }
  152. cmd_buf++;
  153. }
  154. }
  155. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  156. {
  157. struct netxen_recv_context *recv_ctx;
  158. struct nx_host_rds_ring *rds_ring;
  159. struct nx_host_tx_ring *tx_ring;
  160. int ring;
  161. recv_ctx = &adapter->recv_ctx;
  162. if (recv_ctx->rds_rings == NULL)
  163. goto skip_rds;
  164. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  165. rds_ring = &recv_ctx->rds_rings[ring];
  166. vfree(rds_ring->rx_buf_arr);
  167. rds_ring->rx_buf_arr = NULL;
  168. }
  169. kfree(recv_ctx->rds_rings);
  170. skip_rds:
  171. if (adapter->tx_ring == NULL)
  172. return;
  173. tx_ring = adapter->tx_ring;
  174. vfree(tx_ring->cmd_buf_arr);
  175. }
  176. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  177. {
  178. struct netxen_recv_context *recv_ctx;
  179. struct nx_host_rds_ring *rds_ring;
  180. struct nx_host_sds_ring *sds_ring;
  181. struct nx_host_tx_ring *tx_ring;
  182. struct netxen_rx_buffer *rx_buf;
  183. int ring, i, size;
  184. struct netxen_cmd_buffer *cmd_buf_arr;
  185. struct net_device *netdev = adapter->netdev;
  186. struct pci_dev *pdev = adapter->pdev;
  187. size = sizeof(struct nx_host_tx_ring);
  188. tx_ring = kzalloc(size, GFP_KERNEL);
  189. if (tx_ring == NULL) {
  190. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  191. netdev->name);
  192. return -ENOMEM;
  193. }
  194. adapter->tx_ring = tx_ring;
  195. tx_ring->num_desc = adapter->num_txd;
  196. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  197. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  198. if (cmd_buf_arr == NULL) {
  199. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  200. netdev->name);
  201. return -ENOMEM;
  202. }
  203. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  204. tx_ring->cmd_buf_arr = cmd_buf_arr;
  205. recv_ctx = &adapter->recv_ctx;
  206. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  207. rds_ring = kzalloc(size, GFP_KERNEL);
  208. if (rds_ring == NULL) {
  209. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  210. netdev->name);
  211. return -ENOMEM;
  212. }
  213. recv_ctx->rds_rings = rds_ring;
  214. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  215. rds_ring = &recv_ctx->rds_rings[ring];
  216. switch (ring) {
  217. case RCV_RING_NORMAL:
  218. rds_ring->num_desc = adapter->num_rxd;
  219. if (adapter->ahw.cut_through) {
  220. rds_ring->dma_size =
  221. NX_CT_DEFAULT_RX_BUF_LEN;
  222. rds_ring->skb_size =
  223. NX_CT_DEFAULT_RX_BUF_LEN;
  224. } else {
  225. rds_ring->dma_size = RX_DMA_MAP_LEN;
  226. rds_ring->skb_size =
  227. MAX_RX_BUFFER_LENGTH;
  228. }
  229. break;
  230. case RCV_RING_JUMBO:
  231. rds_ring->num_desc = adapter->num_jumbo_rxd;
  232. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  233. rds_ring->dma_size =
  234. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  235. else
  236. rds_ring->dma_size =
  237. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  238. rds_ring->skb_size =
  239. rds_ring->dma_size + NET_IP_ALIGN;
  240. break;
  241. case RCV_RING_LRO:
  242. rds_ring->num_desc = adapter->num_lro_rxd;
  243. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  244. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  245. break;
  246. }
  247. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  248. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  249. if (rds_ring->rx_buf_arr == NULL) {
  250. printk(KERN_ERR "%s: Failed to allocate "
  251. "rx buffer ring %d\n",
  252. netdev->name, ring);
  253. /* free whatever was already allocated */
  254. goto err_out;
  255. }
  256. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  257. INIT_LIST_HEAD(&rds_ring->free_list);
  258. /*
  259. * Now go through all of them, set reference handles
  260. * and put them in the queues.
  261. */
  262. rx_buf = rds_ring->rx_buf_arr;
  263. for (i = 0; i < rds_ring->num_desc; i++) {
  264. list_add_tail(&rx_buf->list,
  265. &rds_ring->free_list);
  266. rx_buf->ref_handle = i;
  267. rx_buf->state = NETXEN_BUFFER_FREE;
  268. rx_buf++;
  269. }
  270. spin_lock_init(&rds_ring->lock);
  271. }
  272. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  273. sds_ring = &recv_ctx->sds_rings[ring];
  274. sds_ring->irq = adapter->msix_entries[ring].vector;
  275. sds_ring->adapter = adapter;
  276. sds_ring->num_desc = adapter->num_rxd;
  277. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  278. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  279. }
  280. return 0;
  281. err_out:
  282. netxen_free_sw_resources(adapter);
  283. return -ENOMEM;
  284. }
  285. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  286. {
  287. adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
  288. adapter->set_multi = netxen_p2_nic_set_multi;
  289. switch (adapter->ahw.port_type) {
  290. case NETXEN_NIC_GBE:
  291. adapter->enable_phy_interrupts =
  292. netxen_niu_gbe_enable_phy_interrupts;
  293. adapter->disable_phy_interrupts =
  294. netxen_niu_gbe_disable_phy_interrupts;
  295. adapter->set_mtu = netxen_nic_set_mtu_gb;
  296. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  297. adapter->phy_read = netxen_niu_gbe_phy_read;
  298. adapter->phy_write = netxen_niu_gbe_phy_write;
  299. adapter->init_port = netxen_niu_gbe_init_port;
  300. adapter->stop_port = netxen_niu_disable_gbe_port;
  301. break;
  302. case NETXEN_NIC_XGBE:
  303. adapter->enable_phy_interrupts =
  304. netxen_niu_xgbe_enable_phy_interrupts;
  305. adapter->disable_phy_interrupts =
  306. netxen_niu_xgbe_disable_phy_interrupts;
  307. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  308. adapter->init_port = netxen_niu_xg_init_port;
  309. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  310. adapter->stop_port = netxen_niu_disable_xg_port;
  311. break;
  312. default:
  313. break;
  314. }
  315. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  316. adapter->set_mtu = nx_fw_cmd_set_mtu;
  317. adapter->set_promisc = netxen_p3_nic_set_promisc;
  318. adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
  319. adapter->set_multi = netxen_p3_nic_set_multi;
  320. }
  321. }
  322. /*
  323. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  324. * address to external PCI CRB address.
  325. */
  326. static u32 netxen_decode_crb_addr(u32 addr)
  327. {
  328. int i;
  329. u32 base_addr, offset, pci_base;
  330. crb_addr_transform_setup();
  331. pci_base = NETXEN_ADDR_ERROR;
  332. base_addr = addr & 0xfff00000;
  333. offset = addr & 0x000fffff;
  334. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  335. if (crb_addr_xform[i] == base_addr) {
  336. pci_base = i << 20;
  337. break;
  338. }
  339. }
  340. if (pci_base == NETXEN_ADDR_ERROR)
  341. return pci_base;
  342. else
  343. return (pci_base + offset);
  344. }
  345. static long rom_max_timeout = 100;
  346. static long rom_lock_timeout = 10000;
  347. static int rom_lock(struct netxen_adapter *adapter)
  348. {
  349. int iter;
  350. u32 done = 0;
  351. int timeout = 0;
  352. while (!done) {
  353. /* acquire semaphore2 from PCI HW block */
  354. done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
  355. if (done == 1)
  356. break;
  357. if (timeout >= rom_lock_timeout)
  358. return -EIO;
  359. timeout++;
  360. /*
  361. * Yield CPU
  362. */
  363. if (!in_atomic())
  364. schedule();
  365. else {
  366. for (iter = 0; iter < 20; iter++)
  367. cpu_relax(); /*This a nop instr on i386 */
  368. }
  369. }
  370. NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  371. return 0;
  372. }
  373. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  374. {
  375. long timeout = 0;
  376. long done = 0;
  377. cond_resched();
  378. while (done == 0) {
  379. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  380. done &= 2;
  381. timeout++;
  382. if (timeout >= rom_max_timeout) {
  383. printk("Timeout reached waiting for rom done");
  384. return -EIO;
  385. }
  386. }
  387. return 0;
  388. }
  389. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  390. {
  391. /* release semaphore2 */
  392. NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
  393. }
  394. static int do_rom_fast_read(struct netxen_adapter *adapter,
  395. int addr, int *valp)
  396. {
  397. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  398. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  399. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  400. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  401. if (netxen_wait_rom_done(adapter)) {
  402. printk("Error waiting for rom done\n");
  403. return -EIO;
  404. }
  405. /* reset abyte_cnt and dummy_byte_cnt */
  406. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  407. udelay(10);
  408. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  409. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  410. return 0;
  411. }
  412. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  413. u8 *bytes, size_t size)
  414. {
  415. int addridx;
  416. int ret = 0;
  417. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  418. int v;
  419. ret = do_rom_fast_read(adapter, addridx, &v);
  420. if (ret != 0)
  421. break;
  422. *(__le32 *)bytes = cpu_to_le32(v);
  423. bytes += 4;
  424. }
  425. return ret;
  426. }
  427. int
  428. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  429. u8 *bytes, size_t size)
  430. {
  431. int ret;
  432. ret = rom_lock(adapter);
  433. if (ret < 0)
  434. return ret;
  435. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  436. netxen_rom_unlock(adapter);
  437. return ret;
  438. }
  439. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  440. {
  441. int ret;
  442. if (rom_lock(adapter) != 0)
  443. return -EIO;
  444. ret = do_rom_fast_read(adapter, addr, valp);
  445. netxen_rom_unlock(adapter);
  446. return ret;
  447. }
  448. #define NETXEN_BOARDTYPE 0x4008
  449. #define NETXEN_BOARDNUM 0x400c
  450. #define NETXEN_CHIPNUM 0x4010
  451. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  452. {
  453. int addr, val;
  454. int i, n, init_delay = 0;
  455. struct crb_addr_pair *buf;
  456. unsigned offset;
  457. u32 off;
  458. /* resetall */
  459. rom_lock(adapter);
  460. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  461. netxen_rom_unlock(adapter);
  462. if (verbose) {
  463. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  464. printk("P2 ROM board type: 0x%08x\n", val);
  465. else
  466. printk("Could not read board type\n");
  467. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  468. printk("P2 ROM board num: 0x%08x\n", val);
  469. else
  470. printk("Could not read board number\n");
  471. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  472. printk("P2 ROM chip num: 0x%08x\n", val);
  473. else
  474. printk("Could not read chip number\n");
  475. }
  476. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  477. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  478. (n != 0xcafecafe) ||
  479. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  480. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  481. "n: %08x\n", netxen_nic_driver_name, n);
  482. return -EIO;
  483. }
  484. offset = n & 0xffffU;
  485. n = (n >> 16) & 0xffffU;
  486. } else {
  487. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  488. !(n & 0x80000000)) {
  489. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  490. "n: %08x\n", netxen_nic_driver_name, n);
  491. return -EIO;
  492. }
  493. offset = 1;
  494. n &= ~0x80000000;
  495. }
  496. if (n < 1024) {
  497. if (verbose)
  498. printk(KERN_DEBUG "%s: %d CRB init values found"
  499. " in ROM.\n", netxen_nic_driver_name, n);
  500. } else {
  501. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  502. " initialized.\n", __func__, n);
  503. return -EIO;
  504. }
  505. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  506. if (buf == NULL) {
  507. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  508. netxen_nic_driver_name);
  509. return -ENOMEM;
  510. }
  511. for (i = 0; i < n; i++) {
  512. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  513. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  514. kfree(buf);
  515. return -EIO;
  516. }
  517. buf[i].addr = addr;
  518. buf[i].data = val;
  519. if (verbose)
  520. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  521. netxen_nic_driver_name,
  522. (u32)netxen_decode_crb_addr(addr), val);
  523. }
  524. for (i = 0; i < n; i++) {
  525. off = netxen_decode_crb_addr(buf[i].addr);
  526. if (off == NETXEN_ADDR_ERROR) {
  527. printk(KERN_ERR"CRB init value out of range %x\n",
  528. buf[i].addr);
  529. continue;
  530. }
  531. off += NETXEN_PCI_CRBSPACE;
  532. /* skipping cold reboot MAGIC */
  533. if (off == NETXEN_CAM_RAM(0x1fc))
  534. continue;
  535. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  536. /* do not reset PCI */
  537. if (off == (ROMUSB_GLB + 0xbc))
  538. continue;
  539. if (off == (ROMUSB_GLB + 0xa8))
  540. continue;
  541. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  542. continue;
  543. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  544. continue;
  545. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  546. continue;
  547. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  548. buf[i].data = 0x1020;
  549. /* skip the function enable register */
  550. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  551. continue;
  552. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  553. continue;
  554. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  555. continue;
  556. }
  557. if (off == NETXEN_ADDR_ERROR) {
  558. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  559. netxen_nic_driver_name, buf[i].addr);
  560. continue;
  561. }
  562. init_delay = 1;
  563. /* After writing this register, HW needs time for CRB */
  564. /* to quiet down (else crb_window returns 0xffffffff) */
  565. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  566. init_delay = 1000;
  567. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  568. /* hold xdma in reset also */
  569. buf[i].data = NETXEN_NIC_XDMA_RESET;
  570. buf[i].data = 0x8000ff;
  571. }
  572. }
  573. NXWR32(adapter, off, buf[i].data);
  574. msleep(init_delay);
  575. }
  576. kfree(buf);
  577. /* disable_peg_cache_all */
  578. /* unreset_net_cache */
  579. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  580. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  581. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  582. }
  583. /* p2dn replyCount */
  584. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  585. /* disable_peg_cache 0 */
  586. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  587. /* disable_peg_cache 1 */
  588. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  589. /* peg_clr_all */
  590. /* peg_clr 0 */
  591. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  592. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  593. /* peg_clr 1 */
  594. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  595. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  596. /* peg_clr 2 */
  597. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  598. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  599. /* peg_clr 3 */
  600. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  601. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  602. return 0;
  603. }
  604. int
  605. netxen_need_fw_reset(struct netxen_adapter *adapter)
  606. {
  607. u32 count, old_count;
  608. u32 val, version, major, minor, build;
  609. int i, timeout;
  610. u8 fw_type;
  611. /* NX2031 firmware doesn't support heartbit */
  612. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  613. return 1;
  614. /* last attempt had failed */
  615. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  616. return 1;
  617. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  618. for (i = 0; i < 10; i++) {
  619. timeout = msleep_interruptible(200);
  620. if (timeout) {
  621. NXWR32(adapter, CRB_CMDPEG_STATE,
  622. PHAN_INITIALIZE_FAILED);
  623. return -EINTR;
  624. }
  625. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  626. if (count != old_count)
  627. break;
  628. }
  629. /* firmware is dead */
  630. if (count == old_count)
  631. return 1;
  632. /* check if we have got newer or different file firmware */
  633. if (adapter->fw) {
  634. const struct firmware *fw = adapter->fw;
  635. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  636. version = NETXEN_DECODE_VERSION(val);
  637. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  638. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  639. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  640. if (version > NETXEN_VERSION_CODE(major, minor, build))
  641. return 1;
  642. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  643. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  644. fw_type = (val & 0x4) ?
  645. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  646. if (adapter->fw_type != fw_type)
  647. return 1;
  648. }
  649. }
  650. return 0;
  651. }
  652. static char *fw_name[] = {
  653. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  654. };
  655. int
  656. netxen_load_firmware(struct netxen_adapter *adapter)
  657. {
  658. u64 *ptr64;
  659. u32 i, flashaddr, size;
  660. const struct firmware *fw = adapter->fw;
  661. struct pci_dev *pdev = adapter->pdev;
  662. dev_info(&pdev->dev, "loading firmware from %s\n",
  663. fw_name[adapter->fw_type]);
  664. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  665. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  666. if (fw) {
  667. __le64 data;
  668. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  669. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  670. flashaddr = NETXEN_BOOTLD_START;
  671. for (i = 0; i < size; i++) {
  672. data = cpu_to_le64(ptr64[i]);
  673. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  674. flashaddr += 8;
  675. }
  676. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  677. size = (__force u32)cpu_to_le32(size) / 8;
  678. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  679. flashaddr = NETXEN_IMAGE_START;
  680. for (i = 0; i < size; i++) {
  681. data = cpu_to_le64(ptr64[i]);
  682. if (adapter->pci_mem_write(adapter,
  683. flashaddr, &data, 8))
  684. return -EIO;
  685. flashaddr += 8;
  686. }
  687. } else {
  688. u32 data;
  689. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
  690. flashaddr = NETXEN_BOOTLD_START;
  691. for (i = 0; i < size; i++) {
  692. if (netxen_rom_fast_read(adapter,
  693. flashaddr, (int *)&data) != 0)
  694. return -EIO;
  695. if (adapter->pci_mem_write(adapter,
  696. flashaddr, &data, 4))
  697. return -EIO;
  698. flashaddr += 4;
  699. }
  700. }
  701. msleep(1);
  702. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  703. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  704. else {
  705. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  706. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  707. }
  708. return 0;
  709. }
  710. static int
  711. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  712. {
  713. __le32 val;
  714. u32 ver, min_ver, bios;
  715. struct pci_dev *pdev = adapter->pdev;
  716. const struct firmware *fw = adapter->fw;
  717. if (fw->size < NX_FW_MIN_SIZE)
  718. return -EINVAL;
  719. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  720. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  721. return -EINVAL;
  722. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  723. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  724. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  725. else
  726. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  727. ver = NETXEN_DECODE_VERSION(val);
  728. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  729. dev_err(&pdev->dev,
  730. "%s: firmware version %d.%d.%d unsupported\n",
  731. fwname, _major(ver), _minor(ver), _build(ver));
  732. return -EINVAL;
  733. }
  734. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  735. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  736. if ((__force u32)val != bios) {
  737. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  738. fwname);
  739. return -EINVAL;
  740. }
  741. /* check if flashed firmware is newer */
  742. if (netxen_rom_fast_read(adapter,
  743. NX_FW_VERSION_OFFSET, (int *)&val))
  744. return -EIO;
  745. val = NETXEN_DECODE_VERSION(val);
  746. if (val > ver) {
  747. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  748. fwname);
  749. return -EINVAL;
  750. }
  751. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  752. return 0;
  753. }
  754. void netxen_request_firmware(struct netxen_adapter *adapter)
  755. {
  756. u32 capability, flashed_ver;
  757. u8 fw_type;
  758. struct pci_dev *pdev = adapter->pdev;
  759. int rc = 0;
  760. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  761. fw_type = NX_P2_MN_ROMIMAGE;
  762. goto request_fw;
  763. } else {
  764. fw_type = NX_P3_CT_ROMIMAGE;
  765. goto request_fw;
  766. }
  767. request_mn:
  768. capability = 0;
  769. netxen_rom_fast_read(adapter,
  770. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  771. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  772. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  773. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  774. if (capability & NX_PEG_TUNE_MN_PRESENT) {
  775. fw_type = NX_P3_MN_ROMIMAGE;
  776. goto request_fw;
  777. }
  778. }
  779. fw_type = NX_FLASH_ROMIMAGE;
  780. adapter->fw = NULL;
  781. goto done;
  782. request_fw:
  783. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  784. if (rc != 0) {
  785. if (fw_type == NX_P3_CT_ROMIMAGE) {
  786. msleep(1);
  787. goto request_mn;
  788. }
  789. fw_type = NX_FLASH_ROMIMAGE;
  790. adapter->fw = NULL;
  791. goto done;
  792. }
  793. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  794. if (rc != 0) {
  795. release_firmware(adapter->fw);
  796. if (fw_type == NX_P3_CT_ROMIMAGE) {
  797. msleep(1);
  798. goto request_mn;
  799. }
  800. fw_type = NX_FLASH_ROMIMAGE;
  801. adapter->fw = NULL;
  802. goto done;
  803. }
  804. done:
  805. adapter->fw_type = fw_type;
  806. }
  807. void
  808. netxen_release_firmware(struct netxen_adapter *adapter)
  809. {
  810. if (adapter->fw)
  811. release_firmware(adapter->fw);
  812. }
  813. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  814. {
  815. uint64_t addr;
  816. uint32_t hi;
  817. uint32_t lo;
  818. adapter->dummy_dma.addr =
  819. pci_alloc_consistent(adapter->pdev,
  820. NETXEN_HOST_DUMMY_DMA_SIZE,
  821. &adapter->dummy_dma.phys_addr);
  822. if (adapter->dummy_dma.addr == NULL) {
  823. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  824. __func__);
  825. return -ENOMEM;
  826. }
  827. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  828. hi = (addr >> 32) & 0xffffffff;
  829. lo = addr & 0xffffffff;
  830. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  831. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  832. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  833. uint32_t temp = 0;
  834. NXWR32(adapter, CRB_HOST_DUMMY_BUF, temp);
  835. }
  836. return 0;
  837. }
  838. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  839. {
  840. int i = 100;
  841. if (!adapter->dummy_dma.addr)
  842. return;
  843. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  844. do {
  845. if (dma_watchdog_shutdown_request(adapter) == 1)
  846. break;
  847. msleep(50);
  848. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  849. break;
  850. } while (--i);
  851. }
  852. if (i) {
  853. pci_free_consistent(adapter->pdev,
  854. NETXEN_HOST_DUMMY_DMA_SIZE,
  855. adapter->dummy_dma.addr,
  856. adapter->dummy_dma.phys_addr);
  857. adapter->dummy_dma.addr = NULL;
  858. } else {
  859. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  860. adapter->netdev->name);
  861. }
  862. }
  863. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  864. {
  865. u32 val = 0;
  866. int retries = 60;
  867. if (pegtune_val)
  868. return 0;
  869. do {
  870. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  871. switch (val) {
  872. case PHAN_INITIALIZE_COMPLETE:
  873. case PHAN_INITIALIZE_ACK:
  874. return 0;
  875. case PHAN_INITIALIZE_FAILED:
  876. goto out_err;
  877. default:
  878. break;
  879. }
  880. msleep(500);
  881. } while (--retries);
  882. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  883. out_err:
  884. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  885. return -EIO;
  886. }
  887. static int
  888. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  889. {
  890. u32 val = 0;
  891. int retries = 2000;
  892. do {
  893. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  894. if (val == PHAN_PEG_RCV_INITIALIZED)
  895. return 0;
  896. msleep(10);
  897. } while (--retries);
  898. if (!retries) {
  899. printk(KERN_ERR "Receive Peg initialization not "
  900. "complete, state: 0x%x.\n", val);
  901. return -EIO;
  902. }
  903. return 0;
  904. }
  905. int netxen_init_firmware(struct netxen_adapter *adapter)
  906. {
  907. int err;
  908. err = netxen_receive_peg_ready(adapter);
  909. if (err)
  910. return err;
  911. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  912. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  913. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  914. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  915. if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222)) {
  916. adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
  917. }
  918. return err;
  919. }
  920. static void
  921. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  922. {
  923. u32 cable_OUI;
  924. u16 cable_len;
  925. u16 link_speed;
  926. u8 link_status, module, duplex, autoneg;
  927. struct net_device *netdev = adapter->netdev;
  928. adapter->has_link_events = 1;
  929. cable_OUI = msg->body[1] & 0xffffffff;
  930. cable_len = (msg->body[1] >> 32) & 0xffff;
  931. link_speed = (msg->body[1] >> 48) & 0xffff;
  932. link_status = msg->body[2] & 0xff;
  933. duplex = (msg->body[2] >> 16) & 0xff;
  934. autoneg = (msg->body[2] >> 24) & 0xff;
  935. module = (msg->body[2] >> 8) & 0xff;
  936. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  937. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  938. netdev->name, cable_OUI, cable_len);
  939. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  940. printk(KERN_INFO "%s: unsupported cable length %d\n",
  941. netdev->name, cable_len);
  942. }
  943. netxen_advert_link_change(adapter, link_status);
  944. /* update link parameters */
  945. if (duplex == LINKEVENT_FULL_DUPLEX)
  946. adapter->link_duplex = DUPLEX_FULL;
  947. else
  948. adapter->link_duplex = DUPLEX_HALF;
  949. adapter->module_type = module;
  950. adapter->link_autoneg = autoneg;
  951. adapter->link_speed = link_speed;
  952. }
  953. static void
  954. netxen_handle_fw_message(int desc_cnt, int index,
  955. struct nx_host_sds_ring *sds_ring)
  956. {
  957. nx_fw_msg_t msg;
  958. struct status_desc *desc;
  959. int i = 0, opcode;
  960. while (desc_cnt > 0 && i < 8) {
  961. desc = &sds_ring->desc_head[index];
  962. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  963. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  964. index = get_next_index(index, sds_ring->num_desc);
  965. desc_cnt--;
  966. }
  967. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  968. switch (opcode) {
  969. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  970. netxen_handle_linkevent(sds_ring->adapter, &msg);
  971. break;
  972. default:
  973. break;
  974. }
  975. }
  976. static int
  977. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  978. struct nx_host_rds_ring *rds_ring,
  979. struct netxen_rx_buffer *buffer)
  980. {
  981. struct sk_buff *skb;
  982. dma_addr_t dma;
  983. struct pci_dev *pdev = adapter->pdev;
  984. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  985. if (!buffer->skb)
  986. return 1;
  987. skb = buffer->skb;
  988. if (!adapter->ahw.cut_through)
  989. skb_reserve(skb, 2);
  990. dma = pci_map_single(pdev, skb->data,
  991. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  992. if (pci_dma_mapping_error(pdev, dma)) {
  993. dev_kfree_skb_any(skb);
  994. buffer->skb = NULL;
  995. return 1;
  996. }
  997. buffer->skb = skb;
  998. buffer->dma = dma;
  999. buffer->state = NETXEN_BUFFER_BUSY;
  1000. return 0;
  1001. }
  1002. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1003. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1004. {
  1005. struct netxen_rx_buffer *buffer;
  1006. struct sk_buff *skb;
  1007. buffer = &rds_ring->rx_buf_arr[index];
  1008. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1009. PCI_DMA_FROMDEVICE);
  1010. skb = buffer->skb;
  1011. if (!skb)
  1012. goto no_skb;
  1013. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1014. adapter->stats.csummed++;
  1015. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1016. } else
  1017. skb->ip_summed = CHECKSUM_NONE;
  1018. skb->dev = adapter->netdev;
  1019. buffer->skb = NULL;
  1020. no_skb:
  1021. buffer->state = NETXEN_BUFFER_FREE;
  1022. return skb;
  1023. }
  1024. static struct netxen_rx_buffer *
  1025. netxen_process_rcv(struct netxen_adapter *adapter,
  1026. int ring, int index, int length, int cksum, int pkt_offset,
  1027. struct nx_host_sds_ring *sds_ring)
  1028. {
  1029. struct net_device *netdev = adapter->netdev;
  1030. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1031. struct netxen_rx_buffer *buffer;
  1032. struct sk_buff *skb;
  1033. struct nx_host_rds_ring *rds_ring = &recv_ctx->rds_rings[ring];
  1034. if (unlikely(index > rds_ring->num_desc))
  1035. return NULL;
  1036. buffer = &rds_ring->rx_buf_arr[index];
  1037. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1038. if (!skb)
  1039. return buffer;
  1040. if (length > rds_ring->skb_size)
  1041. skb_put(skb, rds_ring->skb_size);
  1042. else
  1043. skb_put(skb, length);
  1044. if (pkt_offset)
  1045. skb_pull(skb, pkt_offset);
  1046. skb->protocol = eth_type_trans(skb, netdev);
  1047. napi_gro_receive(&sds_ring->napi, skb);
  1048. adapter->stats.no_rcv++;
  1049. adapter->stats.rxbytes += length;
  1050. return buffer;
  1051. }
  1052. #define netxen_merge_rx_buffers(list, head) \
  1053. do { list_splice_tail_init(list, head); } while (0);
  1054. int
  1055. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1056. {
  1057. struct netxen_adapter *adapter = sds_ring->adapter;
  1058. struct list_head *cur;
  1059. struct status_desc *desc;
  1060. struct netxen_rx_buffer *rxbuf;
  1061. u32 consumer = sds_ring->consumer;
  1062. int count = 0;
  1063. u64 sts_data;
  1064. int opcode, ring, index, length, cksum, pkt_offset, desc_cnt;
  1065. while (count < max) {
  1066. desc = &sds_ring->desc_head[consumer];
  1067. sts_data = le64_to_cpu(desc->status_desc_data[0]);
  1068. if (!(sts_data & STATUS_OWNER_HOST))
  1069. break;
  1070. desc_cnt = netxen_get_sts_desc_cnt(sts_data);
  1071. ring = netxen_get_sts_type(sts_data);
  1072. if (ring > RCV_RING_JUMBO)
  1073. goto skip;
  1074. opcode = netxen_get_sts_opcode(sts_data);
  1075. switch (opcode) {
  1076. case NETXEN_NIC_RXPKT_DESC:
  1077. case NETXEN_OLD_RXPKT_DESC:
  1078. break;
  1079. case NETXEN_NIC_RESPONSE_DESC:
  1080. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1081. default:
  1082. goto skip;
  1083. }
  1084. WARN_ON(desc_cnt > 1);
  1085. index = netxen_get_sts_refhandle(sts_data);
  1086. length = netxen_get_sts_totallength(sts_data);
  1087. cksum = netxen_get_sts_status(sts_data);
  1088. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  1089. rxbuf = netxen_process_rcv(adapter, ring, index,
  1090. length, cksum, pkt_offset, sds_ring);
  1091. if (rxbuf)
  1092. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1093. skip:
  1094. for (; desc_cnt > 0; desc_cnt--) {
  1095. desc = &sds_ring->desc_head[consumer];
  1096. desc->status_desc_data[0] =
  1097. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1098. consumer = get_next_index(consumer, sds_ring->num_desc);
  1099. }
  1100. count++;
  1101. }
  1102. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1103. struct nx_host_rds_ring *rds_ring =
  1104. &adapter->recv_ctx.rds_rings[ring];
  1105. if (!list_empty(&sds_ring->free_list[ring])) {
  1106. list_for_each(cur, &sds_ring->free_list[ring]) {
  1107. rxbuf = list_entry(cur,
  1108. struct netxen_rx_buffer, list);
  1109. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1110. }
  1111. spin_lock(&rds_ring->lock);
  1112. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1113. &rds_ring->free_list);
  1114. spin_unlock(&rds_ring->lock);
  1115. }
  1116. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1117. }
  1118. if (count) {
  1119. sds_ring->consumer = consumer;
  1120. NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
  1121. }
  1122. return count;
  1123. }
  1124. /* Process Command status ring */
  1125. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1126. {
  1127. u32 sw_consumer, hw_consumer;
  1128. int count = 0, i;
  1129. struct netxen_cmd_buffer *buffer;
  1130. struct pci_dev *pdev = adapter->pdev;
  1131. struct net_device *netdev = adapter->netdev;
  1132. struct netxen_skb_frag *frag;
  1133. int done = 0;
  1134. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1135. if (!spin_trylock(&adapter->tx_clean_lock))
  1136. return 1;
  1137. sw_consumer = tx_ring->sw_consumer;
  1138. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1139. while (sw_consumer != hw_consumer) {
  1140. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1141. if (buffer->skb) {
  1142. frag = &buffer->frag_array[0];
  1143. pci_unmap_single(pdev, frag->dma, frag->length,
  1144. PCI_DMA_TODEVICE);
  1145. frag->dma = 0ULL;
  1146. for (i = 1; i < buffer->frag_count; i++) {
  1147. frag++; /* Get the next frag */
  1148. pci_unmap_page(pdev, frag->dma, frag->length,
  1149. PCI_DMA_TODEVICE);
  1150. frag->dma = 0ULL;
  1151. }
  1152. adapter->stats.xmitfinished++;
  1153. dev_kfree_skb_any(buffer->skb);
  1154. buffer->skb = NULL;
  1155. }
  1156. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1157. if (++count >= MAX_STATUS_HANDLE)
  1158. break;
  1159. }
  1160. if (count && netif_running(netdev)) {
  1161. tx_ring->sw_consumer = sw_consumer;
  1162. smp_mb();
  1163. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1164. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1165. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1166. netif_wake_queue(netdev);
  1167. __netif_tx_unlock(tx_ring->txq);
  1168. }
  1169. }
  1170. /*
  1171. * If everything is freed up to consumer then check if the ring is full
  1172. * If the ring is full then check if more needs to be freed and
  1173. * schedule the call back again.
  1174. *
  1175. * This happens when there are 2 CPUs. One could be freeing and the
  1176. * other filling it. If the ring is full when we get out of here and
  1177. * the card has already interrupted the host then the host can miss the
  1178. * interrupt.
  1179. *
  1180. * There is still a possible race condition and the host could miss an
  1181. * interrupt. The card has to take care of this.
  1182. */
  1183. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1184. done = (sw_consumer == hw_consumer);
  1185. spin_unlock(&adapter->tx_clean_lock);
  1186. return (done);
  1187. }
  1188. void
  1189. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1190. struct nx_host_rds_ring *rds_ring)
  1191. {
  1192. struct rcv_desc *pdesc;
  1193. struct netxen_rx_buffer *buffer;
  1194. int producer, count = 0;
  1195. netxen_ctx_msg msg = 0;
  1196. struct list_head *head;
  1197. producer = rds_ring->producer;
  1198. spin_lock(&rds_ring->lock);
  1199. head = &rds_ring->free_list;
  1200. while (!list_empty(head)) {
  1201. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1202. if (!buffer->skb) {
  1203. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1204. break;
  1205. }
  1206. count++;
  1207. list_del(&buffer->list);
  1208. /* make a rcv descriptor */
  1209. pdesc = &rds_ring->desc_head[producer];
  1210. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1211. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1212. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1213. producer = get_next_index(producer, rds_ring->num_desc);
  1214. }
  1215. spin_unlock(&rds_ring->lock);
  1216. if (count) {
  1217. rds_ring->producer = producer;
  1218. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1219. (producer-1) & (rds_ring->num_desc-1));
  1220. if (adapter->fw_major < 4) {
  1221. /*
  1222. * Write a doorbell msg to tell phanmon of change in
  1223. * receive ring producer
  1224. * Only for firmware version < 4.0.0
  1225. */
  1226. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1227. netxen_set_msg_privid(msg);
  1228. netxen_set_msg_count(msg,
  1229. ((producer - 1) &
  1230. (rds_ring->num_desc - 1)));
  1231. netxen_set_msg_ctxid(msg, adapter->portnum);
  1232. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1233. writel(msg,
  1234. DB_NORMALIZE(adapter,
  1235. NETXEN_RCV_PRODUCER_OFFSET));
  1236. }
  1237. }
  1238. }
  1239. static void
  1240. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1241. struct nx_host_rds_ring *rds_ring)
  1242. {
  1243. struct rcv_desc *pdesc;
  1244. struct netxen_rx_buffer *buffer;
  1245. int producer, count = 0;
  1246. struct list_head *head;
  1247. producer = rds_ring->producer;
  1248. if (!spin_trylock(&rds_ring->lock))
  1249. return;
  1250. head = &rds_ring->free_list;
  1251. while (!list_empty(head)) {
  1252. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1253. if (!buffer->skb) {
  1254. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1255. break;
  1256. }
  1257. count++;
  1258. list_del(&buffer->list);
  1259. /* make a rcv descriptor */
  1260. pdesc = &rds_ring->desc_head[producer];
  1261. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1262. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1263. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1264. producer = get_next_index(producer, rds_ring->num_desc);
  1265. }
  1266. if (count) {
  1267. rds_ring->producer = producer;
  1268. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1269. (producer - 1) & (rds_ring->num_desc - 1));
  1270. }
  1271. spin_unlock(&rds_ring->lock);
  1272. }
  1273. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1274. {
  1275. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1276. return;
  1277. }