en_rx.c 28 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/mlx4/cq.h>
  34. #include <linux/mlx4/qp.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/if_ether.h>
  37. #include <linux/if_vlan.h>
  38. #include <linux/vmalloc.h>
  39. #include "mlx4_en.h"
  40. static void *get_wqe(struct mlx4_en_rx_ring *ring, int n)
  41. {
  42. int offset = n << ring->srq.wqe_shift;
  43. return ring->buf + offset;
  44. }
  45. static void mlx4_en_srq_event(struct mlx4_srq *srq, enum mlx4_event type)
  46. {
  47. return;
  48. }
  49. static int mlx4_en_get_frag_header(struct skb_frag_struct *frags, void **mac_hdr,
  50. void **ip_hdr, void **tcpudp_hdr,
  51. u64 *hdr_flags, void *priv)
  52. {
  53. *mac_hdr = page_address(frags->page) + frags->page_offset;
  54. *ip_hdr = *mac_hdr + ETH_HLEN;
  55. *tcpudp_hdr = (struct tcphdr *)(*ip_hdr + sizeof(struct iphdr));
  56. *hdr_flags = LRO_IPV4 | LRO_TCP;
  57. return 0;
  58. }
  59. static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
  60. struct mlx4_en_rx_desc *rx_desc,
  61. struct skb_frag_struct *skb_frags,
  62. struct mlx4_en_rx_alloc *ring_alloc,
  63. int i)
  64. {
  65. struct mlx4_en_dev *mdev = priv->mdev;
  66. struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  67. struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
  68. struct page *page;
  69. dma_addr_t dma;
  70. if (page_alloc->offset == frag_info->last_offset) {
  71. /* Allocate new page */
  72. page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
  73. if (!page)
  74. return -ENOMEM;
  75. skb_frags[i].page = page_alloc->page;
  76. skb_frags[i].page_offset = page_alloc->offset;
  77. page_alloc->page = page;
  78. page_alloc->offset = frag_info->frag_align;
  79. } else {
  80. page = page_alloc->page;
  81. get_page(page);
  82. skb_frags[i].page = page;
  83. skb_frags[i].page_offset = page_alloc->offset;
  84. page_alloc->offset += frag_info->frag_stride;
  85. }
  86. dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
  87. skb_frags[i].page_offset, frag_info->frag_size,
  88. PCI_DMA_FROMDEVICE);
  89. rx_desc->data[i].addr = cpu_to_be64(dma);
  90. return 0;
  91. }
  92. static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
  93. struct mlx4_en_rx_ring *ring)
  94. {
  95. struct mlx4_en_rx_alloc *page_alloc;
  96. int i;
  97. for (i = 0; i < priv->num_frags; i++) {
  98. page_alloc = &ring->page_alloc[i];
  99. page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
  100. MLX4_EN_ALLOC_ORDER);
  101. if (!page_alloc->page)
  102. goto out;
  103. page_alloc->offset = priv->frag_info[i].frag_align;
  104. en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
  105. i, page_alloc->page);
  106. }
  107. return 0;
  108. out:
  109. while (i--) {
  110. page_alloc = &ring->page_alloc[i];
  111. put_page(page_alloc->page);
  112. page_alloc->page = NULL;
  113. }
  114. return -ENOMEM;
  115. }
  116. static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
  117. struct mlx4_en_rx_ring *ring)
  118. {
  119. struct mlx4_en_rx_alloc *page_alloc;
  120. int i;
  121. for (i = 0; i < priv->num_frags; i++) {
  122. page_alloc = &ring->page_alloc[i];
  123. en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
  124. i, page_count(page_alloc->page));
  125. put_page(page_alloc->page);
  126. page_alloc->page = NULL;
  127. }
  128. }
  129. static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
  130. struct mlx4_en_rx_ring *ring, int index)
  131. {
  132. struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
  133. struct skb_frag_struct *skb_frags = ring->rx_info +
  134. (index << priv->log_rx_info);
  135. int possible_frags;
  136. int i;
  137. /* Pre-link descriptor */
  138. rx_desc->next.next_wqe_index = cpu_to_be16((index + 1) & ring->size_mask);
  139. /* Set size and memtype fields */
  140. for (i = 0; i < priv->num_frags; i++) {
  141. skb_frags[i].size = priv->frag_info[i].frag_size;
  142. rx_desc->data[i].byte_count =
  143. cpu_to_be32(priv->frag_info[i].frag_size);
  144. rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
  145. }
  146. /* If the number of used fragments does not fill up the ring stride,
  147. * remaining (unused) fragments must be padded with null address/size
  148. * and a special memory key */
  149. possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
  150. for (i = priv->num_frags; i < possible_frags; i++) {
  151. rx_desc->data[i].byte_count = 0;
  152. rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
  153. rx_desc->data[i].addr = 0;
  154. }
  155. }
  156. static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
  157. struct mlx4_en_rx_ring *ring, int index)
  158. {
  159. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
  160. struct skb_frag_struct *skb_frags = ring->rx_info +
  161. (index << priv->log_rx_info);
  162. int i;
  163. for (i = 0; i < priv->num_frags; i++)
  164. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
  165. goto err;
  166. return 0;
  167. err:
  168. while (i--)
  169. put_page(skb_frags[i].page);
  170. return -ENOMEM;
  171. }
  172. static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
  173. {
  174. *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
  175. }
  176. static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
  177. struct mlx4_en_rx_ring *ring,
  178. int index)
  179. {
  180. struct mlx4_en_dev *mdev = priv->mdev;
  181. struct skb_frag_struct *skb_frags;
  182. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
  183. dma_addr_t dma;
  184. int nr;
  185. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  186. for (nr = 0; nr < priv->num_frags; nr++) {
  187. en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
  188. dma = be64_to_cpu(rx_desc->data[nr].addr);
  189. en_dbg(DRV, priv, "Unmaping buffer at dma:0x%llx\n", (u64) dma);
  190. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  191. PCI_DMA_FROMDEVICE);
  192. put_page(skb_frags[nr].page);
  193. }
  194. }
  195. static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
  196. {
  197. struct mlx4_en_rx_ring *ring;
  198. int ring_ind;
  199. int buf_ind;
  200. int new_size;
  201. for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
  202. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  203. ring = &priv->rx_ring[ring_ind];
  204. if (mlx4_en_prepare_rx_desc(priv, ring,
  205. ring->actual_size)) {
  206. if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
  207. en_err(priv, "Failed to allocate "
  208. "enough rx buffers\n");
  209. return -ENOMEM;
  210. } else {
  211. new_size = rounddown_pow_of_two(ring->actual_size);
  212. en_warn(priv, "Only %d buffers allocated "
  213. "reducing ring size to %d",
  214. ring->actual_size, new_size);
  215. goto reduce_rings;
  216. }
  217. }
  218. ring->actual_size++;
  219. ring->prod++;
  220. }
  221. }
  222. return 0;
  223. reduce_rings:
  224. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  225. ring = &priv->rx_ring[ring_ind];
  226. while (ring->actual_size > new_size) {
  227. ring->actual_size--;
  228. ring->prod--;
  229. mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
  230. }
  231. ring->size_mask = ring->actual_size - 1;
  232. }
  233. return 0;
  234. }
  235. static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
  236. struct mlx4_en_rx_ring *ring)
  237. {
  238. int index;
  239. en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
  240. ring->cons, ring->prod);
  241. /* Unmap and free Rx buffers */
  242. BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
  243. while (ring->cons != ring->prod) {
  244. index = ring->cons & ring->size_mask;
  245. en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
  246. mlx4_en_free_rx_desc(priv, ring, index);
  247. ++ring->cons;
  248. }
  249. }
  250. int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
  251. struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
  252. {
  253. struct mlx4_en_dev *mdev = priv->mdev;
  254. int err;
  255. int tmp;
  256. /* Sanity check SRQ size before proceeding */
  257. if (size >= mdev->dev->caps.max_srq_wqes)
  258. return -EINVAL;
  259. ring->prod = 0;
  260. ring->cons = 0;
  261. ring->size = size;
  262. ring->size_mask = size - 1;
  263. ring->stride = stride;
  264. ring->log_stride = ffs(ring->stride) - 1;
  265. ring->buf_size = ring->size * ring->stride;
  266. tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
  267. sizeof(struct skb_frag_struct));
  268. ring->rx_info = vmalloc(tmp);
  269. if (!ring->rx_info) {
  270. en_err(priv, "Failed allocating rx_info ring\n");
  271. return -ENOMEM;
  272. }
  273. en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
  274. ring->rx_info, tmp);
  275. err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
  276. ring->buf_size, 2 * PAGE_SIZE);
  277. if (err)
  278. goto err_ring;
  279. err = mlx4_en_map_buffer(&ring->wqres.buf);
  280. if (err) {
  281. en_err(priv, "Failed to map RX buffer\n");
  282. goto err_hwq;
  283. }
  284. ring->buf = ring->wqres.buf.direct.buf;
  285. /* Configure lro mngr */
  286. memset(&ring->lro, 0, sizeof(struct net_lro_mgr));
  287. ring->lro.dev = priv->dev;
  288. ring->lro.features = LRO_F_NAPI;
  289. ring->lro.frag_align_pad = NET_IP_ALIGN;
  290. ring->lro.ip_summed = CHECKSUM_UNNECESSARY;
  291. ring->lro.ip_summed_aggr = CHECKSUM_UNNECESSARY;
  292. ring->lro.max_desc = mdev->profile.num_lro;
  293. ring->lro.max_aggr = MAX_SKB_FRAGS;
  294. ring->lro.lro_arr = kzalloc(mdev->profile.num_lro *
  295. sizeof(struct net_lro_desc),
  296. GFP_KERNEL);
  297. if (!ring->lro.lro_arr) {
  298. en_err(priv, "Failed to allocate lro array\n");
  299. goto err_map;
  300. }
  301. ring->lro.get_frag_header = mlx4_en_get_frag_header;
  302. return 0;
  303. err_map:
  304. mlx4_en_unmap_buffer(&ring->wqres.buf);
  305. err_hwq:
  306. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  307. err_ring:
  308. vfree(ring->rx_info);
  309. ring->rx_info = NULL;
  310. return err;
  311. }
  312. int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
  313. {
  314. struct mlx4_en_dev *mdev = priv->mdev;
  315. struct mlx4_wqe_srq_next_seg *next;
  316. struct mlx4_en_rx_ring *ring;
  317. int i;
  318. int ring_ind;
  319. int err;
  320. int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
  321. DS_SIZE * priv->num_frags);
  322. int max_gs = (stride - sizeof(struct mlx4_wqe_srq_next_seg)) / DS_SIZE;
  323. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  324. ring = &priv->rx_ring[ring_ind];
  325. ring->prod = 0;
  326. ring->cons = 0;
  327. ring->actual_size = 0;
  328. ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
  329. ring->stride = stride;
  330. ring->log_stride = ffs(ring->stride) - 1;
  331. ring->buf_size = ring->size * ring->stride;
  332. memset(ring->buf, 0, ring->buf_size);
  333. mlx4_en_update_rx_prod_db(ring);
  334. /* Initailize all descriptors */
  335. for (i = 0; i < ring->size; i++)
  336. mlx4_en_init_rx_desc(priv, ring, i);
  337. /* Initialize page allocators */
  338. err = mlx4_en_init_allocator(priv, ring);
  339. if (err) {
  340. en_err(priv, "Failed initializing ring allocator\n");
  341. ring_ind--;
  342. goto err_allocator;
  343. }
  344. }
  345. err = mlx4_en_fill_rx_buffers(priv);
  346. if (err)
  347. goto err_buffers;
  348. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  349. ring = &priv->rx_ring[ring_ind];
  350. mlx4_en_update_rx_prod_db(ring);
  351. /* Configure SRQ representing the ring */
  352. ring->srq.max = ring->actual_size;
  353. ring->srq.max_gs = max_gs;
  354. ring->srq.wqe_shift = ilog2(ring->stride);
  355. for (i = 0; i < ring->srq.max; ++i) {
  356. next = get_wqe(ring, i);
  357. next->next_wqe_index =
  358. cpu_to_be16((i + 1) & (ring->srq.max - 1));
  359. }
  360. err = mlx4_srq_alloc(mdev->dev, mdev->priv_pdn, &ring->wqres.mtt,
  361. ring->wqres.db.dma, &ring->srq);
  362. if (err){
  363. en_err(priv, "Failed to allocate srq\n");
  364. ring_ind--;
  365. goto err_srq;
  366. }
  367. ring->srq.event = mlx4_en_srq_event;
  368. }
  369. return 0;
  370. err_srq:
  371. while (ring_ind >= 0) {
  372. ring = &priv->rx_ring[ring_ind];
  373. mlx4_srq_free(mdev->dev, &ring->srq);
  374. ring_ind--;
  375. }
  376. err_buffers:
  377. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
  378. mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
  379. ring_ind = priv->rx_ring_num - 1;
  380. err_allocator:
  381. while (ring_ind >= 0) {
  382. mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
  383. ring_ind--;
  384. }
  385. return err;
  386. }
  387. void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
  388. struct mlx4_en_rx_ring *ring)
  389. {
  390. struct mlx4_en_dev *mdev = priv->mdev;
  391. kfree(ring->lro.lro_arr);
  392. mlx4_en_unmap_buffer(&ring->wqres.buf);
  393. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  394. vfree(ring->rx_info);
  395. ring->rx_info = NULL;
  396. }
  397. void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
  398. struct mlx4_en_rx_ring *ring)
  399. {
  400. struct mlx4_en_dev *mdev = priv->mdev;
  401. mlx4_srq_free(mdev->dev, &ring->srq);
  402. mlx4_en_free_rx_buf(priv, ring);
  403. mlx4_en_destroy_allocator(priv, ring);
  404. }
  405. /* Unmap a completed descriptor and free unused pages */
  406. static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
  407. struct mlx4_en_rx_desc *rx_desc,
  408. struct skb_frag_struct *skb_frags,
  409. struct skb_frag_struct *skb_frags_rx,
  410. struct mlx4_en_rx_alloc *page_alloc,
  411. int length)
  412. {
  413. struct mlx4_en_dev *mdev = priv->mdev;
  414. struct mlx4_en_frag_info *frag_info;
  415. int nr;
  416. dma_addr_t dma;
  417. /* Collect used fragments while replacing them in the HW descirptors */
  418. for (nr = 0; nr < priv->num_frags; nr++) {
  419. frag_info = &priv->frag_info[nr];
  420. if (length <= frag_info->frag_prefix_size)
  421. break;
  422. /* Save page reference in skb */
  423. skb_frags_rx[nr].page = skb_frags[nr].page;
  424. skb_frags_rx[nr].size = skb_frags[nr].size;
  425. skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset;
  426. dma = be64_to_cpu(rx_desc->data[nr].addr);
  427. /* Allocate a replacement page */
  428. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
  429. goto fail;
  430. /* Unmap buffer */
  431. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  432. PCI_DMA_FROMDEVICE);
  433. }
  434. /* Adjust size of last fragment to match actual length */
  435. skb_frags_rx[nr - 1].size = length -
  436. priv->frag_info[nr - 1].frag_prefix_size;
  437. return nr;
  438. fail:
  439. /* Drop all accumulated fragments (which have already been replaced in
  440. * the descriptor) of this packet; remaining fragments are reused... */
  441. while (nr > 0) {
  442. nr--;
  443. put_page(skb_frags_rx[nr].page);
  444. }
  445. return 0;
  446. }
  447. static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
  448. struct mlx4_en_rx_desc *rx_desc,
  449. struct skb_frag_struct *skb_frags,
  450. struct mlx4_en_rx_alloc *page_alloc,
  451. unsigned int length)
  452. {
  453. struct mlx4_en_dev *mdev = priv->mdev;
  454. struct sk_buff *skb;
  455. void *va;
  456. int used_frags;
  457. dma_addr_t dma;
  458. skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
  459. if (!skb) {
  460. en_dbg(RX_ERR, priv, "Failed allocating skb\n");
  461. return NULL;
  462. }
  463. skb->dev = priv->dev;
  464. skb_reserve(skb, NET_IP_ALIGN);
  465. skb->len = length;
  466. skb->truesize = length + sizeof(struct sk_buff);
  467. /* Get pointer to first fragment so we could copy the headers into the
  468. * (linear part of the) skb */
  469. va = page_address(skb_frags[0].page) + skb_frags[0].page_offset;
  470. if (length <= SMALL_PACKET_SIZE) {
  471. /* We are copying all relevant data to the skb - temporarily
  472. * synch buffers for the copy */
  473. dma = be64_to_cpu(rx_desc->data[0].addr);
  474. dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0,
  475. length, DMA_FROM_DEVICE);
  476. skb_copy_to_linear_data(skb, va, length);
  477. dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0,
  478. length, DMA_FROM_DEVICE);
  479. skb->tail += length;
  480. } else {
  481. /* Move relevant fragments to skb */
  482. used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
  483. skb_shinfo(skb)->frags,
  484. page_alloc, length);
  485. if (unlikely(!used_frags)) {
  486. kfree_skb(skb);
  487. return NULL;
  488. }
  489. skb_shinfo(skb)->nr_frags = used_frags;
  490. /* Copy headers into the skb linear buffer */
  491. memcpy(skb->data, va, HEADER_COPY_SIZE);
  492. skb->tail += HEADER_COPY_SIZE;
  493. /* Skip headers in first fragment */
  494. skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
  495. /* Adjust size of first fragment */
  496. skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE;
  497. skb->data_len = length - HEADER_COPY_SIZE;
  498. }
  499. return skb;
  500. }
  501. int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
  502. {
  503. struct mlx4_en_priv *priv = netdev_priv(dev);
  504. struct mlx4_cqe *cqe;
  505. struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
  506. struct skb_frag_struct *skb_frags;
  507. struct skb_frag_struct lro_frags[MLX4_EN_MAX_RX_FRAGS];
  508. struct mlx4_en_rx_desc *rx_desc;
  509. struct sk_buff *skb;
  510. int index;
  511. int nr;
  512. unsigned int length;
  513. int polled = 0;
  514. int ip_summed;
  515. if (!priv->port_up)
  516. return 0;
  517. /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
  518. * descriptor offset can be deduced from the CQE index instead of
  519. * reading 'cqe->index' */
  520. index = cq->mcq.cons_index & ring->size_mask;
  521. cqe = &cq->buf[index];
  522. /* Process all completed CQEs */
  523. while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
  524. cq->mcq.cons_index & cq->size)) {
  525. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  526. rx_desc = ring->buf + (index << ring->log_stride);
  527. /*
  528. * make sure we read the CQE after we read the ownership bit
  529. */
  530. rmb();
  531. /* Drop packet on bad receive or bad checksum */
  532. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  533. MLX4_CQE_OPCODE_ERROR)) {
  534. en_err(priv, "CQE completed in error - vendor "
  535. "syndrom:%d syndrom:%d\n",
  536. ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
  537. ((struct mlx4_err_cqe *) cqe)->syndrome);
  538. goto next;
  539. }
  540. if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
  541. en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
  542. goto next;
  543. }
  544. /*
  545. * Packet is OK - process it.
  546. */
  547. length = be32_to_cpu(cqe->byte_cnt);
  548. ring->bytes += length;
  549. ring->packets++;
  550. if (likely(priv->rx_csum)) {
  551. if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
  552. (cqe->checksum == cpu_to_be16(0xffff))) {
  553. priv->port_stats.rx_chksum_good++;
  554. /* This packet is eligible for LRO if it is:
  555. * - DIX Ethernet (type interpretation)
  556. * - TCP/IP (v4)
  557. * - without IP options
  558. * - not an IP fragment */
  559. if (mlx4_en_can_lro(cqe->status) &&
  560. dev->features & NETIF_F_LRO) {
  561. nr = mlx4_en_complete_rx_desc(
  562. priv, rx_desc,
  563. skb_frags, lro_frags,
  564. ring->page_alloc, length);
  565. if (!nr)
  566. goto next;
  567. if (priv->vlgrp && (cqe->vlan_my_qpn &
  568. cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK))) {
  569. lro_vlan_hwaccel_receive_frags(
  570. &ring->lro, lro_frags,
  571. length, length,
  572. priv->vlgrp,
  573. be16_to_cpu(cqe->sl_vid),
  574. NULL, 0);
  575. } else
  576. lro_receive_frags(&ring->lro,
  577. lro_frags,
  578. length,
  579. length,
  580. NULL, 0);
  581. goto next;
  582. }
  583. /* LRO not possible, complete processing here */
  584. ip_summed = CHECKSUM_UNNECESSARY;
  585. INC_PERF_COUNTER(priv->pstats.lro_misses);
  586. } else {
  587. ip_summed = CHECKSUM_NONE;
  588. priv->port_stats.rx_chksum_none++;
  589. }
  590. } else {
  591. ip_summed = CHECKSUM_NONE;
  592. priv->port_stats.rx_chksum_none++;
  593. }
  594. skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
  595. ring->page_alloc, length);
  596. if (!skb) {
  597. priv->stats.rx_dropped++;
  598. goto next;
  599. }
  600. skb->ip_summed = ip_summed;
  601. skb->protocol = eth_type_trans(skb, dev);
  602. skb_record_rx_queue(skb, cq->ring);
  603. /* Push it up the stack */
  604. if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) &
  605. MLX4_CQE_VLAN_PRESENT_MASK)) {
  606. vlan_hwaccel_receive_skb(skb, priv->vlgrp,
  607. be16_to_cpu(cqe->sl_vid));
  608. } else
  609. netif_receive_skb(skb);
  610. next:
  611. ++cq->mcq.cons_index;
  612. index = (cq->mcq.cons_index) & ring->size_mask;
  613. cqe = &cq->buf[index];
  614. if (++polled == budget) {
  615. /* We are here because we reached the NAPI budget -
  616. * flush only pending LRO sessions */
  617. lro_flush_all(&ring->lro);
  618. goto out;
  619. }
  620. }
  621. /* If CQ is empty flush all LRO sessions unconditionally */
  622. lro_flush_all(&ring->lro);
  623. out:
  624. AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
  625. mlx4_cq_set_ci(&cq->mcq);
  626. wmb(); /* ensure HW sees CQ consumer before we post new buffers */
  627. ring->cons = cq->mcq.cons_index;
  628. ring->prod += polled; /* Polled descriptors were realocated in place */
  629. mlx4_en_update_rx_prod_db(ring);
  630. return polled;
  631. }
  632. void mlx4_en_rx_irq(struct mlx4_cq *mcq)
  633. {
  634. struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
  635. struct mlx4_en_priv *priv = netdev_priv(cq->dev);
  636. if (priv->port_up)
  637. napi_schedule(&cq->napi);
  638. else
  639. mlx4_en_arm_cq(priv, cq);
  640. }
  641. /* Rx CQ polling - called by NAPI */
  642. int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
  643. {
  644. struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
  645. struct net_device *dev = cq->dev;
  646. struct mlx4_en_priv *priv = netdev_priv(dev);
  647. int done;
  648. done = mlx4_en_process_rx_cq(dev, cq, budget);
  649. /* If we used up all the quota - we're probably not done yet... */
  650. if (done == budget)
  651. INC_PERF_COUNTER(priv->pstats.napi_quota);
  652. else {
  653. /* Done for now */
  654. napi_complete(napi);
  655. mlx4_en_arm_cq(priv, cq);
  656. }
  657. return done;
  658. }
  659. /* Calculate the last offset position that accomodates a full fragment
  660. * (assuming fagment size = stride-align) */
  661. static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
  662. {
  663. u16 res = MLX4_EN_ALLOC_SIZE % stride;
  664. u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
  665. en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
  666. "res:%d offset:%d\n", stride, align, res, offset);
  667. return offset;
  668. }
  669. static int frag_sizes[] = {
  670. FRAG_SZ0,
  671. FRAG_SZ1,
  672. FRAG_SZ2,
  673. FRAG_SZ3
  674. };
  675. void mlx4_en_calc_rx_buf(struct net_device *dev)
  676. {
  677. struct mlx4_en_priv *priv = netdev_priv(dev);
  678. int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
  679. int buf_size = 0;
  680. int i = 0;
  681. while (buf_size < eff_mtu) {
  682. priv->frag_info[i].frag_size =
  683. (eff_mtu > buf_size + frag_sizes[i]) ?
  684. frag_sizes[i] : eff_mtu - buf_size;
  685. priv->frag_info[i].frag_prefix_size = buf_size;
  686. if (!i) {
  687. priv->frag_info[i].frag_align = NET_IP_ALIGN;
  688. priv->frag_info[i].frag_stride =
  689. ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
  690. } else {
  691. priv->frag_info[i].frag_align = 0;
  692. priv->frag_info[i].frag_stride =
  693. ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
  694. }
  695. priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
  696. priv, priv->frag_info[i].frag_stride,
  697. priv->frag_info[i].frag_align);
  698. buf_size += priv->frag_info[i].frag_size;
  699. i++;
  700. }
  701. priv->num_frags = i;
  702. priv->rx_skb_size = eff_mtu;
  703. priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
  704. en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
  705. "num_frags:%d):\n", eff_mtu, priv->num_frags);
  706. for (i = 0; i < priv->num_frags; i++) {
  707. en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
  708. "stride:%d last_offset:%d\n", i,
  709. priv->frag_info[i].frag_size,
  710. priv->frag_info[i].frag_prefix_size,
  711. priv->frag_info[i].frag_align,
  712. priv->frag_info[i].frag_stride,
  713. priv->frag_info[i].last_offset);
  714. }
  715. }
  716. /* RSS related functions */
  717. /* Calculate rss size and map each entry in rss table to rx ring */
  718. void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
  719. struct mlx4_en_rss_map *rss_map,
  720. int num_entries, int num_rings)
  721. {
  722. int i;
  723. rss_map->size = roundup_pow_of_two(num_entries);
  724. en_dbg(DRV, priv, "Setting default RSS map of %d entires\n",
  725. rss_map->size);
  726. for (i = 0; i < rss_map->size; i++) {
  727. rss_map->map[i] = i % num_rings;
  728. en_dbg(DRV, priv, "Entry %d ---> ring %d\n", i, rss_map->map[i]);
  729. }
  730. }
  731. static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv,
  732. int qpn, int srqn, int cqn,
  733. enum mlx4_qp_state *state,
  734. struct mlx4_qp *qp)
  735. {
  736. struct mlx4_en_dev *mdev = priv->mdev;
  737. struct mlx4_qp_context *context;
  738. int err = 0;
  739. context = kmalloc(sizeof *context , GFP_KERNEL);
  740. if (!context) {
  741. en_err(priv, "Failed to allocate qp context\n");
  742. return -ENOMEM;
  743. }
  744. err = mlx4_qp_alloc(mdev->dev, qpn, qp);
  745. if (err) {
  746. en_err(priv, "Failed to allocate qp #%x\n", qpn);
  747. goto out;
  748. }
  749. qp->event = mlx4_en_sqp_event;
  750. memset(context, 0, sizeof *context);
  751. mlx4_en_fill_qp_context(priv, 0, 0, 0, 0, qpn, cqn, srqn, context);
  752. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, context, qp, state);
  753. if (err) {
  754. mlx4_qp_remove(mdev->dev, qp);
  755. mlx4_qp_free(mdev->dev, qp);
  756. }
  757. out:
  758. kfree(context);
  759. return err;
  760. }
  761. /* Allocate rx qp's and configure them according to rss map */
  762. int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
  763. {
  764. struct mlx4_en_dev *mdev = priv->mdev;
  765. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  766. struct mlx4_qp_context context;
  767. struct mlx4_en_rss_context *rss_context;
  768. void *ptr;
  769. int rss_xor = mdev->profile.rss_xor;
  770. u8 rss_mask = mdev->profile.rss_mask;
  771. int i, srqn, qpn, cqn;
  772. int err = 0;
  773. int good_qps = 0;
  774. en_dbg(DRV, priv, "Configuring rss steering\n");
  775. err = mlx4_qp_reserve_range(mdev->dev, rss_map->size,
  776. rss_map->size, &rss_map->base_qpn);
  777. if (err) {
  778. en_err(priv, "Failed reserving %d qps\n", rss_map->size);
  779. return err;
  780. }
  781. for (i = 0; i < rss_map->size; i++) {
  782. cqn = priv->rx_ring[rss_map->map[i]].cqn;
  783. srqn = priv->rx_ring[rss_map->map[i]].srq.srqn;
  784. qpn = rss_map->base_qpn + i;
  785. err = mlx4_en_config_rss_qp(priv, qpn, srqn, cqn,
  786. &rss_map->state[i],
  787. &rss_map->qps[i]);
  788. if (err)
  789. goto rss_err;
  790. ++good_qps;
  791. }
  792. /* Configure RSS indirection qp */
  793. err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn);
  794. if (err) {
  795. en_err(priv, "Failed to reserve range for RSS "
  796. "indirection qp\n");
  797. goto rss_err;
  798. }
  799. err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
  800. if (err) {
  801. en_err(priv, "Failed to allocate RSS indirection QP\n");
  802. goto reserve_err;
  803. }
  804. rss_map->indir_qp.event = mlx4_en_sqp_event;
  805. mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
  806. priv->rx_ring[0].cqn, 0, &context);
  807. ptr = ((void *) &context) + 0x3c;
  808. rss_context = (struct mlx4_en_rss_context *) ptr;
  809. rss_context->base_qpn = cpu_to_be32(ilog2(rss_map->size) << 24 |
  810. (rss_map->base_qpn));
  811. rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
  812. rss_context->hash_fn = rss_xor & 0x3;
  813. rss_context->flags = rss_mask << 2;
  814. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
  815. &rss_map->indir_qp, &rss_map->indir_state);
  816. if (err)
  817. goto indir_err;
  818. return 0;
  819. indir_err:
  820. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  821. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  822. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  823. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  824. reserve_err:
  825. mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
  826. rss_err:
  827. for (i = 0; i < good_qps; i++) {
  828. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  829. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  830. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  831. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  832. }
  833. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
  834. return err;
  835. }
  836. void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
  837. {
  838. struct mlx4_en_dev *mdev = priv->mdev;
  839. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  840. int i;
  841. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  842. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  843. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  844. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  845. mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
  846. for (i = 0; i < rss_map->size; i++) {
  847. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  848. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  849. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  850. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  851. }
  852. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
  853. }