cnic.c 65 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2009 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/errno.h>
  15. #include <linux/list.h>
  16. #include <linux/slab.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/uio_driver.h>
  21. #include <linux/in.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/delay.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/if_vlan.h>
  26. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  27. #define BCM_VLAN 1
  28. #endif
  29. #include <net/ip.h>
  30. #include <net/tcp.h>
  31. #include <net/route.h>
  32. #include <net/ipv6.h>
  33. #include <net/ip6_route.h>
  34. #include <scsi/iscsi_if.h>
  35. #include "cnic_if.h"
  36. #include "bnx2.h"
  37. #include "cnic.h"
  38. #include "cnic_defs.h"
  39. #define DRV_MODULE_NAME "cnic"
  40. #define PFX DRV_MODULE_NAME ": "
  41. static char version[] __devinitdata =
  42. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  43. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  44. "Chen (zongxi@broadcom.com");
  45. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  46. MODULE_LICENSE("GPL");
  47. MODULE_VERSION(CNIC_MODULE_VERSION);
  48. static LIST_HEAD(cnic_dev_list);
  49. static DEFINE_RWLOCK(cnic_dev_lock);
  50. static DEFINE_MUTEX(cnic_lock);
  51. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  52. static int cnic_service_bnx2(void *, void *);
  53. static int cnic_ctl(void *, struct cnic_ctl_info *);
  54. static struct cnic_ops cnic_bnx2_ops = {
  55. .cnic_owner = THIS_MODULE,
  56. .cnic_handler = cnic_service_bnx2,
  57. .cnic_ctl = cnic_ctl,
  58. };
  59. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *);
  60. static void cnic_init_bnx2_tx_ring(struct cnic_dev *);
  61. static void cnic_init_bnx2_rx_ring(struct cnic_dev *);
  62. static int cnic_cm_set_pg(struct cnic_sock *);
  63. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  64. {
  65. struct cnic_dev *dev = uinfo->priv;
  66. struct cnic_local *cp = dev->cnic_priv;
  67. if (!capable(CAP_NET_ADMIN))
  68. return -EPERM;
  69. if (cp->uio_dev != -1)
  70. return -EBUSY;
  71. cp->uio_dev = iminor(inode);
  72. cnic_shutdown_bnx2_rx_ring(dev);
  73. cnic_init_bnx2_tx_ring(dev);
  74. cnic_init_bnx2_rx_ring(dev);
  75. return 0;
  76. }
  77. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  78. {
  79. struct cnic_dev *dev = uinfo->priv;
  80. struct cnic_local *cp = dev->cnic_priv;
  81. cp->uio_dev = -1;
  82. return 0;
  83. }
  84. static inline void cnic_hold(struct cnic_dev *dev)
  85. {
  86. atomic_inc(&dev->ref_count);
  87. }
  88. static inline void cnic_put(struct cnic_dev *dev)
  89. {
  90. atomic_dec(&dev->ref_count);
  91. }
  92. static inline void csk_hold(struct cnic_sock *csk)
  93. {
  94. atomic_inc(&csk->ref_count);
  95. }
  96. static inline void csk_put(struct cnic_sock *csk)
  97. {
  98. atomic_dec(&csk->ref_count);
  99. }
  100. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  101. {
  102. struct cnic_dev *cdev;
  103. read_lock(&cnic_dev_lock);
  104. list_for_each_entry(cdev, &cnic_dev_list, list) {
  105. if (netdev == cdev->netdev) {
  106. cnic_hold(cdev);
  107. read_unlock(&cnic_dev_lock);
  108. return cdev;
  109. }
  110. }
  111. read_unlock(&cnic_dev_lock);
  112. return NULL;
  113. }
  114. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  115. {
  116. struct cnic_local *cp = dev->cnic_priv;
  117. struct cnic_eth_dev *ethdev = cp->ethdev;
  118. struct drv_ctl_info info;
  119. struct drv_ctl_io *io = &info.data.io;
  120. info.cmd = DRV_CTL_CTX_WR_CMD;
  121. io->cid_addr = cid_addr;
  122. io->offset = off;
  123. io->data = val;
  124. ethdev->drv_ctl(dev->netdev, &info);
  125. }
  126. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  127. {
  128. struct cnic_local *cp = dev->cnic_priv;
  129. struct cnic_eth_dev *ethdev = cp->ethdev;
  130. struct drv_ctl_info info;
  131. struct drv_ctl_io *io = &info.data.io;
  132. info.cmd = DRV_CTL_IO_WR_CMD;
  133. io->offset = off;
  134. io->data = val;
  135. ethdev->drv_ctl(dev->netdev, &info);
  136. }
  137. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  138. {
  139. struct cnic_local *cp = dev->cnic_priv;
  140. struct cnic_eth_dev *ethdev = cp->ethdev;
  141. struct drv_ctl_info info;
  142. struct drv_ctl_io *io = &info.data.io;
  143. info.cmd = DRV_CTL_IO_RD_CMD;
  144. io->offset = off;
  145. ethdev->drv_ctl(dev->netdev, &info);
  146. return io->data;
  147. }
  148. static int cnic_in_use(struct cnic_sock *csk)
  149. {
  150. return test_bit(SK_F_INUSE, &csk->flags);
  151. }
  152. static void cnic_kwq_completion(struct cnic_dev *dev, u32 count)
  153. {
  154. struct cnic_local *cp = dev->cnic_priv;
  155. struct cnic_eth_dev *ethdev = cp->ethdev;
  156. struct drv_ctl_info info;
  157. info.cmd = DRV_CTL_COMPLETION_CMD;
  158. info.data.comp.comp_count = count;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  162. struct cnic_sock *csk)
  163. {
  164. struct iscsi_path path_req;
  165. char *buf = NULL;
  166. u16 len = 0;
  167. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  168. struct cnic_ulp_ops *ulp_ops;
  169. if (cp->uio_dev == -1)
  170. return -ENODEV;
  171. if (csk) {
  172. len = sizeof(path_req);
  173. buf = (char *) &path_req;
  174. memset(&path_req, 0, len);
  175. msg_type = ISCSI_KEVENT_PATH_REQ;
  176. path_req.handle = (u64) csk->l5_cid;
  177. if (test_bit(SK_F_IPV6, &csk->flags)) {
  178. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  179. sizeof(struct in6_addr));
  180. path_req.ip_addr_len = 16;
  181. } else {
  182. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  183. sizeof(struct in_addr));
  184. path_req.ip_addr_len = 4;
  185. }
  186. path_req.vlan_id = csk->vlan_id;
  187. path_req.pmtu = csk->mtu;
  188. }
  189. rcu_read_lock();
  190. ulp_ops = rcu_dereference(cp->ulp_ops[CNIC_ULP_ISCSI]);
  191. if (ulp_ops)
  192. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  193. rcu_read_unlock();
  194. return 0;
  195. }
  196. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  197. char *buf, u16 len)
  198. {
  199. int rc = -EINVAL;
  200. switch (msg_type) {
  201. case ISCSI_UEVENT_PATH_UPDATE: {
  202. struct cnic_local *cp;
  203. u32 l5_cid;
  204. struct cnic_sock *csk;
  205. struct iscsi_path *path_resp;
  206. if (len < sizeof(*path_resp))
  207. break;
  208. path_resp = (struct iscsi_path *) buf;
  209. cp = dev->cnic_priv;
  210. l5_cid = (u32) path_resp->handle;
  211. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  212. break;
  213. csk = &cp->csk_tbl[l5_cid];
  214. csk_hold(csk);
  215. if (cnic_in_use(csk)) {
  216. memcpy(csk->ha, path_resp->mac_addr, 6);
  217. if (test_bit(SK_F_IPV6, &csk->flags))
  218. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  219. sizeof(struct in6_addr));
  220. else
  221. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  222. sizeof(struct in_addr));
  223. if (is_valid_ether_addr(csk->ha))
  224. cnic_cm_set_pg(csk);
  225. }
  226. csk_put(csk);
  227. rc = 0;
  228. }
  229. }
  230. return rc;
  231. }
  232. static int cnic_offld_prep(struct cnic_sock *csk)
  233. {
  234. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  235. return 0;
  236. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  237. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  238. return 0;
  239. }
  240. return 1;
  241. }
  242. static int cnic_close_prep(struct cnic_sock *csk)
  243. {
  244. clear_bit(SK_F_CONNECT_START, &csk->flags);
  245. smp_mb__after_clear_bit();
  246. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  247. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  248. msleep(1);
  249. return 1;
  250. }
  251. return 0;
  252. }
  253. static int cnic_abort_prep(struct cnic_sock *csk)
  254. {
  255. clear_bit(SK_F_CONNECT_START, &csk->flags);
  256. smp_mb__after_clear_bit();
  257. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  258. msleep(1);
  259. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  260. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  261. return 1;
  262. }
  263. return 0;
  264. }
  265. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  266. {
  267. struct cnic_dev *dev;
  268. if (ulp_type >= MAX_CNIC_ULP_TYPE) {
  269. printk(KERN_ERR PFX "cnic_register_driver: Bad type %d\n",
  270. ulp_type);
  271. return -EINVAL;
  272. }
  273. mutex_lock(&cnic_lock);
  274. if (cnic_ulp_tbl[ulp_type]) {
  275. printk(KERN_ERR PFX "cnic_register_driver: Type %d has already "
  276. "been registered\n", ulp_type);
  277. mutex_unlock(&cnic_lock);
  278. return -EBUSY;
  279. }
  280. read_lock(&cnic_dev_lock);
  281. list_for_each_entry(dev, &cnic_dev_list, list) {
  282. struct cnic_local *cp = dev->cnic_priv;
  283. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  284. }
  285. read_unlock(&cnic_dev_lock);
  286. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  287. mutex_unlock(&cnic_lock);
  288. /* Prevent race conditions with netdev_event */
  289. rtnl_lock();
  290. read_lock(&cnic_dev_lock);
  291. list_for_each_entry(dev, &cnic_dev_list, list) {
  292. struct cnic_local *cp = dev->cnic_priv;
  293. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  294. ulp_ops->cnic_init(dev);
  295. }
  296. read_unlock(&cnic_dev_lock);
  297. rtnl_unlock();
  298. return 0;
  299. }
  300. int cnic_unregister_driver(int ulp_type)
  301. {
  302. struct cnic_dev *dev;
  303. if (ulp_type >= MAX_CNIC_ULP_TYPE) {
  304. printk(KERN_ERR PFX "cnic_unregister_driver: Bad type %d\n",
  305. ulp_type);
  306. return -EINVAL;
  307. }
  308. mutex_lock(&cnic_lock);
  309. if (!cnic_ulp_tbl[ulp_type]) {
  310. printk(KERN_ERR PFX "cnic_unregister_driver: Type %d has not "
  311. "been registered\n", ulp_type);
  312. goto out_unlock;
  313. }
  314. read_lock(&cnic_dev_lock);
  315. list_for_each_entry(dev, &cnic_dev_list, list) {
  316. struct cnic_local *cp = dev->cnic_priv;
  317. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  318. printk(KERN_ERR PFX "cnic_unregister_driver: Type %d "
  319. "still has devices registered\n", ulp_type);
  320. read_unlock(&cnic_dev_lock);
  321. goto out_unlock;
  322. }
  323. }
  324. read_unlock(&cnic_dev_lock);
  325. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  326. mutex_unlock(&cnic_lock);
  327. synchronize_rcu();
  328. return 0;
  329. out_unlock:
  330. mutex_unlock(&cnic_lock);
  331. return -EINVAL;
  332. }
  333. static int cnic_start_hw(struct cnic_dev *);
  334. static void cnic_stop_hw(struct cnic_dev *);
  335. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  336. void *ulp_ctx)
  337. {
  338. struct cnic_local *cp = dev->cnic_priv;
  339. struct cnic_ulp_ops *ulp_ops;
  340. if (ulp_type >= MAX_CNIC_ULP_TYPE) {
  341. printk(KERN_ERR PFX "cnic_register_device: Bad type %d\n",
  342. ulp_type);
  343. return -EINVAL;
  344. }
  345. mutex_lock(&cnic_lock);
  346. if (cnic_ulp_tbl[ulp_type] == NULL) {
  347. printk(KERN_ERR PFX "cnic_register_device: Driver with type %d "
  348. "has not been registered\n", ulp_type);
  349. mutex_unlock(&cnic_lock);
  350. return -EAGAIN;
  351. }
  352. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  353. printk(KERN_ERR PFX "cnic_register_device: Type %d has already "
  354. "been registered to this device\n", ulp_type);
  355. mutex_unlock(&cnic_lock);
  356. return -EBUSY;
  357. }
  358. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  359. cp->ulp_handle[ulp_type] = ulp_ctx;
  360. ulp_ops = cnic_ulp_tbl[ulp_type];
  361. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  362. cnic_hold(dev);
  363. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  364. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  365. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  366. mutex_unlock(&cnic_lock);
  367. return 0;
  368. }
  369. EXPORT_SYMBOL(cnic_register_driver);
  370. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  371. {
  372. struct cnic_local *cp = dev->cnic_priv;
  373. if (ulp_type >= MAX_CNIC_ULP_TYPE) {
  374. printk(KERN_ERR PFX "cnic_unregister_device: Bad type %d\n",
  375. ulp_type);
  376. return -EINVAL;
  377. }
  378. mutex_lock(&cnic_lock);
  379. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  380. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  381. cnic_put(dev);
  382. } else {
  383. printk(KERN_ERR PFX "cnic_unregister_device: device not "
  384. "registered to this ulp type %d\n", ulp_type);
  385. mutex_unlock(&cnic_lock);
  386. return -EINVAL;
  387. }
  388. mutex_unlock(&cnic_lock);
  389. synchronize_rcu();
  390. return 0;
  391. }
  392. EXPORT_SYMBOL(cnic_unregister_driver);
  393. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  394. {
  395. id_tbl->start = start_id;
  396. id_tbl->max = size;
  397. id_tbl->next = 0;
  398. spin_lock_init(&id_tbl->lock);
  399. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  400. if (!id_tbl->table)
  401. return -ENOMEM;
  402. return 0;
  403. }
  404. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  405. {
  406. kfree(id_tbl->table);
  407. id_tbl->table = NULL;
  408. }
  409. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  410. {
  411. int ret = -1;
  412. id -= id_tbl->start;
  413. if (id >= id_tbl->max)
  414. return ret;
  415. spin_lock(&id_tbl->lock);
  416. if (!test_bit(id, id_tbl->table)) {
  417. set_bit(id, id_tbl->table);
  418. ret = 0;
  419. }
  420. spin_unlock(&id_tbl->lock);
  421. return ret;
  422. }
  423. /* Returns -1 if not successful */
  424. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  425. {
  426. u32 id;
  427. spin_lock(&id_tbl->lock);
  428. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  429. if (id >= id_tbl->max) {
  430. id = -1;
  431. if (id_tbl->next != 0) {
  432. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  433. if (id >= id_tbl->next)
  434. id = -1;
  435. }
  436. }
  437. if (id < id_tbl->max) {
  438. set_bit(id, id_tbl->table);
  439. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  440. id += id_tbl->start;
  441. }
  442. spin_unlock(&id_tbl->lock);
  443. return id;
  444. }
  445. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  446. {
  447. if (id == -1)
  448. return;
  449. id -= id_tbl->start;
  450. if (id >= id_tbl->max)
  451. return;
  452. clear_bit(id, id_tbl->table);
  453. }
  454. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  455. {
  456. int i;
  457. if (!dma->pg_arr)
  458. return;
  459. for (i = 0; i < dma->num_pages; i++) {
  460. if (dma->pg_arr[i]) {
  461. pci_free_consistent(dev->pcidev, BCM_PAGE_SIZE,
  462. dma->pg_arr[i], dma->pg_map_arr[i]);
  463. dma->pg_arr[i] = NULL;
  464. }
  465. }
  466. if (dma->pgtbl) {
  467. pci_free_consistent(dev->pcidev, dma->pgtbl_size,
  468. dma->pgtbl, dma->pgtbl_map);
  469. dma->pgtbl = NULL;
  470. }
  471. kfree(dma->pg_arr);
  472. dma->pg_arr = NULL;
  473. dma->num_pages = 0;
  474. }
  475. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  476. {
  477. int i;
  478. u32 *page_table = dma->pgtbl;
  479. for (i = 0; i < dma->num_pages; i++) {
  480. /* Each entry needs to be in big endian format. */
  481. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  482. page_table++;
  483. *page_table = (u32) dma->pg_map_arr[i];
  484. page_table++;
  485. }
  486. }
  487. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  488. int pages, int use_pg_tbl)
  489. {
  490. int i, size;
  491. struct cnic_local *cp = dev->cnic_priv;
  492. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  493. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  494. if (dma->pg_arr == NULL)
  495. return -ENOMEM;
  496. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  497. dma->num_pages = pages;
  498. for (i = 0; i < pages; i++) {
  499. dma->pg_arr[i] = pci_alloc_consistent(dev->pcidev,
  500. BCM_PAGE_SIZE,
  501. &dma->pg_map_arr[i]);
  502. if (dma->pg_arr[i] == NULL)
  503. goto error;
  504. }
  505. if (!use_pg_tbl)
  506. return 0;
  507. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  508. ~(BCM_PAGE_SIZE - 1);
  509. dma->pgtbl = pci_alloc_consistent(dev->pcidev, dma->pgtbl_size,
  510. &dma->pgtbl_map);
  511. if (dma->pgtbl == NULL)
  512. goto error;
  513. cp->setup_pgtbl(dev, dma);
  514. return 0;
  515. error:
  516. cnic_free_dma(dev, dma);
  517. return -ENOMEM;
  518. }
  519. static void cnic_free_resc(struct cnic_dev *dev)
  520. {
  521. struct cnic_local *cp = dev->cnic_priv;
  522. int i = 0;
  523. if (cp->cnic_uinfo) {
  524. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  525. while (cp->uio_dev != -1 && i < 15) {
  526. msleep(100);
  527. i++;
  528. }
  529. uio_unregister_device(cp->cnic_uinfo);
  530. kfree(cp->cnic_uinfo);
  531. cp->cnic_uinfo = NULL;
  532. }
  533. if (cp->l2_buf) {
  534. pci_free_consistent(dev->pcidev, cp->l2_buf_size,
  535. cp->l2_buf, cp->l2_buf_map);
  536. cp->l2_buf = NULL;
  537. }
  538. if (cp->l2_ring) {
  539. pci_free_consistent(dev->pcidev, cp->l2_ring_size,
  540. cp->l2_ring, cp->l2_ring_map);
  541. cp->l2_ring = NULL;
  542. }
  543. for (i = 0; i < cp->ctx_blks; i++) {
  544. if (cp->ctx_arr[i].ctx) {
  545. pci_free_consistent(dev->pcidev, cp->ctx_blk_size,
  546. cp->ctx_arr[i].ctx,
  547. cp->ctx_arr[i].mapping);
  548. cp->ctx_arr[i].ctx = NULL;
  549. }
  550. }
  551. kfree(cp->ctx_arr);
  552. cp->ctx_arr = NULL;
  553. cp->ctx_blks = 0;
  554. cnic_free_dma(dev, &cp->gbl_buf_info);
  555. cnic_free_dma(dev, &cp->conn_buf_info);
  556. cnic_free_dma(dev, &cp->kwq_info);
  557. cnic_free_dma(dev, &cp->kcq_info);
  558. kfree(cp->iscsi_tbl);
  559. cp->iscsi_tbl = NULL;
  560. kfree(cp->ctx_tbl);
  561. cp->ctx_tbl = NULL;
  562. cnic_free_id_tbl(&cp->cid_tbl);
  563. }
  564. static int cnic_alloc_context(struct cnic_dev *dev)
  565. {
  566. struct cnic_local *cp = dev->cnic_priv;
  567. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  568. int i, k, arr_size;
  569. cp->ctx_blk_size = BCM_PAGE_SIZE;
  570. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  571. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  572. sizeof(struct cnic_ctx);
  573. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  574. if (cp->ctx_arr == NULL)
  575. return -ENOMEM;
  576. k = 0;
  577. for (i = 0; i < 2; i++) {
  578. u32 j, reg, off, lo, hi;
  579. if (i == 0)
  580. off = BNX2_PG_CTX_MAP;
  581. else
  582. off = BNX2_ISCSI_CTX_MAP;
  583. reg = cnic_reg_rd_ind(dev, off);
  584. lo = reg >> 16;
  585. hi = reg & 0xffff;
  586. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  587. cp->ctx_arr[k].cid = j;
  588. }
  589. cp->ctx_blks = k;
  590. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  591. cp->ctx_blks = 0;
  592. return -ENOMEM;
  593. }
  594. for (i = 0; i < cp->ctx_blks; i++) {
  595. cp->ctx_arr[i].ctx =
  596. pci_alloc_consistent(dev->pcidev, BCM_PAGE_SIZE,
  597. &cp->ctx_arr[i].mapping);
  598. if (cp->ctx_arr[i].ctx == NULL)
  599. return -ENOMEM;
  600. }
  601. }
  602. return 0;
  603. }
  604. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  605. {
  606. struct cnic_local *cp = dev->cnic_priv;
  607. struct uio_info *uinfo;
  608. int ret;
  609. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  610. if (ret)
  611. goto error;
  612. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  613. ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 1);
  614. if (ret)
  615. goto error;
  616. cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
  617. ret = cnic_alloc_context(dev);
  618. if (ret)
  619. goto error;
  620. cp->l2_ring_size = 2 * BCM_PAGE_SIZE;
  621. cp->l2_ring = pci_alloc_consistent(dev->pcidev, cp->l2_ring_size,
  622. &cp->l2_ring_map);
  623. if (!cp->l2_ring)
  624. goto error;
  625. cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  626. cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
  627. cp->l2_buf = pci_alloc_consistent(dev->pcidev, cp->l2_buf_size,
  628. &cp->l2_buf_map);
  629. if (!cp->l2_buf)
  630. goto error;
  631. uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
  632. if (!uinfo)
  633. goto error;
  634. uinfo->mem[0].addr = dev->netdev->base_addr;
  635. uinfo->mem[0].internal_addr = dev->regview;
  636. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  637. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  638. uinfo->mem[1].addr = (unsigned long) cp->status_blk & PAGE_MASK;
  639. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  640. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  641. else
  642. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  643. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  644. uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
  645. uinfo->mem[2].size = cp->l2_ring_size;
  646. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  647. uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
  648. uinfo->mem[3].size = cp->l2_buf_size;
  649. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  650. uinfo->name = "bnx2_cnic";
  651. uinfo->version = CNIC_MODULE_VERSION;
  652. uinfo->irq = UIO_IRQ_CUSTOM;
  653. uinfo->open = cnic_uio_open;
  654. uinfo->release = cnic_uio_close;
  655. uinfo->priv = dev;
  656. ret = uio_register_device(&dev->pcidev->dev, uinfo);
  657. if (ret) {
  658. kfree(uinfo);
  659. goto error;
  660. }
  661. cp->cnic_uinfo = uinfo;
  662. return 0;
  663. error:
  664. cnic_free_resc(dev);
  665. return ret;
  666. }
  667. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  668. {
  669. return cp->max_kwq_idx -
  670. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  671. }
  672. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  673. u32 num_wqes)
  674. {
  675. struct cnic_local *cp = dev->cnic_priv;
  676. struct kwqe *prod_qe;
  677. u16 prod, sw_prod, i;
  678. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  679. return -EAGAIN; /* bnx2 is down */
  680. spin_lock_bh(&cp->cnic_ulp_lock);
  681. if (num_wqes > cnic_kwq_avail(cp) &&
  682. !(cp->cnic_local_flags & CNIC_LCL_FL_KWQ_INIT)) {
  683. spin_unlock_bh(&cp->cnic_ulp_lock);
  684. return -EAGAIN;
  685. }
  686. cp->cnic_local_flags &= ~CNIC_LCL_FL_KWQ_INIT;
  687. prod = cp->kwq_prod_idx;
  688. sw_prod = prod & MAX_KWQ_IDX;
  689. for (i = 0; i < num_wqes; i++) {
  690. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  691. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  692. prod++;
  693. sw_prod = prod & MAX_KWQ_IDX;
  694. }
  695. cp->kwq_prod_idx = prod;
  696. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  697. spin_unlock_bh(&cp->cnic_ulp_lock);
  698. return 0;
  699. }
  700. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  701. {
  702. struct cnic_local *cp = dev->cnic_priv;
  703. int i, j;
  704. i = 0;
  705. j = 1;
  706. while (num_cqes) {
  707. struct cnic_ulp_ops *ulp_ops;
  708. int ulp_type;
  709. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  710. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  711. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  712. cnic_kwq_completion(dev, 1);
  713. while (j < num_cqes) {
  714. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  715. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  716. break;
  717. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  718. cnic_kwq_completion(dev, 1);
  719. j++;
  720. }
  721. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  722. ulp_type = CNIC_ULP_RDMA;
  723. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  724. ulp_type = CNIC_ULP_ISCSI;
  725. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  726. ulp_type = CNIC_ULP_L4;
  727. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  728. goto end;
  729. else {
  730. printk(KERN_ERR PFX "%s: Unknown type of KCQE(0x%x)\n",
  731. dev->netdev->name, kcqe_op_flag);
  732. goto end;
  733. }
  734. rcu_read_lock();
  735. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  736. if (likely(ulp_ops)) {
  737. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  738. cp->completed_kcq + i, j);
  739. }
  740. rcu_read_unlock();
  741. end:
  742. num_cqes -= j;
  743. i += j;
  744. j = 1;
  745. }
  746. return;
  747. }
  748. static u16 cnic_bnx2_next_idx(u16 idx)
  749. {
  750. return idx + 1;
  751. }
  752. static u16 cnic_bnx2_hw_idx(u16 idx)
  753. {
  754. return idx;
  755. }
  756. static int cnic_get_kcqes(struct cnic_dev *dev, u16 hw_prod, u16 *sw_prod)
  757. {
  758. struct cnic_local *cp = dev->cnic_priv;
  759. u16 i, ri, last;
  760. struct kcqe *kcqe;
  761. int kcqe_cnt = 0, last_cnt = 0;
  762. i = ri = last = *sw_prod;
  763. ri &= MAX_KCQ_IDX;
  764. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  765. kcqe = &cp->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  766. cp->completed_kcq[kcqe_cnt++] = kcqe;
  767. i = cp->next_idx(i);
  768. ri = i & MAX_KCQ_IDX;
  769. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  770. last_cnt = kcqe_cnt;
  771. last = i;
  772. }
  773. }
  774. *sw_prod = last;
  775. return last_cnt;
  776. }
  777. static void cnic_chk_bnx2_pkt_rings(struct cnic_local *cp)
  778. {
  779. u16 rx_cons = *cp->rx_cons_ptr;
  780. u16 tx_cons = *cp->tx_cons_ptr;
  781. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  782. cp->tx_cons = tx_cons;
  783. cp->rx_cons = rx_cons;
  784. uio_event_notify(cp->cnic_uinfo);
  785. }
  786. }
  787. static int cnic_service_bnx2(void *data, void *status_blk)
  788. {
  789. struct cnic_dev *dev = data;
  790. struct status_block *sblk = status_blk;
  791. struct cnic_local *cp = dev->cnic_priv;
  792. u32 status_idx = sblk->status_idx;
  793. u16 hw_prod, sw_prod;
  794. int kcqe_cnt;
  795. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  796. return status_idx;
  797. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  798. hw_prod = sblk->status_completion_producer_index;
  799. sw_prod = cp->kcq_prod_idx;
  800. while (sw_prod != hw_prod) {
  801. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  802. if (kcqe_cnt == 0)
  803. goto done;
  804. service_kcqes(dev, kcqe_cnt);
  805. /* Tell compiler that status_blk fields can change. */
  806. barrier();
  807. if (status_idx != sblk->status_idx) {
  808. status_idx = sblk->status_idx;
  809. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  810. hw_prod = sblk->status_completion_producer_index;
  811. } else
  812. break;
  813. }
  814. done:
  815. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  816. cp->kcq_prod_idx = sw_prod;
  817. cnic_chk_bnx2_pkt_rings(cp);
  818. return status_idx;
  819. }
  820. static void cnic_service_bnx2_msix(unsigned long data)
  821. {
  822. struct cnic_dev *dev = (struct cnic_dev *) data;
  823. struct cnic_local *cp = dev->cnic_priv;
  824. struct status_block_msix *status_blk = cp->bnx2_status_blk;
  825. u32 status_idx = status_blk->status_idx;
  826. u16 hw_prod, sw_prod;
  827. int kcqe_cnt;
  828. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  829. hw_prod = status_blk->status_completion_producer_index;
  830. sw_prod = cp->kcq_prod_idx;
  831. while (sw_prod != hw_prod) {
  832. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  833. if (kcqe_cnt == 0)
  834. goto done;
  835. service_kcqes(dev, kcqe_cnt);
  836. /* Tell compiler that status_blk fields can change. */
  837. barrier();
  838. if (status_idx != status_blk->status_idx) {
  839. status_idx = status_blk->status_idx;
  840. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  841. hw_prod = status_blk->status_completion_producer_index;
  842. } else
  843. break;
  844. }
  845. done:
  846. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  847. cp->kcq_prod_idx = sw_prod;
  848. cnic_chk_bnx2_pkt_rings(cp);
  849. cp->last_status_idx = status_idx;
  850. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  851. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  852. }
  853. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  854. {
  855. struct cnic_dev *dev = dev_instance;
  856. struct cnic_local *cp = dev->cnic_priv;
  857. u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
  858. if (cp->ack_int)
  859. cp->ack_int(dev);
  860. prefetch(cp->status_blk);
  861. prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  862. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  863. tasklet_schedule(&cp->cnic_irq_task);
  864. return IRQ_HANDLED;
  865. }
  866. static void cnic_ulp_stop(struct cnic_dev *dev)
  867. {
  868. struct cnic_local *cp = dev->cnic_priv;
  869. int if_type;
  870. rcu_read_lock();
  871. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  872. struct cnic_ulp_ops *ulp_ops;
  873. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  874. if (!ulp_ops)
  875. continue;
  876. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  877. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  878. }
  879. rcu_read_unlock();
  880. }
  881. static void cnic_ulp_start(struct cnic_dev *dev)
  882. {
  883. struct cnic_local *cp = dev->cnic_priv;
  884. int if_type;
  885. rcu_read_lock();
  886. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  887. struct cnic_ulp_ops *ulp_ops;
  888. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  889. if (!ulp_ops || !ulp_ops->cnic_start)
  890. continue;
  891. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  892. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  893. }
  894. rcu_read_unlock();
  895. }
  896. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  897. {
  898. struct cnic_dev *dev = data;
  899. switch (info->cmd) {
  900. case CNIC_CTL_STOP_CMD:
  901. cnic_hold(dev);
  902. mutex_lock(&cnic_lock);
  903. cnic_ulp_stop(dev);
  904. cnic_stop_hw(dev);
  905. mutex_unlock(&cnic_lock);
  906. cnic_put(dev);
  907. break;
  908. case CNIC_CTL_START_CMD:
  909. cnic_hold(dev);
  910. mutex_lock(&cnic_lock);
  911. if (!cnic_start_hw(dev))
  912. cnic_ulp_start(dev);
  913. mutex_unlock(&cnic_lock);
  914. cnic_put(dev);
  915. break;
  916. default:
  917. return -EINVAL;
  918. }
  919. return 0;
  920. }
  921. static void cnic_ulp_init(struct cnic_dev *dev)
  922. {
  923. int i;
  924. struct cnic_local *cp = dev->cnic_priv;
  925. rcu_read_lock();
  926. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  927. struct cnic_ulp_ops *ulp_ops;
  928. ulp_ops = rcu_dereference(cnic_ulp_tbl[i]);
  929. if (!ulp_ops || !ulp_ops->cnic_init)
  930. continue;
  931. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  932. ulp_ops->cnic_init(dev);
  933. }
  934. rcu_read_unlock();
  935. }
  936. static void cnic_ulp_exit(struct cnic_dev *dev)
  937. {
  938. int i;
  939. struct cnic_local *cp = dev->cnic_priv;
  940. rcu_read_lock();
  941. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  942. struct cnic_ulp_ops *ulp_ops;
  943. ulp_ops = rcu_dereference(cnic_ulp_tbl[i]);
  944. if (!ulp_ops || !ulp_ops->cnic_exit)
  945. continue;
  946. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  947. ulp_ops->cnic_exit(dev);
  948. }
  949. rcu_read_unlock();
  950. }
  951. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  952. {
  953. struct cnic_dev *dev = csk->dev;
  954. struct l4_kwq_offload_pg *l4kwqe;
  955. struct kwqe *wqes[1];
  956. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  957. memset(l4kwqe, 0, sizeof(*l4kwqe));
  958. wqes[0] = (struct kwqe *) l4kwqe;
  959. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  960. l4kwqe->flags =
  961. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  962. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  963. l4kwqe->da0 = csk->ha[0];
  964. l4kwqe->da1 = csk->ha[1];
  965. l4kwqe->da2 = csk->ha[2];
  966. l4kwqe->da3 = csk->ha[3];
  967. l4kwqe->da4 = csk->ha[4];
  968. l4kwqe->da5 = csk->ha[5];
  969. l4kwqe->sa0 = dev->mac_addr[0];
  970. l4kwqe->sa1 = dev->mac_addr[1];
  971. l4kwqe->sa2 = dev->mac_addr[2];
  972. l4kwqe->sa3 = dev->mac_addr[3];
  973. l4kwqe->sa4 = dev->mac_addr[4];
  974. l4kwqe->sa5 = dev->mac_addr[5];
  975. l4kwqe->etype = ETH_P_IP;
  976. l4kwqe->ipid_count = DEF_IPID_COUNT;
  977. l4kwqe->host_opaque = csk->l5_cid;
  978. if (csk->vlan_id) {
  979. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  980. l4kwqe->vlan_tag = csk->vlan_id;
  981. l4kwqe->l2hdr_nbytes += 4;
  982. }
  983. return dev->submit_kwqes(dev, wqes, 1);
  984. }
  985. static int cnic_cm_update_pg(struct cnic_sock *csk)
  986. {
  987. struct cnic_dev *dev = csk->dev;
  988. struct l4_kwq_update_pg *l4kwqe;
  989. struct kwqe *wqes[1];
  990. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  991. memset(l4kwqe, 0, sizeof(*l4kwqe));
  992. wqes[0] = (struct kwqe *) l4kwqe;
  993. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  994. l4kwqe->flags =
  995. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  996. l4kwqe->pg_cid = csk->pg_cid;
  997. l4kwqe->da0 = csk->ha[0];
  998. l4kwqe->da1 = csk->ha[1];
  999. l4kwqe->da2 = csk->ha[2];
  1000. l4kwqe->da3 = csk->ha[3];
  1001. l4kwqe->da4 = csk->ha[4];
  1002. l4kwqe->da5 = csk->ha[5];
  1003. l4kwqe->pg_host_opaque = csk->l5_cid;
  1004. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  1005. return dev->submit_kwqes(dev, wqes, 1);
  1006. }
  1007. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  1008. {
  1009. struct cnic_dev *dev = csk->dev;
  1010. struct l4_kwq_upload *l4kwqe;
  1011. struct kwqe *wqes[1];
  1012. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  1013. memset(l4kwqe, 0, sizeof(*l4kwqe));
  1014. wqes[0] = (struct kwqe *) l4kwqe;
  1015. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  1016. l4kwqe->flags =
  1017. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  1018. l4kwqe->cid = csk->pg_cid;
  1019. return dev->submit_kwqes(dev, wqes, 1);
  1020. }
  1021. static int cnic_cm_conn_req(struct cnic_sock *csk)
  1022. {
  1023. struct cnic_dev *dev = csk->dev;
  1024. struct l4_kwq_connect_req1 *l4kwqe1;
  1025. struct l4_kwq_connect_req2 *l4kwqe2;
  1026. struct l4_kwq_connect_req3 *l4kwqe3;
  1027. struct kwqe *wqes[3];
  1028. u8 tcp_flags = 0;
  1029. int num_wqes = 2;
  1030. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  1031. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  1032. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  1033. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  1034. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  1035. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  1036. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  1037. l4kwqe3->flags =
  1038. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  1039. l4kwqe3->ka_timeout = csk->ka_timeout;
  1040. l4kwqe3->ka_interval = csk->ka_interval;
  1041. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  1042. l4kwqe3->tos = csk->tos;
  1043. l4kwqe3->ttl = csk->ttl;
  1044. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  1045. l4kwqe3->pmtu = csk->mtu;
  1046. l4kwqe3->rcv_buf = csk->rcv_buf;
  1047. l4kwqe3->snd_buf = csk->snd_buf;
  1048. l4kwqe3->seed = csk->seed;
  1049. wqes[0] = (struct kwqe *) l4kwqe1;
  1050. if (test_bit(SK_F_IPV6, &csk->flags)) {
  1051. wqes[1] = (struct kwqe *) l4kwqe2;
  1052. wqes[2] = (struct kwqe *) l4kwqe3;
  1053. num_wqes = 3;
  1054. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  1055. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  1056. l4kwqe2->flags =
  1057. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  1058. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  1059. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  1060. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  1061. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  1062. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  1063. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  1064. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  1065. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  1066. sizeof(struct tcphdr);
  1067. } else {
  1068. wqes[1] = (struct kwqe *) l4kwqe3;
  1069. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  1070. sizeof(struct tcphdr);
  1071. }
  1072. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  1073. l4kwqe1->flags =
  1074. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  1075. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  1076. l4kwqe1->cid = csk->cid;
  1077. l4kwqe1->pg_cid = csk->pg_cid;
  1078. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  1079. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  1080. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  1081. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  1082. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  1083. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  1084. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  1085. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  1086. if (csk->tcp_flags & SK_TCP_NAGLE)
  1087. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  1088. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  1089. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  1090. if (csk->tcp_flags & SK_TCP_SACK)
  1091. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  1092. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  1093. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  1094. l4kwqe1->tcp_flags = tcp_flags;
  1095. return dev->submit_kwqes(dev, wqes, num_wqes);
  1096. }
  1097. static int cnic_cm_close_req(struct cnic_sock *csk)
  1098. {
  1099. struct cnic_dev *dev = csk->dev;
  1100. struct l4_kwq_close_req *l4kwqe;
  1101. struct kwqe *wqes[1];
  1102. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  1103. memset(l4kwqe, 0, sizeof(*l4kwqe));
  1104. wqes[0] = (struct kwqe *) l4kwqe;
  1105. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  1106. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  1107. l4kwqe->cid = csk->cid;
  1108. return dev->submit_kwqes(dev, wqes, 1);
  1109. }
  1110. static int cnic_cm_abort_req(struct cnic_sock *csk)
  1111. {
  1112. struct cnic_dev *dev = csk->dev;
  1113. struct l4_kwq_reset_req *l4kwqe;
  1114. struct kwqe *wqes[1];
  1115. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  1116. memset(l4kwqe, 0, sizeof(*l4kwqe));
  1117. wqes[0] = (struct kwqe *) l4kwqe;
  1118. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  1119. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  1120. l4kwqe->cid = csk->cid;
  1121. return dev->submit_kwqes(dev, wqes, 1);
  1122. }
  1123. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  1124. u32 l5_cid, struct cnic_sock **csk, void *context)
  1125. {
  1126. struct cnic_local *cp = dev->cnic_priv;
  1127. struct cnic_sock *csk1;
  1128. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  1129. return -EINVAL;
  1130. csk1 = &cp->csk_tbl[l5_cid];
  1131. if (atomic_read(&csk1->ref_count))
  1132. return -EAGAIN;
  1133. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  1134. return -EBUSY;
  1135. csk1->dev = dev;
  1136. csk1->cid = cid;
  1137. csk1->l5_cid = l5_cid;
  1138. csk1->ulp_type = ulp_type;
  1139. csk1->context = context;
  1140. csk1->ka_timeout = DEF_KA_TIMEOUT;
  1141. csk1->ka_interval = DEF_KA_INTERVAL;
  1142. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  1143. csk1->tos = DEF_TOS;
  1144. csk1->ttl = DEF_TTL;
  1145. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  1146. csk1->rcv_buf = DEF_RCV_BUF;
  1147. csk1->snd_buf = DEF_SND_BUF;
  1148. csk1->seed = DEF_SEED;
  1149. *csk = csk1;
  1150. return 0;
  1151. }
  1152. static void cnic_cm_cleanup(struct cnic_sock *csk)
  1153. {
  1154. if (csk->src_port) {
  1155. struct cnic_dev *dev = csk->dev;
  1156. struct cnic_local *cp = dev->cnic_priv;
  1157. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  1158. csk->src_port = 0;
  1159. }
  1160. }
  1161. static void cnic_close_conn(struct cnic_sock *csk)
  1162. {
  1163. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  1164. cnic_cm_upload_pg(csk);
  1165. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  1166. }
  1167. cnic_cm_cleanup(csk);
  1168. }
  1169. static int cnic_cm_destroy(struct cnic_sock *csk)
  1170. {
  1171. if (!cnic_in_use(csk))
  1172. return -EINVAL;
  1173. csk_hold(csk);
  1174. clear_bit(SK_F_INUSE, &csk->flags);
  1175. smp_mb__after_clear_bit();
  1176. while (atomic_read(&csk->ref_count) != 1)
  1177. msleep(1);
  1178. cnic_cm_cleanup(csk);
  1179. csk->flags = 0;
  1180. csk_put(csk);
  1181. return 0;
  1182. }
  1183. static inline u16 cnic_get_vlan(struct net_device *dev,
  1184. struct net_device **vlan_dev)
  1185. {
  1186. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  1187. *vlan_dev = vlan_dev_real_dev(dev);
  1188. return vlan_dev_vlan_id(dev);
  1189. }
  1190. *vlan_dev = dev;
  1191. return 0;
  1192. }
  1193. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  1194. struct dst_entry **dst)
  1195. {
  1196. #if defined(CONFIG_INET)
  1197. struct flowi fl;
  1198. int err;
  1199. struct rtable *rt;
  1200. memset(&fl, 0, sizeof(fl));
  1201. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  1202. err = ip_route_output_key(&init_net, &rt, &fl);
  1203. if (!err)
  1204. *dst = &rt->u.dst;
  1205. return err;
  1206. #else
  1207. return -ENETUNREACH;
  1208. #endif
  1209. }
  1210. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  1211. struct dst_entry **dst)
  1212. {
  1213. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  1214. struct flowi fl;
  1215. memset(&fl, 0, sizeof(fl));
  1216. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  1217. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  1218. fl.oif = dst_addr->sin6_scope_id;
  1219. *dst = ip6_route_output(&init_net, NULL, &fl);
  1220. if (*dst)
  1221. return 0;
  1222. #endif
  1223. return -ENETUNREACH;
  1224. }
  1225. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  1226. int ulp_type)
  1227. {
  1228. struct cnic_dev *dev = NULL;
  1229. struct dst_entry *dst;
  1230. struct net_device *netdev = NULL;
  1231. int err = -ENETUNREACH;
  1232. if (dst_addr->sin_family == AF_INET)
  1233. err = cnic_get_v4_route(dst_addr, &dst);
  1234. else if (dst_addr->sin_family == AF_INET6) {
  1235. struct sockaddr_in6 *dst_addr6 =
  1236. (struct sockaddr_in6 *) dst_addr;
  1237. err = cnic_get_v6_route(dst_addr6, &dst);
  1238. } else
  1239. return NULL;
  1240. if (err)
  1241. return NULL;
  1242. if (!dst->dev)
  1243. goto done;
  1244. cnic_get_vlan(dst->dev, &netdev);
  1245. dev = cnic_from_netdev(netdev);
  1246. done:
  1247. dst_release(dst);
  1248. if (dev)
  1249. cnic_put(dev);
  1250. return dev;
  1251. }
  1252. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  1253. {
  1254. struct cnic_dev *dev = csk->dev;
  1255. struct cnic_local *cp = dev->cnic_priv;
  1256. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  1257. }
  1258. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  1259. {
  1260. struct cnic_dev *dev = csk->dev;
  1261. struct cnic_local *cp = dev->cnic_priv;
  1262. int is_v6, err, rc = -ENETUNREACH;
  1263. struct dst_entry *dst;
  1264. struct net_device *realdev;
  1265. u32 local_port;
  1266. if (saddr->local.v6.sin6_family == AF_INET6 &&
  1267. saddr->remote.v6.sin6_family == AF_INET6)
  1268. is_v6 = 1;
  1269. else if (saddr->local.v4.sin_family == AF_INET &&
  1270. saddr->remote.v4.sin_family == AF_INET)
  1271. is_v6 = 0;
  1272. else
  1273. return -EINVAL;
  1274. clear_bit(SK_F_IPV6, &csk->flags);
  1275. if (is_v6) {
  1276. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  1277. set_bit(SK_F_IPV6, &csk->flags);
  1278. err = cnic_get_v6_route(&saddr->remote.v6, &dst);
  1279. if (err)
  1280. return err;
  1281. if (!dst || dst->error || !dst->dev)
  1282. goto err_out;
  1283. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  1284. sizeof(struct in6_addr));
  1285. csk->dst_port = saddr->remote.v6.sin6_port;
  1286. local_port = saddr->local.v6.sin6_port;
  1287. #else
  1288. return rc;
  1289. #endif
  1290. } else {
  1291. err = cnic_get_v4_route(&saddr->remote.v4, &dst);
  1292. if (err)
  1293. return err;
  1294. if (!dst || dst->error || !dst->dev)
  1295. goto err_out;
  1296. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  1297. csk->dst_port = saddr->remote.v4.sin_port;
  1298. local_port = saddr->local.v4.sin_port;
  1299. }
  1300. csk->vlan_id = cnic_get_vlan(dst->dev, &realdev);
  1301. if (realdev != dev->netdev)
  1302. goto err_out;
  1303. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  1304. local_port < CNIC_LOCAL_PORT_MAX) {
  1305. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  1306. local_port = 0;
  1307. } else
  1308. local_port = 0;
  1309. if (!local_port) {
  1310. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  1311. if (local_port == -1) {
  1312. rc = -ENOMEM;
  1313. goto err_out;
  1314. }
  1315. }
  1316. csk->src_port = local_port;
  1317. csk->mtu = dst_mtu(dst);
  1318. rc = 0;
  1319. err_out:
  1320. dst_release(dst);
  1321. return rc;
  1322. }
  1323. static void cnic_init_csk_state(struct cnic_sock *csk)
  1324. {
  1325. csk->state = 0;
  1326. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  1327. clear_bit(SK_F_CLOSING, &csk->flags);
  1328. }
  1329. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  1330. {
  1331. int err = 0;
  1332. if (!cnic_in_use(csk))
  1333. return -EINVAL;
  1334. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  1335. return -EINVAL;
  1336. cnic_init_csk_state(csk);
  1337. err = cnic_get_route(csk, saddr);
  1338. if (err)
  1339. goto err_out;
  1340. err = cnic_resolve_addr(csk, saddr);
  1341. if (!err)
  1342. return 0;
  1343. err_out:
  1344. clear_bit(SK_F_CONNECT_START, &csk->flags);
  1345. return err;
  1346. }
  1347. static int cnic_cm_abort(struct cnic_sock *csk)
  1348. {
  1349. struct cnic_local *cp = csk->dev->cnic_priv;
  1350. u32 opcode;
  1351. if (!cnic_in_use(csk))
  1352. return -EINVAL;
  1353. if (cnic_abort_prep(csk))
  1354. return cnic_cm_abort_req(csk);
  1355. /* Getting here means that we haven't started connect, or
  1356. * connect was not successful.
  1357. */
  1358. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  1359. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  1360. opcode = csk->state;
  1361. else
  1362. opcode = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  1363. cp->close_conn(csk, opcode);
  1364. return 0;
  1365. }
  1366. static int cnic_cm_close(struct cnic_sock *csk)
  1367. {
  1368. if (!cnic_in_use(csk))
  1369. return -EINVAL;
  1370. if (cnic_close_prep(csk)) {
  1371. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  1372. return cnic_cm_close_req(csk);
  1373. }
  1374. return 0;
  1375. }
  1376. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  1377. u8 opcode)
  1378. {
  1379. struct cnic_ulp_ops *ulp_ops;
  1380. int ulp_type = csk->ulp_type;
  1381. rcu_read_lock();
  1382. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1383. if (ulp_ops) {
  1384. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  1385. ulp_ops->cm_connect_complete(csk);
  1386. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  1387. ulp_ops->cm_close_complete(csk);
  1388. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  1389. ulp_ops->cm_remote_abort(csk);
  1390. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  1391. ulp_ops->cm_abort_complete(csk);
  1392. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  1393. ulp_ops->cm_remote_close(csk);
  1394. }
  1395. rcu_read_unlock();
  1396. }
  1397. static int cnic_cm_set_pg(struct cnic_sock *csk)
  1398. {
  1399. if (cnic_offld_prep(csk)) {
  1400. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  1401. cnic_cm_update_pg(csk);
  1402. else
  1403. cnic_cm_offload_pg(csk);
  1404. }
  1405. return 0;
  1406. }
  1407. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  1408. {
  1409. struct cnic_local *cp = dev->cnic_priv;
  1410. u32 l5_cid = kcqe->pg_host_opaque;
  1411. u8 opcode = kcqe->op_code;
  1412. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1413. csk_hold(csk);
  1414. if (!cnic_in_use(csk))
  1415. goto done;
  1416. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  1417. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  1418. goto done;
  1419. }
  1420. csk->pg_cid = kcqe->pg_cid;
  1421. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  1422. cnic_cm_conn_req(csk);
  1423. done:
  1424. csk_put(csk);
  1425. }
  1426. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  1427. {
  1428. struct cnic_local *cp = dev->cnic_priv;
  1429. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  1430. u8 opcode = l4kcqe->op_code;
  1431. u32 l5_cid;
  1432. struct cnic_sock *csk;
  1433. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  1434. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  1435. cnic_cm_process_offld_pg(dev, l4kcqe);
  1436. return;
  1437. }
  1438. l5_cid = l4kcqe->conn_id;
  1439. if (opcode & 0x80)
  1440. l5_cid = l4kcqe->cid;
  1441. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  1442. return;
  1443. csk = &cp->csk_tbl[l5_cid];
  1444. csk_hold(csk);
  1445. if (!cnic_in_use(csk)) {
  1446. csk_put(csk);
  1447. return;
  1448. }
  1449. switch (opcode) {
  1450. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  1451. if (l4kcqe->status == 0)
  1452. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  1453. smp_mb__before_clear_bit();
  1454. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  1455. cnic_cm_upcall(cp, csk, opcode);
  1456. break;
  1457. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  1458. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags))
  1459. csk->state = opcode;
  1460. /* fall through */
  1461. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  1462. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  1463. cp->close_conn(csk, opcode);
  1464. break;
  1465. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  1466. cnic_cm_upcall(cp, csk, opcode);
  1467. break;
  1468. }
  1469. csk_put(csk);
  1470. }
  1471. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  1472. {
  1473. struct cnic_dev *dev = data;
  1474. int i;
  1475. for (i = 0; i < num; i++)
  1476. cnic_cm_process_kcqe(dev, kcqe[i]);
  1477. }
  1478. static struct cnic_ulp_ops cm_ulp_ops = {
  1479. .indicate_kcqes = cnic_cm_indicate_kcqe,
  1480. };
  1481. static void cnic_cm_free_mem(struct cnic_dev *dev)
  1482. {
  1483. struct cnic_local *cp = dev->cnic_priv;
  1484. kfree(cp->csk_tbl);
  1485. cp->csk_tbl = NULL;
  1486. cnic_free_id_tbl(&cp->csk_port_tbl);
  1487. }
  1488. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  1489. {
  1490. struct cnic_local *cp = dev->cnic_priv;
  1491. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  1492. GFP_KERNEL);
  1493. if (!cp->csk_tbl)
  1494. return -ENOMEM;
  1495. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  1496. CNIC_LOCAL_PORT_MIN)) {
  1497. cnic_cm_free_mem(dev);
  1498. return -ENOMEM;
  1499. }
  1500. return 0;
  1501. }
  1502. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  1503. {
  1504. if ((opcode == csk->state) ||
  1505. (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED &&
  1506. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)) {
  1507. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags))
  1508. return 1;
  1509. }
  1510. return 0;
  1511. }
  1512. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  1513. {
  1514. struct cnic_dev *dev = csk->dev;
  1515. struct cnic_local *cp = dev->cnic_priv;
  1516. clear_bit(SK_F_CONNECT_START, &csk->flags);
  1517. if (cnic_ready_to_close(csk, opcode)) {
  1518. cnic_close_conn(csk);
  1519. cnic_cm_upcall(cp, csk, opcode);
  1520. }
  1521. }
  1522. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  1523. {
  1524. }
  1525. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  1526. {
  1527. u32 seed;
  1528. get_random_bytes(&seed, 4);
  1529. cnic_ctx_wr(dev, 45, 0, seed);
  1530. return 0;
  1531. }
  1532. static int cnic_cm_open(struct cnic_dev *dev)
  1533. {
  1534. struct cnic_local *cp = dev->cnic_priv;
  1535. int err;
  1536. err = cnic_cm_alloc_mem(dev);
  1537. if (err)
  1538. return err;
  1539. err = cp->start_cm(dev);
  1540. if (err)
  1541. goto err_out;
  1542. dev->cm_create = cnic_cm_create;
  1543. dev->cm_destroy = cnic_cm_destroy;
  1544. dev->cm_connect = cnic_cm_connect;
  1545. dev->cm_abort = cnic_cm_abort;
  1546. dev->cm_close = cnic_cm_close;
  1547. dev->cm_select_dev = cnic_cm_select_dev;
  1548. cp->ulp_handle[CNIC_ULP_L4] = dev;
  1549. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  1550. return 0;
  1551. err_out:
  1552. cnic_cm_free_mem(dev);
  1553. return err;
  1554. }
  1555. static int cnic_cm_shutdown(struct cnic_dev *dev)
  1556. {
  1557. struct cnic_local *cp = dev->cnic_priv;
  1558. int i;
  1559. cp->stop_cm(dev);
  1560. if (!cp->csk_tbl)
  1561. return 0;
  1562. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  1563. struct cnic_sock *csk = &cp->csk_tbl[i];
  1564. clear_bit(SK_F_INUSE, &csk->flags);
  1565. cnic_cm_cleanup(csk);
  1566. }
  1567. cnic_cm_free_mem(dev);
  1568. return 0;
  1569. }
  1570. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  1571. {
  1572. struct cnic_local *cp = dev->cnic_priv;
  1573. u32 cid_addr;
  1574. int i;
  1575. if (CHIP_NUM(cp) == CHIP_NUM_5709)
  1576. return;
  1577. cid_addr = GET_CID_ADDR(cid);
  1578. for (i = 0; i < CTX_SIZE; i += 4)
  1579. cnic_ctx_wr(dev, cid_addr, i, 0);
  1580. }
  1581. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  1582. {
  1583. struct cnic_local *cp = dev->cnic_priv;
  1584. int ret = 0, i;
  1585. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  1586. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  1587. return 0;
  1588. for (i = 0; i < cp->ctx_blks; i++) {
  1589. int j;
  1590. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  1591. u32 val;
  1592. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  1593. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  1594. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  1595. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  1596. (u64) cp->ctx_arr[i].mapping >> 32);
  1597. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  1598. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  1599. for (j = 0; j < 10; j++) {
  1600. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  1601. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  1602. break;
  1603. udelay(5);
  1604. }
  1605. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  1606. ret = -EBUSY;
  1607. break;
  1608. }
  1609. }
  1610. return ret;
  1611. }
  1612. static void cnic_free_irq(struct cnic_dev *dev)
  1613. {
  1614. struct cnic_local *cp = dev->cnic_priv;
  1615. struct cnic_eth_dev *ethdev = cp->ethdev;
  1616. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  1617. cp->disable_int_sync(dev);
  1618. tasklet_disable(&cp->cnic_irq_task);
  1619. free_irq(ethdev->irq_arr[0].vector, dev);
  1620. }
  1621. }
  1622. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  1623. {
  1624. struct cnic_local *cp = dev->cnic_priv;
  1625. struct cnic_eth_dev *ethdev = cp->ethdev;
  1626. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  1627. int err, i = 0;
  1628. int sblk_num = cp->status_blk_num;
  1629. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  1630. BNX2_HC_SB_CONFIG_1;
  1631. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  1632. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  1633. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  1634. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  1635. cp->bnx2_status_blk = cp->status_blk;
  1636. cp->last_status_idx = cp->bnx2_status_blk->status_idx;
  1637. tasklet_init(&cp->cnic_irq_task, &cnic_service_bnx2_msix,
  1638. (unsigned long) dev);
  1639. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  1640. "cnic", dev);
  1641. if (err) {
  1642. tasklet_disable(&cp->cnic_irq_task);
  1643. return err;
  1644. }
  1645. while (cp->bnx2_status_blk->status_completion_producer_index &&
  1646. i < 10) {
  1647. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  1648. 1 << (11 + sblk_num));
  1649. udelay(10);
  1650. i++;
  1651. barrier();
  1652. }
  1653. if (cp->bnx2_status_blk->status_completion_producer_index) {
  1654. cnic_free_irq(dev);
  1655. goto failed;
  1656. }
  1657. } else {
  1658. struct status_block *sblk = cp->status_blk;
  1659. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  1660. int i = 0;
  1661. while (sblk->status_completion_producer_index && i < 10) {
  1662. CNIC_WR(dev, BNX2_HC_COMMAND,
  1663. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  1664. udelay(10);
  1665. i++;
  1666. barrier();
  1667. }
  1668. if (sblk->status_completion_producer_index)
  1669. goto failed;
  1670. }
  1671. return 0;
  1672. failed:
  1673. printk(KERN_ERR PFX "%s: " "KCQ index not resetting to 0.\n",
  1674. dev->netdev->name);
  1675. return -EBUSY;
  1676. }
  1677. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  1678. {
  1679. struct cnic_local *cp = dev->cnic_priv;
  1680. struct cnic_eth_dev *ethdev = cp->ethdev;
  1681. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  1682. return;
  1683. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1684. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1685. }
  1686. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  1687. {
  1688. struct cnic_local *cp = dev->cnic_priv;
  1689. struct cnic_eth_dev *ethdev = cp->ethdev;
  1690. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  1691. return;
  1692. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1693. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  1694. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  1695. synchronize_irq(ethdev->irq_arr[0].vector);
  1696. }
  1697. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  1698. {
  1699. struct cnic_local *cp = dev->cnic_priv;
  1700. struct cnic_eth_dev *ethdev = cp->ethdev;
  1701. u32 cid_addr, tx_cid, sb_id;
  1702. u32 val, offset0, offset1, offset2, offset3;
  1703. int i;
  1704. struct tx_bd *txbd;
  1705. dma_addr_t buf_map;
  1706. struct status_block *s_blk = cp->status_blk;
  1707. sb_id = cp->status_blk_num;
  1708. tx_cid = 20;
  1709. cnic_init_context(dev, tx_cid);
  1710. cnic_init_context(dev, tx_cid + 1);
  1711. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  1712. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  1713. struct status_block_msix *sblk = cp->status_blk;
  1714. tx_cid = TX_TSS_CID + sb_id - 1;
  1715. cnic_init_context(dev, tx_cid);
  1716. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  1717. (TX_TSS_CID << 7));
  1718. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  1719. }
  1720. cp->tx_cons = *cp->tx_cons_ptr;
  1721. cid_addr = GET_CID_ADDR(tx_cid);
  1722. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  1723. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  1724. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  1725. cnic_ctx_wr(dev, cid_addr2, i, 0);
  1726. offset0 = BNX2_L2CTX_TYPE_XI;
  1727. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  1728. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  1729. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  1730. } else {
  1731. offset0 = BNX2_L2CTX_TYPE;
  1732. offset1 = BNX2_L2CTX_CMD_TYPE;
  1733. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  1734. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  1735. }
  1736. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  1737. cnic_ctx_wr(dev, cid_addr, offset0, val);
  1738. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  1739. cnic_ctx_wr(dev, cid_addr, offset1, val);
  1740. txbd = (struct tx_bd *) cp->l2_ring;
  1741. buf_map = cp->l2_buf_map;
  1742. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  1743. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  1744. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  1745. }
  1746. val = (u64) cp->l2_ring_map >> 32;
  1747. cnic_ctx_wr(dev, cid_addr, offset2, val);
  1748. txbd->tx_bd_haddr_hi = val;
  1749. val = (u64) cp->l2_ring_map & 0xffffffff;
  1750. cnic_ctx_wr(dev, cid_addr, offset3, val);
  1751. txbd->tx_bd_haddr_lo = val;
  1752. }
  1753. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  1754. {
  1755. struct cnic_local *cp = dev->cnic_priv;
  1756. struct cnic_eth_dev *ethdev = cp->ethdev;
  1757. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  1758. int i;
  1759. struct rx_bd *rxbd;
  1760. struct status_block *s_blk = cp->status_blk;
  1761. sb_id = cp->status_blk_num;
  1762. cnic_init_context(dev, 2);
  1763. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  1764. coal_reg = BNX2_HC_COMMAND;
  1765. coal_val = CNIC_RD(dev, coal_reg);
  1766. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  1767. struct status_block_msix *sblk = cp->status_blk;
  1768. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  1769. coal_reg = BNX2_HC_COALESCE_NOW;
  1770. coal_val = 1 << (11 + sb_id);
  1771. }
  1772. i = 0;
  1773. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  1774. CNIC_WR(dev, coal_reg, coal_val);
  1775. udelay(10);
  1776. i++;
  1777. barrier();
  1778. }
  1779. cp->rx_cons = *cp->rx_cons_ptr;
  1780. cid_addr = GET_CID_ADDR(2);
  1781. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  1782. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  1783. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  1784. if (sb_id == 0)
  1785. val = 2 << BNX2_L2CTX_STATUSB_NUM_SHIFT;
  1786. else
  1787. val = BNX2_L2CTX_STATUSB_NUM(sb_id);
  1788. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  1789. rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
  1790. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  1791. dma_addr_t buf_map;
  1792. int n = (i % cp->l2_rx_ring_size) + 1;
  1793. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  1794. rxbd->rx_bd_len = cp->l2_single_buf_size;
  1795. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  1796. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  1797. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  1798. }
  1799. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  1800. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  1801. rxbd->rx_bd_haddr_hi = val;
  1802. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  1803. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  1804. rxbd->rx_bd_haddr_lo = val;
  1805. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  1806. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  1807. }
  1808. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  1809. {
  1810. struct kwqe *wqes[1], l2kwqe;
  1811. memset(&l2kwqe, 0, sizeof(l2kwqe));
  1812. wqes[0] = &l2kwqe;
  1813. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  1814. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  1815. KWQE_OPCODE_SHIFT) | 2;
  1816. dev->submit_kwqes(dev, wqes, 1);
  1817. }
  1818. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  1819. {
  1820. struct cnic_local *cp = dev->cnic_priv;
  1821. u32 val;
  1822. val = cp->func << 2;
  1823. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  1824. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  1825. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  1826. dev->mac_addr[0] = (u8) (val >> 8);
  1827. dev->mac_addr[1] = (u8) val;
  1828. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  1829. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  1830. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  1831. dev->mac_addr[2] = (u8) (val >> 24);
  1832. dev->mac_addr[3] = (u8) (val >> 16);
  1833. dev->mac_addr[4] = (u8) (val >> 8);
  1834. dev->mac_addr[5] = (u8) val;
  1835. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  1836. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  1837. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  1838. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  1839. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  1840. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  1841. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  1842. }
  1843. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  1844. {
  1845. struct cnic_local *cp = dev->cnic_priv;
  1846. struct cnic_eth_dev *ethdev = cp->ethdev;
  1847. struct status_block *sblk = cp->status_blk;
  1848. u32 val;
  1849. int err;
  1850. cnic_set_bnx2_mac(dev);
  1851. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  1852. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  1853. if (BCM_PAGE_BITS > 12)
  1854. val |= (12 - 8) << 4;
  1855. else
  1856. val |= (BCM_PAGE_BITS - 8) << 4;
  1857. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  1858. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  1859. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  1860. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  1861. err = cnic_setup_5709_context(dev, 1);
  1862. if (err)
  1863. return err;
  1864. cnic_init_context(dev, KWQ_CID);
  1865. cnic_init_context(dev, KCQ_CID);
  1866. cp->kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  1867. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  1868. cp->max_kwq_idx = MAX_KWQ_IDX;
  1869. cp->kwq_prod_idx = 0;
  1870. cp->kwq_con_idx = 0;
  1871. cp->cnic_local_flags |= CNIC_LCL_FL_KWQ_INIT;
  1872. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  1873. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  1874. else
  1875. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  1876. /* Initialize the kernel work queue context. */
  1877. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  1878. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  1879. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_TYPE, val);
  1880. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  1881. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  1882. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  1883. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  1884. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  1885. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  1886. val = (u32) cp->kwq_info.pgtbl_map;
  1887. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  1888. cp->kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  1889. cp->kcq_io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  1890. cp->kcq_prod_idx = 0;
  1891. /* Initialize the kernel complete queue context. */
  1892. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  1893. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  1894. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_TYPE, val);
  1895. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  1896. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  1897. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  1898. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  1899. val = (u32) ((u64) cp->kcq_info.pgtbl_map >> 32);
  1900. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  1901. val = (u32) cp->kcq_info.pgtbl_map;
  1902. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  1903. cp->int_num = 0;
  1904. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  1905. u32 sb_id = cp->status_blk_num;
  1906. u32 sb = BNX2_L2CTX_STATUSB_NUM(sb_id);
  1907. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  1908. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  1909. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  1910. }
  1911. /* Enable Commnad Scheduler notification when we write to the
  1912. * host producer index of the kernel contexts. */
  1913. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  1914. /* Enable Command Scheduler notification when we write to either
  1915. * the Send Queue or Receive Queue producer indexes of the kernel
  1916. * bypass contexts. */
  1917. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  1918. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  1919. /* Notify COM when the driver post an application buffer. */
  1920. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  1921. /* Set the CP and COM doorbells. These two processors polls the
  1922. * doorbell for a non zero value before running. This must be done
  1923. * after setting up the kernel queue contexts. */
  1924. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  1925. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  1926. cnic_init_bnx2_tx_ring(dev);
  1927. cnic_init_bnx2_rx_ring(dev);
  1928. err = cnic_init_bnx2_irq(dev);
  1929. if (err) {
  1930. printk(KERN_ERR PFX "%s: cnic_init_irq failed\n",
  1931. dev->netdev->name);
  1932. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  1933. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  1934. return err;
  1935. }
  1936. return 0;
  1937. }
  1938. static int cnic_start_hw(struct cnic_dev *dev)
  1939. {
  1940. struct cnic_local *cp = dev->cnic_priv;
  1941. struct cnic_eth_dev *ethdev = cp->ethdev;
  1942. int err;
  1943. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1944. return -EALREADY;
  1945. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  1946. if (err) {
  1947. printk(KERN_ERR PFX "%s: register_cnic failed\n",
  1948. dev->netdev->name);
  1949. goto err2;
  1950. }
  1951. dev->regview = ethdev->io_base;
  1952. cp->chip_id = ethdev->chip_id;
  1953. pci_dev_get(dev->pcidev);
  1954. cp->func = PCI_FUNC(dev->pcidev->devfn);
  1955. cp->status_blk = ethdev->irq_arr[0].status_blk;
  1956. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  1957. err = cp->alloc_resc(dev);
  1958. if (err) {
  1959. printk(KERN_ERR PFX "%s: allocate resource failure\n",
  1960. dev->netdev->name);
  1961. goto err1;
  1962. }
  1963. err = cp->start_hw(dev);
  1964. if (err)
  1965. goto err1;
  1966. err = cnic_cm_open(dev);
  1967. if (err)
  1968. goto err1;
  1969. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  1970. cp->enable_int(dev);
  1971. return 0;
  1972. err1:
  1973. ethdev->drv_unregister_cnic(dev->netdev);
  1974. cp->free_resc(dev);
  1975. pci_dev_put(dev->pcidev);
  1976. err2:
  1977. return err;
  1978. }
  1979. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  1980. {
  1981. struct cnic_local *cp = dev->cnic_priv;
  1982. struct cnic_eth_dev *ethdev = cp->ethdev;
  1983. cnic_disable_bnx2_int_sync(dev);
  1984. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  1985. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  1986. cnic_init_context(dev, KWQ_CID);
  1987. cnic_init_context(dev, KCQ_CID);
  1988. cnic_setup_5709_context(dev, 0);
  1989. cnic_free_irq(dev);
  1990. ethdev->drv_unregister_cnic(dev->netdev);
  1991. cnic_free_resc(dev);
  1992. }
  1993. static void cnic_stop_hw(struct cnic_dev *dev)
  1994. {
  1995. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  1996. struct cnic_local *cp = dev->cnic_priv;
  1997. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  1998. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  1999. synchronize_rcu();
  2000. cnic_cm_shutdown(dev);
  2001. cp->stop_hw(dev);
  2002. pci_dev_put(dev->pcidev);
  2003. }
  2004. }
  2005. static void cnic_free_dev(struct cnic_dev *dev)
  2006. {
  2007. int i = 0;
  2008. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  2009. msleep(100);
  2010. i++;
  2011. }
  2012. if (atomic_read(&dev->ref_count) != 0)
  2013. printk(KERN_ERR PFX "%s: Failed waiting for ref count to go"
  2014. " to zero.\n", dev->netdev->name);
  2015. printk(KERN_INFO PFX "Removed CNIC device: %s\n", dev->netdev->name);
  2016. dev_put(dev->netdev);
  2017. kfree(dev);
  2018. }
  2019. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  2020. struct pci_dev *pdev)
  2021. {
  2022. struct cnic_dev *cdev;
  2023. struct cnic_local *cp;
  2024. int alloc_size;
  2025. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  2026. cdev = kzalloc(alloc_size , GFP_KERNEL);
  2027. if (cdev == NULL) {
  2028. printk(KERN_ERR PFX "%s: allocate dev struct failure\n",
  2029. dev->name);
  2030. return NULL;
  2031. }
  2032. cdev->netdev = dev;
  2033. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  2034. cdev->register_device = cnic_register_device;
  2035. cdev->unregister_device = cnic_unregister_device;
  2036. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  2037. cp = cdev->cnic_priv;
  2038. cp->dev = cdev;
  2039. cp->uio_dev = -1;
  2040. cp->l2_single_buf_size = 0x400;
  2041. cp->l2_rx_ring_size = 3;
  2042. spin_lock_init(&cp->cnic_ulp_lock);
  2043. printk(KERN_INFO PFX "Added CNIC device: %s\n", dev->name);
  2044. return cdev;
  2045. }
  2046. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  2047. {
  2048. struct pci_dev *pdev;
  2049. struct cnic_dev *cdev;
  2050. struct cnic_local *cp;
  2051. struct cnic_eth_dev *ethdev = NULL;
  2052. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  2053. probe = symbol_get(bnx2_cnic_probe);
  2054. if (probe) {
  2055. ethdev = (*probe)(dev);
  2056. symbol_put_addr(probe);
  2057. }
  2058. if (!ethdev)
  2059. return NULL;
  2060. pdev = ethdev->pdev;
  2061. if (!pdev)
  2062. return NULL;
  2063. dev_hold(dev);
  2064. pci_dev_get(pdev);
  2065. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  2066. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  2067. u8 rev;
  2068. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  2069. if (rev < 0x10) {
  2070. pci_dev_put(pdev);
  2071. goto cnic_err;
  2072. }
  2073. }
  2074. pci_dev_put(pdev);
  2075. cdev = cnic_alloc_dev(dev, pdev);
  2076. if (cdev == NULL)
  2077. goto cnic_err;
  2078. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  2079. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  2080. cp = cdev->cnic_priv;
  2081. cp->ethdev = ethdev;
  2082. cdev->pcidev = pdev;
  2083. cp->cnic_ops = &cnic_bnx2_ops;
  2084. cp->start_hw = cnic_start_bnx2_hw;
  2085. cp->stop_hw = cnic_stop_bnx2_hw;
  2086. cp->setup_pgtbl = cnic_setup_page_tbl;
  2087. cp->alloc_resc = cnic_alloc_bnx2_resc;
  2088. cp->free_resc = cnic_free_resc;
  2089. cp->start_cm = cnic_cm_init_bnx2_hw;
  2090. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  2091. cp->enable_int = cnic_enable_bnx2_int;
  2092. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  2093. cp->close_conn = cnic_close_bnx2_conn;
  2094. cp->next_idx = cnic_bnx2_next_idx;
  2095. cp->hw_idx = cnic_bnx2_hw_idx;
  2096. return cdev;
  2097. cnic_err:
  2098. dev_put(dev);
  2099. return NULL;
  2100. }
  2101. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  2102. {
  2103. struct ethtool_drvinfo drvinfo;
  2104. struct cnic_dev *cdev = NULL;
  2105. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  2106. memset(&drvinfo, 0, sizeof(drvinfo));
  2107. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  2108. if (!strcmp(drvinfo.driver, "bnx2"))
  2109. cdev = init_bnx2_cnic(dev);
  2110. if (cdev) {
  2111. write_lock(&cnic_dev_lock);
  2112. list_add(&cdev->list, &cnic_dev_list);
  2113. write_unlock(&cnic_dev_lock);
  2114. }
  2115. }
  2116. return cdev;
  2117. }
  2118. /**
  2119. * netdev event handler
  2120. */
  2121. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  2122. void *ptr)
  2123. {
  2124. struct net_device *netdev = ptr;
  2125. struct cnic_dev *dev;
  2126. int if_type;
  2127. int new_dev = 0;
  2128. dev = cnic_from_netdev(netdev);
  2129. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  2130. /* Check for the hot-plug device */
  2131. dev = is_cnic_dev(netdev);
  2132. if (dev) {
  2133. new_dev = 1;
  2134. cnic_hold(dev);
  2135. }
  2136. }
  2137. if (dev) {
  2138. struct cnic_local *cp = dev->cnic_priv;
  2139. if (new_dev)
  2140. cnic_ulp_init(dev);
  2141. else if (event == NETDEV_UNREGISTER)
  2142. cnic_ulp_exit(dev);
  2143. else if (event == NETDEV_UP) {
  2144. mutex_lock(&cnic_lock);
  2145. if (!cnic_start_hw(dev))
  2146. cnic_ulp_start(dev);
  2147. mutex_unlock(&cnic_lock);
  2148. }
  2149. rcu_read_lock();
  2150. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2151. struct cnic_ulp_ops *ulp_ops;
  2152. void *ctx;
  2153. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  2154. if (!ulp_ops || !ulp_ops->indicate_netevent)
  2155. continue;
  2156. ctx = cp->ulp_handle[if_type];
  2157. ulp_ops->indicate_netevent(ctx, event);
  2158. }
  2159. rcu_read_unlock();
  2160. if (event == NETDEV_GOING_DOWN) {
  2161. mutex_lock(&cnic_lock);
  2162. cnic_ulp_stop(dev);
  2163. cnic_stop_hw(dev);
  2164. mutex_unlock(&cnic_lock);
  2165. } else if (event == NETDEV_UNREGISTER) {
  2166. write_lock(&cnic_dev_lock);
  2167. list_del_init(&dev->list);
  2168. write_unlock(&cnic_dev_lock);
  2169. cnic_put(dev);
  2170. cnic_free_dev(dev);
  2171. goto done;
  2172. }
  2173. cnic_put(dev);
  2174. }
  2175. done:
  2176. return NOTIFY_DONE;
  2177. }
  2178. static struct notifier_block cnic_netdev_notifier = {
  2179. .notifier_call = cnic_netdev_event
  2180. };
  2181. static void cnic_release(void)
  2182. {
  2183. struct cnic_dev *dev;
  2184. while (!list_empty(&cnic_dev_list)) {
  2185. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  2186. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  2187. cnic_ulp_stop(dev);
  2188. cnic_stop_hw(dev);
  2189. }
  2190. cnic_ulp_exit(dev);
  2191. list_del_init(&dev->list);
  2192. cnic_free_dev(dev);
  2193. }
  2194. }
  2195. static int __init cnic_init(void)
  2196. {
  2197. int rc = 0;
  2198. printk(KERN_INFO "%s", version);
  2199. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  2200. if (rc) {
  2201. cnic_release();
  2202. return rc;
  2203. }
  2204. return 0;
  2205. }
  2206. static void __exit cnic_exit(void)
  2207. {
  2208. unregister_netdevice_notifier(&cnic_netdev_notifier);
  2209. cnic_release();
  2210. return;
  2211. }
  2212. module_init(cnic_init);
  2213. module_exit(cnic_exit);