w90p910_ether.c 26 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105
  1. /*
  2. * Copyright (c) 2008-2009 Nuvoton technology corporation.
  3. *
  4. * Wan ZongShun <mcuos.com@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation;version 2 of the License.
  9. *
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/mii.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/skbuff.h>
  17. #include <linux/ethtool.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/clk.h>
  20. #define DRV_MODULE_NAME "w90p910-emc"
  21. #define DRV_MODULE_VERSION "0.1"
  22. /* Ethernet MAC Registers */
  23. #define REG_CAMCMR 0x00
  24. #define REG_CAMEN 0x04
  25. #define REG_CAMM_BASE 0x08
  26. #define REG_CAML_BASE 0x0c
  27. #define REG_TXDLSA 0x88
  28. #define REG_RXDLSA 0x8C
  29. #define REG_MCMDR 0x90
  30. #define REG_MIID 0x94
  31. #define REG_MIIDA 0x98
  32. #define REG_FFTCR 0x9C
  33. #define REG_TSDR 0xa0
  34. #define REG_RSDR 0xa4
  35. #define REG_DMARFC 0xa8
  36. #define REG_MIEN 0xac
  37. #define REG_MISTA 0xb0
  38. #define REG_CTXDSA 0xcc
  39. #define REG_CTXBSA 0xd0
  40. #define REG_CRXDSA 0xd4
  41. #define REG_CRXBSA 0xd8
  42. /* mac controller bit */
  43. #define MCMDR_RXON 0x01
  44. #define MCMDR_ACP (0x01 << 3)
  45. #define MCMDR_SPCRC (0x01 << 5)
  46. #define MCMDR_TXON (0x01 << 8)
  47. #define MCMDR_FDUP (0x01 << 18)
  48. #define MCMDR_ENMDC (0x01 << 19)
  49. #define MCMDR_OPMOD (0x01 << 20)
  50. #define SWR (0x01 << 24)
  51. /* cam command regiser */
  52. #define CAMCMR_AUP 0x01
  53. #define CAMCMR_AMP (0x01 << 1)
  54. #define CAMCMR_ABP (0x01 << 2)
  55. #define CAMCMR_CCAM (0x01 << 3)
  56. #define CAMCMR_ECMP (0x01 << 4)
  57. #define CAM0EN 0x01
  58. /* mac mii controller bit */
  59. #define MDCCR (0x0a << 20)
  60. #define PHYAD (0x01 << 8)
  61. #define PHYWR (0x01 << 16)
  62. #define PHYBUSY (0x01 << 17)
  63. #define PHYPRESP (0x01 << 18)
  64. #define CAM_ENTRY_SIZE 0x08
  65. /* rx and tx status */
  66. #define TXDS_TXCP (0x01 << 19)
  67. #define RXDS_CRCE (0x01 << 17)
  68. #define RXDS_PTLE (0x01 << 19)
  69. #define RXDS_RXGD (0x01 << 20)
  70. #define RXDS_ALIE (0x01 << 21)
  71. #define RXDS_RP (0x01 << 22)
  72. /* mac interrupt status*/
  73. #define MISTA_EXDEF (0x01 << 19)
  74. #define MISTA_TXBERR (0x01 << 24)
  75. #define MISTA_TDU (0x01 << 23)
  76. #define MISTA_RDU (0x01 << 10)
  77. #define MISTA_RXBERR (0x01 << 11)
  78. #define ENSTART 0x01
  79. #define ENRXINTR 0x01
  80. #define ENRXGD (0x01 << 4)
  81. #define ENRXBERR (0x01 << 11)
  82. #define ENTXINTR (0x01 << 16)
  83. #define ENTXCP (0x01 << 18)
  84. #define ENTXABT (0x01 << 21)
  85. #define ENTXBERR (0x01 << 24)
  86. #define ENMDC (0x01 << 19)
  87. #define PHYBUSY (0x01 << 17)
  88. #define MDCCR_VAL 0xa00000
  89. /* rx and tx owner bit */
  90. #define RX_OWEN_DMA (0x01 << 31)
  91. #define RX_OWEN_CPU (~(0x03 << 30))
  92. #define TX_OWEN_DMA (0x01 << 31)
  93. #define TX_OWEN_CPU (~(0x01 << 31))
  94. /* tx frame desc controller bit */
  95. #define MACTXINTEN 0x04
  96. #define CRCMODE 0x02
  97. #define PADDINGMODE 0x01
  98. /* fftcr controller bit */
  99. #define TXTHD (0x03 << 8)
  100. #define BLENGTH (0x01 << 20)
  101. /* global setting for driver */
  102. #define RX_DESC_SIZE 50
  103. #define TX_DESC_SIZE 10
  104. #define MAX_RBUFF_SZ 0x600
  105. #define MAX_TBUFF_SZ 0x600
  106. #define TX_TIMEOUT 50
  107. #define DELAY 1000
  108. #define CAM0 0x0
  109. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg);
  110. struct w90p910_rxbd {
  111. unsigned int sl;
  112. unsigned int buffer;
  113. unsigned int reserved;
  114. unsigned int next;
  115. };
  116. struct w90p910_txbd {
  117. unsigned int mode;
  118. unsigned int buffer;
  119. unsigned int sl;
  120. unsigned int next;
  121. };
  122. struct recv_pdesc {
  123. struct w90p910_rxbd desclist[RX_DESC_SIZE];
  124. char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ];
  125. };
  126. struct tran_pdesc {
  127. struct w90p910_txbd desclist[TX_DESC_SIZE];
  128. char tran_buf[RX_DESC_SIZE][MAX_TBUFF_SZ];
  129. };
  130. struct w90p910_ether {
  131. struct recv_pdesc *rdesc;
  132. struct recv_pdesc *rdesc_phys;
  133. struct tran_pdesc *tdesc;
  134. struct tran_pdesc *tdesc_phys;
  135. struct net_device_stats stats;
  136. struct platform_device *pdev;
  137. struct sk_buff *skb;
  138. struct clk *clk;
  139. struct clk *rmiiclk;
  140. struct mii_if_info mii;
  141. struct timer_list check_timer;
  142. void __iomem *reg;
  143. unsigned int rxirq;
  144. unsigned int txirq;
  145. unsigned int cur_tx;
  146. unsigned int cur_rx;
  147. unsigned int finish_tx;
  148. unsigned int rx_packets;
  149. unsigned int rx_bytes;
  150. unsigned int start_tx_ptr;
  151. unsigned int start_rx_ptr;
  152. unsigned int linkflag;
  153. spinlock_t lock;
  154. };
  155. static void update_linkspeed_register(struct net_device *dev,
  156. unsigned int speed, unsigned int duplex)
  157. {
  158. struct w90p910_ether *ether = netdev_priv(dev);
  159. unsigned int val;
  160. val = __raw_readl(ether->reg + REG_MCMDR);
  161. if (speed == SPEED_100) {
  162. /* 100 full/half duplex */
  163. if (duplex == DUPLEX_FULL) {
  164. val |= (MCMDR_OPMOD | MCMDR_FDUP);
  165. } else {
  166. val |= MCMDR_OPMOD;
  167. val &= ~MCMDR_FDUP;
  168. }
  169. } else {
  170. /* 10 full/half duplex */
  171. if (duplex == DUPLEX_FULL) {
  172. val |= MCMDR_FDUP;
  173. val &= ~MCMDR_OPMOD;
  174. } else {
  175. val &= ~(MCMDR_FDUP | MCMDR_OPMOD);
  176. }
  177. }
  178. __raw_writel(val, ether->reg + REG_MCMDR);
  179. }
  180. static void update_linkspeed(struct net_device *dev)
  181. {
  182. struct w90p910_ether *ether = netdev_priv(dev);
  183. struct platform_device *pdev;
  184. unsigned int bmsr, bmcr, lpa, speed, duplex;
  185. pdev = ether->pdev;
  186. if (!mii_link_ok(&ether->mii)) {
  187. ether->linkflag = 0x0;
  188. netif_carrier_off(dev);
  189. dev_warn(&pdev->dev, "%s: Link down.\n", dev->name);
  190. return;
  191. }
  192. if (ether->linkflag == 1)
  193. return;
  194. bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR);
  195. bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR);
  196. if (bmcr & BMCR_ANENABLE) {
  197. if (!(bmsr & BMSR_ANEGCOMPLETE))
  198. return;
  199. lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA);
  200. if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
  201. speed = SPEED_100;
  202. else
  203. speed = SPEED_10;
  204. if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
  205. duplex = DUPLEX_FULL;
  206. else
  207. duplex = DUPLEX_HALF;
  208. } else {
  209. speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
  210. duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
  211. }
  212. update_linkspeed_register(dev, speed, duplex);
  213. dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed,
  214. (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
  215. ether->linkflag = 0x01;
  216. netif_carrier_on(dev);
  217. }
  218. static void w90p910_check_link(unsigned long dev_id)
  219. {
  220. struct net_device *dev = (struct net_device *) dev_id;
  221. struct w90p910_ether *ether = netdev_priv(dev);
  222. update_linkspeed(dev);
  223. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  224. }
  225. static void w90p910_write_cam(struct net_device *dev,
  226. unsigned int x, unsigned char *pval)
  227. {
  228. struct w90p910_ether *ether = netdev_priv(dev);
  229. unsigned int msw, lsw;
  230. msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
  231. lsw = (pval[4] << 24) | (pval[5] << 16);
  232. __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE);
  233. __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE);
  234. }
  235. static void w90p910_init_desc(struct net_device *dev)
  236. {
  237. struct w90p910_ether *ether;
  238. struct w90p910_txbd *tdesc, *tdesc_phys;
  239. struct w90p910_rxbd *rdesc, *rdesc_phys;
  240. unsigned int i, j;
  241. ether = netdev_priv(dev);
  242. ether->tdesc = (struct tran_pdesc *)
  243. dma_alloc_coherent(NULL, sizeof(struct tran_pdesc),
  244. (dma_addr_t *) &ether->tdesc_phys, GFP_KERNEL);
  245. ether->rdesc = (struct recv_pdesc *)
  246. dma_alloc_coherent(NULL, sizeof(struct recv_pdesc),
  247. (dma_addr_t *) &ether->rdesc_phys, GFP_KERNEL);
  248. for (i = 0; i < TX_DESC_SIZE; i++) {
  249. tdesc = &(ether->tdesc->desclist[i]);
  250. j = ((i + 1) / TX_DESC_SIZE);
  251. if (j != 0) {
  252. tdesc_phys = &(ether->tdesc_phys->desclist[0]);
  253. ether->start_tx_ptr = (unsigned int)tdesc_phys;
  254. tdesc->next = (unsigned int)ether->start_tx_ptr;
  255. } else {
  256. tdesc_phys = &(ether->tdesc_phys->desclist[i+1]);
  257. tdesc->next = (unsigned int)tdesc_phys;
  258. }
  259. tdesc->buffer = (unsigned int)ether->tdesc_phys->tran_buf[i];
  260. tdesc->sl = 0;
  261. tdesc->mode = 0;
  262. }
  263. for (i = 0; i < RX_DESC_SIZE; i++) {
  264. rdesc = &(ether->rdesc->desclist[i]);
  265. j = ((i + 1) / RX_DESC_SIZE);
  266. if (j != 0) {
  267. rdesc_phys = &(ether->rdesc_phys->desclist[0]);
  268. ether->start_rx_ptr = (unsigned int)rdesc_phys;
  269. rdesc->next = (unsigned int)ether->start_rx_ptr;
  270. } else {
  271. rdesc_phys = &(ether->rdesc_phys->desclist[i+1]);
  272. rdesc->next = (unsigned int)rdesc_phys;
  273. }
  274. rdesc->sl = RX_OWEN_DMA;
  275. rdesc->buffer = (unsigned int)ether->rdesc_phys->recv_buf[i];
  276. }
  277. }
  278. static void w90p910_set_fifo_threshold(struct net_device *dev)
  279. {
  280. struct w90p910_ether *ether = netdev_priv(dev);
  281. unsigned int val;
  282. val = TXTHD | BLENGTH;
  283. __raw_writel(val, ether->reg + REG_FFTCR);
  284. }
  285. static void w90p910_return_default_idle(struct net_device *dev)
  286. {
  287. struct w90p910_ether *ether = netdev_priv(dev);
  288. unsigned int val;
  289. val = __raw_readl(ether->reg + REG_MCMDR);
  290. val |= SWR;
  291. __raw_writel(val, ether->reg + REG_MCMDR);
  292. }
  293. static void w90p910_trigger_rx(struct net_device *dev)
  294. {
  295. struct w90p910_ether *ether = netdev_priv(dev);
  296. __raw_writel(ENSTART, ether->reg + REG_RSDR);
  297. }
  298. static void w90p910_trigger_tx(struct net_device *dev)
  299. {
  300. struct w90p910_ether *ether = netdev_priv(dev);
  301. __raw_writel(ENSTART, ether->reg + REG_TSDR);
  302. }
  303. static void w90p910_enable_mac_interrupt(struct net_device *dev)
  304. {
  305. struct w90p910_ether *ether = netdev_priv(dev);
  306. unsigned int val;
  307. val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP;
  308. val |= ENTXBERR | ENRXBERR | ENTXABT;
  309. __raw_writel(val, ether->reg + REG_MIEN);
  310. }
  311. static void w90p910_get_and_clear_int(struct net_device *dev,
  312. unsigned int *val)
  313. {
  314. struct w90p910_ether *ether = netdev_priv(dev);
  315. *val = __raw_readl(ether->reg + REG_MISTA);
  316. __raw_writel(*val, ether->reg + REG_MISTA);
  317. }
  318. static void w90p910_set_global_maccmd(struct net_device *dev)
  319. {
  320. struct w90p910_ether *ether = netdev_priv(dev);
  321. unsigned int val;
  322. val = __raw_readl(ether->reg + REG_MCMDR);
  323. val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC;
  324. __raw_writel(val, ether->reg + REG_MCMDR);
  325. }
  326. static void w90p910_enable_cam(struct net_device *dev)
  327. {
  328. struct w90p910_ether *ether = netdev_priv(dev);
  329. unsigned int val;
  330. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  331. val = __raw_readl(ether->reg + REG_CAMEN);
  332. val |= CAM0EN;
  333. __raw_writel(val, ether->reg + REG_CAMEN);
  334. }
  335. static void w90p910_enable_cam_command(struct net_device *dev)
  336. {
  337. struct w90p910_ether *ether = netdev_priv(dev);
  338. unsigned int val;
  339. val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP;
  340. __raw_writel(val, ether->reg + REG_CAMCMR);
  341. }
  342. static void w90p910_enable_tx(struct net_device *dev, unsigned int enable)
  343. {
  344. struct w90p910_ether *ether = netdev_priv(dev);
  345. unsigned int val;
  346. val = __raw_readl(ether->reg + REG_MCMDR);
  347. if (enable)
  348. val |= MCMDR_TXON;
  349. else
  350. val &= ~MCMDR_TXON;
  351. __raw_writel(val, ether->reg + REG_MCMDR);
  352. }
  353. static void w90p910_enable_rx(struct net_device *dev, unsigned int enable)
  354. {
  355. struct w90p910_ether *ether = netdev_priv(dev);
  356. unsigned int val;
  357. val = __raw_readl(ether->reg + REG_MCMDR);
  358. if (enable)
  359. val |= MCMDR_RXON;
  360. else
  361. val &= ~MCMDR_RXON;
  362. __raw_writel(val, ether->reg + REG_MCMDR);
  363. }
  364. static void w90p910_set_curdest(struct net_device *dev)
  365. {
  366. struct w90p910_ether *ether = netdev_priv(dev);
  367. __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA);
  368. __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA);
  369. }
  370. static void w90p910_reset_mac(struct net_device *dev)
  371. {
  372. struct w90p910_ether *ether = netdev_priv(dev);
  373. spin_lock(&ether->lock);
  374. w90p910_enable_tx(dev, 0);
  375. w90p910_enable_rx(dev, 0);
  376. w90p910_set_fifo_threshold(dev);
  377. w90p910_return_default_idle(dev);
  378. if (!netif_queue_stopped(dev))
  379. netif_stop_queue(dev);
  380. w90p910_init_desc(dev);
  381. dev->trans_start = jiffies;
  382. ether->cur_tx = 0x0;
  383. ether->finish_tx = 0x0;
  384. ether->cur_rx = 0x0;
  385. w90p910_set_curdest(dev);
  386. w90p910_enable_cam(dev);
  387. w90p910_enable_cam_command(dev);
  388. w90p910_enable_mac_interrupt(dev);
  389. w90p910_enable_tx(dev, 1);
  390. w90p910_enable_rx(dev, 1);
  391. w90p910_trigger_tx(dev);
  392. w90p910_trigger_rx(dev);
  393. dev->trans_start = jiffies;
  394. if (netif_queue_stopped(dev))
  395. netif_wake_queue(dev);
  396. spin_unlock(&ether->lock);
  397. }
  398. static void w90p910_mdio_write(struct net_device *dev,
  399. int phy_id, int reg, int data)
  400. {
  401. struct w90p910_ether *ether = netdev_priv(dev);
  402. struct platform_device *pdev;
  403. unsigned int val, i;
  404. pdev = ether->pdev;
  405. __raw_writel(data, ether->reg + REG_MIID);
  406. val = (phy_id << 0x08) | reg;
  407. val |= PHYBUSY | PHYWR | MDCCR_VAL;
  408. __raw_writel(val, ether->reg + REG_MIIDA);
  409. for (i = 0; i < DELAY; i++) {
  410. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  411. break;
  412. }
  413. if (i == DELAY)
  414. dev_warn(&pdev->dev, "mdio write timed out\n");
  415. }
  416. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg)
  417. {
  418. struct w90p910_ether *ether = netdev_priv(dev);
  419. struct platform_device *pdev;
  420. unsigned int val, i, data;
  421. pdev = ether->pdev;
  422. val = (phy_id << 0x08) | reg;
  423. val |= PHYBUSY | MDCCR_VAL;
  424. __raw_writel(val, ether->reg + REG_MIIDA);
  425. for (i = 0; i < DELAY; i++) {
  426. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  427. break;
  428. }
  429. if (i == DELAY) {
  430. dev_warn(&pdev->dev, "mdio read timed out\n");
  431. data = 0xffff;
  432. } else {
  433. data = __raw_readl(ether->reg + REG_MIID);
  434. }
  435. return data;
  436. }
  437. static int set_mac_address(struct net_device *dev, void *addr)
  438. {
  439. struct sockaddr *address = addr;
  440. if (!is_valid_ether_addr(address->sa_data))
  441. return -EADDRNOTAVAIL;
  442. memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
  443. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  444. return 0;
  445. }
  446. static int w90p910_ether_close(struct net_device *dev)
  447. {
  448. struct w90p910_ether *ether = netdev_priv(dev);
  449. dma_free_writecombine(NULL, sizeof(struct w90p910_rxbd),
  450. ether->rdesc, (dma_addr_t)ether->rdesc_phys);
  451. dma_free_writecombine(NULL, sizeof(struct w90p910_txbd),
  452. ether->tdesc, (dma_addr_t)ether->tdesc_phys);
  453. netif_stop_queue(dev);
  454. del_timer_sync(&ether->check_timer);
  455. clk_disable(ether->rmiiclk);
  456. clk_disable(ether->clk);
  457. free_irq(ether->txirq, dev);
  458. free_irq(ether->rxirq, dev);
  459. return 0;
  460. }
  461. static struct net_device_stats *w90p910_ether_stats(struct net_device *dev)
  462. {
  463. struct w90p910_ether *ether;
  464. ether = netdev_priv(dev);
  465. return &ether->stats;
  466. }
  467. static int w90p910_send_frame(struct net_device *dev,
  468. unsigned char *data, int length)
  469. {
  470. struct w90p910_ether *ether;
  471. struct w90p910_txbd *txbd;
  472. struct platform_device *pdev;
  473. unsigned char *buffer;
  474. ether = netdev_priv(dev);
  475. pdev = ether->pdev;
  476. txbd = &ether->tdesc->desclist[ether->cur_tx];
  477. buffer = ether->tdesc->tran_buf[ether->cur_tx];
  478. if (length > 1514) {
  479. dev_err(&pdev->dev, "send data %d bytes, check it\n", length);
  480. length = 1514;
  481. }
  482. txbd->sl = length & 0xFFFF;
  483. memcpy(buffer, data, length);
  484. txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN;
  485. w90p910_enable_tx(dev, 1);
  486. w90p910_trigger_tx(dev);
  487. ether->cur_tx = (ether->cur_tx+1) % TX_DESC_SIZE;
  488. txbd = &ether->tdesc->desclist[ether->cur_tx];
  489. dev->trans_start = jiffies;
  490. if (txbd->mode & TX_OWEN_DMA)
  491. netif_stop_queue(dev);
  492. return 0;
  493. }
  494. static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
  495. {
  496. struct w90p910_ether *ether = netdev_priv(dev);
  497. if (!(w90p910_send_frame(dev, skb->data, skb->len))) {
  498. ether->skb = skb;
  499. dev_kfree_skb_irq(skb);
  500. return 0;
  501. }
  502. return -1;
  503. }
  504. static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id)
  505. {
  506. struct w90p910_ether *ether;
  507. struct w90p910_txbd *txbd;
  508. struct platform_device *pdev;
  509. struct tran_pdesc *tran_pdesc;
  510. struct net_device *dev;
  511. unsigned int cur_entry, entry, status;
  512. dev = (struct net_device *)dev_id;
  513. ether = netdev_priv(dev);
  514. pdev = ether->pdev;
  515. spin_lock(&ether->lock);
  516. w90p910_get_and_clear_int(dev, &status);
  517. cur_entry = __raw_readl(ether->reg + REG_CTXDSA);
  518. tran_pdesc = ether->tdesc_phys;
  519. entry = (unsigned int)(&tran_pdesc->desclist[ether->finish_tx]);
  520. while (entry != cur_entry) {
  521. txbd = &ether->tdesc->desclist[ether->finish_tx];
  522. ether->finish_tx = (ether->finish_tx + 1) % TX_DESC_SIZE;
  523. if (txbd->sl & TXDS_TXCP) {
  524. ether->stats.tx_packets++;
  525. ether->stats.tx_bytes += txbd->sl & 0xFFFF;
  526. } else {
  527. ether->stats.tx_errors++;
  528. }
  529. txbd->sl = 0x0;
  530. txbd->mode = 0x0;
  531. if (netif_queue_stopped(dev))
  532. netif_wake_queue(dev);
  533. entry = (unsigned int)(&tran_pdesc->desclist[ether->finish_tx]);
  534. }
  535. if (status & MISTA_EXDEF) {
  536. dev_err(&pdev->dev, "emc defer exceed interrupt\n");
  537. } else if (status & MISTA_TXBERR) {
  538. dev_err(&pdev->dev, "emc bus error interrupt\n");
  539. w90p910_reset_mac(dev);
  540. } else if (status & MISTA_TDU) {
  541. if (netif_queue_stopped(dev))
  542. netif_wake_queue(dev);
  543. }
  544. spin_unlock(&ether->lock);
  545. return IRQ_HANDLED;
  546. }
  547. static void netdev_rx(struct net_device *dev)
  548. {
  549. struct w90p910_ether *ether;
  550. struct w90p910_rxbd *rxbd;
  551. struct platform_device *pdev;
  552. struct recv_pdesc *rdesc_phys;
  553. struct sk_buff *skb;
  554. unsigned char *data;
  555. unsigned int length, status, val, entry;
  556. ether = netdev_priv(dev);
  557. pdev = ether->pdev;
  558. rdesc_phys = ether->rdesc_phys;
  559. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  560. do {
  561. val = __raw_readl(ether->reg + REG_CRXDSA);
  562. entry = (unsigned int)&rdesc_phys->desclist[ether->cur_rx];
  563. if (val == entry)
  564. break;
  565. status = rxbd->sl;
  566. length = status & 0xFFFF;
  567. if (status & RXDS_RXGD) {
  568. data = ether->rdesc->recv_buf[ether->cur_rx];
  569. skb = dev_alloc_skb(length+2);
  570. if (!skb) {
  571. dev_err(&pdev->dev, "get skb buffer error\n");
  572. ether->stats.rx_dropped++;
  573. return;
  574. }
  575. skb->dev = dev;
  576. skb_reserve(skb, 2);
  577. skb_put(skb, length);
  578. skb_copy_to_linear_data(skb, data, length);
  579. skb->protocol = eth_type_trans(skb, dev);
  580. ether->stats.rx_packets++;
  581. ether->stats.rx_bytes += length;
  582. netif_rx(skb);
  583. } else {
  584. ether->stats.rx_errors++;
  585. if (status & RXDS_RP) {
  586. dev_err(&pdev->dev, "rx runt err\n");
  587. ether->stats.rx_length_errors++;
  588. } else if (status & RXDS_CRCE) {
  589. dev_err(&pdev->dev, "rx crc err\n");
  590. ether->stats.rx_crc_errors++;
  591. }
  592. if (status & RXDS_ALIE) {
  593. dev_err(&pdev->dev, "rx aligment err\n");
  594. ether->stats.rx_frame_errors++;
  595. } else if (status & RXDS_PTLE) {
  596. dev_err(&pdev->dev, "rx longer err\n");
  597. ether->stats.rx_over_errors++;
  598. }
  599. }
  600. rxbd->sl = RX_OWEN_DMA;
  601. rxbd->reserved = 0x0;
  602. ether->cur_rx = (ether->cur_rx+1) % RX_DESC_SIZE;
  603. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  604. dev->last_rx = jiffies;
  605. } while (1);
  606. }
  607. static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id)
  608. {
  609. struct net_device *dev;
  610. struct w90p910_ether *ether;
  611. struct platform_device *pdev;
  612. unsigned int status;
  613. dev = (struct net_device *)dev_id;
  614. ether = netdev_priv(dev);
  615. pdev = ether->pdev;
  616. spin_lock(&ether->lock);
  617. w90p910_get_and_clear_int(dev, &status);
  618. if (status & MISTA_RDU) {
  619. netdev_rx(dev);
  620. w90p910_trigger_rx(dev);
  621. spin_unlock(&ether->lock);
  622. return IRQ_HANDLED;
  623. } else if (status & MISTA_RXBERR) {
  624. dev_err(&pdev->dev, "emc rx bus error\n");
  625. w90p910_reset_mac(dev);
  626. }
  627. netdev_rx(dev);
  628. spin_unlock(&ether->lock);
  629. return IRQ_HANDLED;
  630. }
  631. static int w90p910_ether_open(struct net_device *dev)
  632. {
  633. struct w90p910_ether *ether;
  634. struct platform_device *pdev;
  635. ether = netdev_priv(dev);
  636. pdev = ether->pdev;
  637. w90p910_reset_mac(dev);
  638. w90p910_set_fifo_threshold(dev);
  639. w90p910_set_curdest(dev);
  640. w90p910_enable_cam(dev);
  641. w90p910_enable_cam_command(dev);
  642. w90p910_enable_mac_interrupt(dev);
  643. w90p910_set_global_maccmd(dev);
  644. w90p910_enable_rx(dev, 1);
  645. ether->rx_packets = 0x0;
  646. ether->rx_bytes = 0x0;
  647. if (request_irq(ether->txirq, w90p910_tx_interrupt,
  648. 0x0, pdev->name, dev)) {
  649. dev_err(&pdev->dev, "register irq tx failed\n");
  650. return -EAGAIN;
  651. }
  652. if (request_irq(ether->rxirq, w90p910_rx_interrupt,
  653. 0x0, pdev->name, dev)) {
  654. dev_err(&pdev->dev, "register irq rx failed\n");
  655. return -EAGAIN;
  656. }
  657. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  658. netif_start_queue(dev);
  659. w90p910_trigger_rx(dev);
  660. dev_info(&pdev->dev, "%s is OPENED\n", dev->name);
  661. return 0;
  662. }
  663. static void w90p910_ether_set_multicast_list(struct net_device *dev)
  664. {
  665. struct w90p910_ether *ether;
  666. unsigned int rx_mode;
  667. ether = netdev_priv(dev);
  668. if (dev->flags & IFF_PROMISC)
  669. rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  670. else if ((dev->flags & IFF_ALLMULTI) || dev->mc_list)
  671. rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  672. else
  673. rx_mode = CAMCMR_ECMP | CAMCMR_ABP;
  674. __raw_writel(rx_mode, ether->reg + REG_CAMCMR);
  675. }
  676. static int w90p910_ether_ioctl(struct net_device *dev,
  677. struct ifreq *ifr, int cmd)
  678. {
  679. struct w90p910_ether *ether = netdev_priv(dev);
  680. struct mii_ioctl_data *data = if_mii(ifr);
  681. return generic_mii_ioctl(&ether->mii, data, cmd, NULL);
  682. }
  683. static void w90p910_get_drvinfo(struct net_device *dev,
  684. struct ethtool_drvinfo *info)
  685. {
  686. strcpy(info->driver, DRV_MODULE_NAME);
  687. strcpy(info->version, DRV_MODULE_VERSION);
  688. }
  689. static int w90p910_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  690. {
  691. struct w90p910_ether *ether = netdev_priv(dev);
  692. return mii_ethtool_gset(&ether->mii, cmd);
  693. }
  694. static int w90p910_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  695. {
  696. struct w90p910_ether *ether = netdev_priv(dev);
  697. return mii_ethtool_sset(&ether->mii, cmd);
  698. }
  699. static int w90p910_nway_reset(struct net_device *dev)
  700. {
  701. struct w90p910_ether *ether = netdev_priv(dev);
  702. return mii_nway_restart(&ether->mii);
  703. }
  704. static u32 w90p910_get_link(struct net_device *dev)
  705. {
  706. struct w90p910_ether *ether = netdev_priv(dev);
  707. return mii_link_ok(&ether->mii);
  708. }
  709. static const struct ethtool_ops w90p910_ether_ethtool_ops = {
  710. .get_settings = w90p910_get_settings,
  711. .set_settings = w90p910_set_settings,
  712. .get_drvinfo = w90p910_get_drvinfo,
  713. .nway_reset = w90p910_nway_reset,
  714. .get_link = w90p910_get_link,
  715. };
  716. static const struct net_device_ops w90p910_ether_netdev_ops = {
  717. .ndo_open = w90p910_ether_open,
  718. .ndo_stop = w90p910_ether_close,
  719. .ndo_start_xmit = w90p910_ether_start_xmit,
  720. .ndo_get_stats = w90p910_ether_stats,
  721. .ndo_set_multicast_list = w90p910_ether_set_multicast_list,
  722. .ndo_set_mac_address = set_mac_address,
  723. .ndo_do_ioctl = w90p910_ether_ioctl,
  724. .ndo_validate_addr = eth_validate_addr,
  725. .ndo_change_mtu = eth_change_mtu,
  726. };
  727. static void __init get_mac_address(struct net_device *dev)
  728. {
  729. struct w90p910_ether *ether = netdev_priv(dev);
  730. struct platform_device *pdev;
  731. char addr[6];
  732. pdev = ether->pdev;
  733. addr[0] = 0x00;
  734. addr[1] = 0x02;
  735. addr[2] = 0xac;
  736. addr[3] = 0x55;
  737. addr[4] = 0x88;
  738. addr[5] = 0xa8;
  739. if (is_valid_ether_addr(addr))
  740. memcpy(dev->dev_addr, &addr, 0x06);
  741. else
  742. dev_err(&pdev->dev, "invalid mac address\n");
  743. }
  744. static int w90p910_ether_setup(struct net_device *dev)
  745. {
  746. struct w90p910_ether *ether = netdev_priv(dev);
  747. ether_setup(dev);
  748. dev->netdev_ops = &w90p910_ether_netdev_ops;
  749. dev->ethtool_ops = &w90p910_ether_ethtool_ops;
  750. dev->tx_queue_len = 16;
  751. dev->dma = 0x0;
  752. dev->watchdog_timeo = TX_TIMEOUT;
  753. get_mac_address(dev);
  754. spin_lock_init(&ether->lock);
  755. ether->cur_tx = 0x0;
  756. ether->cur_rx = 0x0;
  757. ether->finish_tx = 0x0;
  758. ether->linkflag = 0x0;
  759. ether->mii.phy_id = 0x01;
  760. ether->mii.phy_id_mask = 0x1f;
  761. ether->mii.reg_num_mask = 0x1f;
  762. ether->mii.dev = dev;
  763. ether->mii.mdio_read = w90p910_mdio_read;
  764. ether->mii.mdio_write = w90p910_mdio_write;
  765. setup_timer(&ether->check_timer, w90p910_check_link,
  766. (unsigned long)dev);
  767. return 0;
  768. }
  769. static int __devinit w90p910_ether_probe(struct platform_device *pdev)
  770. {
  771. struct w90p910_ether *ether;
  772. struct net_device *dev;
  773. struct resource *res;
  774. int error;
  775. dev = alloc_etherdev(sizeof(struct w90p910_ether));
  776. if (!dev)
  777. return -ENOMEM;
  778. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  779. if (res == NULL) {
  780. dev_err(&pdev->dev, "failed to get I/O memory\n");
  781. error = -ENXIO;
  782. goto failed_free;
  783. }
  784. res = request_mem_region(res->start, resource_size(res), pdev->name);
  785. if (res == NULL) {
  786. dev_err(&pdev->dev, "failed to request I/O memory\n");
  787. error = -EBUSY;
  788. goto failed_free;
  789. }
  790. ether = netdev_priv(dev);
  791. ether->reg = ioremap(res->start, resource_size(res));
  792. if (ether->reg == NULL) {
  793. dev_err(&pdev->dev, "failed to remap I/O memory\n");
  794. error = -ENXIO;
  795. goto failed_free_mem;
  796. }
  797. ether->txirq = platform_get_irq(pdev, 0);
  798. if (ether->txirq < 0) {
  799. dev_err(&pdev->dev, "failed to get ether tx irq\n");
  800. error = -ENXIO;
  801. goto failed_free_io;
  802. }
  803. ether->rxirq = platform_get_irq(pdev, 1);
  804. if (ether->rxirq < 0) {
  805. dev_err(&pdev->dev, "failed to get ether rx irq\n");
  806. error = -ENXIO;
  807. goto failed_free_txirq;
  808. }
  809. platform_set_drvdata(pdev, dev);
  810. ether->clk = clk_get(&pdev->dev, NULL);
  811. if (IS_ERR(ether->clk)) {
  812. dev_err(&pdev->dev, "failed to get ether clock\n");
  813. error = PTR_ERR(ether->clk);
  814. goto failed_free_rxirq;
  815. }
  816. ether->rmiiclk = clk_get(&pdev->dev, "RMII");
  817. if (IS_ERR(ether->rmiiclk)) {
  818. dev_err(&pdev->dev, "failed to get ether clock\n");
  819. error = PTR_ERR(ether->rmiiclk);
  820. goto failed_put_clk;
  821. }
  822. ether->pdev = pdev;
  823. w90p910_ether_setup(dev);
  824. error = register_netdev(dev);
  825. if (error != 0) {
  826. dev_err(&pdev->dev, "Regiter EMC w90p910 FAILED\n");
  827. error = -ENODEV;
  828. goto failed_put_rmiiclk;
  829. }
  830. return 0;
  831. failed_put_rmiiclk:
  832. clk_put(ether->rmiiclk);
  833. failed_put_clk:
  834. clk_put(ether->clk);
  835. failed_free_rxirq:
  836. free_irq(ether->rxirq, pdev);
  837. platform_set_drvdata(pdev, NULL);
  838. failed_free_txirq:
  839. free_irq(ether->txirq, pdev);
  840. failed_free_io:
  841. iounmap(ether->reg);
  842. failed_free_mem:
  843. release_mem_region(res->start, resource_size(res));
  844. failed_free:
  845. free_netdev(dev);
  846. return error;
  847. }
  848. static int __devexit w90p910_ether_remove(struct platform_device *pdev)
  849. {
  850. struct net_device *dev = platform_get_drvdata(pdev);
  851. struct w90p910_ether *ether = netdev_priv(dev);
  852. unregister_netdev(dev);
  853. clk_put(ether->rmiiclk);
  854. clk_put(ether->clk);
  855. del_timer_sync(&ether->check_timer);
  856. platform_set_drvdata(pdev, NULL);
  857. free_netdev(dev);
  858. return 0;
  859. }
  860. static struct platform_driver w90p910_ether_driver = {
  861. .probe = w90p910_ether_probe,
  862. .remove = __devexit_p(w90p910_ether_remove),
  863. .driver = {
  864. .name = "w90p910-emc",
  865. .owner = THIS_MODULE,
  866. },
  867. };
  868. static int __init w90p910_ether_init(void)
  869. {
  870. return platform_driver_register(&w90p910_ether_driver);
  871. }
  872. static void __exit w90p910_ether_exit(void)
  873. {
  874. platform_driver_unregister(&w90p910_ether_driver);
  875. }
  876. module_init(w90p910_ether_init);
  877. module_exit(w90p910_ether_exit);
  878. MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
  879. MODULE_DESCRIPTION("w90p910 MAC driver!");
  880. MODULE_LICENSE("GPL");
  881. MODULE_ALIAS("platform:w90p910-emc");