tmio_mmc.c 16 KB

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  1. /*
  2. * linux/drivers/mmc/tmio_mmc.c
  3. *
  4. * Copyright (C) 2004 Ian Molton
  5. * Copyright (C) 2007 Ian Molton
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Driver for the MMC / SD / SDIO cell found in:
  12. *
  13. * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
  14. *
  15. * This driver draws mainly on scattered spec sheets, Reverse engineering
  16. * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
  17. * support). (Further 4 bit support from a later datasheet).
  18. *
  19. * TODO:
  20. * Investigate using a workqueue for PIO transfers
  21. * Eliminate FIXMEs
  22. * SDIO support
  23. * Better Power management
  24. * Handle MMC errors better
  25. * double buffer support
  26. *
  27. */
  28. #include <linux/module.h>
  29. #include <linux/irq.h>
  30. #include <linux/device.h>
  31. #include <linux/delay.h>
  32. #include <linux/mmc/host.h>
  33. #include <linux/mfd/core.h>
  34. #include <linux/mfd/tmio.h>
  35. #include "tmio_mmc.h"
  36. static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
  37. {
  38. u32 clk = 0, clock;
  39. if (new_clock) {
  40. for (clock = host->mmc->f_min, clk = 0x80000080;
  41. new_clock >= (clock<<1); clk >>= 1)
  42. clock <<= 1;
  43. clk |= 0x100;
  44. }
  45. sd_config_write8(host, CNF_SD_CLK_MODE, clk >> 22);
  46. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
  47. }
  48. static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
  49. {
  50. sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
  51. msleep(10);
  52. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
  53. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  54. msleep(10);
  55. }
  56. static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
  57. {
  58. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
  59. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  60. msleep(10);
  61. sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
  62. msleep(10);
  63. }
  64. static void reset(struct tmio_mmc_host *host)
  65. {
  66. /* FIXME - should we set stop clock reg here */
  67. sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
  68. sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
  69. msleep(10);
  70. sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
  71. sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
  72. msleep(10);
  73. }
  74. static void
  75. tmio_mmc_finish_request(struct tmio_mmc_host *host)
  76. {
  77. struct mmc_request *mrq = host->mrq;
  78. host->mrq = NULL;
  79. host->cmd = NULL;
  80. host->data = NULL;
  81. mmc_request_done(host->mmc, mrq);
  82. }
  83. /* These are the bitmasks the tmio chip requires to implement the MMC response
  84. * types. Note that R1 and R6 are the same in this scheme. */
  85. #define APP_CMD 0x0040
  86. #define RESP_NONE 0x0300
  87. #define RESP_R1 0x0400
  88. #define RESP_R1B 0x0500
  89. #define RESP_R2 0x0600
  90. #define RESP_R3 0x0700
  91. #define DATA_PRESENT 0x0800
  92. #define TRANSFER_READ 0x1000
  93. #define TRANSFER_MULTI 0x2000
  94. #define SECURITY_CMD 0x4000
  95. static int
  96. tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
  97. {
  98. struct mmc_data *data = host->data;
  99. int c = cmd->opcode;
  100. /* Command 12 is handled by hardware */
  101. if (cmd->opcode == 12 && !cmd->arg) {
  102. sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
  103. return 0;
  104. }
  105. switch (mmc_resp_type(cmd)) {
  106. case MMC_RSP_NONE: c |= RESP_NONE; break;
  107. case MMC_RSP_R1: c |= RESP_R1; break;
  108. case MMC_RSP_R1B: c |= RESP_R1B; break;
  109. case MMC_RSP_R2: c |= RESP_R2; break;
  110. case MMC_RSP_R3: c |= RESP_R3; break;
  111. default:
  112. pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
  113. return -EINVAL;
  114. }
  115. host->cmd = cmd;
  116. /* FIXME - this seems to be ok comented out but the spec suggest this bit should
  117. * be set when issuing app commands.
  118. * if(cmd->flags & MMC_FLAG_ACMD)
  119. * c |= APP_CMD;
  120. */
  121. if (data) {
  122. c |= DATA_PRESENT;
  123. if (data->blocks > 1) {
  124. sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
  125. c |= TRANSFER_MULTI;
  126. }
  127. if (data->flags & MMC_DATA_READ)
  128. c |= TRANSFER_READ;
  129. }
  130. enable_mmc_irqs(host, TMIO_MASK_CMD);
  131. /* Fire off the command */
  132. sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
  133. sd_ctrl_write16(host, CTL_SD_CMD, c);
  134. return 0;
  135. }
  136. /* This chip always returns (at least?) as much data as you ask for.
  137. * I'm unsure what happens if you ask for less than a block. This should be
  138. * looked into to ensure that a funny length read doesnt hose the controller.
  139. *
  140. */
  141. static inline void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
  142. {
  143. struct mmc_data *data = host->data;
  144. unsigned short *buf;
  145. unsigned int count;
  146. unsigned long flags;
  147. if (!data) {
  148. pr_debug("Spurious PIO IRQ\n");
  149. return;
  150. }
  151. buf = (unsigned short *)(tmio_mmc_kmap_atomic(host, &flags) +
  152. host->sg_off);
  153. count = host->sg_ptr->length - host->sg_off;
  154. if (count > data->blksz)
  155. count = data->blksz;
  156. pr_debug("count: %08x offset: %08x flags %08x\n",
  157. count, host->sg_off, data->flags);
  158. /* Transfer the data */
  159. if (data->flags & MMC_DATA_READ)
  160. sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
  161. else
  162. sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
  163. host->sg_off += count;
  164. tmio_mmc_kunmap_atomic(host, &flags);
  165. if (host->sg_off == host->sg_ptr->length)
  166. tmio_mmc_next_sg(host);
  167. return;
  168. }
  169. static inline void tmio_mmc_data_irq(struct tmio_mmc_host *host)
  170. {
  171. struct mmc_data *data = host->data;
  172. struct mmc_command *stop;
  173. host->data = NULL;
  174. if (!data) {
  175. pr_debug("Spurious data end IRQ\n");
  176. return;
  177. }
  178. stop = data->stop;
  179. /* FIXME - return correct transfer count on errors */
  180. if (!data->error)
  181. data->bytes_xfered = data->blocks * data->blksz;
  182. else
  183. data->bytes_xfered = 0;
  184. pr_debug("Completed data request\n");
  185. /*FIXME - other drivers allow an optional stop command of any given type
  186. * which we dont do, as the chip can auto generate them.
  187. * Perhaps we can be smarter about when to use auto CMD12 and
  188. * only issue the auto request when we know this is the desired
  189. * stop command, allowing fallback to the stop command the
  190. * upper layers expect. For now, we do what works.
  191. */
  192. if (data->flags & MMC_DATA_READ)
  193. disable_mmc_irqs(host, TMIO_MASK_READOP);
  194. else
  195. disable_mmc_irqs(host, TMIO_MASK_WRITEOP);
  196. if (stop) {
  197. if (stop->opcode == 12 && !stop->arg)
  198. sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
  199. else
  200. BUG();
  201. }
  202. tmio_mmc_finish_request(host);
  203. }
  204. static inline void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
  205. unsigned int stat)
  206. {
  207. struct mmc_command *cmd = host->cmd;
  208. int i, addr;
  209. if (!host->cmd) {
  210. pr_debug("Spurious CMD irq\n");
  211. return;
  212. }
  213. host->cmd = NULL;
  214. /* This controller is sicker than the PXA one. Not only do we need to
  215. * drop the top 8 bits of the first response word, we also need to
  216. * modify the order of the response for short response command types.
  217. */
  218. for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
  219. cmd->resp[i] = sd_ctrl_read32(host, addr);
  220. if (cmd->flags & MMC_RSP_136) {
  221. cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
  222. cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
  223. cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
  224. cmd->resp[3] <<= 8;
  225. } else if (cmd->flags & MMC_RSP_R3) {
  226. cmd->resp[0] = cmd->resp[3];
  227. }
  228. if (stat & TMIO_STAT_CMDTIMEOUT)
  229. cmd->error = -ETIMEDOUT;
  230. else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
  231. cmd->error = -EILSEQ;
  232. /* If there is data to handle we enable data IRQs here, and
  233. * we will ultimatley finish the request in the data_end handler.
  234. * If theres no data or we encountered an error, finish now.
  235. */
  236. if (host->data && !cmd->error) {
  237. if (host->data->flags & MMC_DATA_READ)
  238. enable_mmc_irqs(host, TMIO_MASK_READOP);
  239. else
  240. enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
  241. } else {
  242. tmio_mmc_finish_request(host);
  243. }
  244. return;
  245. }
  246. static irqreturn_t tmio_mmc_irq(int irq, void *devid)
  247. {
  248. struct tmio_mmc_host *host = devid;
  249. unsigned int ireg, irq_mask, status;
  250. pr_debug("MMC IRQ begin\n");
  251. status = sd_ctrl_read32(host, CTL_STATUS);
  252. irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
  253. ireg = status & TMIO_MASK_IRQ & ~irq_mask;
  254. pr_debug_status(status);
  255. pr_debug_status(ireg);
  256. if (!ireg) {
  257. disable_mmc_irqs(host, status & ~irq_mask);
  258. pr_debug("tmio_mmc: Spurious irq, disabling! "
  259. "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
  260. pr_debug_status(status);
  261. goto out;
  262. }
  263. while (ireg) {
  264. /* Card insert / remove attempts */
  265. if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
  266. ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
  267. TMIO_STAT_CARD_REMOVE);
  268. mmc_detect_change(host->mmc, 0);
  269. }
  270. /* CRC and other errors */
  271. /* if (ireg & TMIO_STAT_ERR_IRQ)
  272. * handled |= tmio_error_irq(host, irq, stat);
  273. */
  274. /* Command completion */
  275. if (ireg & TMIO_MASK_CMD) {
  276. ack_mmc_irqs(host, TMIO_MASK_CMD);
  277. tmio_mmc_cmd_irq(host, status);
  278. }
  279. /* Data transfer */
  280. if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
  281. ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
  282. tmio_mmc_pio_irq(host);
  283. }
  284. /* Data transfer completion */
  285. if (ireg & TMIO_STAT_DATAEND) {
  286. ack_mmc_irqs(host, TMIO_STAT_DATAEND);
  287. tmio_mmc_data_irq(host);
  288. }
  289. /* Check status - keep going until we've handled it all */
  290. status = sd_ctrl_read32(host, CTL_STATUS);
  291. irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
  292. ireg = status & TMIO_MASK_IRQ & ~irq_mask;
  293. pr_debug("Status at end of loop: %08x\n", status);
  294. pr_debug_status(status);
  295. }
  296. pr_debug("MMC IRQ end\n");
  297. out:
  298. return IRQ_HANDLED;
  299. }
  300. static int tmio_mmc_start_data(struct tmio_mmc_host *host,
  301. struct mmc_data *data)
  302. {
  303. pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
  304. data->blksz, data->blocks);
  305. /* Hardware cannot perform 1 and 2 byte requests in 4 bit mode */
  306. if (data->blksz < 4 && host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
  307. printk(KERN_ERR "%s: %d byte block unsupported in 4 bit mode\n",
  308. mmc_hostname(host->mmc), data->blksz);
  309. return -EINVAL;
  310. }
  311. tmio_mmc_init_sg(host, data);
  312. host->data = data;
  313. /* Set transfer length / blocksize */
  314. sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
  315. sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
  316. return 0;
  317. }
  318. /* Process requests from the MMC layer */
  319. static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  320. {
  321. struct tmio_mmc_host *host = mmc_priv(mmc);
  322. int ret;
  323. if (host->mrq)
  324. pr_debug("request not null\n");
  325. host->mrq = mrq;
  326. if (mrq->data) {
  327. ret = tmio_mmc_start_data(host, mrq->data);
  328. if (ret)
  329. goto fail;
  330. }
  331. ret = tmio_mmc_start_command(host, mrq->cmd);
  332. if (!ret)
  333. return;
  334. fail:
  335. mrq->cmd->error = ret;
  336. mmc_request_done(mmc, mrq);
  337. }
  338. /* Set MMC clock / power.
  339. * Note: This controller uses a simple divider scheme therefore it cannot
  340. * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
  341. * MMC wont run that fast, it has to be clocked at 12MHz which is the next
  342. * slowest setting.
  343. */
  344. static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  345. {
  346. struct tmio_mmc_host *host = mmc_priv(mmc);
  347. if (ios->clock)
  348. tmio_mmc_set_clock(host, ios->clock);
  349. /* Power sequence - OFF -> ON -> UP */
  350. switch (ios->power_mode) {
  351. case MMC_POWER_OFF: /* power down SD bus */
  352. sd_config_write8(host, CNF_PWR_CTL_2, 0x00);
  353. tmio_mmc_clk_stop(host);
  354. break;
  355. case MMC_POWER_ON: /* power up SD bus */
  356. sd_config_write8(host, CNF_PWR_CTL_2, 0x02);
  357. break;
  358. case MMC_POWER_UP: /* start bus clock */
  359. tmio_mmc_clk_start(host);
  360. break;
  361. }
  362. switch (ios->bus_width) {
  363. case MMC_BUS_WIDTH_1:
  364. sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
  365. break;
  366. case MMC_BUS_WIDTH_4:
  367. sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
  368. break;
  369. }
  370. /* Let things settle. delay taken from winCE driver */
  371. udelay(140);
  372. }
  373. static int tmio_mmc_get_ro(struct mmc_host *mmc)
  374. {
  375. struct tmio_mmc_host *host = mmc_priv(mmc);
  376. return (sd_ctrl_read16(host, CTL_STATUS) & TMIO_STAT_WRPROTECT) ? 0 : 1;
  377. }
  378. static struct mmc_host_ops tmio_mmc_ops = {
  379. .request = tmio_mmc_request,
  380. .set_ios = tmio_mmc_set_ios,
  381. .get_ro = tmio_mmc_get_ro,
  382. };
  383. #ifdef CONFIG_PM
  384. static int tmio_mmc_suspend(struct platform_device *dev, pm_message_t state)
  385. {
  386. struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
  387. struct mmc_host *mmc = platform_get_drvdata(dev);
  388. int ret;
  389. ret = mmc_suspend_host(mmc, state);
  390. /* Tell MFD core it can disable us now.*/
  391. if (!ret && cell->disable)
  392. cell->disable(dev);
  393. return ret;
  394. }
  395. static int tmio_mmc_resume(struct platform_device *dev)
  396. {
  397. struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
  398. struct mmc_host *mmc = platform_get_drvdata(dev);
  399. struct tmio_mmc_host *host = mmc_priv(mmc);
  400. int ret = 0;
  401. /* Tell the MFD core we are ready to be enabled */
  402. if (cell->enable) {
  403. ret = cell->enable(dev);
  404. if (ret)
  405. goto out;
  406. }
  407. /* Enable the MMC/SD Control registers */
  408. sd_config_write16(host, CNF_CMD, SDCREN);
  409. sd_config_write32(host, CNF_CTL_BASE,
  410. (dev->resource[0].start >> host->bus_shift) & 0xfffe);
  411. mmc_resume_host(mmc);
  412. out:
  413. return ret;
  414. }
  415. #else
  416. #define tmio_mmc_suspend NULL
  417. #define tmio_mmc_resume NULL
  418. #endif
  419. static int __devinit tmio_mmc_probe(struct platform_device *dev)
  420. {
  421. struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
  422. struct tmio_mmc_data *pdata;
  423. struct resource *res_ctl, *res_cnf;
  424. struct tmio_mmc_host *host;
  425. struct mmc_host *mmc;
  426. int ret = -EINVAL;
  427. if (dev->num_resources != 3)
  428. goto out;
  429. res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0);
  430. res_cnf = platform_get_resource(dev, IORESOURCE_MEM, 1);
  431. if (!res_ctl || !res_cnf)
  432. goto out;
  433. pdata = cell->driver_data;
  434. if (!pdata || !pdata->hclk)
  435. goto out;
  436. ret = -ENOMEM;
  437. mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
  438. if (!mmc)
  439. goto out;
  440. host = mmc_priv(mmc);
  441. host->mmc = mmc;
  442. platform_set_drvdata(dev, mmc);
  443. /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
  444. host->bus_shift = resource_size(res_ctl) >> 10;
  445. host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
  446. if (!host->ctl)
  447. goto host_free;
  448. host->cnf = ioremap(res_cnf->start, resource_size(res_cnf));
  449. if (!host->cnf)
  450. goto unmap_ctl;
  451. mmc->ops = &tmio_mmc_ops;
  452. mmc->caps = MMC_CAP_4_BIT_DATA;
  453. mmc->f_max = pdata->hclk;
  454. mmc->f_min = mmc->f_max / 512;
  455. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  456. /* Tell the MFD core we are ready to be enabled */
  457. if (cell->enable) {
  458. ret = cell->enable(dev);
  459. if (ret)
  460. goto unmap_cnf;
  461. }
  462. /* Enable the MMC/SD Control registers */
  463. sd_config_write16(host, CNF_CMD, SDCREN);
  464. sd_config_write32(host, CNF_CTL_BASE,
  465. (dev->resource[0].start >> host->bus_shift) & 0xfffe);
  466. /* Disable SD power during suspend */
  467. sd_config_write8(host, CNF_PWR_CTL_3, 0x01);
  468. /* The below is required but why? FIXME */
  469. sd_config_write8(host, CNF_STOP_CLK_CTL, 0x1f);
  470. /* Power down SD bus*/
  471. sd_config_write8(host, CNF_PWR_CTL_2, 0x00);
  472. tmio_mmc_clk_stop(host);
  473. reset(host);
  474. ret = platform_get_irq(dev, 0);
  475. if (ret >= 0)
  476. host->irq = ret;
  477. else
  478. goto unmap_cnf;
  479. disable_mmc_irqs(host, TMIO_MASK_ALL);
  480. ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED |
  481. IRQF_TRIGGER_FALLING, "tmio-mmc", host);
  482. if (ret)
  483. goto unmap_cnf;
  484. mmc_add_host(mmc);
  485. printk(KERN_INFO "%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
  486. (unsigned long)host->ctl, host->irq);
  487. /* Unmask the IRQs we want to know about */
  488. enable_mmc_irqs(host, TMIO_MASK_IRQ);
  489. return 0;
  490. unmap_cnf:
  491. iounmap(host->cnf);
  492. unmap_ctl:
  493. iounmap(host->ctl);
  494. host_free:
  495. mmc_free_host(mmc);
  496. out:
  497. return ret;
  498. }
  499. static int __devexit tmio_mmc_remove(struct platform_device *dev)
  500. {
  501. struct mmc_host *mmc = platform_get_drvdata(dev);
  502. platform_set_drvdata(dev, NULL);
  503. if (mmc) {
  504. struct tmio_mmc_host *host = mmc_priv(mmc);
  505. mmc_remove_host(mmc);
  506. free_irq(host->irq, host);
  507. iounmap(host->ctl);
  508. iounmap(host->cnf);
  509. mmc_free_host(mmc);
  510. }
  511. return 0;
  512. }
  513. /* ------------------- device registration ----------------------- */
  514. static struct platform_driver tmio_mmc_driver = {
  515. .driver = {
  516. .name = "tmio-mmc",
  517. .owner = THIS_MODULE,
  518. },
  519. .probe = tmio_mmc_probe,
  520. .remove = __devexit_p(tmio_mmc_remove),
  521. .suspend = tmio_mmc_suspend,
  522. .resume = tmio_mmc_resume,
  523. };
  524. static int __init tmio_mmc_init(void)
  525. {
  526. return platform_driver_register(&tmio_mmc_driver);
  527. }
  528. static void __exit tmio_mmc_exit(void)
  529. {
  530. platform_driver_unregister(&tmio_mmc_driver);
  531. }
  532. module_init(tmio_mmc_init);
  533. module_exit(tmio_mmc_exit);
  534. MODULE_DESCRIPTION("Toshiba TMIO SD/MMC driver");
  535. MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
  536. MODULE_LICENSE("GPL v2");
  537. MODULE_ALIAS("platform:tmio-mmc");