tifm_sd.c 29 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Special thanks to Brad Campbell for extensive testing of this driver.
  11. *
  12. */
  13. #include <linux/tifm.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/highmem.h>
  16. #include <linux/scatterlist.h>
  17. #include <asm/io.h>
  18. #define DRIVER_NAME "tifm_sd"
  19. #define DRIVER_VERSION "0.8"
  20. static int no_dma = 0;
  21. static int fixed_timeout = 0;
  22. module_param(no_dma, bool, 0644);
  23. module_param(fixed_timeout, bool, 0644);
  24. /* Constants here are mostly from OMAP5912 datasheet */
  25. #define TIFM_MMCSD_RESET 0x0002
  26. #define TIFM_MMCSD_CLKMASK 0x03ff
  27. #define TIFM_MMCSD_POWER 0x0800
  28. #define TIFM_MMCSD_4BBUS 0x8000
  29. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  30. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  31. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  32. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  33. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  34. #define TIFM_MMCSD_READ 0x8000
  35. #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
  36. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  37. #define TIFM_MMCSD_CD 0x0002 /* card detect */
  38. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  39. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  40. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  41. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  42. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  43. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  44. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  45. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  46. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  47. #define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
  48. #define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
  49. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  50. #define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
  51. #define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
  52. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  53. #define TIFM_MMCSD_RSP_R0 0x0000
  54. #define TIFM_MMCSD_RSP_R1 0x0100
  55. #define TIFM_MMCSD_RSP_R2 0x0200
  56. #define TIFM_MMCSD_RSP_R3 0x0300
  57. #define TIFM_MMCSD_RSP_R4 0x0400
  58. #define TIFM_MMCSD_RSP_R5 0x0500
  59. #define TIFM_MMCSD_RSP_R6 0x0600
  60. #define TIFM_MMCSD_RSP_BUSY 0x0800
  61. #define TIFM_MMCSD_CMD_BC 0x0000
  62. #define TIFM_MMCSD_CMD_BCR 0x1000
  63. #define TIFM_MMCSD_CMD_AC 0x2000
  64. #define TIFM_MMCSD_CMD_ADTC 0x3000
  65. #define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
  66. enum {
  67. CMD_READY = 0x0001,
  68. FIFO_READY = 0x0002,
  69. BRS_READY = 0x0004,
  70. SCMD_ACTIVE = 0x0008,
  71. SCMD_READY = 0x0010,
  72. CARD_BUSY = 0x0020,
  73. DATA_CARRY = 0x0040
  74. };
  75. struct tifm_sd {
  76. struct tifm_dev *dev;
  77. unsigned short eject:1,
  78. open_drain:1,
  79. no_dma:1;
  80. unsigned short cmd_flags;
  81. unsigned int clk_freq;
  82. unsigned int clk_div;
  83. unsigned long timeout_jiffies;
  84. struct tasklet_struct finish_tasklet;
  85. struct timer_list timer;
  86. struct mmc_request *req;
  87. int sg_len;
  88. int sg_pos;
  89. unsigned int block_pos;
  90. struct scatterlist bounce_buf;
  91. unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
  92. };
  93. /* for some reason, host won't respond correctly to readw/writew */
  94. static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
  95. unsigned int off, unsigned int cnt)
  96. {
  97. struct tifm_dev *sock = host->dev;
  98. unsigned char *buf;
  99. unsigned int pos = 0, val;
  100. buf = kmap_atomic(pg, KM_BIO_DST_IRQ) + off;
  101. if (host->cmd_flags & DATA_CARRY) {
  102. buf[pos++] = host->bounce_buf_data[0];
  103. host->cmd_flags &= ~DATA_CARRY;
  104. }
  105. while (pos < cnt) {
  106. val = readl(sock->addr + SOCK_MMCSD_DATA);
  107. buf[pos++] = val & 0xff;
  108. if (pos == cnt) {
  109. host->bounce_buf_data[0] = (val >> 8) & 0xff;
  110. host->cmd_flags |= DATA_CARRY;
  111. break;
  112. }
  113. buf[pos++] = (val >> 8) & 0xff;
  114. }
  115. kunmap_atomic(buf - off, KM_BIO_DST_IRQ);
  116. }
  117. static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
  118. unsigned int off, unsigned int cnt)
  119. {
  120. struct tifm_dev *sock = host->dev;
  121. unsigned char *buf;
  122. unsigned int pos = 0, val;
  123. buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + off;
  124. if (host->cmd_flags & DATA_CARRY) {
  125. val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
  126. writel(val, sock->addr + SOCK_MMCSD_DATA);
  127. host->cmd_flags &= ~DATA_CARRY;
  128. }
  129. while (pos < cnt) {
  130. val = buf[pos++];
  131. if (pos == cnt) {
  132. host->bounce_buf_data[0] = val & 0xff;
  133. host->cmd_flags |= DATA_CARRY;
  134. break;
  135. }
  136. val |= (buf[pos++] << 8) & 0xff00;
  137. writel(val, sock->addr + SOCK_MMCSD_DATA);
  138. }
  139. kunmap_atomic(buf - off, KM_BIO_SRC_IRQ);
  140. }
  141. static void tifm_sd_transfer_data(struct tifm_sd *host)
  142. {
  143. struct mmc_data *r_data = host->req->cmd->data;
  144. struct scatterlist *sg = r_data->sg;
  145. unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
  146. unsigned int p_off, p_cnt;
  147. struct page *pg;
  148. if (host->sg_pos == host->sg_len)
  149. return;
  150. while (t_size) {
  151. cnt = sg[host->sg_pos].length - host->block_pos;
  152. if (!cnt) {
  153. host->block_pos = 0;
  154. host->sg_pos++;
  155. if (host->sg_pos == host->sg_len) {
  156. if ((r_data->flags & MMC_DATA_WRITE)
  157. && (host->cmd_flags & DATA_CARRY))
  158. writel(host->bounce_buf_data[0],
  159. host->dev->addr
  160. + SOCK_MMCSD_DATA);
  161. return;
  162. }
  163. cnt = sg[host->sg_pos].length;
  164. }
  165. off = sg[host->sg_pos].offset + host->block_pos;
  166. pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
  167. p_off = offset_in_page(off);
  168. p_cnt = PAGE_SIZE - p_off;
  169. p_cnt = min(p_cnt, cnt);
  170. p_cnt = min(p_cnt, t_size);
  171. if (r_data->flags & MMC_DATA_READ)
  172. tifm_sd_read_fifo(host, pg, p_off, p_cnt);
  173. else if (r_data->flags & MMC_DATA_WRITE)
  174. tifm_sd_write_fifo(host, pg, p_off, p_cnt);
  175. t_size -= p_cnt;
  176. host->block_pos += p_cnt;
  177. }
  178. }
  179. static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
  180. struct page *src, unsigned int src_off,
  181. unsigned int count)
  182. {
  183. unsigned char *src_buf = kmap_atomic(src, KM_BIO_SRC_IRQ) + src_off;
  184. unsigned char *dst_buf = kmap_atomic(dst, KM_BIO_DST_IRQ) + dst_off;
  185. memcpy(dst_buf, src_buf, count);
  186. kunmap_atomic(dst_buf - dst_off, KM_BIO_DST_IRQ);
  187. kunmap_atomic(src_buf - src_off, KM_BIO_SRC_IRQ);
  188. }
  189. static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
  190. {
  191. struct scatterlist *sg = r_data->sg;
  192. unsigned int t_size = r_data->blksz;
  193. unsigned int off, cnt;
  194. unsigned int p_off, p_cnt;
  195. struct page *pg;
  196. dev_dbg(&host->dev->dev, "bouncing block\n");
  197. while (t_size) {
  198. cnt = sg[host->sg_pos].length - host->block_pos;
  199. if (!cnt) {
  200. host->block_pos = 0;
  201. host->sg_pos++;
  202. if (host->sg_pos == host->sg_len)
  203. return;
  204. cnt = sg[host->sg_pos].length;
  205. }
  206. off = sg[host->sg_pos].offset + host->block_pos;
  207. pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
  208. p_off = offset_in_page(off);
  209. p_cnt = PAGE_SIZE - p_off;
  210. p_cnt = min(p_cnt, cnt);
  211. p_cnt = min(p_cnt, t_size);
  212. if (r_data->flags & MMC_DATA_WRITE)
  213. tifm_sd_copy_page(sg_page(&host->bounce_buf),
  214. r_data->blksz - t_size,
  215. pg, p_off, p_cnt);
  216. else if (r_data->flags & MMC_DATA_READ)
  217. tifm_sd_copy_page(pg, p_off, sg_page(&host->bounce_buf),
  218. r_data->blksz - t_size, p_cnt);
  219. t_size -= p_cnt;
  220. host->block_pos += p_cnt;
  221. }
  222. }
  223. static int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
  224. {
  225. struct tifm_dev *sock = host->dev;
  226. unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
  227. unsigned int dma_len, dma_blk_cnt, dma_off;
  228. struct scatterlist *sg = NULL;
  229. unsigned long flags;
  230. if (host->sg_pos == host->sg_len)
  231. return 1;
  232. if (host->cmd_flags & DATA_CARRY) {
  233. host->cmd_flags &= ~DATA_CARRY;
  234. local_irq_save(flags);
  235. tifm_sd_bounce_block(host, r_data);
  236. local_irq_restore(flags);
  237. if (host->sg_pos == host->sg_len)
  238. return 1;
  239. }
  240. dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
  241. if (!dma_len) {
  242. host->block_pos = 0;
  243. host->sg_pos++;
  244. if (host->sg_pos == host->sg_len)
  245. return 1;
  246. dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
  247. }
  248. if (dma_len < t_size) {
  249. dma_blk_cnt = dma_len / r_data->blksz;
  250. dma_off = host->block_pos;
  251. host->block_pos += dma_blk_cnt * r_data->blksz;
  252. } else {
  253. dma_blk_cnt = TIFM_DMA_TSIZE;
  254. dma_off = host->block_pos;
  255. host->block_pos += t_size;
  256. }
  257. if (dma_blk_cnt)
  258. sg = &r_data->sg[host->sg_pos];
  259. else if (dma_len) {
  260. if (r_data->flags & MMC_DATA_WRITE) {
  261. local_irq_save(flags);
  262. tifm_sd_bounce_block(host, r_data);
  263. local_irq_restore(flags);
  264. } else
  265. host->cmd_flags |= DATA_CARRY;
  266. sg = &host->bounce_buf;
  267. dma_off = 0;
  268. dma_blk_cnt = 1;
  269. } else
  270. return 1;
  271. dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
  272. writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
  273. if (r_data->flags & MMC_DATA_WRITE)
  274. writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
  275. sock->addr + SOCK_DMA_CONTROL);
  276. else
  277. writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
  278. sock->addr + SOCK_DMA_CONTROL);
  279. return 0;
  280. }
  281. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  282. {
  283. unsigned int rc = 0;
  284. switch (mmc_resp_type(cmd)) {
  285. case MMC_RSP_NONE:
  286. rc |= TIFM_MMCSD_RSP_R0;
  287. break;
  288. case MMC_RSP_R1B:
  289. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  290. case MMC_RSP_R1:
  291. rc |= TIFM_MMCSD_RSP_R1;
  292. break;
  293. case MMC_RSP_R2:
  294. rc |= TIFM_MMCSD_RSP_R2;
  295. break;
  296. case MMC_RSP_R3:
  297. rc |= TIFM_MMCSD_RSP_R3;
  298. break;
  299. default:
  300. BUG();
  301. }
  302. switch (mmc_cmd_type(cmd)) {
  303. case MMC_CMD_BC:
  304. rc |= TIFM_MMCSD_CMD_BC;
  305. break;
  306. case MMC_CMD_BCR:
  307. rc |= TIFM_MMCSD_CMD_BCR;
  308. break;
  309. case MMC_CMD_AC:
  310. rc |= TIFM_MMCSD_CMD_AC;
  311. break;
  312. case MMC_CMD_ADTC:
  313. rc |= TIFM_MMCSD_CMD_ADTC;
  314. break;
  315. default:
  316. BUG();
  317. }
  318. return rc;
  319. }
  320. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  321. {
  322. struct tifm_dev *sock = host->dev;
  323. unsigned int cmd_mask = tifm_sd_op_flags(cmd);
  324. if (host->open_drain)
  325. cmd_mask |= TIFM_MMCSD_ODTO;
  326. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  327. cmd_mask |= TIFM_MMCSD_READ;
  328. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  329. cmd->opcode, cmd->arg, cmd_mask);
  330. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  331. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  332. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  333. }
  334. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  335. {
  336. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  337. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  338. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  339. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  340. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  341. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  342. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  343. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  344. }
  345. static void tifm_sd_check_status(struct tifm_sd *host)
  346. {
  347. struct tifm_dev *sock = host->dev;
  348. struct mmc_command *cmd = host->req->cmd;
  349. if (cmd->error)
  350. goto finish_request;
  351. if (!(host->cmd_flags & CMD_READY))
  352. return;
  353. if (cmd->data) {
  354. if (cmd->data->error) {
  355. if ((host->cmd_flags & SCMD_ACTIVE)
  356. && !(host->cmd_flags & SCMD_READY))
  357. return;
  358. goto finish_request;
  359. }
  360. if (!(host->cmd_flags & BRS_READY))
  361. return;
  362. if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
  363. return;
  364. if (cmd->data->flags & MMC_DATA_WRITE) {
  365. if (host->req->stop) {
  366. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  367. host->cmd_flags |= SCMD_ACTIVE;
  368. writel(TIFM_MMCSD_EOFB
  369. | readl(sock->addr
  370. + SOCK_MMCSD_INT_ENABLE),
  371. sock->addr
  372. + SOCK_MMCSD_INT_ENABLE);
  373. tifm_sd_exec(host, host->req->stop);
  374. return;
  375. } else {
  376. if (!(host->cmd_flags & SCMD_READY)
  377. || (host->cmd_flags & CARD_BUSY))
  378. return;
  379. writel((~TIFM_MMCSD_EOFB)
  380. & readl(sock->addr
  381. + SOCK_MMCSD_INT_ENABLE),
  382. sock->addr
  383. + SOCK_MMCSD_INT_ENABLE);
  384. }
  385. } else {
  386. if (host->cmd_flags & CARD_BUSY)
  387. return;
  388. writel((~TIFM_MMCSD_EOFB)
  389. & readl(sock->addr
  390. + SOCK_MMCSD_INT_ENABLE),
  391. sock->addr + SOCK_MMCSD_INT_ENABLE);
  392. }
  393. } else {
  394. if (host->req->stop) {
  395. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  396. host->cmd_flags |= SCMD_ACTIVE;
  397. tifm_sd_exec(host, host->req->stop);
  398. return;
  399. } else {
  400. if (!(host->cmd_flags & SCMD_READY))
  401. return;
  402. }
  403. }
  404. }
  405. }
  406. finish_request:
  407. tasklet_schedule(&host->finish_tasklet);
  408. }
  409. /* Called from interrupt handler */
  410. static void tifm_sd_data_event(struct tifm_dev *sock)
  411. {
  412. struct tifm_sd *host;
  413. unsigned int fifo_status = 0;
  414. struct mmc_data *r_data = NULL;
  415. spin_lock(&sock->lock);
  416. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  417. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  418. dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
  419. fifo_status, host->cmd_flags);
  420. if (host->req) {
  421. r_data = host->req->cmd->data;
  422. if (r_data && (fifo_status & TIFM_FIFO_READY)) {
  423. if (tifm_sd_set_dma_data(host, r_data)) {
  424. host->cmd_flags |= FIFO_READY;
  425. tifm_sd_check_status(host);
  426. }
  427. }
  428. }
  429. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  430. spin_unlock(&sock->lock);
  431. }
  432. /* Called from interrupt handler */
  433. static void tifm_sd_card_event(struct tifm_dev *sock)
  434. {
  435. struct tifm_sd *host;
  436. unsigned int host_status = 0;
  437. int cmd_error = 0;
  438. struct mmc_command *cmd = NULL;
  439. unsigned long flags;
  440. spin_lock(&sock->lock);
  441. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  442. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  443. dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
  444. host_status, host->cmd_flags);
  445. if (host->req) {
  446. cmd = host->req->cmd;
  447. if (host_status & TIFM_MMCSD_ERRMASK) {
  448. writel(host_status & TIFM_MMCSD_ERRMASK,
  449. sock->addr + SOCK_MMCSD_STATUS);
  450. if (host_status & TIFM_MMCSD_CTO)
  451. cmd_error = -ETIMEDOUT;
  452. else if (host_status & TIFM_MMCSD_CCRC)
  453. cmd_error = -EILSEQ;
  454. if (cmd->data) {
  455. if (host_status & TIFM_MMCSD_DTO)
  456. cmd->data->error = -ETIMEDOUT;
  457. else if (host_status & TIFM_MMCSD_DCRC)
  458. cmd->data->error = -EILSEQ;
  459. }
  460. writel(TIFM_FIFO_INT_SETALL,
  461. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  462. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  463. if (host->req->stop) {
  464. if (host->cmd_flags & SCMD_ACTIVE) {
  465. host->req->stop->error = cmd_error;
  466. host->cmd_flags |= SCMD_READY;
  467. } else {
  468. cmd->error = cmd_error;
  469. host->cmd_flags |= SCMD_ACTIVE;
  470. tifm_sd_exec(host, host->req->stop);
  471. goto done;
  472. }
  473. } else
  474. cmd->error = cmd_error;
  475. } else {
  476. if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
  477. if (!(host->cmd_flags & CMD_READY)) {
  478. host->cmd_flags |= CMD_READY;
  479. tifm_sd_fetch_resp(cmd, sock);
  480. } else if (host->cmd_flags & SCMD_ACTIVE) {
  481. host->cmd_flags |= SCMD_READY;
  482. tifm_sd_fetch_resp(host->req->stop,
  483. sock);
  484. }
  485. }
  486. if (host_status & TIFM_MMCSD_BRS)
  487. host->cmd_flags |= BRS_READY;
  488. }
  489. if (host->no_dma && cmd->data) {
  490. if (host_status & TIFM_MMCSD_AE)
  491. writel(host_status & TIFM_MMCSD_AE,
  492. sock->addr + SOCK_MMCSD_STATUS);
  493. if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
  494. | TIFM_MMCSD_BRS)) {
  495. local_irq_save(flags);
  496. tifm_sd_transfer_data(host);
  497. local_irq_restore(flags);
  498. host_status &= ~TIFM_MMCSD_AE;
  499. }
  500. }
  501. if (host_status & TIFM_MMCSD_EOFB)
  502. host->cmd_flags &= ~CARD_BUSY;
  503. else if (host_status & TIFM_MMCSD_CB)
  504. host->cmd_flags |= CARD_BUSY;
  505. tifm_sd_check_status(host);
  506. }
  507. done:
  508. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  509. spin_unlock(&sock->lock);
  510. }
  511. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  512. struct mmc_data *data)
  513. {
  514. struct tifm_dev *sock = host->dev;
  515. unsigned int data_timeout = data->timeout_clks;
  516. if (fixed_timeout)
  517. return;
  518. data_timeout += data->timeout_ns /
  519. ((1000000000UL / host->clk_freq) * host->clk_div);
  520. if (data_timeout < 0xffff) {
  521. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  522. writel((~TIFM_MMCSD_DPE)
  523. & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  524. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  525. } else {
  526. data_timeout = (data_timeout >> 10) + 1;
  527. if (data_timeout > 0xffff)
  528. data_timeout = 0; /* set to unlimited */
  529. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  530. writel(TIFM_MMCSD_DPE
  531. | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  532. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  533. }
  534. }
  535. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  536. {
  537. struct tifm_sd *host = mmc_priv(mmc);
  538. struct tifm_dev *sock = host->dev;
  539. unsigned long flags;
  540. struct mmc_data *r_data = mrq->cmd->data;
  541. spin_lock_irqsave(&sock->lock, flags);
  542. if (host->eject) {
  543. mrq->cmd->error = -ENOMEDIUM;
  544. goto err_out;
  545. }
  546. if (host->req) {
  547. printk(KERN_ERR "%s : unfinished request detected\n",
  548. dev_name(&sock->dev));
  549. mrq->cmd->error = -ETIMEDOUT;
  550. goto err_out;
  551. }
  552. host->cmd_flags = 0;
  553. host->block_pos = 0;
  554. host->sg_pos = 0;
  555. if (mrq->data && !is_power_of_2(mrq->data->blksz))
  556. host->no_dma = 1;
  557. else
  558. host->no_dma = no_dma ? 1 : 0;
  559. if (r_data) {
  560. tifm_sd_set_data_timeout(host, r_data);
  561. if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
  562. writel(TIFM_MMCSD_EOFB
  563. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  564. sock->addr + SOCK_MMCSD_INT_ENABLE);
  565. if (host->no_dma) {
  566. writel(TIFM_MMCSD_BUFINT
  567. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  568. sock->addr + SOCK_MMCSD_INT_ENABLE);
  569. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
  570. | (TIFM_MMCSD_FIFO_SIZE - 1),
  571. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  572. host->sg_len = r_data->sg_len;
  573. } else {
  574. sg_init_one(&host->bounce_buf, host->bounce_buf_data,
  575. r_data->blksz);
  576. if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
  577. r_data->flags & MMC_DATA_WRITE
  578. ? PCI_DMA_TODEVICE
  579. : PCI_DMA_FROMDEVICE)) {
  580. printk(KERN_ERR "%s : scatterlist map failed\n",
  581. dev_name(&sock->dev));
  582. mrq->cmd->error = -ENOMEM;
  583. goto err_out;
  584. }
  585. host->sg_len = tifm_map_sg(sock, r_data->sg,
  586. r_data->sg_len,
  587. r_data->flags
  588. & MMC_DATA_WRITE
  589. ? PCI_DMA_TODEVICE
  590. : PCI_DMA_FROMDEVICE);
  591. if (host->sg_len < 1) {
  592. printk(KERN_ERR "%s : scatterlist map failed\n",
  593. dev_name(&sock->dev));
  594. tifm_unmap_sg(sock, &host->bounce_buf, 1,
  595. r_data->flags & MMC_DATA_WRITE
  596. ? PCI_DMA_TODEVICE
  597. : PCI_DMA_FROMDEVICE);
  598. mrq->cmd->error = -ENOMEM;
  599. goto err_out;
  600. }
  601. writel(TIFM_FIFO_INT_SETALL,
  602. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  603. writel(ilog2(r_data->blksz) - 2,
  604. sock->addr + SOCK_FIFO_PAGE_SIZE);
  605. writel(TIFM_FIFO_ENABLE,
  606. sock->addr + SOCK_FIFO_CONTROL);
  607. writel(TIFM_FIFO_INTMASK,
  608. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  609. if (r_data->flags & MMC_DATA_WRITE)
  610. writel(TIFM_MMCSD_TXDE,
  611. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  612. else
  613. writel(TIFM_MMCSD_RXDE,
  614. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  615. tifm_sd_set_dma_data(host, r_data);
  616. }
  617. writel(r_data->blocks - 1,
  618. sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  619. writel(r_data->blksz - 1,
  620. sock->addr + SOCK_MMCSD_BLOCK_LEN);
  621. }
  622. host->req = mrq;
  623. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  624. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  625. sock->addr + SOCK_CONTROL);
  626. tifm_sd_exec(host, mrq->cmd);
  627. spin_unlock_irqrestore(&sock->lock, flags);
  628. return;
  629. err_out:
  630. spin_unlock_irqrestore(&sock->lock, flags);
  631. mmc_request_done(mmc, mrq);
  632. }
  633. static void tifm_sd_end_cmd(unsigned long data)
  634. {
  635. struct tifm_sd *host = (struct tifm_sd*)data;
  636. struct tifm_dev *sock = host->dev;
  637. struct mmc_host *mmc = tifm_get_drvdata(sock);
  638. struct mmc_request *mrq;
  639. struct mmc_data *r_data = NULL;
  640. unsigned long flags;
  641. spin_lock_irqsave(&sock->lock, flags);
  642. del_timer(&host->timer);
  643. mrq = host->req;
  644. host->req = NULL;
  645. if (!mrq) {
  646. printk(KERN_ERR " %s : no request to complete?\n",
  647. dev_name(&sock->dev));
  648. spin_unlock_irqrestore(&sock->lock, flags);
  649. return;
  650. }
  651. r_data = mrq->cmd->data;
  652. if (r_data) {
  653. if (host->no_dma) {
  654. writel((~TIFM_MMCSD_BUFINT)
  655. & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  656. sock->addr + SOCK_MMCSD_INT_ENABLE);
  657. } else {
  658. tifm_unmap_sg(sock, &host->bounce_buf, 1,
  659. (r_data->flags & MMC_DATA_WRITE)
  660. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  661. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  662. (r_data->flags & MMC_DATA_WRITE)
  663. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  664. }
  665. r_data->bytes_xfered = r_data->blocks
  666. - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  667. r_data->bytes_xfered *= r_data->blksz;
  668. r_data->bytes_xfered += r_data->blksz
  669. - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  670. }
  671. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  672. sock->addr + SOCK_CONTROL);
  673. spin_unlock_irqrestore(&sock->lock, flags);
  674. mmc_request_done(mmc, mrq);
  675. }
  676. static void tifm_sd_abort(unsigned long data)
  677. {
  678. struct tifm_sd *host = (struct tifm_sd*)data;
  679. printk(KERN_ERR
  680. "%s : card failed to respond for a long period of time "
  681. "(%x, %x)\n",
  682. dev_name(&host->dev->dev), host->req->cmd->opcode, host->cmd_flags);
  683. tifm_eject(host->dev);
  684. }
  685. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  686. {
  687. struct tifm_sd *host = mmc_priv(mmc);
  688. struct tifm_dev *sock = host->dev;
  689. unsigned int clk_div1, clk_div2;
  690. unsigned long flags;
  691. spin_lock_irqsave(&sock->lock, flags);
  692. dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
  693. "chip_select = %x, power_mode = %x, bus_width = %x\n",
  694. ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
  695. ios->power_mode, ios->bus_width);
  696. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  697. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  698. sock->addr + SOCK_MMCSD_CONFIG);
  699. } else {
  700. writel((~TIFM_MMCSD_4BBUS)
  701. & readl(sock->addr + SOCK_MMCSD_CONFIG),
  702. sock->addr + SOCK_MMCSD_CONFIG);
  703. }
  704. if (ios->clock) {
  705. clk_div1 = 20000000 / ios->clock;
  706. if (!clk_div1)
  707. clk_div1 = 1;
  708. clk_div2 = 24000000 / ios->clock;
  709. if (!clk_div2)
  710. clk_div2 = 1;
  711. if ((20000000 / clk_div1) > ios->clock)
  712. clk_div1++;
  713. if ((24000000 / clk_div2) > ios->clock)
  714. clk_div2++;
  715. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  716. host->clk_freq = 20000000;
  717. host->clk_div = clk_div1;
  718. writel((~TIFM_CTRL_FAST_CLK)
  719. & readl(sock->addr + SOCK_CONTROL),
  720. sock->addr + SOCK_CONTROL);
  721. } else {
  722. host->clk_freq = 24000000;
  723. host->clk_div = clk_div2;
  724. writel(TIFM_CTRL_FAST_CLK
  725. | readl(sock->addr + SOCK_CONTROL),
  726. sock->addr + SOCK_CONTROL);
  727. }
  728. } else {
  729. host->clk_div = 0;
  730. }
  731. host->clk_div &= TIFM_MMCSD_CLKMASK;
  732. writel(host->clk_div
  733. | ((~TIFM_MMCSD_CLKMASK)
  734. & readl(sock->addr + SOCK_MMCSD_CONFIG)),
  735. sock->addr + SOCK_MMCSD_CONFIG);
  736. host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
  737. /* chip_select : maybe later */
  738. //vdd
  739. //power is set before probe / after remove
  740. spin_unlock_irqrestore(&sock->lock, flags);
  741. }
  742. static int tifm_sd_ro(struct mmc_host *mmc)
  743. {
  744. int rc = 0;
  745. struct tifm_sd *host = mmc_priv(mmc);
  746. struct tifm_dev *sock = host->dev;
  747. unsigned long flags;
  748. spin_lock_irqsave(&sock->lock, flags);
  749. if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
  750. rc = 1;
  751. spin_unlock_irqrestore(&sock->lock, flags);
  752. return rc;
  753. }
  754. static const struct mmc_host_ops tifm_sd_ops = {
  755. .request = tifm_sd_request,
  756. .set_ios = tifm_sd_ios,
  757. .get_ro = tifm_sd_ro
  758. };
  759. static int tifm_sd_initialize_host(struct tifm_sd *host)
  760. {
  761. int rc;
  762. unsigned int host_status = 0;
  763. struct tifm_dev *sock = host->dev;
  764. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  765. mmiowb();
  766. host->clk_div = 61;
  767. host->clk_freq = 20000000;
  768. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  769. writel(host->clk_div | TIFM_MMCSD_POWER,
  770. sock->addr + SOCK_MMCSD_CONFIG);
  771. /* wait up to 0.51 sec for reset */
  772. for (rc = 32; rc <= 256; rc <<= 1) {
  773. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  774. rc = 0;
  775. break;
  776. }
  777. msleep(rc);
  778. }
  779. if (rc) {
  780. printk(KERN_ERR "%s : controller failed to reset\n",
  781. dev_name(&sock->dev));
  782. return -ENODEV;
  783. }
  784. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  785. writel(host->clk_div | TIFM_MMCSD_POWER,
  786. sock->addr + SOCK_MMCSD_CONFIG);
  787. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  788. // command timeout fixed to 64 clocks for now
  789. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
  790. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  791. for (rc = 16; rc <= 64; rc <<= 1) {
  792. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  793. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  794. if (!(host_status & TIFM_MMCSD_ERRMASK)
  795. && (host_status & TIFM_MMCSD_EOC)) {
  796. rc = 0;
  797. break;
  798. }
  799. msleep(rc);
  800. }
  801. if (rc) {
  802. printk(KERN_ERR
  803. "%s : card not ready - probe failed on initialization\n",
  804. dev_name(&sock->dev));
  805. return -ENODEV;
  806. }
  807. writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
  808. | TIFM_MMCSD_ERRMASK,
  809. sock->addr + SOCK_MMCSD_INT_ENABLE);
  810. mmiowb();
  811. return 0;
  812. }
  813. static int tifm_sd_probe(struct tifm_dev *sock)
  814. {
  815. struct mmc_host *mmc;
  816. struct tifm_sd *host;
  817. int rc = -EIO;
  818. if (!(TIFM_SOCK_STATE_OCCUPIED
  819. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  820. printk(KERN_WARNING "%s : card gone, unexpectedly\n",
  821. dev_name(&sock->dev));
  822. return rc;
  823. }
  824. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  825. if (!mmc)
  826. return -ENOMEM;
  827. host = mmc_priv(mmc);
  828. tifm_set_drvdata(sock, mmc);
  829. host->dev = sock;
  830. host->timeout_jiffies = msecs_to_jiffies(1000);
  831. tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
  832. (unsigned long)host);
  833. setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
  834. mmc->ops = &tifm_sd_ops;
  835. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  836. mmc->caps = MMC_CAP_4_BIT_DATA;
  837. mmc->f_min = 20000000 / 60;
  838. mmc->f_max = 24000000;
  839. mmc->max_blk_count = 2048;
  840. mmc->max_hw_segs = mmc->max_blk_count;
  841. mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
  842. mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
  843. mmc->max_req_size = mmc->max_seg_size;
  844. mmc->max_phys_segs = mmc->max_hw_segs;
  845. sock->card_event = tifm_sd_card_event;
  846. sock->data_event = tifm_sd_data_event;
  847. rc = tifm_sd_initialize_host(host);
  848. if (!rc)
  849. rc = mmc_add_host(mmc);
  850. if (!rc)
  851. return 0;
  852. mmc_free_host(mmc);
  853. return rc;
  854. }
  855. static void tifm_sd_remove(struct tifm_dev *sock)
  856. {
  857. struct mmc_host *mmc = tifm_get_drvdata(sock);
  858. struct tifm_sd *host = mmc_priv(mmc);
  859. unsigned long flags;
  860. spin_lock_irqsave(&sock->lock, flags);
  861. host->eject = 1;
  862. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  863. mmiowb();
  864. spin_unlock_irqrestore(&sock->lock, flags);
  865. tasklet_kill(&host->finish_tasklet);
  866. spin_lock_irqsave(&sock->lock, flags);
  867. if (host->req) {
  868. writel(TIFM_FIFO_INT_SETALL,
  869. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  870. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  871. host->req->cmd->error = -ENOMEDIUM;
  872. if (host->req->stop)
  873. host->req->stop->error = -ENOMEDIUM;
  874. tasklet_schedule(&host->finish_tasklet);
  875. }
  876. spin_unlock_irqrestore(&sock->lock, flags);
  877. mmc_remove_host(mmc);
  878. dev_dbg(&sock->dev, "after remove\n");
  879. mmc_free_host(mmc);
  880. }
  881. #ifdef CONFIG_PM
  882. static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
  883. {
  884. return mmc_suspend_host(tifm_get_drvdata(sock), state);
  885. }
  886. static int tifm_sd_resume(struct tifm_dev *sock)
  887. {
  888. struct mmc_host *mmc = tifm_get_drvdata(sock);
  889. struct tifm_sd *host = mmc_priv(mmc);
  890. int rc;
  891. rc = tifm_sd_initialize_host(host);
  892. dev_dbg(&sock->dev, "resume initialize %d\n", rc);
  893. if (rc)
  894. host->eject = 1;
  895. else
  896. rc = mmc_resume_host(mmc);
  897. return rc;
  898. }
  899. #else
  900. #define tifm_sd_suspend NULL
  901. #define tifm_sd_resume NULL
  902. #endif /* CONFIG_PM */
  903. static struct tifm_device_id tifm_sd_id_tbl[] = {
  904. { TIFM_TYPE_SD }, { }
  905. };
  906. static struct tifm_driver tifm_sd_driver = {
  907. .driver = {
  908. .name = DRIVER_NAME,
  909. .owner = THIS_MODULE
  910. },
  911. .id_table = tifm_sd_id_tbl,
  912. .probe = tifm_sd_probe,
  913. .remove = tifm_sd_remove,
  914. .suspend = tifm_sd_suspend,
  915. .resume = tifm_sd_resume
  916. };
  917. static int __init tifm_sd_init(void)
  918. {
  919. return tifm_register_driver(&tifm_sd_driver);
  920. }
  921. static void __exit tifm_sd_exit(void)
  922. {
  923. tifm_unregister_driver(&tifm_sd_driver);
  924. }
  925. MODULE_AUTHOR("Alex Dubov");
  926. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  927. MODULE_LICENSE("GPL");
  928. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  929. MODULE_VERSION(DRIVER_VERSION);
  930. module_init(tifm_sd_init);
  931. module_exit(tifm_sd_exit);