mthca_mr.c 24 KB

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  1. /*
  2. * Copyright (c) 2004 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/slab.h>
  34. #include <linux/errno.h>
  35. #include "mthca_dev.h"
  36. #include "mthca_cmd.h"
  37. #include "mthca_memfree.h"
  38. struct mthca_mtt {
  39. struct mthca_buddy *buddy;
  40. int order;
  41. u32 first_seg;
  42. };
  43. /*
  44. * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
  45. */
  46. struct mthca_mpt_entry {
  47. __be32 flags;
  48. __be32 page_size;
  49. __be32 key;
  50. __be32 pd;
  51. __be64 start;
  52. __be64 length;
  53. __be32 lkey;
  54. __be32 window_count;
  55. __be32 window_count_limit;
  56. __be64 mtt_seg;
  57. __be32 mtt_sz; /* Arbel only */
  58. u32 reserved[2];
  59. } __attribute__((packed));
  60. #define MTHCA_MPT_FLAG_SW_OWNS (0xfUL << 28)
  61. #define MTHCA_MPT_FLAG_MIO (1 << 17)
  62. #define MTHCA_MPT_FLAG_BIND_ENABLE (1 << 15)
  63. #define MTHCA_MPT_FLAG_PHYSICAL (1 << 9)
  64. #define MTHCA_MPT_FLAG_REGION (1 << 8)
  65. #define MTHCA_MTT_FLAG_PRESENT 1
  66. #define MTHCA_MPT_STATUS_SW 0xF0
  67. #define MTHCA_MPT_STATUS_HW 0x00
  68. #define SINAI_FMR_KEY_INC 0x1000000
  69. /*
  70. * Buddy allocator for MTT segments (currently not very efficient
  71. * since it doesn't keep a free list and just searches linearly
  72. * through the bitmaps)
  73. */
  74. static u32 mthca_buddy_alloc(struct mthca_buddy *buddy, int order)
  75. {
  76. int o;
  77. int m;
  78. u32 seg;
  79. spin_lock(&buddy->lock);
  80. for (o = order; o <= buddy->max_order; ++o)
  81. if (buddy->num_free[o]) {
  82. m = 1 << (buddy->max_order - o);
  83. seg = find_first_bit(buddy->bits[o], m);
  84. if (seg < m)
  85. goto found;
  86. }
  87. spin_unlock(&buddy->lock);
  88. return -1;
  89. found:
  90. clear_bit(seg, buddy->bits[o]);
  91. --buddy->num_free[o];
  92. while (o > order) {
  93. --o;
  94. seg <<= 1;
  95. set_bit(seg ^ 1, buddy->bits[o]);
  96. ++buddy->num_free[o];
  97. }
  98. spin_unlock(&buddy->lock);
  99. seg <<= order;
  100. return seg;
  101. }
  102. static void mthca_buddy_free(struct mthca_buddy *buddy, u32 seg, int order)
  103. {
  104. seg >>= order;
  105. spin_lock(&buddy->lock);
  106. while (test_bit(seg ^ 1, buddy->bits[order])) {
  107. clear_bit(seg ^ 1, buddy->bits[order]);
  108. --buddy->num_free[order];
  109. seg >>= 1;
  110. ++order;
  111. }
  112. set_bit(seg, buddy->bits[order]);
  113. ++buddy->num_free[order];
  114. spin_unlock(&buddy->lock);
  115. }
  116. static int mthca_buddy_init(struct mthca_buddy *buddy, int max_order)
  117. {
  118. int i, s;
  119. buddy->max_order = max_order;
  120. spin_lock_init(&buddy->lock);
  121. buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
  122. GFP_KERNEL);
  123. buddy->num_free = kzalloc((buddy->max_order + 1) * sizeof (int *),
  124. GFP_KERNEL);
  125. if (!buddy->bits || !buddy->num_free)
  126. goto err_out;
  127. for (i = 0; i <= buddy->max_order; ++i) {
  128. s = BITS_TO_LONGS(1 << (buddy->max_order - i));
  129. buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
  130. if (!buddy->bits[i])
  131. goto err_out_free;
  132. bitmap_zero(buddy->bits[i],
  133. 1 << (buddy->max_order - i));
  134. }
  135. set_bit(0, buddy->bits[buddy->max_order]);
  136. buddy->num_free[buddy->max_order] = 1;
  137. return 0;
  138. err_out_free:
  139. for (i = 0; i <= buddy->max_order; ++i)
  140. kfree(buddy->bits[i]);
  141. err_out:
  142. kfree(buddy->bits);
  143. kfree(buddy->num_free);
  144. return -ENOMEM;
  145. }
  146. static void mthca_buddy_cleanup(struct mthca_buddy *buddy)
  147. {
  148. int i;
  149. for (i = 0; i <= buddy->max_order; ++i)
  150. kfree(buddy->bits[i]);
  151. kfree(buddy->bits);
  152. kfree(buddy->num_free);
  153. }
  154. static u32 mthca_alloc_mtt_range(struct mthca_dev *dev, int order,
  155. struct mthca_buddy *buddy)
  156. {
  157. u32 seg = mthca_buddy_alloc(buddy, order);
  158. if (seg == -1)
  159. return -1;
  160. if (mthca_is_memfree(dev))
  161. if (mthca_table_get_range(dev, dev->mr_table.mtt_table, seg,
  162. seg + (1 << order) - 1)) {
  163. mthca_buddy_free(buddy, seg, order);
  164. seg = -1;
  165. }
  166. return seg;
  167. }
  168. static struct mthca_mtt *__mthca_alloc_mtt(struct mthca_dev *dev, int size,
  169. struct mthca_buddy *buddy)
  170. {
  171. struct mthca_mtt *mtt;
  172. int i;
  173. if (size <= 0)
  174. return ERR_PTR(-EINVAL);
  175. mtt = kmalloc(sizeof *mtt, GFP_KERNEL);
  176. if (!mtt)
  177. return ERR_PTR(-ENOMEM);
  178. mtt->buddy = buddy;
  179. mtt->order = 0;
  180. for (i = dev->limits.mtt_seg_size / 8; i < size; i <<= 1)
  181. ++mtt->order;
  182. mtt->first_seg = mthca_alloc_mtt_range(dev, mtt->order, buddy);
  183. if (mtt->first_seg == -1) {
  184. kfree(mtt);
  185. return ERR_PTR(-ENOMEM);
  186. }
  187. return mtt;
  188. }
  189. struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size)
  190. {
  191. return __mthca_alloc_mtt(dev, size, &dev->mr_table.mtt_buddy);
  192. }
  193. void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt)
  194. {
  195. if (!mtt)
  196. return;
  197. mthca_buddy_free(mtt->buddy, mtt->first_seg, mtt->order);
  198. mthca_table_put_range(dev, dev->mr_table.mtt_table,
  199. mtt->first_seg,
  200. mtt->first_seg + (1 << mtt->order) - 1);
  201. kfree(mtt);
  202. }
  203. static int __mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
  204. int start_index, u64 *buffer_list, int list_len)
  205. {
  206. struct mthca_mailbox *mailbox;
  207. __be64 *mtt_entry;
  208. int err = 0;
  209. u8 status;
  210. int i;
  211. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  212. if (IS_ERR(mailbox))
  213. return PTR_ERR(mailbox);
  214. mtt_entry = mailbox->buf;
  215. while (list_len > 0) {
  216. mtt_entry[0] = cpu_to_be64(dev->mr_table.mtt_base +
  217. mtt->first_seg * dev->limits.mtt_seg_size +
  218. start_index * 8);
  219. mtt_entry[1] = 0;
  220. for (i = 0; i < list_len && i < MTHCA_MAILBOX_SIZE / 8 - 2; ++i)
  221. mtt_entry[i + 2] = cpu_to_be64(buffer_list[i] |
  222. MTHCA_MTT_FLAG_PRESENT);
  223. /*
  224. * If we have an odd number of entries to write, add
  225. * one more dummy entry for firmware efficiency.
  226. */
  227. if (i & 1)
  228. mtt_entry[i + 2] = 0;
  229. err = mthca_WRITE_MTT(dev, mailbox, (i + 1) & ~1, &status);
  230. if (err) {
  231. mthca_warn(dev, "WRITE_MTT failed (%d)\n", err);
  232. goto out;
  233. }
  234. if (status) {
  235. mthca_warn(dev, "WRITE_MTT returned status 0x%02x\n",
  236. status);
  237. err = -EINVAL;
  238. goto out;
  239. }
  240. list_len -= i;
  241. start_index += i;
  242. buffer_list += i;
  243. }
  244. out:
  245. mthca_free_mailbox(dev, mailbox);
  246. return err;
  247. }
  248. int mthca_write_mtt_size(struct mthca_dev *dev)
  249. {
  250. if (dev->mr_table.fmr_mtt_buddy != &dev->mr_table.mtt_buddy ||
  251. !(dev->mthca_flags & MTHCA_FLAG_FMR))
  252. /*
  253. * Be friendly to WRITE_MTT command
  254. * and leave two empty slots for the
  255. * index and reserved fields of the
  256. * mailbox.
  257. */
  258. return PAGE_SIZE / sizeof (u64) - 2;
  259. /* For Arbel, all MTTs must fit in the same page. */
  260. return mthca_is_memfree(dev) ? (PAGE_SIZE / sizeof (u64)) : 0x7ffffff;
  261. }
  262. static void mthca_tavor_write_mtt_seg(struct mthca_dev *dev,
  263. struct mthca_mtt *mtt, int start_index,
  264. u64 *buffer_list, int list_len)
  265. {
  266. u64 __iomem *mtts;
  267. int i;
  268. mtts = dev->mr_table.tavor_fmr.mtt_base + mtt->first_seg * dev->limits.mtt_seg_size +
  269. start_index * sizeof (u64);
  270. for (i = 0; i < list_len; ++i)
  271. mthca_write64_raw(cpu_to_be64(buffer_list[i] | MTHCA_MTT_FLAG_PRESENT),
  272. mtts + i);
  273. }
  274. static void mthca_arbel_write_mtt_seg(struct mthca_dev *dev,
  275. struct mthca_mtt *mtt, int start_index,
  276. u64 *buffer_list, int list_len)
  277. {
  278. __be64 *mtts;
  279. dma_addr_t dma_handle;
  280. int i;
  281. int s = start_index * sizeof (u64);
  282. /* For Arbel, all MTTs must fit in the same page. */
  283. BUG_ON(s / PAGE_SIZE != (s + list_len * sizeof(u64) - 1) / PAGE_SIZE);
  284. /* Require full segments */
  285. BUG_ON(s % dev->limits.mtt_seg_size);
  286. mtts = mthca_table_find(dev->mr_table.mtt_table, mtt->first_seg +
  287. s / dev->limits.mtt_seg_size, &dma_handle);
  288. BUG_ON(!mtts);
  289. dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle,
  290. list_len * sizeof (u64), DMA_TO_DEVICE);
  291. for (i = 0; i < list_len; ++i)
  292. mtts[i] = cpu_to_be64(buffer_list[i] | MTHCA_MTT_FLAG_PRESENT);
  293. dma_sync_single_for_device(&dev->pdev->dev, dma_handle,
  294. list_len * sizeof (u64), DMA_TO_DEVICE);
  295. }
  296. int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
  297. int start_index, u64 *buffer_list, int list_len)
  298. {
  299. int size = mthca_write_mtt_size(dev);
  300. int chunk;
  301. if (dev->mr_table.fmr_mtt_buddy != &dev->mr_table.mtt_buddy ||
  302. !(dev->mthca_flags & MTHCA_FLAG_FMR))
  303. return __mthca_write_mtt(dev, mtt, start_index, buffer_list, list_len);
  304. while (list_len > 0) {
  305. chunk = min(size, list_len);
  306. if (mthca_is_memfree(dev))
  307. mthca_arbel_write_mtt_seg(dev, mtt, start_index,
  308. buffer_list, chunk);
  309. else
  310. mthca_tavor_write_mtt_seg(dev, mtt, start_index,
  311. buffer_list, chunk);
  312. list_len -= chunk;
  313. start_index += chunk;
  314. buffer_list += chunk;
  315. }
  316. return 0;
  317. }
  318. static inline u32 tavor_hw_index_to_key(u32 ind)
  319. {
  320. return ind;
  321. }
  322. static inline u32 tavor_key_to_hw_index(u32 key)
  323. {
  324. return key;
  325. }
  326. static inline u32 arbel_hw_index_to_key(u32 ind)
  327. {
  328. return (ind >> 24) | (ind << 8);
  329. }
  330. static inline u32 arbel_key_to_hw_index(u32 key)
  331. {
  332. return (key << 24) | (key >> 8);
  333. }
  334. static inline u32 hw_index_to_key(struct mthca_dev *dev, u32 ind)
  335. {
  336. if (mthca_is_memfree(dev))
  337. return arbel_hw_index_to_key(ind);
  338. else
  339. return tavor_hw_index_to_key(ind);
  340. }
  341. static inline u32 key_to_hw_index(struct mthca_dev *dev, u32 key)
  342. {
  343. if (mthca_is_memfree(dev))
  344. return arbel_key_to_hw_index(key);
  345. else
  346. return tavor_key_to_hw_index(key);
  347. }
  348. static inline u32 adjust_key(struct mthca_dev *dev, u32 key)
  349. {
  350. if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  351. return ((key << 20) & 0x800000) | (key & 0x7fffff);
  352. else
  353. return key;
  354. }
  355. int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
  356. u64 iova, u64 total_size, u32 access, struct mthca_mr *mr)
  357. {
  358. struct mthca_mailbox *mailbox;
  359. struct mthca_mpt_entry *mpt_entry;
  360. u32 key;
  361. int i;
  362. int err;
  363. u8 status;
  364. WARN_ON(buffer_size_shift >= 32);
  365. key = mthca_alloc(&dev->mr_table.mpt_alloc);
  366. if (key == -1)
  367. return -ENOMEM;
  368. key = adjust_key(dev, key);
  369. mr->ibmr.rkey = mr->ibmr.lkey = hw_index_to_key(dev, key);
  370. if (mthca_is_memfree(dev)) {
  371. err = mthca_table_get(dev, dev->mr_table.mpt_table, key);
  372. if (err)
  373. goto err_out_mpt_free;
  374. }
  375. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  376. if (IS_ERR(mailbox)) {
  377. err = PTR_ERR(mailbox);
  378. goto err_out_table;
  379. }
  380. mpt_entry = mailbox->buf;
  381. mpt_entry->flags = cpu_to_be32(MTHCA_MPT_FLAG_SW_OWNS |
  382. MTHCA_MPT_FLAG_MIO |
  383. MTHCA_MPT_FLAG_REGION |
  384. access);
  385. if (!mr->mtt)
  386. mpt_entry->flags |= cpu_to_be32(MTHCA_MPT_FLAG_PHYSICAL);
  387. mpt_entry->page_size = cpu_to_be32(buffer_size_shift - 12);
  388. mpt_entry->key = cpu_to_be32(key);
  389. mpt_entry->pd = cpu_to_be32(pd);
  390. mpt_entry->start = cpu_to_be64(iova);
  391. mpt_entry->length = cpu_to_be64(total_size);
  392. memset(&mpt_entry->lkey, 0,
  393. sizeof *mpt_entry - offsetof(struct mthca_mpt_entry, lkey));
  394. if (mr->mtt)
  395. mpt_entry->mtt_seg =
  396. cpu_to_be64(dev->mr_table.mtt_base +
  397. mr->mtt->first_seg * dev->limits.mtt_seg_size);
  398. if (0) {
  399. mthca_dbg(dev, "Dumping MPT entry %08x:\n", mr->ibmr.lkey);
  400. for (i = 0; i < sizeof (struct mthca_mpt_entry) / 4; ++i) {
  401. if (i % 4 == 0)
  402. printk("[%02x] ", i * 4);
  403. printk(" %08x", be32_to_cpu(((__be32 *) mpt_entry)[i]));
  404. if ((i + 1) % 4 == 0)
  405. printk("\n");
  406. }
  407. }
  408. err = mthca_SW2HW_MPT(dev, mailbox,
  409. key & (dev->limits.num_mpts - 1),
  410. &status);
  411. if (err) {
  412. mthca_warn(dev, "SW2HW_MPT failed (%d)\n", err);
  413. goto err_out_mailbox;
  414. } else if (status) {
  415. mthca_warn(dev, "SW2HW_MPT returned status 0x%02x\n",
  416. status);
  417. err = -EINVAL;
  418. goto err_out_mailbox;
  419. }
  420. mthca_free_mailbox(dev, mailbox);
  421. return err;
  422. err_out_mailbox:
  423. mthca_free_mailbox(dev, mailbox);
  424. err_out_table:
  425. mthca_table_put(dev, dev->mr_table.mpt_table, key);
  426. err_out_mpt_free:
  427. mthca_free(&dev->mr_table.mpt_alloc, key);
  428. return err;
  429. }
  430. int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
  431. u32 access, struct mthca_mr *mr)
  432. {
  433. mr->mtt = NULL;
  434. return mthca_mr_alloc(dev, pd, 12, 0, ~0ULL, access, mr);
  435. }
  436. int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
  437. u64 *buffer_list, int buffer_size_shift,
  438. int list_len, u64 iova, u64 total_size,
  439. u32 access, struct mthca_mr *mr)
  440. {
  441. int err;
  442. mr->mtt = mthca_alloc_mtt(dev, list_len);
  443. if (IS_ERR(mr->mtt))
  444. return PTR_ERR(mr->mtt);
  445. err = mthca_write_mtt(dev, mr->mtt, 0, buffer_list, list_len);
  446. if (err) {
  447. mthca_free_mtt(dev, mr->mtt);
  448. return err;
  449. }
  450. err = mthca_mr_alloc(dev, pd, buffer_size_shift, iova,
  451. total_size, access, mr);
  452. if (err)
  453. mthca_free_mtt(dev, mr->mtt);
  454. return err;
  455. }
  456. /* Free mr or fmr */
  457. static void mthca_free_region(struct mthca_dev *dev, u32 lkey)
  458. {
  459. mthca_table_put(dev, dev->mr_table.mpt_table,
  460. key_to_hw_index(dev, lkey));
  461. mthca_free(&dev->mr_table.mpt_alloc, key_to_hw_index(dev, lkey));
  462. }
  463. void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr)
  464. {
  465. int err;
  466. u8 status;
  467. err = mthca_HW2SW_MPT(dev, NULL,
  468. key_to_hw_index(dev, mr->ibmr.lkey) &
  469. (dev->limits.num_mpts - 1),
  470. &status);
  471. if (err)
  472. mthca_warn(dev, "HW2SW_MPT failed (%d)\n", err);
  473. else if (status)
  474. mthca_warn(dev, "HW2SW_MPT returned status 0x%02x\n",
  475. status);
  476. mthca_free_region(dev, mr->ibmr.lkey);
  477. mthca_free_mtt(dev, mr->mtt);
  478. }
  479. int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
  480. u32 access, struct mthca_fmr *mr)
  481. {
  482. struct mthca_mpt_entry *mpt_entry;
  483. struct mthca_mailbox *mailbox;
  484. u64 mtt_seg;
  485. u32 key, idx;
  486. u8 status;
  487. int list_len = mr->attr.max_pages;
  488. int err = -ENOMEM;
  489. int i;
  490. if (mr->attr.page_shift < 12 || mr->attr.page_shift >= 32)
  491. return -EINVAL;
  492. /* For Arbel, all MTTs must fit in the same page. */
  493. if (mthca_is_memfree(dev) &&
  494. mr->attr.max_pages * sizeof *mr->mem.arbel.mtts > PAGE_SIZE)
  495. return -EINVAL;
  496. mr->maps = 0;
  497. key = mthca_alloc(&dev->mr_table.mpt_alloc);
  498. if (key == -1)
  499. return -ENOMEM;
  500. key = adjust_key(dev, key);
  501. idx = key & (dev->limits.num_mpts - 1);
  502. mr->ibmr.rkey = mr->ibmr.lkey = hw_index_to_key(dev, key);
  503. if (mthca_is_memfree(dev)) {
  504. err = mthca_table_get(dev, dev->mr_table.mpt_table, key);
  505. if (err)
  506. goto err_out_mpt_free;
  507. mr->mem.arbel.mpt = mthca_table_find(dev->mr_table.mpt_table, key, NULL);
  508. BUG_ON(!mr->mem.arbel.mpt);
  509. } else
  510. mr->mem.tavor.mpt = dev->mr_table.tavor_fmr.mpt_base +
  511. sizeof *(mr->mem.tavor.mpt) * idx;
  512. mr->mtt = __mthca_alloc_mtt(dev, list_len, dev->mr_table.fmr_mtt_buddy);
  513. if (IS_ERR(mr->mtt)) {
  514. err = PTR_ERR(mr->mtt);
  515. goto err_out_table;
  516. }
  517. mtt_seg = mr->mtt->first_seg * dev->limits.mtt_seg_size;
  518. if (mthca_is_memfree(dev)) {
  519. mr->mem.arbel.mtts = mthca_table_find(dev->mr_table.mtt_table,
  520. mr->mtt->first_seg,
  521. &mr->mem.arbel.dma_handle);
  522. BUG_ON(!mr->mem.arbel.mtts);
  523. } else
  524. mr->mem.tavor.mtts = dev->mr_table.tavor_fmr.mtt_base + mtt_seg;
  525. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  526. if (IS_ERR(mailbox)) {
  527. err = PTR_ERR(mailbox);
  528. goto err_out_free_mtt;
  529. }
  530. mpt_entry = mailbox->buf;
  531. mpt_entry->flags = cpu_to_be32(MTHCA_MPT_FLAG_SW_OWNS |
  532. MTHCA_MPT_FLAG_MIO |
  533. MTHCA_MPT_FLAG_REGION |
  534. access);
  535. mpt_entry->page_size = cpu_to_be32(mr->attr.page_shift - 12);
  536. mpt_entry->key = cpu_to_be32(key);
  537. mpt_entry->pd = cpu_to_be32(pd);
  538. memset(&mpt_entry->start, 0,
  539. sizeof *mpt_entry - offsetof(struct mthca_mpt_entry, start));
  540. mpt_entry->mtt_seg = cpu_to_be64(dev->mr_table.mtt_base + mtt_seg);
  541. if (0) {
  542. mthca_dbg(dev, "Dumping MPT entry %08x:\n", mr->ibmr.lkey);
  543. for (i = 0; i < sizeof (struct mthca_mpt_entry) / 4; ++i) {
  544. if (i % 4 == 0)
  545. printk("[%02x] ", i * 4);
  546. printk(" %08x", be32_to_cpu(((__be32 *) mpt_entry)[i]));
  547. if ((i + 1) % 4 == 0)
  548. printk("\n");
  549. }
  550. }
  551. err = mthca_SW2HW_MPT(dev, mailbox,
  552. key & (dev->limits.num_mpts - 1),
  553. &status);
  554. if (err) {
  555. mthca_warn(dev, "SW2HW_MPT failed (%d)\n", err);
  556. goto err_out_mailbox_free;
  557. }
  558. if (status) {
  559. mthca_warn(dev, "SW2HW_MPT returned status 0x%02x\n",
  560. status);
  561. err = -EINVAL;
  562. goto err_out_mailbox_free;
  563. }
  564. mthca_free_mailbox(dev, mailbox);
  565. return 0;
  566. err_out_mailbox_free:
  567. mthca_free_mailbox(dev, mailbox);
  568. err_out_free_mtt:
  569. mthca_free_mtt(dev, mr->mtt);
  570. err_out_table:
  571. mthca_table_put(dev, dev->mr_table.mpt_table, key);
  572. err_out_mpt_free:
  573. mthca_free(&dev->mr_table.mpt_alloc, key);
  574. return err;
  575. }
  576. int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr)
  577. {
  578. if (fmr->maps)
  579. return -EBUSY;
  580. mthca_free_region(dev, fmr->ibmr.lkey);
  581. mthca_free_mtt(dev, fmr->mtt);
  582. return 0;
  583. }
  584. static inline int mthca_check_fmr(struct mthca_fmr *fmr, u64 *page_list,
  585. int list_len, u64 iova)
  586. {
  587. int i, page_mask;
  588. if (list_len > fmr->attr.max_pages)
  589. return -EINVAL;
  590. page_mask = (1 << fmr->attr.page_shift) - 1;
  591. /* We are getting page lists, so va must be page aligned. */
  592. if (iova & page_mask)
  593. return -EINVAL;
  594. /* Trust the user not to pass misaligned data in page_list */
  595. if (0)
  596. for (i = 0; i < list_len; ++i) {
  597. if (page_list[i] & ~page_mask)
  598. return -EINVAL;
  599. }
  600. if (fmr->maps >= fmr->attr.max_maps)
  601. return -EINVAL;
  602. return 0;
  603. }
  604. int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
  605. int list_len, u64 iova)
  606. {
  607. struct mthca_fmr *fmr = to_mfmr(ibfmr);
  608. struct mthca_dev *dev = to_mdev(ibfmr->device);
  609. struct mthca_mpt_entry mpt_entry;
  610. u32 key;
  611. int i, err;
  612. err = mthca_check_fmr(fmr, page_list, list_len, iova);
  613. if (err)
  614. return err;
  615. ++fmr->maps;
  616. key = tavor_key_to_hw_index(fmr->ibmr.lkey);
  617. key += dev->limits.num_mpts;
  618. fmr->ibmr.lkey = fmr->ibmr.rkey = tavor_hw_index_to_key(key);
  619. writeb(MTHCA_MPT_STATUS_SW, fmr->mem.tavor.mpt);
  620. for (i = 0; i < list_len; ++i) {
  621. __be64 mtt_entry = cpu_to_be64(page_list[i] |
  622. MTHCA_MTT_FLAG_PRESENT);
  623. mthca_write64_raw(mtt_entry, fmr->mem.tavor.mtts + i);
  624. }
  625. mpt_entry.lkey = cpu_to_be32(key);
  626. mpt_entry.length = cpu_to_be64(list_len * (1ull << fmr->attr.page_shift));
  627. mpt_entry.start = cpu_to_be64(iova);
  628. __raw_writel((__force u32) mpt_entry.lkey, &fmr->mem.tavor.mpt->key);
  629. memcpy_toio(&fmr->mem.tavor.mpt->start, &mpt_entry.start,
  630. offsetof(struct mthca_mpt_entry, window_count) -
  631. offsetof(struct mthca_mpt_entry, start));
  632. writeb(MTHCA_MPT_STATUS_HW, fmr->mem.tavor.mpt);
  633. return 0;
  634. }
  635. int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
  636. int list_len, u64 iova)
  637. {
  638. struct mthca_fmr *fmr = to_mfmr(ibfmr);
  639. struct mthca_dev *dev = to_mdev(ibfmr->device);
  640. u32 key;
  641. int i, err;
  642. err = mthca_check_fmr(fmr, page_list, list_len, iova);
  643. if (err)
  644. return err;
  645. ++fmr->maps;
  646. key = arbel_key_to_hw_index(fmr->ibmr.lkey);
  647. if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  648. key += SINAI_FMR_KEY_INC;
  649. else
  650. key += dev->limits.num_mpts;
  651. fmr->ibmr.lkey = fmr->ibmr.rkey = arbel_hw_index_to_key(key);
  652. *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_SW;
  653. wmb();
  654. dma_sync_single_for_cpu(&dev->pdev->dev, fmr->mem.arbel.dma_handle,
  655. list_len * sizeof(u64), DMA_TO_DEVICE);
  656. for (i = 0; i < list_len; ++i)
  657. fmr->mem.arbel.mtts[i] = cpu_to_be64(page_list[i] |
  658. MTHCA_MTT_FLAG_PRESENT);
  659. dma_sync_single_for_device(&dev->pdev->dev, fmr->mem.arbel.dma_handle,
  660. list_len * sizeof(u64), DMA_TO_DEVICE);
  661. fmr->mem.arbel.mpt->key = cpu_to_be32(key);
  662. fmr->mem.arbel.mpt->lkey = cpu_to_be32(key);
  663. fmr->mem.arbel.mpt->length = cpu_to_be64(list_len * (1ull << fmr->attr.page_shift));
  664. fmr->mem.arbel.mpt->start = cpu_to_be64(iova);
  665. wmb();
  666. *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_HW;
  667. wmb();
  668. return 0;
  669. }
  670. void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr)
  671. {
  672. if (!fmr->maps)
  673. return;
  674. fmr->maps = 0;
  675. writeb(MTHCA_MPT_STATUS_SW, fmr->mem.tavor.mpt);
  676. }
  677. void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr)
  678. {
  679. if (!fmr->maps)
  680. return;
  681. fmr->maps = 0;
  682. *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_SW;
  683. }
  684. int mthca_init_mr_table(struct mthca_dev *dev)
  685. {
  686. unsigned long addr;
  687. int mpts, mtts, err, i;
  688. err = mthca_alloc_init(&dev->mr_table.mpt_alloc,
  689. dev->limits.num_mpts,
  690. ~0, dev->limits.reserved_mrws);
  691. if (err)
  692. return err;
  693. if (!mthca_is_memfree(dev) &&
  694. (dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN))
  695. dev->limits.fmr_reserved_mtts = 0;
  696. else
  697. dev->mthca_flags |= MTHCA_FLAG_FMR;
  698. if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  699. mthca_dbg(dev, "Memory key throughput optimization activated.\n");
  700. err = mthca_buddy_init(&dev->mr_table.mtt_buddy,
  701. fls(dev->limits.num_mtt_segs - 1));
  702. if (err)
  703. goto err_mtt_buddy;
  704. dev->mr_table.tavor_fmr.mpt_base = NULL;
  705. dev->mr_table.tavor_fmr.mtt_base = NULL;
  706. if (dev->limits.fmr_reserved_mtts) {
  707. i = fls(dev->limits.fmr_reserved_mtts - 1);
  708. if (i >= 31) {
  709. mthca_warn(dev, "Unable to reserve 2^31 FMR MTTs.\n");
  710. err = -EINVAL;
  711. goto err_fmr_mpt;
  712. }
  713. mpts = mtts = 1 << i;
  714. } else {
  715. mtts = dev->limits.num_mtt_segs;
  716. mpts = dev->limits.num_mpts;
  717. }
  718. if (!mthca_is_memfree(dev) &&
  719. (dev->mthca_flags & MTHCA_FLAG_FMR)) {
  720. addr = pci_resource_start(dev->pdev, 4) +
  721. ((pci_resource_len(dev->pdev, 4) - 1) &
  722. dev->mr_table.mpt_base);
  723. dev->mr_table.tavor_fmr.mpt_base =
  724. ioremap(addr, mpts * sizeof(struct mthca_mpt_entry));
  725. if (!dev->mr_table.tavor_fmr.mpt_base) {
  726. mthca_warn(dev, "MPT ioremap for FMR failed.\n");
  727. err = -ENOMEM;
  728. goto err_fmr_mpt;
  729. }
  730. addr = pci_resource_start(dev->pdev, 4) +
  731. ((pci_resource_len(dev->pdev, 4) - 1) &
  732. dev->mr_table.mtt_base);
  733. dev->mr_table.tavor_fmr.mtt_base =
  734. ioremap(addr, mtts * dev->limits.mtt_seg_size);
  735. if (!dev->mr_table.tavor_fmr.mtt_base) {
  736. mthca_warn(dev, "MTT ioremap for FMR failed.\n");
  737. err = -ENOMEM;
  738. goto err_fmr_mtt;
  739. }
  740. }
  741. if (dev->limits.fmr_reserved_mtts) {
  742. err = mthca_buddy_init(&dev->mr_table.tavor_fmr.mtt_buddy, fls(mtts - 1));
  743. if (err)
  744. goto err_fmr_mtt_buddy;
  745. /* Prevent regular MRs from using FMR keys */
  746. err = mthca_buddy_alloc(&dev->mr_table.mtt_buddy, fls(mtts - 1));
  747. if (err)
  748. goto err_reserve_fmr;
  749. dev->mr_table.fmr_mtt_buddy =
  750. &dev->mr_table.tavor_fmr.mtt_buddy;
  751. } else
  752. dev->mr_table.fmr_mtt_buddy = &dev->mr_table.mtt_buddy;
  753. /* FMR table is always the first, take reserved MTTs out of there */
  754. if (dev->limits.reserved_mtts) {
  755. i = fls(dev->limits.reserved_mtts - 1);
  756. if (mthca_alloc_mtt_range(dev, i,
  757. dev->mr_table.fmr_mtt_buddy) == -1) {
  758. mthca_warn(dev, "MTT table of order %d is too small.\n",
  759. dev->mr_table.fmr_mtt_buddy->max_order);
  760. err = -ENOMEM;
  761. goto err_reserve_mtts;
  762. }
  763. }
  764. return 0;
  765. err_reserve_mtts:
  766. err_reserve_fmr:
  767. if (dev->limits.fmr_reserved_mtts)
  768. mthca_buddy_cleanup(&dev->mr_table.tavor_fmr.mtt_buddy);
  769. err_fmr_mtt_buddy:
  770. if (dev->mr_table.tavor_fmr.mtt_base)
  771. iounmap(dev->mr_table.tavor_fmr.mtt_base);
  772. err_fmr_mtt:
  773. if (dev->mr_table.tavor_fmr.mpt_base)
  774. iounmap(dev->mr_table.tavor_fmr.mpt_base);
  775. err_fmr_mpt:
  776. mthca_buddy_cleanup(&dev->mr_table.mtt_buddy);
  777. err_mtt_buddy:
  778. mthca_alloc_cleanup(&dev->mr_table.mpt_alloc);
  779. return err;
  780. }
  781. void mthca_cleanup_mr_table(struct mthca_dev *dev)
  782. {
  783. /* XXX check if any MRs are still allocated? */
  784. if (dev->limits.fmr_reserved_mtts)
  785. mthca_buddy_cleanup(&dev->mr_table.tavor_fmr.mtt_buddy);
  786. mthca_buddy_cleanup(&dev->mr_table.mtt_buddy);
  787. if (dev->mr_table.tavor_fmr.mtt_base)
  788. iounmap(dev->mr_table.tavor_fmr.mtt_base);
  789. if (dev->mr_table.tavor_fmr.mpt_base)
  790. iounmap(dev->mr_table.tavor_fmr.mpt_base);
  791. mthca_alloc_cleanup(&dev->mr_table.mpt_alloc);
  792. }