mthca_main.c 36 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/module.h>
  35. #include <linux/init.h>
  36. #include <linux/errno.h>
  37. #include <linux/pci.h>
  38. #include <linux/interrupt.h>
  39. #include "mthca_dev.h"
  40. #include "mthca_config_reg.h"
  41. #include "mthca_cmd.h"
  42. #include "mthca_profile.h"
  43. #include "mthca_memfree.h"
  44. #include "mthca_wqe.h"
  45. MODULE_AUTHOR("Roland Dreier");
  46. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  47. MODULE_LICENSE("Dual BSD/GPL");
  48. MODULE_VERSION(DRV_VERSION);
  49. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  50. int mthca_debug_level = 0;
  51. module_param_named(debug_level, mthca_debug_level, int, 0644);
  52. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  53. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  54. #ifdef CONFIG_PCI_MSI
  55. static int msi_x = 1;
  56. module_param(msi_x, int, 0444);
  57. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #endif /* CONFIG_PCI_MSI */
  61. static int tune_pci = 0;
  62. module_param(tune_pci, int, 0444);
  63. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  64. DEFINE_MUTEX(mthca_device_mutex);
  65. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  66. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  67. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  68. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  69. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  70. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  71. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  72. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  73. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  74. static struct mthca_profile hca_profile = {
  75. .num_qp = MTHCA_DEFAULT_NUM_QP,
  76. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  77. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  78. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  79. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  80. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  81. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  82. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  83. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  84. };
  85. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  86. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  87. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  88. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  89. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  90. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  91. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  92. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  93. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  94. MODULE_PARM_DESC(num_mpt,
  95. "maximum number of memory protection table entries per HCA");
  96. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  97. MODULE_PARM_DESC(num_mtt,
  98. "maximum number of memory translation table segments per HCA");
  99. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  100. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  101. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  102. MODULE_PARM_DESC(fmr_reserved_mtts,
  103. "number of memory translation table segments reserved for FMR");
  104. static int log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
  105. module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
  106. MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)");
  107. static char mthca_version[] __devinitdata =
  108. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  109. DRV_VERSION " (" DRV_RELDATE ")\n";
  110. static int mthca_tune_pci(struct mthca_dev *mdev)
  111. {
  112. if (!tune_pci)
  113. return 0;
  114. /* First try to max out Read Byte Count */
  115. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
  116. if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
  117. mthca_err(mdev, "Couldn't set PCI-X max read count, "
  118. "aborting.\n");
  119. return -ENODEV;
  120. }
  121. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  122. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  123. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP)) {
  124. if (pcie_set_readrq(mdev->pdev, 4096)) {
  125. mthca_err(mdev, "Couldn't write PCI Express read request, "
  126. "aborting.\n");
  127. return -ENODEV;
  128. }
  129. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  130. mthca_info(mdev, "No PCI Express capability, "
  131. "not setting Max Read Request Size.\n");
  132. return 0;
  133. }
  134. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  135. {
  136. int err;
  137. u8 status;
  138. mdev->limits.mtt_seg_size = (1 << log_mtts_per_seg) * 8;
  139. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  140. if (err) {
  141. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  142. return err;
  143. }
  144. if (status) {
  145. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  146. "aborting.\n", status);
  147. return -EINVAL;
  148. }
  149. if (dev_lim->min_page_sz > PAGE_SIZE) {
  150. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  151. "kernel PAGE_SIZE of %ld, aborting.\n",
  152. dev_lim->min_page_sz, PAGE_SIZE);
  153. return -ENODEV;
  154. }
  155. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  156. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  157. "aborting.\n",
  158. dev_lim->num_ports, MTHCA_MAX_PORTS);
  159. return -ENODEV;
  160. }
  161. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  162. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  163. "PCI resource 2 size of 0x%llx, aborting.\n",
  164. dev_lim->uar_size,
  165. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  166. return -ENODEV;
  167. }
  168. mdev->limits.num_ports = dev_lim->num_ports;
  169. mdev->limits.vl_cap = dev_lim->max_vl;
  170. mdev->limits.mtu_cap = dev_lim->max_mtu;
  171. mdev->limits.gid_table_len = dev_lim->max_gids;
  172. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  173. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  174. /*
  175. * Need to allow for worst case send WQE overhead and check
  176. * whether max_desc_sz imposes a lower limit than max_sg; UD
  177. * send has the biggest overhead.
  178. */
  179. mdev->limits.max_sg = min_t(int, dev_lim->max_sg,
  180. (dev_lim->max_desc_sz -
  181. sizeof (struct mthca_next_seg) -
  182. (mthca_is_memfree(mdev) ?
  183. sizeof (struct mthca_arbel_ud_seg) :
  184. sizeof (struct mthca_tavor_ud_seg))) /
  185. sizeof (struct mthca_data_seg));
  186. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  187. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  188. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  189. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  190. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  191. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  192. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  193. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  194. /*
  195. * Subtract 1 from the limit because we need to allocate a
  196. * spare CQE so the HCA HW can tell the difference between an
  197. * empty CQ and a full CQ.
  198. */
  199. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  200. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  201. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  202. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  203. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  204. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  205. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  206. mdev->limits.port_width_cap = dev_lim->max_port_width;
  207. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  208. mdev->limits.flags = dev_lim->flags;
  209. /*
  210. * For old FW that doesn't return static rate support, use a
  211. * value of 0x3 (only static rate values of 0 or 1 are handled),
  212. * except on Sinai, where even old FW can handle static rate
  213. * values of 2 and 3.
  214. */
  215. if (dev_lim->stat_rate_support)
  216. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  217. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  218. mdev->limits.stat_rate_support = 0xf;
  219. else
  220. mdev->limits.stat_rate_support = 0x3;
  221. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  222. May be doable since hardware supports it for SRQ.
  223. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  224. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  225. supported by driver. */
  226. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  227. IB_DEVICE_PORT_ACTIVE_EVENT |
  228. IB_DEVICE_SYS_IMAGE_GUID |
  229. IB_DEVICE_RC_RNR_NAK_GEN;
  230. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  231. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  232. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  233. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  234. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  235. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  236. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  237. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  238. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  239. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  240. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  241. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  242. if (mthca_is_memfree(mdev))
  243. if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
  244. mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  245. return 0;
  246. }
  247. static int mthca_init_tavor(struct mthca_dev *mdev)
  248. {
  249. s64 size;
  250. u8 status;
  251. int err;
  252. struct mthca_dev_lim dev_lim;
  253. struct mthca_profile profile;
  254. struct mthca_init_hca_param init_hca;
  255. err = mthca_SYS_EN(mdev, &status);
  256. if (err) {
  257. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  258. return err;
  259. }
  260. if (status) {
  261. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  262. "aborting.\n", status);
  263. return -EINVAL;
  264. }
  265. err = mthca_QUERY_FW(mdev, &status);
  266. if (err) {
  267. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  268. goto err_disable;
  269. }
  270. if (status) {
  271. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  272. "aborting.\n", status);
  273. err = -EINVAL;
  274. goto err_disable;
  275. }
  276. err = mthca_QUERY_DDR(mdev, &status);
  277. if (err) {
  278. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  279. goto err_disable;
  280. }
  281. if (status) {
  282. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  283. "aborting.\n", status);
  284. err = -EINVAL;
  285. goto err_disable;
  286. }
  287. err = mthca_dev_lim(mdev, &dev_lim);
  288. if (err) {
  289. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  290. goto err_disable;
  291. }
  292. profile = hca_profile;
  293. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  294. profile.uarc_size = 0;
  295. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  296. profile.num_srq = dev_lim.max_srqs;
  297. size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  298. if (size < 0) {
  299. err = size;
  300. goto err_disable;
  301. }
  302. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  303. if (err) {
  304. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  305. goto err_disable;
  306. }
  307. if (status) {
  308. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  309. "aborting.\n", status);
  310. err = -EINVAL;
  311. goto err_disable;
  312. }
  313. return 0;
  314. err_disable:
  315. mthca_SYS_DIS(mdev, &status);
  316. return err;
  317. }
  318. static int mthca_load_fw(struct mthca_dev *mdev)
  319. {
  320. u8 status;
  321. int err;
  322. /* FIXME: use HCA-attached memory for FW if present */
  323. mdev->fw.arbel.fw_icm =
  324. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  325. GFP_HIGHUSER | __GFP_NOWARN, 0);
  326. if (!mdev->fw.arbel.fw_icm) {
  327. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  328. return -ENOMEM;
  329. }
  330. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  331. if (err) {
  332. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  333. goto err_free;
  334. }
  335. if (status) {
  336. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  337. err = -EINVAL;
  338. goto err_free;
  339. }
  340. err = mthca_RUN_FW(mdev, &status);
  341. if (err) {
  342. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  343. goto err_unmap_fa;
  344. }
  345. if (status) {
  346. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  347. err = -EINVAL;
  348. goto err_unmap_fa;
  349. }
  350. return 0;
  351. err_unmap_fa:
  352. mthca_UNMAP_FA(mdev, &status);
  353. err_free:
  354. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  355. return err;
  356. }
  357. static int mthca_init_icm(struct mthca_dev *mdev,
  358. struct mthca_dev_lim *dev_lim,
  359. struct mthca_init_hca_param *init_hca,
  360. u64 icm_size)
  361. {
  362. u64 aux_pages;
  363. u8 status;
  364. int err;
  365. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  366. if (err) {
  367. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  368. return err;
  369. }
  370. if (status) {
  371. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  372. "aborting.\n", status);
  373. return -EINVAL;
  374. }
  375. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  376. (unsigned long long) icm_size >> 10,
  377. (unsigned long long) aux_pages << 2);
  378. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  379. GFP_HIGHUSER | __GFP_NOWARN, 0);
  380. if (!mdev->fw.arbel.aux_icm) {
  381. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  382. return -ENOMEM;
  383. }
  384. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  385. if (err) {
  386. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  387. goto err_free_aux;
  388. }
  389. if (status) {
  390. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  391. err = -EINVAL;
  392. goto err_free_aux;
  393. }
  394. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  395. if (err) {
  396. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  397. goto err_unmap_aux;
  398. }
  399. /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
  400. mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * mdev->limits.mtt_seg_size,
  401. dma_get_cache_alignment()) / mdev->limits.mtt_seg_size;
  402. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  403. mdev->limits.mtt_seg_size,
  404. mdev->limits.num_mtt_segs,
  405. mdev->limits.reserved_mtts,
  406. 1, 0);
  407. if (!mdev->mr_table.mtt_table) {
  408. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  409. err = -ENOMEM;
  410. goto err_unmap_eq;
  411. }
  412. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  413. dev_lim->mpt_entry_sz,
  414. mdev->limits.num_mpts,
  415. mdev->limits.reserved_mrws,
  416. 1, 1);
  417. if (!mdev->mr_table.mpt_table) {
  418. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  419. err = -ENOMEM;
  420. goto err_unmap_mtt;
  421. }
  422. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  423. dev_lim->qpc_entry_sz,
  424. mdev->limits.num_qps,
  425. mdev->limits.reserved_qps,
  426. 0, 0);
  427. if (!mdev->qp_table.qp_table) {
  428. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  429. err = -ENOMEM;
  430. goto err_unmap_mpt;
  431. }
  432. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  433. dev_lim->eqpc_entry_sz,
  434. mdev->limits.num_qps,
  435. mdev->limits.reserved_qps,
  436. 0, 0);
  437. if (!mdev->qp_table.eqp_table) {
  438. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  439. err = -ENOMEM;
  440. goto err_unmap_qp;
  441. }
  442. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  443. MTHCA_RDB_ENTRY_SIZE,
  444. mdev->limits.num_qps <<
  445. mdev->qp_table.rdb_shift, 0,
  446. 0, 0);
  447. if (!mdev->qp_table.rdb_table) {
  448. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  449. err = -ENOMEM;
  450. goto err_unmap_eqp;
  451. }
  452. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  453. dev_lim->cqc_entry_sz,
  454. mdev->limits.num_cqs,
  455. mdev->limits.reserved_cqs,
  456. 0, 0);
  457. if (!mdev->cq_table.table) {
  458. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  459. err = -ENOMEM;
  460. goto err_unmap_rdb;
  461. }
  462. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  463. mdev->srq_table.table =
  464. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  465. dev_lim->srq_entry_sz,
  466. mdev->limits.num_srqs,
  467. mdev->limits.reserved_srqs,
  468. 0, 0);
  469. if (!mdev->srq_table.table) {
  470. mthca_err(mdev, "Failed to map SRQ context memory, "
  471. "aborting.\n");
  472. err = -ENOMEM;
  473. goto err_unmap_cq;
  474. }
  475. }
  476. /*
  477. * It's not strictly required, but for simplicity just map the
  478. * whole multicast group table now. The table isn't very big
  479. * and it's a lot easier than trying to track ref counts.
  480. */
  481. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  482. MTHCA_MGM_ENTRY_SIZE,
  483. mdev->limits.num_mgms +
  484. mdev->limits.num_amgms,
  485. mdev->limits.num_mgms +
  486. mdev->limits.num_amgms,
  487. 0, 0);
  488. if (!mdev->mcg_table.table) {
  489. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  490. err = -ENOMEM;
  491. goto err_unmap_srq;
  492. }
  493. return 0;
  494. err_unmap_srq:
  495. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  496. mthca_free_icm_table(mdev, mdev->srq_table.table);
  497. err_unmap_cq:
  498. mthca_free_icm_table(mdev, mdev->cq_table.table);
  499. err_unmap_rdb:
  500. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  501. err_unmap_eqp:
  502. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  503. err_unmap_qp:
  504. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  505. err_unmap_mpt:
  506. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  507. err_unmap_mtt:
  508. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  509. err_unmap_eq:
  510. mthca_unmap_eq_icm(mdev);
  511. err_unmap_aux:
  512. mthca_UNMAP_ICM_AUX(mdev, &status);
  513. err_free_aux:
  514. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  515. return err;
  516. }
  517. static void mthca_free_icms(struct mthca_dev *mdev)
  518. {
  519. u8 status;
  520. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  521. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  522. mthca_free_icm_table(mdev, mdev->srq_table.table);
  523. mthca_free_icm_table(mdev, mdev->cq_table.table);
  524. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  525. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  526. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  527. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  528. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  529. mthca_unmap_eq_icm(mdev);
  530. mthca_UNMAP_ICM_AUX(mdev, &status);
  531. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  532. }
  533. static int mthca_init_arbel(struct mthca_dev *mdev)
  534. {
  535. struct mthca_dev_lim dev_lim;
  536. struct mthca_profile profile;
  537. struct mthca_init_hca_param init_hca;
  538. s64 icm_size;
  539. u8 status;
  540. int err;
  541. err = mthca_QUERY_FW(mdev, &status);
  542. if (err) {
  543. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  544. return err;
  545. }
  546. if (status) {
  547. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  548. "aborting.\n", status);
  549. return -EINVAL;
  550. }
  551. err = mthca_ENABLE_LAM(mdev, &status);
  552. if (err) {
  553. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  554. return err;
  555. }
  556. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  557. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  558. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  559. } else if (status) {
  560. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  561. "aborting.\n", status);
  562. return -EINVAL;
  563. }
  564. err = mthca_load_fw(mdev);
  565. if (err) {
  566. mthca_err(mdev, "Failed to start FW, aborting.\n");
  567. goto err_disable;
  568. }
  569. err = mthca_dev_lim(mdev, &dev_lim);
  570. if (err) {
  571. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  572. goto err_stop_fw;
  573. }
  574. profile = hca_profile;
  575. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  576. profile.num_udav = 0;
  577. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  578. profile.num_srq = dev_lim.max_srqs;
  579. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  580. if (icm_size < 0) {
  581. err = icm_size;
  582. goto err_stop_fw;
  583. }
  584. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  585. if (err)
  586. goto err_stop_fw;
  587. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  588. if (err) {
  589. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  590. goto err_free_icm;
  591. }
  592. if (status) {
  593. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  594. "aborting.\n", status);
  595. err = -EINVAL;
  596. goto err_free_icm;
  597. }
  598. return 0;
  599. err_free_icm:
  600. mthca_free_icms(mdev);
  601. err_stop_fw:
  602. mthca_UNMAP_FA(mdev, &status);
  603. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  604. err_disable:
  605. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  606. mthca_DISABLE_LAM(mdev, &status);
  607. return err;
  608. }
  609. static void mthca_close_hca(struct mthca_dev *mdev)
  610. {
  611. u8 status;
  612. mthca_CLOSE_HCA(mdev, 0, &status);
  613. if (mthca_is_memfree(mdev)) {
  614. mthca_free_icms(mdev);
  615. mthca_UNMAP_FA(mdev, &status);
  616. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  617. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  618. mthca_DISABLE_LAM(mdev, &status);
  619. } else
  620. mthca_SYS_DIS(mdev, &status);
  621. }
  622. static int mthca_init_hca(struct mthca_dev *mdev)
  623. {
  624. u8 status;
  625. int err;
  626. struct mthca_adapter adapter;
  627. if (mthca_is_memfree(mdev))
  628. err = mthca_init_arbel(mdev);
  629. else
  630. err = mthca_init_tavor(mdev);
  631. if (err)
  632. return err;
  633. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  634. if (err) {
  635. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  636. goto err_close;
  637. }
  638. if (status) {
  639. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  640. "aborting.\n", status);
  641. err = -EINVAL;
  642. goto err_close;
  643. }
  644. mdev->eq_table.inta_pin = adapter.inta_pin;
  645. if (!mthca_is_memfree(mdev))
  646. mdev->rev_id = adapter.revision_id;
  647. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  648. return 0;
  649. err_close:
  650. mthca_close_hca(mdev);
  651. return err;
  652. }
  653. static int mthca_setup_hca(struct mthca_dev *dev)
  654. {
  655. int err;
  656. u8 status;
  657. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  658. err = mthca_init_uar_table(dev);
  659. if (err) {
  660. mthca_err(dev, "Failed to initialize "
  661. "user access region table, aborting.\n");
  662. return err;
  663. }
  664. err = mthca_uar_alloc(dev, &dev->driver_uar);
  665. if (err) {
  666. mthca_err(dev, "Failed to allocate driver access region, "
  667. "aborting.\n");
  668. goto err_uar_table_free;
  669. }
  670. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  671. if (!dev->kar) {
  672. mthca_err(dev, "Couldn't map kernel access region, "
  673. "aborting.\n");
  674. err = -ENOMEM;
  675. goto err_uar_free;
  676. }
  677. err = mthca_init_pd_table(dev);
  678. if (err) {
  679. mthca_err(dev, "Failed to initialize "
  680. "protection domain table, aborting.\n");
  681. goto err_kar_unmap;
  682. }
  683. err = mthca_init_mr_table(dev);
  684. if (err) {
  685. mthca_err(dev, "Failed to initialize "
  686. "memory region table, aborting.\n");
  687. goto err_pd_table_free;
  688. }
  689. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  690. if (err) {
  691. mthca_err(dev, "Failed to create driver PD, "
  692. "aborting.\n");
  693. goto err_mr_table_free;
  694. }
  695. err = mthca_init_eq_table(dev);
  696. if (err) {
  697. mthca_err(dev, "Failed to initialize "
  698. "event queue table, aborting.\n");
  699. goto err_pd_free;
  700. }
  701. err = mthca_cmd_use_events(dev);
  702. if (err) {
  703. mthca_err(dev, "Failed to switch to event-driven "
  704. "firmware commands, aborting.\n");
  705. goto err_eq_table_free;
  706. }
  707. err = mthca_NOP(dev, &status);
  708. if (err || status) {
  709. if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
  710. mthca_warn(dev, "NOP command failed to generate interrupt "
  711. "(IRQ %d).\n",
  712. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
  713. mthca_warn(dev, "Trying again with MSI-X disabled.\n");
  714. } else {
  715. mthca_err(dev, "NOP command failed to generate interrupt "
  716. "(IRQ %d), aborting.\n",
  717. dev->pdev->irq);
  718. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  719. }
  720. goto err_cmd_poll;
  721. }
  722. mthca_dbg(dev, "NOP command IRQ test passed\n");
  723. err = mthca_init_cq_table(dev);
  724. if (err) {
  725. mthca_err(dev, "Failed to initialize "
  726. "completion queue table, aborting.\n");
  727. goto err_cmd_poll;
  728. }
  729. err = mthca_init_srq_table(dev);
  730. if (err) {
  731. mthca_err(dev, "Failed to initialize "
  732. "shared receive queue table, aborting.\n");
  733. goto err_cq_table_free;
  734. }
  735. err = mthca_init_qp_table(dev);
  736. if (err) {
  737. mthca_err(dev, "Failed to initialize "
  738. "queue pair table, aborting.\n");
  739. goto err_srq_table_free;
  740. }
  741. err = mthca_init_av_table(dev);
  742. if (err) {
  743. mthca_err(dev, "Failed to initialize "
  744. "address vector table, aborting.\n");
  745. goto err_qp_table_free;
  746. }
  747. err = mthca_init_mcg_table(dev);
  748. if (err) {
  749. mthca_err(dev, "Failed to initialize "
  750. "multicast group table, aborting.\n");
  751. goto err_av_table_free;
  752. }
  753. return 0;
  754. err_av_table_free:
  755. mthca_cleanup_av_table(dev);
  756. err_qp_table_free:
  757. mthca_cleanup_qp_table(dev);
  758. err_srq_table_free:
  759. mthca_cleanup_srq_table(dev);
  760. err_cq_table_free:
  761. mthca_cleanup_cq_table(dev);
  762. err_cmd_poll:
  763. mthca_cmd_use_polling(dev);
  764. err_eq_table_free:
  765. mthca_cleanup_eq_table(dev);
  766. err_pd_free:
  767. mthca_pd_free(dev, &dev->driver_pd);
  768. err_mr_table_free:
  769. mthca_cleanup_mr_table(dev);
  770. err_pd_table_free:
  771. mthca_cleanup_pd_table(dev);
  772. err_kar_unmap:
  773. iounmap(dev->kar);
  774. err_uar_free:
  775. mthca_uar_free(dev, &dev->driver_uar);
  776. err_uar_table_free:
  777. mthca_cleanup_uar_table(dev);
  778. return err;
  779. }
  780. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  781. {
  782. struct msix_entry entries[3];
  783. int err;
  784. entries[0].entry = 0;
  785. entries[1].entry = 1;
  786. entries[2].entry = 2;
  787. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  788. if (err) {
  789. if (err > 0)
  790. mthca_info(mdev, "Only %d MSI-X vectors available, "
  791. "not using MSI-X\n", err);
  792. return err;
  793. }
  794. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  795. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  796. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  797. return 0;
  798. }
  799. /* Types of supported HCA */
  800. enum {
  801. TAVOR, /* MT23108 */
  802. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  803. ARBEL_NATIVE, /* MT25208 with extended features */
  804. SINAI /* MT25204 */
  805. };
  806. #define MTHCA_FW_VER(major, minor, subminor) \
  807. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  808. static struct {
  809. u64 latest_fw;
  810. u32 flags;
  811. } mthca_hca_table[] = {
  812. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
  813. .flags = 0 },
  814. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
  815. .flags = MTHCA_FLAG_PCIE },
  816. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
  817. .flags = MTHCA_FLAG_MEMFREE |
  818. MTHCA_FLAG_PCIE },
  819. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
  820. .flags = MTHCA_FLAG_MEMFREE |
  821. MTHCA_FLAG_PCIE |
  822. MTHCA_FLAG_SINAI_OPT }
  823. };
  824. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  825. {
  826. int ddr_hidden = 0;
  827. int err;
  828. struct mthca_dev *mdev;
  829. printk(KERN_INFO PFX "Initializing %s\n",
  830. pci_name(pdev));
  831. err = pci_enable_device(pdev);
  832. if (err) {
  833. dev_err(&pdev->dev, "Cannot enable PCI device, "
  834. "aborting.\n");
  835. return err;
  836. }
  837. /*
  838. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  839. * be present)
  840. */
  841. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  842. pci_resource_len(pdev, 0) != 1 << 20) {
  843. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  844. err = -ENODEV;
  845. goto err_disable_pdev;
  846. }
  847. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  848. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  849. err = -ENODEV;
  850. goto err_disable_pdev;
  851. }
  852. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  853. ddr_hidden = 1;
  854. err = pci_request_regions(pdev, DRV_NAME);
  855. if (err) {
  856. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  857. "aborting.\n");
  858. goto err_disable_pdev;
  859. }
  860. pci_set_master(pdev);
  861. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  862. if (err) {
  863. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  864. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  865. if (err) {
  866. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  867. goto err_free_res;
  868. }
  869. }
  870. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  871. if (err) {
  872. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  873. "consistent PCI DMA mask.\n");
  874. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  875. if (err) {
  876. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  877. "aborting.\n");
  878. goto err_free_res;
  879. }
  880. }
  881. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  882. if (!mdev) {
  883. dev_err(&pdev->dev, "Device struct alloc failed, "
  884. "aborting.\n");
  885. err = -ENOMEM;
  886. goto err_free_res;
  887. }
  888. mdev->pdev = pdev;
  889. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  890. if (ddr_hidden)
  891. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  892. /*
  893. * Now reset the HCA before we touch the PCI capabilities or
  894. * attempt a firmware command, since a boot ROM may have left
  895. * the HCA in an undefined state.
  896. */
  897. err = mthca_reset(mdev);
  898. if (err) {
  899. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  900. goto err_free_dev;
  901. }
  902. if (mthca_cmd_init(mdev)) {
  903. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  904. goto err_free_dev;
  905. }
  906. err = mthca_tune_pci(mdev);
  907. if (err)
  908. goto err_cmd;
  909. err = mthca_init_hca(mdev);
  910. if (err)
  911. goto err_cmd;
  912. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  913. mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
  914. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  915. (int) (mdev->fw_ver & 0xffff),
  916. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  917. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  918. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  919. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  920. }
  921. if (msi_x && !mthca_enable_msi_x(mdev))
  922. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  923. err = mthca_setup_hca(mdev);
  924. if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
  925. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  926. pci_disable_msix(pdev);
  927. mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
  928. err = mthca_setup_hca(mdev);
  929. }
  930. if (err)
  931. goto err_close;
  932. err = mthca_register_device(mdev);
  933. if (err)
  934. goto err_cleanup;
  935. err = mthca_create_agents(mdev);
  936. if (err)
  937. goto err_unregister;
  938. pci_set_drvdata(pdev, mdev);
  939. mdev->hca_type = hca_type;
  940. return 0;
  941. err_unregister:
  942. mthca_unregister_device(mdev);
  943. err_cleanup:
  944. mthca_cleanup_mcg_table(mdev);
  945. mthca_cleanup_av_table(mdev);
  946. mthca_cleanup_qp_table(mdev);
  947. mthca_cleanup_srq_table(mdev);
  948. mthca_cleanup_cq_table(mdev);
  949. mthca_cmd_use_polling(mdev);
  950. mthca_cleanup_eq_table(mdev);
  951. mthca_pd_free(mdev, &mdev->driver_pd);
  952. mthca_cleanup_mr_table(mdev);
  953. mthca_cleanup_pd_table(mdev);
  954. mthca_cleanup_uar_table(mdev);
  955. err_close:
  956. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  957. pci_disable_msix(pdev);
  958. mthca_close_hca(mdev);
  959. err_cmd:
  960. mthca_cmd_cleanup(mdev);
  961. err_free_dev:
  962. ib_dealloc_device(&mdev->ib_dev);
  963. err_free_res:
  964. pci_release_regions(pdev);
  965. err_disable_pdev:
  966. pci_disable_device(pdev);
  967. pci_set_drvdata(pdev, NULL);
  968. return err;
  969. }
  970. static void __mthca_remove_one(struct pci_dev *pdev)
  971. {
  972. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  973. u8 status;
  974. int p;
  975. if (mdev) {
  976. mthca_free_agents(mdev);
  977. mthca_unregister_device(mdev);
  978. for (p = 1; p <= mdev->limits.num_ports; ++p)
  979. mthca_CLOSE_IB(mdev, p, &status);
  980. mthca_cleanup_mcg_table(mdev);
  981. mthca_cleanup_av_table(mdev);
  982. mthca_cleanup_qp_table(mdev);
  983. mthca_cleanup_srq_table(mdev);
  984. mthca_cleanup_cq_table(mdev);
  985. mthca_cmd_use_polling(mdev);
  986. mthca_cleanup_eq_table(mdev);
  987. mthca_pd_free(mdev, &mdev->driver_pd);
  988. mthca_cleanup_mr_table(mdev);
  989. mthca_cleanup_pd_table(mdev);
  990. iounmap(mdev->kar);
  991. mthca_uar_free(mdev, &mdev->driver_uar);
  992. mthca_cleanup_uar_table(mdev);
  993. mthca_close_hca(mdev);
  994. mthca_cmd_cleanup(mdev);
  995. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  996. pci_disable_msix(pdev);
  997. ib_dealloc_device(&mdev->ib_dev);
  998. pci_release_regions(pdev);
  999. pci_disable_device(pdev);
  1000. pci_set_drvdata(pdev, NULL);
  1001. }
  1002. }
  1003. int __mthca_restart_one(struct pci_dev *pdev)
  1004. {
  1005. struct mthca_dev *mdev;
  1006. int hca_type;
  1007. mdev = pci_get_drvdata(pdev);
  1008. if (!mdev)
  1009. return -ENODEV;
  1010. hca_type = mdev->hca_type;
  1011. __mthca_remove_one(pdev);
  1012. return __mthca_init_one(pdev, hca_type);
  1013. }
  1014. static int __devinit mthca_init_one(struct pci_dev *pdev,
  1015. const struct pci_device_id *id)
  1016. {
  1017. static int mthca_version_printed = 0;
  1018. int ret;
  1019. mutex_lock(&mthca_device_mutex);
  1020. if (!mthca_version_printed) {
  1021. printk(KERN_INFO "%s", mthca_version);
  1022. ++mthca_version_printed;
  1023. }
  1024. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  1025. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  1026. pci_name(pdev), id->driver_data);
  1027. mutex_unlock(&mthca_device_mutex);
  1028. return -ENODEV;
  1029. }
  1030. ret = __mthca_init_one(pdev, id->driver_data);
  1031. mutex_unlock(&mthca_device_mutex);
  1032. return ret;
  1033. }
  1034. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  1035. {
  1036. mutex_lock(&mthca_device_mutex);
  1037. __mthca_remove_one(pdev);
  1038. mutex_unlock(&mthca_device_mutex);
  1039. }
  1040. static struct pci_device_id mthca_pci_table[] = {
  1041. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1042. .driver_data = TAVOR },
  1043. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1044. .driver_data = TAVOR },
  1045. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1046. .driver_data = ARBEL_COMPAT },
  1047. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1048. .driver_data = ARBEL_COMPAT },
  1049. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1050. .driver_data = ARBEL_NATIVE },
  1051. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1052. .driver_data = ARBEL_NATIVE },
  1053. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1054. .driver_data = SINAI },
  1055. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1056. .driver_data = SINAI },
  1057. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1058. .driver_data = SINAI },
  1059. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1060. .driver_data = SINAI },
  1061. { 0, }
  1062. };
  1063. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1064. static struct pci_driver mthca_driver = {
  1065. .name = DRV_NAME,
  1066. .id_table = mthca_pci_table,
  1067. .probe = mthca_init_one,
  1068. .remove = __devexit_p(mthca_remove_one)
  1069. };
  1070. static void __init __mthca_check_profile_val(const char *name, int *pval,
  1071. int pval_default)
  1072. {
  1073. /* value must be positive and power of 2 */
  1074. int old_pval = *pval;
  1075. if (old_pval <= 0)
  1076. *pval = pval_default;
  1077. else
  1078. *pval = roundup_pow_of_two(old_pval);
  1079. if (old_pval != *pval) {
  1080. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  1081. old_pval, name);
  1082. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  1083. }
  1084. }
  1085. #define mthca_check_profile_val(name, default) \
  1086. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1087. static void __init mthca_validate_profile(void)
  1088. {
  1089. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1090. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1091. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1092. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1093. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1094. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1095. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1096. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1097. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1098. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1099. hca_profile.fmr_reserved_mtts);
  1100. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1101. hca_profile.num_mtt);
  1102. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1103. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1104. hca_profile.fmr_reserved_mtts);
  1105. }
  1106. if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) {
  1107. printk(KERN_WARNING PFX "bad log_mtts_per_seg (%d). Using default - %d\n",
  1108. log_mtts_per_seg, ilog2(MTHCA_MTT_SEG_SIZE / 8));
  1109. log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
  1110. }
  1111. }
  1112. static int __init mthca_init(void)
  1113. {
  1114. int ret;
  1115. mthca_validate_profile();
  1116. ret = mthca_catas_init();
  1117. if (ret)
  1118. return ret;
  1119. ret = pci_register_driver(&mthca_driver);
  1120. if (ret < 0) {
  1121. mthca_catas_cleanup();
  1122. return ret;
  1123. }
  1124. return 0;
  1125. }
  1126. static void __exit mthca_cleanup(void)
  1127. {
  1128. pci_unregister_driver(&mthca_driver);
  1129. mthca_catas_cleanup();
  1130. }
  1131. module_init(mthca_init);
  1132. module_exit(mthca_cleanup);