radeon_object.c 12 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <linux/list.h>
  33. #include <drm/drmP.h>
  34. #include "radeon_drm.h"
  35. #include "radeon.h"
  36. struct radeon_object {
  37. struct ttm_buffer_object tobj;
  38. struct list_head list;
  39. struct radeon_device *rdev;
  40. struct drm_gem_object *gobj;
  41. struct ttm_bo_kmap_obj kmap;
  42. unsigned pin_count;
  43. uint64_t gpu_addr;
  44. void *kptr;
  45. bool is_iomem;
  46. };
  47. int radeon_ttm_init(struct radeon_device *rdev);
  48. void radeon_ttm_fini(struct radeon_device *rdev);
  49. /*
  50. * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  51. * function are calling it.
  52. */
  53. static int radeon_object_reserve(struct radeon_object *robj, bool interruptible)
  54. {
  55. return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0);
  56. }
  57. static void radeon_object_unreserve(struct radeon_object *robj)
  58. {
  59. ttm_bo_unreserve(&robj->tobj);
  60. }
  61. static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj)
  62. {
  63. struct radeon_object *robj;
  64. robj = container_of(tobj, struct radeon_object, tobj);
  65. list_del_init(&robj->list);
  66. kfree(robj);
  67. }
  68. static inline void radeon_object_gpu_addr(struct radeon_object *robj)
  69. {
  70. /* Default gpu address */
  71. robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
  72. if (robj->tobj.mem.mm_node == NULL) {
  73. return;
  74. }
  75. robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT;
  76. switch (robj->tobj.mem.mem_type) {
  77. case TTM_PL_VRAM:
  78. robj->gpu_addr += (u64)robj->rdev->mc.vram_location;
  79. break;
  80. case TTM_PL_TT:
  81. robj->gpu_addr += (u64)robj->rdev->mc.gtt_location;
  82. break;
  83. default:
  84. DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type);
  85. robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
  86. return;
  87. }
  88. }
  89. static inline uint32_t radeon_object_flags_from_domain(uint32_t domain)
  90. {
  91. uint32_t flags = 0;
  92. if (domain & RADEON_GEM_DOMAIN_VRAM) {
  93. flags |= TTM_PL_FLAG_VRAM;
  94. }
  95. if (domain & RADEON_GEM_DOMAIN_GTT) {
  96. flags |= TTM_PL_FLAG_TT;
  97. }
  98. if (domain & RADEON_GEM_DOMAIN_CPU) {
  99. flags |= TTM_PL_FLAG_SYSTEM;
  100. }
  101. if (!flags) {
  102. flags |= TTM_PL_FLAG_SYSTEM;
  103. }
  104. return flags;
  105. }
  106. int radeon_object_create(struct radeon_device *rdev,
  107. struct drm_gem_object *gobj,
  108. unsigned long size,
  109. bool kernel,
  110. uint32_t domain,
  111. bool interruptible,
  112. struct radeon_object **robj_ptr)
  113. {
  114. struct radeon_object *robj;
  115. enum ttm_bo_type type;
  116. uint32_t flags;
  117. int r;
  118. if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  119. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  120. }
  121. if (kernel) {
  122. type = ttm_bo_type_kernel;
  123. } else {
  124. type = ttm_bo_type_device;
  125. }
  126. *robj_ptr = NULL;
  127. robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL);
  128. if (robj == NULL) {
  129. return -ENOMEM;
  130. }
  131. robj->rdev = rdev;
  132. robj->gobj = gobj;
  133. INIT_LIST_HEAD(&robj->list);
  134. flags = radeon_object_flags_from_domain(domain);
  135. r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags,
  136. 0, 0, false, NULL, size,
  137. &radeon_ttm_object_object_destroy);
  138. if (unlikely(r != 0)) {
  139. /* ttm call radeon_ttm_object_object_destroy if error happen */
  140. DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n",
  141. size, flags, 0);
  142. return r;
  143. }
  144. *robj_ptr = robj;
  145. if (gobj) {
  146. list_add_tail(&robj->list, &rdev->gem.objects);
  147. }
  148. return 0;
  149. }
  150. int radeon_object_kmap(struct radeon_object *robj, void **ptr)
  151. {
  152. int r;
  153. spin_lock(&robj->tobj.lock);
  154. if (robj->kptr) {
  155. if (ptr) {
  156. *ptr = robj->kptr;
  157. }
  158. spin_unlock(&robj->tobj.lock);
  159. return 0;
  160. }
  161. spin_unlock(&robj->tobj.lock);
  162. r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap);
  163. if (r) {
  164. return r;
  165. }
  166. spin_lock(&robj->tobj.lock);
  167. robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem);
  168. spin_unlock(&robj->tobj.lock);
  169. if (ptr) {
  170. *ptr = robj->kptr;
  171. }
  172. return 0;
  173. }
  174. void radeon_object_kunmap(struct radeon_object *robj)
  175. {
  176. spin_lock(&robj->tobj.lock);
  177. if (robj->kptr == NULL) {
  178. spin_unlock(&robj->tobj.lock);
  179. return;
  180. }
  181. robj->kptr = NULL;
  182. spin_unlock(&robj->tobj.lock);
  183. ttm_bo_kunmap(&robj->kmap);
  184. }
  185. void radeon_object_unref(struct radeon_object **robj)
  186. {
  187. struct ttm_buffer_object *tobj;
  188. if ((*robj) == NULL) {
  189. return;
  190. }
  191. tobj = &((*robj)->tobj);
  192. ttm_bo_unref(&tobj);
  193. if (tobj == NULL) {
  194. *robj = NULL;
  195. }
  196. }
  197. int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset)
  198. {
  199. *offset = robj->tobj.addr_space_offset;
  200. return 0;
  201. }
  202. int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
  203. uint64_t *gpu_addr)
  204. {
  205. uint32_t flags;
  206. uint32_t tmp;
  207. int r;
  208. flags = radeon_object_flags_from_domain(domain);
  209. spin_lock(&robj->tobj.lock);
  210. if (robj->pin_count) {
  211. robj->pin_count++;
  212. if (gpu_addr != NULL) {
  213. *gpu_addr = robj->gpu_addr;
  214. }
  215. spin_unlock(&robj->tobj.lock);
  216. return 0;
  217. }
  218. spin_unlock(&robj->tobj.lock);
  219. r = radeon_object_reserve(robj, false);
  220. if (unlikely(r != 0)) {
  221. DRM_ERROR("radeon: failed to reserve object for pinning it.\n");
  222. return r;
  223. }
  224. tmp = robj->tobj.mem.placement;
  225. ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
  226. robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING;
  227. r = ttm_buffer_object_validate(&robj->tobj,
  228. robj->tobj.proposed_placement,
  229. false, false);
  230. radeon_object_gpu_addr(robj);
  231. if (gpu_addr != NULL) {
  232. *gpu_addr = robj->gpu_addr;
  233. }
  234. robj->pin_count = 1;
  235. if (unlikely(r != 0)) {
  236. DRM_ERROR("radeon: failed to pin object.\n");
  237. }
  238. radeon_object_unreserve(robj);
  239. return r;
  240. }
  241. void radeon_object_unpin(struct radeon_object *robj)
  242. {
  243. uint32_t flags;
  244. int r;
  245. spin_lock(&robj->tobj.lock);
  246. if (!robj->pin_count) {
  247. spin_unlock(&robj->tobj.lock);
  248. printk(KERN_WARNING "Unpin not necessary for %p !\n", robj);
  249. return;
  250. }
  251. robj->pin_count--;
  252. if (robj->pin_count) {
  253. spin_unlock(&robj->tobj.lock);
  254. return;
  255. }
  256. spin_unlock(&robj->tobj.lock);
  257. r = radeon_object_reserve(robj, false);
  258. if (unlikely(r != 0)) {
  259. DRM_ERROR("radeon: failed to reserve object for unpinning it.\n");
  260. return;
  261. }
  262. flags = robj->tobj.mem.placement;
  263. robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT;
  264. r = ttm_buffer_object_validate(&robj->tobj,
  265. robj->tobj.proposed_placement,
  266. false, false);
  267. if (unlikely(r != 0)) {
  268. DRM_ERROR("radeon: failed to unpin buffer.\n");
  269. }
  270. radeon_object_unreserve(robj);
  271. }
  272. int radeon_object_wait(struct radeon_object *robj)
  273. {
  274. int r = 0;
  275. /* FIXME: should use block reservation instead */
  276. r = radeon_object_reserve(robj, true);
  277. if (unlikely(r != 0)) {
  278. DRM_ERROR("radeon: failed to reserve object for waiting.\n");
  279. return r;
  280. }
  281. spin_lock(&robj->tobj.lock);
  282. if (robj->tobj.sync_obj) {
  283. r = ttm_bo_wait(&robj->tobj, true, false, false);
  284. }
  285. spin_unlock(&robj->tobj.lock);
  286. radeon_object_unreserve(robj);
  287. return r;
  288. }
  289. int radeon_object_evict_vram(struct radeon_device *rdev)
  290. {
  291. if (rdev->flags & RADEON_IS_IGP) {
  292. /* Useless to evict on IGP chips */
  293. return 0;
  294. }
  295. return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  296. }
  297. void radeon_object_force_delete(struct radeon_device *rdev)
  298. {
  299. struct radeon_object *robj, *n;
  300. struct drm_gem_object *gobj;
  301. if (list_empty(&rdev->gem.objects)) {
  302. return;
  303. }
  304. DRM_ERROR("Userspace still has active objects !\n");
  305. list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) {
  306. mutex_lock(&rdev->ddev->struct_mutex);
  307. gobj = robj->gobj;
  308. DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n",
  309. gobj, robj, (unsigned long)gobj->size,
  310. *((unsigned long *)&gobj->refcount));
  311. list_del_init(&robj->list);
  312. radeon_object_unref(&robj);
  313. gobj->driver_private = NULL;
  314. drm_gem_object_unreference(gobj);
  315. mutex_unlock(&rdev->ddev->struct_mutex);
  316. }
  317. }
  318. int radeon_object_init(struct radeon_device *rdev)
  319. {
  320. return radeon_ttm_init(rdev);
  321. }
  322. void radeon_object_fini(struct radeon_device *rdev)
  323. {
  324. radeon_ttm_fini(rdev);
  325. }
  326. void radeon_object_list_add_object(struct radeon_object_list *lobj,
  327. struct list_head *head)
  328. {
  329. if (lobj->wdomain) {
  330. list_add(&lobj->list, head);
  331. } else {
  332. list_add_tail(&lobj->list, head);
  333. }
  334. }
  335. int radeon_object_list_reserve(struct list_head *head)
  336. {
  337. struct radeon_object_list *lobj;
  338. struct list_head *i;
  339. int r;
  340. list_for_each(i, head) {
  341. lobj = list_entry(i, struct radeon_object_list, list);
  342. if (!lobj->robj->pin_count) {
  343. r = radeon_object_reserve(lobj->robj, true);
  344. if (unlikely(r != 0)) {
  345. DRM_ERROR("radeon: failed to reserve object.\n");
  346. return r;
  347. }
  348. } else {
  349. }
  350. }
  351. return 0;
  352. }
  353. void radeon_object_list_unreserve(struct list_head *head)
  354. {
  355. struct radeon_object_list *lobj;
  356. struct list_head *i;
  357. list_for_each(i, head) {
  358. lobj = list_entry(i, struct radeon_object_list, list);
  359. if (!lobj->robj->pin_count) {
  360. radeon_object_unreserve(lobj->robj);
  361. } else {
  362. }
  363. }
  364. }
  365. int radeon_object_list_validate(struct list_head *head, void *fence)
  366. {
  367. struct radeon_object_list *lobj;
  368. struct radeon_object *robj;
  369. struct radeon_fence *old_fence = NULL;
  370. struct list_head *i;
  371. uint32_t flags;
  372. int r;
  373. r = radeon_object_list_reserve(head);
  374. if (unlikely(r != 0)) {
  375. radeon_object_list_unreserve(head);
  376. return r;
  377. }
  378. list_for_each(i, head) {
  379. lobj = list_entry(i, struct radeon_object_list, list);
  380. robj = lobj->robj;
  381. if (lobj->wdomain) {
  382. flags = radeon_object_flags_from_domain(lobj->wdomain);
  383. flags |= TTM_PL_FLAG_TT;
  384. } else {
  385. flags = radeon_object_flags_from_domain(lobj->rdomain);
  386. flags |= TTM_PL_FLAG_TT;
  387. flags |= TTM_PL_FLAG_VRAM;
  388. }
  389. if (!robj->pin_count) {
  390. robj->tobj.proposed_placement = flags | TTM_PL_MASK_CACHING;
  391. r = ttm_buffer_object_validate(&robj->tobj,
  392. robj->tobj.proposed_placement,
  393. true, false);
  394. if (unlikely(r)) {
  395. radeon_object_list_unreserve(head);
  396. DRM_ERROR("radeon: failed to validate.\n");
  397. return r;
  398. }
  399. radeon_object_gpu_addr(robj);
  400. }
  401. lobj->gpu_offset = robj->gpu_addr;
  402. if (fence) {
  403. old_fence = (struct radeon_fence *)robj->tobj.sync_obj;
  404. robj->tobj.sync_obj = radeon_fence_ref(fence);
  405. robj->tobj.sync_obj_arg = NULL;
  406. }
  407. if (old_fence) {
  408. radeon_fence_unref(&old_fence);
  409. }
  410. }
  411. return 0;
  412. }
  413. void radeon_object_list_unvalidate(struct list_head *head)
  414. {
  415. struct radeon_object_list *lobj;
  416. struct radeon_fence *old_fence = NULL;
  417. struct list_head *i;
  418. list_for_each(i, head) {
  419. lobj = list_entry(i, struct radeon_object_list, list);
  420. old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj;
  421. lobj->robj->tobj.sync_obj = NULL;
  422. if (old_fence) {
  423. radeon_fence_unref(&old_fence);
  424. }
  425. }
  426. radeon_object_list_unreserve(head);
  427. }
  428. void radeon_object_list_clean(struct list_head *head)
  429. {
  430. radeon_object_list_unreserve(head);
  431. }
  432. int radeon_object_fbdev_mmap(struct radeon_object *robj,
  433. struct vm_area_struct *vma)
  434. {
  435. return ttm_fbdev_mmap(vma, &robj->tobj);
  436. }
  437. unsigned long radeon_object_size(struct radeon_object *robj)
  438. {
  439. return robj->tobj.num_pages << PAGE_SHIFT;
  440. }